SiC single crystal wafer and method for manufacturing the same

Abstract

To provide a SiC wafer with an epitaxial growth layer that can reduce variations in the life of a gate insulating film after device formation by controlling the composition of the wafer surface in the SiC wafer before device formation.SOLUTION: An SiC single crystal wafer includes an SiC single crystal substrate, and an epitaxial layer formed on the SiC single crystal substrate and containing an SiC single crystal, and is obtained by surface composition analysis using XPS, and the C-Si composition ratio of the epitaxial layer in a region 1 to 3 nm from the surface is 50 atm% or less, the surface of the epitaxial layer contains Si, and the surface of the epitaxial layer is a plane along the main surface of the SiC single crystal substrate.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present invention relates to a SiC wafer, and in particular to a SiC wafer having an epitaxial layer formed thereon and a method for manufacturing the same. [Background technology]

[0002] Semiconductor power elements require not only high breakdown voltage, but also low on-resistance and low switching loss, but silicon (Si) power elements, which are currently the mainstream, are approaching their theoretical performance limits. Silicon carbide (SiC) has a dielectric breakdown field strength approximately one order of magnitude greater than Si, so by making the drift layer that maintains the breakdown voltage approximately one-tenth thinner and increasing the impurity concentration by approximately 100 times, it is theoretically possible to reduce element resistance by more than three orders of magnitude. In addition, because its band gap is approximately three times larger than Si, it is also capable of high-temperature operation, and SiC semiconductor elements are expected to exceed the performance of Si semiconductor elements, and development of SiC power devices is underway.

[0003] Patent Document 1 (Japanese Patent Application Laid-Open No. 2012-142597) describes preventing the occurrence of step bunching on the substrate surface.

[0004] Patent Document 2 (Japanese Patent Laid-Open Publication No. 2010-258294) describes evaporating silicon atoms from the surface of a silicon carbide epitaxial layer to make the silicon carbide surface contain 95 at % or more carbon atoms.

[0005] Patent Documents 3 to 7 describe adjusting the conditions during epitaxial growth to control the flow rate ratio (raw material supply ratio) or the composition ratio of the epitaxially grown layer. However, the techniques described in Patent Documents 3 to 7 do not make the surface of the epitaxially grown layer carbon-rich, and the flow rate ratio does not correlate with the composition ratio of the surface of the SiC wafer. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Laid-Open No. 2012-142597 [Patent Document 2] Japanese Patent Application Laid-Open No. 2010-258294 [Patent Document 3] Japanese Patent Application Laid-Open No. 2003-282451 [Patent Document 4] Japanese Patent Application Laid-Open No. 2015-143168 [Patent Document 5] Japanese Patent Application Laid-Open No. 2009-239103 [Patent Document 6] Japanese Patent Application Laid-Open No. 2007-137689 [Patent Document 7] International Publication No. 2015 / 159949 [Non-patent literature]

[0007] [Non-Patent Document 1] Senzaki, Junji, et al. "Challenges of High-Performance and High-Reliablity in SiC MOS Structures." Materials Science Forum. Vol. 717. Trans TechPublications, 2012. Summary of the Invention [Problem to be solved by the invention]

[0008] In the mass production process of SiC devices, multiple chip formation regions are simultaneously created on a wafer, and the wafer is then divided into multiple chips in the dicing process. While there would be no problem if the characteristics of each chip were identical, there will be a certain number of defective chips, resulting in large variations in device characteristics between chips. Reducing the variations in device characteristics is particularly important for power devices, which require large areas, in order to improve yield. For example, Non-Patent Document 1 describes how preventing step bunching on the substrate surface can improve the reliability of gate insulating films.

[0009] An object of the present invention is to provide a SiC wafer with an epitaxially grown layer that can reduce variations in the lifespan of the gate insulating film by controlling the composition of the wafer surface.

[0010] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0011] A brief summary of a representative embodiment of the present invention will be given below.

[0012] An SiC wafer according to one embodiment includes a SiC substrate and an epitaxial layer formed on the SiC substrate and containing SiC, wherein the C-Si composition ratio of the upper surface of the epitaxial layer is 50 atm% or less. [Effects of the Invention]

[0013] According to the representative embodiment, the reliability of the SiC wafer can be improved. [Brief explanation of the drawings]

[0014] [Figure 1] 1A to 1C are plan views illustrating a manufacturing process of a SiC wafer according to the first embodiment. [Figure 2] 2A to 2C are cross-sectional views showing a manufacturing process of the SiC wafer according to the first embodiment. [Figure 3] 3 is a cross-sectional view showing a manufacturing process following FIG. 2. [Figure 4] 4 is a cross-sectional view showing a manufacturing process following FIG. 3. [Figure 5] FIG. 1 is a schematic diagram illustrating a surface composition analysis method using XPS. [Figure 6] FIG. 1 is a schematic diagram illustrating a surface composition analysis method using XPS. [Figure 7] 1 is a graph showing details of peak separation of a C1s spectrum obtained by surface composition analysis using XPS. [Figure 8]1 is a graph showing details of peak separation of a C1s spectrum obtained by surface composition analysis using XPS. [Figure 9] 1 is a graph showing details of peak separation of a C1s spectrum obtained by surface composition analysis using XPS. [Figure 10] 1 is a graph showing details of peak separation of a C1s spectrum obtained by surface composition analysis using XPS. [Figure 11] 1 is a table showing the relationship between the composition ratio of various bonds containing carbon on the surface of an SiC wafer before carbon-rich processing and the take-off angle for XPS analysis. [Figure 12] 1 is a graph showing the relationship between the composition ratio of various bonds containing carbon on the surface of an SiC wafer before carbon-rich processing and the take-off angle in XPS analysis. [Figure 13] 1 is a table showing the relationship between the composition ratio of various bonds containing carbon on the surface of an SiC wafer after carbon-rich processing and the take-off angle for XPS analysis. [Figure 14] 1 is a graph showing the relationship between the composition ratio of various bonds containing carbon on the surface of an SiC wafer after carbon-rich processing and the take-off angle in XPS analysis. [Figure 15] 1 is a graph showing the composition ratio of C—Si bonds and the total composition ratio of bonds containing carbon other than C—Si before and after carbon-rich treatment. [Figure 16] This is the formula that shows the cumulative failure rate. [Figure 17] 10 is a graph showing the relationship between the dielectric breakdown injection charge amount and the cumulative failure rate in each of the SiC devices of the comparative example and the present embodiment. [Figure 18] 10A to 10C are cross-sectional views showing a manufacturing process of a DMOSFET on a SiC wafer according to a modification of the first embodiment. [Figure 19] FIG. 19 is a cross-sectional view showing a manufacturing process following FIG. [Figure 20] 19A to 19C are cross-sectional views showing the manufacturing process following FIG. [Figure 21] 21 is a cross-sectional view showing a manufacturing process following FIG. 20. [Figure 22] 22 is a cross-sectional view showing a manufacturing process following FIG. 21. [Figure 23] 23 is a cross-sectional view showing a manufacturing process following FIG. 22. [Figure 24] FIG. 24 is a cross-sectional view showing a manufacturing process following FIG. 23. [Figure 25] FIG. 25 is a cross-sectional view showing a manufacturing process following FIG. 24. [Figure 26] FIG. 26 is a cross-sectional view showing a manufacturing process following FIG. 25. [Figure 27] 10A to 10C are plan views illustrating a manufacturing process of a DMOSFET on a SiC wafer according to a modification of the first embodiment. [Figure 28] 1 is a graph showing the composition ratios of C—Si bonds and bonds containing carbon other than C—Si bonds on the top surface of an SiC wafer that has been subjected to an oxidation treatment. [Figure 29] 10 is a graph showing the relationship between the dielectric breakdown injection charge amount and the cumulative failure rate in a SiC device of a comparative example. DETAILED DESCRIPTION OF THE INVENTION

[0015] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In all drawings for explaining the embodiments, components having the same functions are designated by the same reference numerals, and repeated explanations thereof will be omitted. In addition, in the embodiments, explanations of the same or similar parts will not be repeated unless particularly necessary.

[0016] In this application, the term "SiC wafer" refers to both a wafer consisting of only a SiC substrate and a wafer including a SiC substrate and an epitaxial layer on the SiC substrate. The SiC substrate referred to here is a bulk substrate that does not include an epitaxial layer.

[0017] (Embodiment 1) <Details of areas for improvement> SiC (silicon carbide) has a wider band gap than Si (silicon), and insulating films formed on SiC substrates have high dielectric breakdown strength. Taking advantage of these characteristics, it is conceivable to apply high voltages to devices formed on SiC substrates, but in this case, the electric field applied to the insulating film becomes a problem. Therefore, when designing devices using SiC substrates, it is necessary to carefully consider the electric field applied to the insulating film. In particular, in device structures with gate insulating films such as MOSFETs (metal oxide semiconductor field effect transistors) or IGBTs (insulated gate bipolar transistors), if the electric field strength applied to the gate insulating film becomes strong, leakage current will occur in the gate insulating film. The occurrence of such leakage current can shorten the gate insulating film's lifespan and cause device malfunctions, such as dielectric breakdown of the gate insulating film.

[0018] These defects do not occur equally in each chip separated from a single wafer, and the gate insulating film lifespan varies from chip to chip (device). That is, during mass production of devices, multiple chip formation areas are simultaneously created on a wafer, and then a dicing process is performed to separate multiple chips from the wafer. There would be no problem if the characteristics of each chip were all the same, but a certain number of defective chips will exist. Causes of defective chips include the presence of foreign matter during the manufacturing process, as well as defects on the surface of the SiC substrate, for example.

[0019] One such defect is step bunching, which occurs due to the step-flow growth method. Step bunching often forms locally within the wafer surface, and its uneven shape varies widely. When devices are fabricated on wafers with step bunching, the device characteristics vary greatly. Therefore, in order to reduce the variation, it is important to reduce defects such as unevenness. In particular, in power devices that require a large area, it is important to reduce the variation in device characteristics in order to improve yield.

[0020] In Fig. 29, as a comparative example, a MOSFET (SiC device) was fabricated on a wafer mainly composed of silicon carbide, and the Weibull plot of the results of evaluating the CCS-TDDB (Constant Current Stress Time Dependent Dielectric Breakdown) characteristics for a plurality of MOSFETs existing within the same wafer plane is shown. The horizontal axis (semi-logarithmic) of the graph shown in Fig. 29 indicates the amount of charge injected into the insulating film, that is, the breakdown injection charge amount Qbd, until dielectric breakdown occurs in the insulating film formed on the SiC substrate. The vertical axis of the graph indicates the cumulative failure rate. That is, Fig. 29 is a graph showing the relationship between the breakdown injection charge amount and the cumulative failure rate in the SiC device of the comparative example.

[0021] The Weibull plot is a graph in which the breakdown injection charge amounts Qbd of a plurality of devices are plotted in a Weibull distribution when a constant current stress (CCS) is applied to the gate in a MOS structure such as a MOS capacitor or a MOSFET. When a constant current stress (CCS) is applied to the gate, the breakdown injection charge amount Qbd can be calculated from the stress time and the stress current by measuring the stress time until the gate insulating film breaks down.

[0022] In the Weibull plot, when the variation in the time (life) until dielectric breakdown is zero, the distribution of the plot becomes a straight line parallel to the vertical axis. However, in the comparative example shown in Fig. 29, the Weibull plot has a slope. Such a slope of the Weibull plot indicates the presence of variation and means that there are defects that reduce the breakdown injection charge amount Qbd.

[0023] Thus, in the SiC wafer, there is room for improvement in suppressing characteristic variations such as the life of the insulating film between the devices formed thereon.

[0024] <Configuration of SiC Wafer> In the present embodiment 1, a device is implemented to solve the above-mentioned room for improvement. The technical idea of ​​this embodiment that implements this device will be described below.

[0025] As a result of the inventors' research, they discovered that the composition of the wafer surface affects the reliability of the gate insulating film, and that controlling the composition of the SiC wafer surface can reduce the variation in gate insulating film lifetime. Below, we will explain an SiC wafer with an epitaxial layer that can reduce the variation in gate insulating film lifetime by controlling the composition of the SiC wafer surface.

[0026] Here, the manufacturing process of the SiC wafer of this embodiment will be described with reference to Figures 1 to 4. Figure 1 is a plan view showing the manufacturing process of the SiC wafer of this embodiment, and Figures 2 to 4 are cross-sectional views showing the manufacturing process of the SiC wafer of this embodiment.

[0027] When manufacturing the SiC wafer of this embodiment, first, as shown in FIGS. 1 and 2, a SiC wafer 1 consisting of only a SiC substrate (SiC bulk substrate) 2 is prepared. The crystal type of the SiC substrate 2 is, for example, 4H-SiC, but it may also be 6H-SiC or 3C-SiC. The off-angle of the main surface of the SiC substrate 2 is, for example, greater than 0.5 degrees and preferably less than 8 degrees. Here, the off-angle of the main surface of the SiC substrate 2 is, for example, 4 degrees. The plane orientation of the main surface of the SiC substrate 2 may be the Si plane, the C plane, or any other plane orientation, and here the plane orientation of the main surface of the SiC substrate 2 is the Si plane.

[0028] The SiC substrate 2 may be a substrate produced by a sublimation method, a solution method, or a gas growth method. The concentration of n-type impurities in the SiC substrate 2 is, for example, 1×10 18 ~1×10 21 / cm -3 Here, for example, 1 × 10 18 / cm -3 is.

[0029] Next, as shown in FIG. 3, an epitaxial layer (epitaxial growth layer, semiconductor layer) 3 is formed on the main surface of the SiC substrate 2 using an epitaxial growth method. Specifically, at a temperature of 1500°C or higher, SiH4 (monosilane) and C3H8 (propane) are supplied to the SiC substrate 2 using H2 (hydrogen) as a carrier gas. Trichlorosilane or methane may also be used as the gas used for epitaxial growth. Hydrogen chloride may also be introduced to improve the growth rate. This causes epitaxial growth to form the epitaxial layer 3. At this time, the epitaxial layer 3 is mainly composed of SiC.

[0030] The n-type impurity concentration of the epitaxial layer 3 varies depending on the device to be fabricated, but is, for example, 1×10 14 ~1×10 18 / cm -3 The thickness of the epitaxial layer 3 varies depending on the device to be fabricated, but is, for example, several μm to several tens of μm.

[0031] It is also believed that basal plane dislocations (BPDs), which are defects that cause degradation during electrical conduction, exist within the SiC substrate 2. BPDs that extend from the SiC substrate 2 into the epitaxial layer 3 during epitaxial growth hinder electrical conduction and tend to expand when electrical conduction occurs. In contrast, it is believed that some of the BPDs within the SiC substrate 2 are converted into threading edge dislocations (TEDs) at the interface between the SiC substrate 2 and the epitaxial layer 3 and extend into the epitaxial layer 3. TEDs do not hinder electrical conduction within the substrate and do not expand when electrical conduction occurs.

[0032] Therefore, before forming the epitaxial layer 3, a high-concentration buffer layer (semiconductor layer) made of SiC may be formed on the SiC substrate 2. The n-type impurity concentration of the buffer layer is, for example, 1×10 18 / cm -3The probability of BPDs expanding into the epitaxial layer 3 can be reduced by providing a buffer layer between the SiC substrate 2 and the epitaxial layer 3. That is, during epitaxial growth, BPDs in the SiC substrate 2 are more likely to be converted to TEDs at the interface between the SiC substrate 2 and the buffer layer. Furthermore, the presence of the buffer layer reduces the probability of holes reaching BPDs in the SiC substrate 2. This reduces the probability of electrical degradation in devices formed on a laminated substrate including the SiC substrate 2 and the epitaxial layer 3.

[0033] Furthermore, before forming the epitaxial layer 3, the upper surface of the SiC substrate 2 or the upper surface of the buffer layer may be subjected to CMP (Chemical Mechanical Polishing).

[0034] Further, although the formation of the epitaxial layer 3 on the SiC substrate 2 has been described here, instead of the process described using Figures 1 to 3, a laminated substrate (SiC wafer 1) in which the epitaxial layer 3 has already been laminated on the SiC substrate 2 may be prepared.

[0035] Next, as shown in FIG. 4, a carbon-rich treatment is performed. That is, a treatment is performed to make the surface composition of the epitaxial layer 3 carbon-rich. Specifically, the surface composition is modified so that the proportion (atomic percent, atm %) of bonds other than C-Si, such as C-C or C-O, is higher than the proportion of C-Si bonds on the upper surface of the epitaxial layer 3. In other words, carbon-rich in this application refers to a state in which the proportion of bonds other than C-Si, including C, is higher than the proportion of C-Si bonds. In other words, carbon-rich in this application refers to a state in which the C-Si composition ratio on the upper surface of the epitaxial layer is 50 atm % or less.

[0036] There are several possible methods for carbon-rich processing, but here, for example, the surface composition is modified by CMP, thereby forming a carbon-rich layer 4 on the upper surface of the epitaxial layer 3. The modification of the surface composition of the SiC wafer can be achieved by, for example, the CMP method.

[0037] The surface composition of the epitaxial layer 3 (the composition of the carbon-rich layer 4) can be investigated by, for example, surface composition analysis using XPS (X-ray Photoelectron Spectroscopy). Here, in the surface composition analysis using XPS, the conditions of the carbon-rich process are adjusted so that when peak separation of the C1s spectrum is performed, the proportion of bonds other than C-Si, such as C-C or C-O, is greater than the proportion of C-Si bonds.

[0038] 5 and 6 show schematic diagrams illustrating a surface composition analysis method using XPS. Note that the carbon-rich layer formed on the upper surface of the epitaxial layer is not shown in FIGS. 5 and 6. Here, an XPS equipped with a detector 35 having an angle-resolving function is used. When performing surface composition analysis using XPS, the detector 35 has an angle-resolving function, so that information at a depth of several nanometers (e.g., 1 to 3 nm) from the wafer surface can be resolved from information at a deeper position (e.g., about 7 nm) from the wafer surface. In other words, if the detector 35 does not have an angle-resolving function, it is not possible to distinguish and detect the surface composition of a relatively shallow region on the wafer surface from the surface composition of a relatively deep region on the wafer surface.

[0039] In XPS measurements, highly penetrating X-rays 25 are irradiated onto the SiC wafer 1, and the resulting photoelectrons (secondary electrons) are detected. Therefore, the detection depth is determined by the mean free path of the photoelectrons. In XPS with an angle-resolved detector, depth information can be obtained from the position within the detector plane where the photoelectrons are detected. That is, photoelectrons generated in shallow regions of the wafer surface can be detected across the entire surface of the detector 35, as shown in Figure 5. In contrast, photoelectrons generated in deep regions of the wafer surface have a short mean free path within the SiC wafer 1, so they can only escape at low angles, as shown in Figure 6, and cannot escape from the SiC wafer 1 at high angles. Therefore, composition analysis can be performed in relatively shallow regions of the wafer surface (e.g., a region 1 to 3 nm from the wafer surface) using photoelectrons that depart from the wafer toward the detector 35 at low angles. In this way, using an XPS with angle-resolved capability, composition can be resolved and obtained at a depth of several nm from the wafer surface.

[0040] The angles such as high angle and low angle (take-off angle, secondary electron departure angle) referred to here are the angle θ between a line perpendicular to the surface (main surface) of the SiC wafer 1 and the direction of travel of photoelectrons emitted from the surface of the SiC wafer 1 by irradiation with X-rays 25.

[0041] In this embodiment, the surface composition of the SiC wafer was adjusted by carbon-rich processing so that when XPS composition analysis was performed on the very surface of the SiC wafer (e.g., a region 1 to 3 nm from the wafer surface), the surface composition ratio of C-Si was 43 atm%. However, if the composition near the very surface of the SiC wafer (e.g., a region 1 to 3 nm from the wafer surface) is not resolved and detected, the results of the XPS analysis will also include information on the bonding state at a depth of several nm (e.g., 7 nm) from the wafer surface. In this case, the surface composition ratio of C-Si obtained by XPS analysis will be 83 atm%. This will be explained below using Figures 7 to 13.

[0042] 7 to 10 are graphs showing details of peak separation in C1s spectra obtained by surface composition analysis using XPS. In these graphs, the horizontal axis represents the binding energy of the composition on the wafer surface, and the vertical axis represents the photoelectron energy (emitted photoelectron intensity). Figures 7 to 9 show the results of XPS analysis of SiC wafers subjected to the carbon-rich treatment of this embodiment, while Figure 10 shows the results of XPS analysis of a comparative SiC wafer that was not subjected to the carbon-rich treatment of this embodiment.

[0043] 7 and 10 are graphs showing the analysis results when the detection angle of the detector 35 was 81.125 degrees, i.e., a high angle. In other words, FIGS. 7 and 10 show the composition of a relatively shallow region on the wafer surface. FIG. 9 is a graph showing the analysis results when the detection angle of the detector 35 was 24.875 degrees, i.e., a low angle. In other words, FIG. 9 shows the composition of a relatively deep region on the wafer surface. FIG. 8 is a graph showing the analysis results when the detection angle of the detector 35 was 51.125 degrees. In other words, FIG. 8 shows the composition in a region intermediate in depth between FIG. 7, which shows the composition of the shallow region, and FIG. 9, which shows the composition of the deep region. The composition of the relatively deep region on the wafer surface of the comparative example is almost the same as the composition of the relatively shallow region on the wafer surface of the comparative example shown in FIG. 10, and therefore is not shown here.

[0044] 7 to 10 show graphs of the analysis results for C-Si, which is a carbon-silicon bond, CC, which is a carbon-carbon bond, CO, which is a carbon-oxygen bond, C=O, which is a carbon-oxygen double bond, and OCO, which is an oxygen-carbon ether bond. In Figures 7 to 10, the C-Si graph is shown with a solid line, the CC graph is shown with a dashed line, the CO graph is shown with a dashed-dot line, the C=O graph is shown with a dashed-dot line, and the OCO graph is shown with a dashed-dot line.

[0045] As shown in FIGS. 7 to 9, the composition ratios of various carbon-containing bonds are depth-dependent. This will be explained below with reference to FIGS. 11 to 15. FIGS. 11 and 12 are a table and a graph showing the relationship between the composition ratios of various carbon-containing bonds on the surface of a SiC wafer before carbon-rich processing and the take-off angle of XPS analysis. FIGS. 13 and 14 are a table and a graph showing the relationship between the composition ratios of various carbon-containing bonds on the surface of a SiC wafer after carbon-rich processing and the take-off angle of XPS analysis. In FIGS. 12 and 14, the horizontal axis of the graphs shows the take-off angle of XPS analysis, and the vertical axis of the graphs shows the composition ratio. The larger the take-off angle of XPS analysis, which is the horizontal axis of these graphs, the closer the XPS analysis location is to the wafer surface.

[0046] 15 is a graph showing the composition ratio of C-Si bonds and the total composition ratio of bonds containing carbon other than C-Si before and after the carbon-rich treatment. In FIG. 15, the graph before the carbon-rich treatment is shown on the right, and the graph after the carbon-rich treatment is shown on the left. In FIG. 15, the composition ratio of C-Si bonds is shown as a white bar, and the bar showing the ratio of the total composition ratio of bonds containing carbon other than C-Si is hatched.

[0047] In Fig. 12 and Fig. 14, the C-Si graph is shown by a solid line, the CC graph is shown by a dashed line, the CO graph is shown by a dashed line, the C=O graph is shown by a dashed line, and the OC - The graph of O is shown by the three-dot chain line.

[0048] As shown in Figures 11 to 12 and 15, before the carbon-rich treatment, most of the composition ratio near the wafer surface is occupied by C-Si bonds, and the total ratio of the composition ratio of bonds containing carbon other than C-Si bonds is equal to or less than the composition ratio of C-Si bonds. In contrast, as shown in Figures 13 to 15, after the carbon-rich treatment, the composition ratio near the wafer surface, especially in the shallow region, is the highest, at about 43%, for C-Si bonds. However, as shown in Figures 13 to 15, the total ratio of the composition ratio of bonds containing carbon other than C-Si bonds is about 57%, which is greater than the composition ratio of C-Si bonds. In particular, the C-Si bond composition in the relatively shallow region of the wafer surface - The composition ratio of the C bond is close to that of the C-Si bond.

[0049] Thus, at the wafer surface, the sum of the composition ratios of the other carbon-containing bonds in addition to the C-Si bond is greater than the composition ratio of the C-Si bond itself. In other words, the wafer is in a carbon-rich state. Furthermore, when the surface composition of an SiC wafer is adjusted by carbon-rich processing, XPS reveals that the C-Si surface composition ratio near the very surface of the SiC wafer (e.g., a region 1 to 3 nm from the wafer surface) is 43 atm%. Therefore, when measurements are performed using an XPS with angle resolution, if the C-Si composition ratio near the very surface of the epitaxial layer is 50 atm% or less, it can be said to be in a carbon-rich state. In contrast, the carbon-rich processing results in a C-Si surface composition ratio of 83 atm% at a location several nm (e.g., 7 nm) deep from the wafer surface. Therefore, if the C-Si surface composition ratio at a location several nm (e.g., 7 nm) deep from the wafer surface is 83 atm% or less, it can be said to be in a carbon-rich state. In other words, when measurements are performed using an XPS without angle resolution, even if the composition ratio of the wafer surface is measured, it is not possible to distinguish between shallow and deep regions of the wafer surface. Therefore, when measurements are performed using such an XPS, a carbon-rich state can be said to exist when the C-Si composition ratio of the top surface of the epitaxial layer, which is the wafer surface, is 83 atm% or less.

[0050] Here, the inventors confirmed that when the XPS take-off angle was 24.875 degrees, the composition ratio of C C was 8.79 atm% and the composition ratio of CO was 3.6 atm% on the top surface of the epitaxial layer. That is, when the XPS take-off angle was small and a relatively deep region of the epitaxial layer was analyzed, the composition ratio of C C was 8.7 atm% or more and the composition ratio of C - When the composition ratio of O is 3.6 atm % or more, it is considered to be in a carbon-rich state.

[0051] Furthermore, the inventors confirmed that when the XPS take-off angle was 81.125 degrees, the composition ratio of C—C was 36.01 atm% and the composition ratio of CO was 10.55 atm% on the top surface of the epitaxial layer. That is, when the XPS take-off angle was large and a relatively shallow region of the epitaxial layer was analyzed, the composition ratio of C—C was 35 atm% or more and the composition ratio of C was 10.55 atm%. - When the composition ratio of O is 10 atm % or more, it is considered to be in a carbon-rich state.

[0052] <Effects of this embodiment> The inventors performed a TDDB characteristic evaluation on 68 DMOSFETs (Double-Diffused MOSFETs) fabricated on the SiC wafer of this embodiment that had been subjected to carbon-rich processing and on a SiC wafer that had not been subjected to carbon-rich processing. Here, the source and drain potentials were set to 0 V, and a voltage was applied to the gate so that a constant current flowed, and the time until the gate insulating film broke down was measured. The temperature during the measurement was approximately 150°C, and the voltage was adjusted to maintain a constant current density.

[0053] FIG. 17 shows a Weibull plot of the results of evaluating the TDDB characteristics. The horizontal and vertical axes of the graph shown in FIG. 17 represent the dielectric breakdown injection charge Qbd and the cumulative failure rate, respectively, as in FIG. 29. FIG. 17 is a graph showing the relationship between the dielectric breakdown injection charge and the cumulative failure rate for SiC devices of the comparative example and the present embodiment. In FIG. 17, the plot of the evaluation results for the device of the comparative example that was not subjected to the carbon-rich treatment is indicated by diamonds, and the plot of the evaluation results for the device using the wafer of the present embodiment that was subjected to the carbon-rich treatment is indicated by triangles.

[0054] In this evaluation, the shape parameter m was calculated for analysis. Here, the scale parameter is η. Generally, when the cumulative failure rate F(t) follows a Weibull distribution, the cumulative failure rate F(t) can be described by equation (1) shown in Figure 16.

[0055] Furthermore, equation (1) can be rewritten as equation (2) below. ln(-ln(1-F(t))=mln(t)-mlnη) ···(2) In a Weibull plot, when y = ln(-ln(1-F(t)) and x = ln(t), the slope is m and the intercept is -mlnη. That is, an increase in m makes the distribution uniform and reduces the characteristic variation, and an increase in η increases the maximum value of the main distribution. That is, as shown in FIG. 17, the Weibull plot graph of the comparative example has a slope with respect to the vertical axis, but the Weibull plot graph of the present embodiment has a uniform distribution that is parallel to the vertical axis.

[0056] When the shape parameter m was calculated for the present embodiment in which carbon-rich processing was performed and the comparative example in which carbon-rich processing was not performed, it was m = 11.3 for the specification with carbon-rich processing and m = 2.1 for the specification without carbon-rich processing. In other words, the value of m increases due to carbon-rich processing. The inventors have also confirmed that the value of η also increases. This indicates that the slope of the main distribution becomes steeper and the maximum value of Qbd becomes higher. The increase in m and η due to carbon-rich processing is effective from the perspective of improving yield.

[0057] As described above, this embodiment provides a SiC wafer having an epitaxial layer on a SiC substrate, the SiC wafer having a carbon-rich main surface. That is, the C-Si composition ratio of the upper surface of the epitaxial layer is 50 atm% or less. The carbon-rich surface of the SiC wafer extends the time (lifetime) until dielectric breakdown occurs in devices such as MOSFETs having gate insulating films formed on such SiC wafers. Furthermore, the gate insulating films of the devices formed in each chip region arranged in a matrix on the circular SiC wafer can be made uniform in characteristics such as lifetime, thereby preventing characteristic variations. This eliminates the aforementioned room for improvement. The reliability of the SiC wafer can be improved. Furthermore, since the generation of defective chips can be prevented, the use of SiC wafers subjected to the carbon-rich treatment of this embodiment can increase product yield.

[0058] However, it is necessary to pay attention to the composition ratio within the wafer surface after carbon-rich processing. If the SiC surface is completely carbonized by carbon-rich processing, that is, if the composition ratio of bonds other than C-Si on the wafer surface becomes 90-100 atm%, graphene will be present at the interface between the SiC layer (epitaxial layer) and the gate insulating film when devices such as MOSFETs or IGBTs are fabricated. If graphene is present at the SiC / SiO2 interface, there is a risk that conduction will occur between the source and drain regardless of the gate voltage, causing the device to malfunction. Therefore, it is desirable for the C-Si composition ratio on the wafer surface to be greater than 10 atm%.

[0059] Thus, in order to obtain the effect of this embodiment, it is necessary to adjust the composition ratio of the C—Si bond to be greater than 10 atm %.

[0060] <Variation 1> The carbon-rich treatment described above may be a short-time heat treatment performed on the SiC wafer in an inert gas (e.g., Ar (argon)) atmosphere at a temperature of, for example, about 1300° C. The carbon-rich treatment can be performed by carbonizing the surface of the SiC wafer through such heat treatment.

[0061] However, even in this case, it is necessary to pay attention to the composition ratio within the wafer surface after carbon-rich processing. In other words, if the SiC surface is completely carbonized by high-temperature annealing in an Ar atmosphere, graphene will form at the SiC / SiO2 interface, which may cause conduction between the source and drain regardless of the gate voltage, causing the device to malfunction. Therefore, it is desirable for the C-Si composition ratio on the wafer surface to be greater than 10 atm%.

[0062] <Variation 2> 18 to 27, a process for forming a DMOSFET on a SiC wafer will be described as a second modification of the present embodiment. FIGS. 18 to 26 are cross-sectional views showing the process for manufacturing a DMOSFET on a SiC wafer according to this modification. FIG. 27 is a plan view showing the process for manufacturing a DMOSFET on a SiC wafer according to this modification.

[0063] First, as explained with reference to Figures 1 to 4, an SiC wafer 1 is formed having an epitaxial layer 3 that has been subjected to a carbon-rich treatment. Note that in Figures 18 to 26 used in the following explanation, the carbon-rich layer on the upper surface of the epitaxial layer 3 is not shown.

[0064] Next, as shown in FIG. 18, Al (aluminum) ions are implanted into the surface layer of the epitaxial layer 3 using a mask (not shown) provided on the epitaxial layer 3. This forms a p-type semiconductor region, a p-body region 5, on the upper surface of the epitaxial layer 3. The impurity implantation depth is, for example, about 1 μm. The p-type impurity concentration of the p-body region 5 is, for example, 5×10 16 ~1×10 19 cm -3 The ions implanted to form p-body region 5 may be B (boron) ions. Alternatively, a p-type epitaxial layer made of SiC may be formed on epitaxial layer 3, and this epitaxial layer may serve as the p-body region. In this case, the carbon-rich treatment described with reference to FIG. 4 is performed after the formation of the epitaxial layer, but not before, and before the formation of the gate insulating film described below. Thereafter, the mask is removed.

[0065] 19, N (nitrogen) ions are implanted into the upper surface of the epitaxial layer 3 using a mask (not shown) provided on the epitaxial layer 3. As a result, a source region 6, which is an n-type semiconductor region shallower than the p-body region 5, is formed on the upper surface of the p-body region 5. The implantation depth of the impurity is, for example, in the range of 0.1 to 0.5 μm. The n-type impurity concentration of the source region 6 is, for example, 1×1018 ~1×10 21 cm -3 The ions implanted to form the source region 6 may be P (phosphorus) ions. After that, the mask is removed.

[0066] 20, Al ions are implanted into the upper surface of the epitaxial layer 3 using a mask (not shown) provided on the epitaxial layer 3. As a result, a potential fixing region 7, which is a p-type semiconductor region shallower than the p-body region 5 and adjacent to the source region 6, is formed on the upper surface of the p-body region 5. The impurity implantation depth is, for example, in the range of 0.1 to 0.5 μm. The p-type impurity concentration of the potential fixing region 7 is, for example, 1×10 18 ~1×10 21 cm -3 The ions implanted to form the potential fixing region 7 may be B ions. After that, the mask is removed.

[0067] 21, N ions are implanted into the rear surface of the SiC substrate 2 to form a drain region 8, which is an n-type semiconductor region. The n-type impurity concentration of the drain region 8 is, for example, 1×10 16 ~1×10 19 cm -3 The ions implanted to form the drain region 8 may be P ions.

[0068] In this modification, a process for forming a minimum configuration for operating the MOSFET will be described, but a structure that adds a function such as a termination region may also be formed.

[0069] Next, although not shown, a carbon film is deposited as a cap material to cover the periphery of the SiC wafer 1 consisting of the SiC substrate 2 and the epitaxial layer 3, and then impurity activation annealing is performed at a temperature of, for example, 1600 to 1800°C. The carbon film is then removed by oxygen plasma ashing. To obtain an even cleaner surface, a thermal oxide film may then be formed and removed using a diluted hydrofluoric acid solution.

[0070] 22, a gate insulating film 9 is formed on the epitaxial layer 3. In this embodiment, a deposited oxide film having a thickness of about 10 to 100 nm is formed by using, for example, a CVD (Chemical Vapor Deposition) method.

[0071] 23, a gate electrode 10 made of an n-type polycrystalline silicon film having a thickness of approximately 100 to 300 nm is deposited on the epitaxial layer 3. The gate electrode 10 can be formed by forming the silicon film by, for example, a CVD method, and then patterning the silicon film. The upper surfaces of the source region 6 and the potential fixing region 7 are exposed from the gate electrode 10. This forms a MOSFET including the gate electrode 10, the source region 6, and the drain region 8.

[0072] 24, an interlayer film (interlayer insulating film) 11 is formed to cover the gate electrode. The interlayer film 11 can be formed by forming a silicon oxide film on the gate electrode 10 by, for example, a CVD method, and then patterning the silicon oxide film. This patterning forms contact holes that expose the upper surfaces of the source region 6 and the potential fixing region 7.

[0073] Next, as shown in Figure 25, + Type source region 6 and p + To enable electrical conduction with the potential clamping region 7 of the source region 6, a silicide layer 12 is formed on each of the source region 6 and the potential clamping region 7. That is, a metal film for silicide is deposited on the epitaxial layer 3, and silicidation is performed by, for example, annealing at 700°C to 1000°C. This forms the silicide layer 12, which is the source-base common connection portion. Thereafter, in a region not shown, the interlayer film is etched to form a gate contact hole in order to ensure electrical conduction with the gate electrode.

[0074] Subsequently, a source electrode 13 is formed on the epitaxial layer 3 to cover the interlayer film 11 and the silicide layer 12. The source electrode 13 is electrically connected to the source region 6 and the potential fixing region 7 via the silicide layer 12.

[0075] Next, as shown in FIG. 26, the lower surface of the drain region 8 is silicided to form a silicide layer 14. Thereafter, a drain contact electrode 15 is formed below the silicide layer 14. A metal material such as Ni (nickel) or Al is used for each of the silicide metal film, source electrode 13, and drain contact electrode 15. After that, a surface protection film made of an insulator is formed on the upper surface of the SiC wafer 1 to protect the device, and wiring to each electrode is performed, completing the semiconductor device. This results in the SiC wafer shown in FIG. 27. The SiC wafer has chip regions formed in a matrix in plan view. A dicing process is performed to remove the gaps between the chip regions, thereby obtaining multiple semiconductor chips from the SiC wafer.

[0076] In the MOSFET formed in this modification, a carbon-rich layer is formed on the upper surface of the epitaxial layer 3 in contact with the gate insulating film 9. This extends the time (lifetime) until dielectric breakdown occurs in the gate insulating film 9 between the gate electrode 10 and the epitaxial layer 3. In addition, it is possible to uniform the characteristics, such as the lifespan, of the gate insulating films of the elements formed in each of the chip regions arranged in a matrix on the circular SiC wafer, thereby preventing characteristic variations. This therefore improves the reliability of the SiC wafer and further increases the product yield.

[0077] Here, the carbon-rich layer (see FIG. 3) is formed after the epitaxial layer is formed and before the p-body region is formed. However, the carbon-rich process is not limited to this point, and may be performed at any point after the epitaxial layer that constitutes the top surface of the SiC wafer is formed and before the gate insulating film is formed.

[0078] In the case of forming a trench-gate MOSFET, a trench is formed on the upper surface of the epitaxial layer, and then a gate electrode is embedded in the trench via a gate insulating film. In this case, a carbon-rich treatment is performed after the trench is formed but before the gate insulating film is formed.

[0079] (Embodiment 2) The carbon-rich treatment can also be achieved by oxidizing the surface of an SiC wafer having an epitaxial layer and removing the oxide film formed by the oxidation using a chemical such as hydrofluoric acid.

[0080] FIG. 28 is a graph showing the composition ratios of C-Si bonds and carbon-containing bonds other than C-Si bonds on the top surface of a SiC wafer before carbon-rich processing, a SiC wafer from which the oxide film was removed after oxidation processing at 1300°C, and a SiC wafer from which the oxide film was removed after oxidation processing at 1150°C. From right to left, FIG. 28 shows the graphs for the case before carbon-rich processing, the case after oxidation processing at 1300°C, and the case after oxidation processing at 1150°C. That is, FIG. 28 compares the surface composition ratios of SiC wafers obtained by performing oxidation processing at 1150°C and 1300°C in a dry oxygen atmosphere to form an oxide film of approximately 50 nm, followed by removal of the oxide film with hydrofluoric acid. In FIG. 28, the composition ratio of C-Si bonds is shown as a white bar, and the bar representing the total composition ratio of carbon-containing bonds other than C-Si is hatched.

[0081] 28, the composition ratio of C-Si bonds is smaller and the composition ratio of bonds containing carbon other than C-Si bonds is larger when the oxidation treatment is performed at 1300°C than before the carbon-rich treatment. Also, the composition ratio of C-Si bonds is smaller and the composition ratio of bonds containing carbon other than C-Si bonds is larger when the oxidation treatment is performed at 1150°C than when the oxidation treatment is performed at 1300°C.

[0082] That is, in order to reduce the composition ratio of C-Si bonds, it is important to carry out oxidation at a lower temperature.

[0083] The invention made by the present inventors has been specifically described above based on the embodiments thereof, but the present invention is not limited to the above-described embodiments and can be modified in various ways without departing from the spirit of the invention. [Explanation of symbols]

[0084] 1 SiC wafer 2. SiC substrate 3 Epitaxial layer 4 Carbon-rich layer

Claims

1. a 4H—SiC single crystal substrate; an epitaxial layer formed on the 4H—SiC single crystal substrate; Including, a 4H—SiC buffer layer between the 4H—SiC single crystal substrate and the epitaxial layer; a composition ratio of C-Si bonds among carbon-containing C-Si, C-C, C-O, C=O, and O-C-O bonds in the epitaxial layer in a region 1 to 3 nm from the surface, which is obtained by surface composition analysis using XPS, is 50 atomic % or less and more than 10 atomic %, a surface of the epitaxial layer that is a plane along a main surface of the 4H—SiC single crystal substrate and is a surface for device fabrication.

2. (a) providing a 4H—SiC single crystal substrate; (b) forming a 4H—SiC buffer layer on the 4H—SiC single crystal substrate; (b2) forming an epitaxial layer on the buffer layer; (c) modifying the composition of the surface of the epitaxial layer so that the composition ratio of C—Si bonds among carbon-containing C—Si, C—C, C—O, C═O, and O—C—O bonds in the epitaxial layer in a region 1 to 3 nm from the surface, as determined by surface composition analysis using XPS, is 50 atomic % or less and is greater than 10 atomic %; Including, a surface of the epitaxial layer that is a plane along a main surface of the 4H—SiC single crystal substrate and is a surface for device fabrication.

Images