Resistive memory devices with magnetic layers having tunable topological spin textures

Abstract

The resistive memory device includes a magnetic tunnel junction structure that includes a free magnetic layer that includes a magnetic material that can be configured to host a topological spin texture to tune the conductance state of the resistive memory device.

Description

[Technical Field]

[0001] The present disclosure generally relates to nonvolatile analog resistive memory cells for neuromorphic computing and techniques for tuning the conductance of resistive memory devices in nonvolatile analog resistive memory cells. Information processing systems, such as neuromorphic computing systems and artificial neural network systems, are utilized in a variety of applications, including machine learning and inference processing for cognitive recognition and computing. Such systems are typically hardware-based systems that include a large number of highly interconnected processing elements (referred to as "artificial neurons") operating in parallel to perform various types of computations. Artificial neurons (e.g., pre-synaptic and post-synaptic neurons) are coupled using artificial synaptic devices, which provide synaptic weights that represent the connection strengths between the artificial neurons. Synaptic weights can be implemented using analog memory elements, such as tunable resistive memory devices that exhibit nonvolatile, multi-valued memory characteristics. Summary of the Invention

[0002] Embodiments of the present disclosure include resistive memory devices and nonvolatile resistive memory cells that include magnetic layers configured to host topological spin textures, such as magnetic skyrmions, that can tune the conductance of the resistive memory device, as well as computing systems that implement such resistive memory devices.

[0003] In an exemplary embodiment, a resistive memory device includes a magnetic tunnel junction structure including a free magnetic layer, the free magnetic layer including a magnetic material configurable to host a topological spin texture to tune the conductance state of the resistive memory device.

[0004] Other embodiments are described in the following detailed description of exemplary embodiments, which is to be read in conjunction with the accompanying drawings. [Brief explanation of the drawings]

[0005] [Figure 1] 1 illustrates a schematic diagram of a resistive processing unit (RPU) computing system including an array of non-volatile resistive memory cells, which may be implemented using magnetic skyrmion resistive memory devices, according to an exemplary embodiment of the present disclosure. [Figure 2] 1 illustrates a schematic diagram of an exemplary configuration of an RPU system for performing in-memory computing operations, according to an exemplary embodiment of the present disclosure. [Figure 3] 1A and 1B illustrate schematic diagrams of an analog resistive memory cell implementing a magnetic skyrmion resistive memory device, according to exemplary embodiments of the present disclosure. [Figure 4] 1 illustrates a schematic representation of a magnetic skyrmion resistive memory device according to an exemplary embodiment of the present disclosure. [Figure 5A] 1A-1C illustrate schematic diagrams of enhancement and suppression programming operations for generating and annihilating magnetic skyrmions in a magnetic skyrmion resistive memory device, according to exemplary embodiments of the present disclosure. [Figure 5B] 1A-1C illustrate schematic diagrams of magnetic skyrmions generated in a layer of magnetic material with perpendicular magnetic anisotropy, according to exemplary embodiments of the present disclosure; [Figure 5C] 1A-1C illustrate schematic diagrams of magnetic skyrmions generated in a layer of magnetic material with perpendicular magnetic anisotropy, according to exemplary embodiments of the present disclosure; [Figure 6] 10A and 10B illustrate schematically a magnetic skyrmion resistive memory device according to another exemplary embodiment of the present disclosure. [Figure 7] 10A and 10B illustrate schematically a magnetic skyrmion resistive memory device according to another exemplary embodiment of the present disclosure. [Figure 8] 10A and 10B illustrate schematically a magnetic skyrmion resistive memory device according to another exemplary embodiment of the present disclosure. [Figure 9] 10A and 10B illustrate schematically a magnetic skyrmion resistive memory device according to another exemplary embodiment of the present disclosure. [Figure 10] 1 illustrates schematically an exemplary architecture of a computing node capable of hosting a system configured to execute neuromorphic computing applications utilizing a hardware-accelerated computing RPU system, in accordance with an exemplary embodiment of the present disclosure. [Figure 11] 1 illustrates a cloud computing environment in accordance with an exemplary embodiment of the present disclosure. [Figure 12] 1 illustrates an abstraction model layer according to an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0006] Embodiments of the present disclosure are now described in further detail with respect to resistive memory devices and nonvolatile resistive memory cells including magnetic layers configured to host topological spin textures, such as magnetic skyrmions, capable of tuning the conductance of the resistive memory device, as well as computing systems implementing such resistive memory devices. As described in further detail below, exemplary embodiments of the present disclosure include multistate resistive memory devices implementing a free magnetic layer configured to host topological spin textures, such as magnetic skyrmions, where the state of such resistive memory devices is modulated using a programming current to create or eliminate the topological spin texture in the free magnetic layer. As known in the art, a magnetic skyrmion is a type of vortex-like magnetic texture that exhibits topological properties, specifically a non-collinear structure of magnetic moments with a vortex-like magnetic structure. For illustrative purposes, exemplary embodiments of the present disclosure will be described with reference to skyrmion-based resistive memory devices (or more generally, skyrmion resistive memory devices), which utilize the formation / annihilation of magnetic skyrmions in the free magnetic layer of a magnetic tunnel junction structure of a resistive memory device to modulate the magnetoresistance of the resistive memory device. However, it should be understood that the same or similar techniques as those disclosed herein can be used to implement multistate resistive memory devices with a free magnetic layer that can host one of a variety of stable topological spin textures suitable for a given application.

[0007] It should be understood that the various features shown in the accompanying drawings are schematic views and not drawn to scale. Additionally, for ease of illustration and description, one or more layers, structures, regions, features, etc. of a type commonly used to implement resistive memory devices, as well as components of other devices or structures and systems as shown schematically in the drawings, may not be explicitly shown in a given drawing. This does not imply that any layers, structures, regions, features, etc. not explicitly shown are omitted from the actual device or structure. Furthermore, the same or similar reference numbers are used throughout the drawings to indicate the same or similar features, elements, or structures, and thus, detailed descriptions of the same or similar features, elements, or structures will not be repeated in each of the drawings. Furthermore, as used herein, the term "exemplary" means "serving as an example, instance, or illustration." Any embodiment or design described herein as "exemplary" is not to be construed as preferred or advantageous over other embodiments or designs. When used herein to describe the orientation of a given feature relative to another feature, the term "relative to" means that the given feature may be positioned or formed "directly" on (i.e., in direct contact with) the other feature, or that the given feature may be positioned or formed "indirectly" on the other feature by way of one or more intervening features disposed between the given feature and the other feature.

[0008] Furthermore, when used in connection with a circuit, structure, element, component, etc. that performs one or more functions or otherwise provides some functionality, it should be understood that the phrase "configured to" is intended to encompass embodiments in which the circuit, structure, element, component, etc. is implemented in hardware, software, or a combination thereof, or both, and in implementations that include hardware, the hardware may include discrete circuit elements (e.g., transistors, inverters, etc.), programmable elements (e.g., ASICs, FPGAs, etc.), processing devices (e.g., CPUs, GPUs, etc.), one or more integrated circuits, or a combination thereof, or both. Thus, merely by way of example, when a circuit, structure, element, component, etc. is defined as being configured to provide a particular functionality, it is intended to cover, without limitation, embodiments in which the circuit, structure, element, component, etc. is comprised of an element, processing device, and / or integrated circuit that enables the circuit, structure, element, component, etc. to perform the particular function when in an operational state (e.g., connected to or otherwise deployed in a system, powered, receiving input, or generating output, or a combination thereof), as well as embodiments in which the circuit, structure, element, component, etc. is in a non-operational state (e.g., not connected to or otherwise deployed in a system, not powered, not receiving input, or not generating output, or a combination thereof), or in a partially operational state.

[0009] Exemplary embodiments of the present disclosure include a computing system or computational memory system that utilizes an array of nonvolatile analog memory cells for two purposes: data storage and data processing to perform some computational tasks. In some embodiments, the nonvolatile analog memory cells (e.g., resistive processing units) implement magnetic skyrmion resistive memory devices with tunable conductance (G) having variable conductance states ranging from a minimum conductance (G) to a maximum conductance (G). Exemplary embodiments of magnetic skyrmion resistive memory devices and nonvolatile memory cells implementing magnetic skyrmion resistive memory devices as storage elements are described in further detail below in conjunction with Figures 3, 4, 6, 7, 8, and 9. As previously mentioned, neuromorphic computing systems and artificial neural network systems are types of in-memory computing systems in which artificial neurons are coupled using artificial synapse devices to provide synaptic weights that represent the strength of the connection between two artificial neurons. Synaptic weights can be implemented using tunable magnetic skyrmion resistive memory devices, such as those disclosed herein, that utilize the variable conductance states of the magnetic skyrmion resistive memory devices to represent synaptic weights and perform computations, and the conductance states of the magnetic skyrmion resistive memory devices can encode or otherwise map synaptic weights.

[0010] Neuromorphic computing architectures are implemented in various types of artificial neural networks, such as deep neural networks (DNNs) and convolutional neural networks (CNNs), for machine learning applications such as image recognition, object recognition, and speech recognition. The in-memory computations associated with such neural networks include training computations, which optimize the synaptic weights of resistive memory cells by processing a training data set, and forward inference computations, which process input data using the trained neural network for purposes such as classifying the input data or predicting events based on the input data.

[0011] Training a DNN typically relies on a backpropagation algorithm, which includes three iterative cycles: forward, backward, and weight update, and is repeated multiple times until a convergence criterion is met. The forward and backward cycles primarily involve computing forward and backward vector-matrix multiplications. This operation can be performed on a 2D array of analog resistive memory cells. In the forward cycle, the stored conductance values ​​of the resistive memory devices in the 2D array form a matrix, and each input row of the 2D array transmits an input vector as a voltage pulse to perform the matrix-vector multiplication operation. In the backward cycle, voltage pulses are supplied as inputs from the columns, and the matrix-vector product is calculated using the matrix transpose. Weight updates involve computing a vector-vector cross product, which consists of a multiplication operation and incremental weight updates performed locally at each resistive memory cell in the 2D array.

[0012] A stochastically trained DNN, including an array of RPU cells, may have synaptic weights implemented using tunable magnetic skyrmion resistive memory devices according to exemplary embodiments of the present disclosure. To properly train a DNN and achieve high accuracy, the operating characteristics of the tunable resistive devices must meet a strict set of specifications for acceptable RPU device parameters that a given DNN algorithm can tolerate without incurring significant error penalties. These specifications include, for example, the minimum incremental conductance change (±Δg) resulting from a certain number (e.g., one or more) of enhancement / inhibition pulses. min These include variations in the switching characteristics of the resistive memory device, such as the symmetry of the conductance change from high to low, and the range of adjustable conductance values. In particular, one important specification for training DNNs is that the RPU cell must have an adjustable conductance with a resolution (or dynamic range) of a relatively large number (e.g., 100, 1000, or more) of conductance levels (or steps), and the conductance levels must be able to be switched (by a 1-nanosecond pulse) from the lowest to the highest conductance state in an analog, symmetrically incremental manner (with at least one order of magnitude difference in conductance (on / off ratio) between the maximum and minimum conductance states). The smallest unit weight value (±Δw min To achieve symmetry in the up and down changes of the conductance (Δg) of the RPU cell, each incremental increase (step-up, Δg) in the relevant conductance level is + min ) and incremental decrease (step down, Δg - min ) must be identical or similar within a mismatch error of 5% or less. In other words, for a tunable resistive RPU device that is analog in nature, the upper and lower conductance changes must respond symmetrically when identical but opposite pulse stimuli are provided. In particular, the upper and lower symmetry, Δg + min / Δg ―min must be equal to 1.0 ± 0.05. The parameter Δg ± min is the gain defined by the peripheral circuit, and the parameter Δw ± min Note that it is proportional to

[0013] However, despite these requirements, tunable resistive devices not only exhibit limited dynamic range and resolution, but can also exhibit variability in tuning / programming characteristics, making it difficult to achieve symmetric weight updates across a range of conductance levels (minimum to maximum). Therefore, hardware implementation of an RPU architecture is not trivial. More specifically, in practice, most resistive memory devices do not exhibit symmetric switching behavior; rather, they exhibit highly nonlinear changes in conductance as a function of the number of successively applied pulses. This leads to significant errors in weight updates. On the other hand, linear resistance changes imply similar incremental adjustments of synaptic weights with repeated input pulses, which is highly desirable for fast learning using simple neuron circuit operations that determine synaptic weight changes using only pulse counts. Furthermore, symmetric adjustment of synaptic weights for synaptic potentiation and depression is preferable because it allows the neuron circuit to generate voltage pulses with the same amplitude and duration (e.g., the same programming pulse scheme) but with opposite polarities for potentiation and depression.

[0014] FIG. 1 schematically illustrates a resistive processing unit (RPU) computing system including an array of nonvolatile resistive memory cells, which may be implemented using magnetic skyrmion resistive memory devices according to exemplary embodiments of the present disclosure. In particular, FIG. 1 schematically illustrates a neuromorphic computing system implemented using a crossbar array of resistive processing units. The computing system 100 comprises a two-dimensional (2D) crossbar array of RPU cells 110 arranged in a plurality of rows R1, R2, R3, ..., Rm and a plurality of columns C1, C2, C3, ..., Cn. The RPU cells 110 in each row R1, R2, R3, ..., Rm are typically connected to respective row control lines RL1, RL2, RL3, ..., RLm (collectively referred to as row control lines RL). The RPU cells 110 in each column C1, C2, C3, ..., Cn are typically connected to respective column control lines CL1, CL2, CL3, ..., CLn (collectively referred to as column control lines CL). Each RPU cell 110 is connected at (and between) the intersections (or crossing points) of respective row and column lines. In one exemplary embodiment, RPU system 100 comprises a 4,096 by 4,096 array of RPU cells 110.

[0015] Computing system 100 further includes peripheral circuitry 120 connected to row control lines RL1, RL2, RL3, ..., RLm, and peripheral circuitry 130 connected to column control lines CL1, CL2, CL3, ..., CLn. Peripheral circuitry 120 is further connected to a data input / output (I / O) interface block 125, and peripheral circuitry 130 is connected to a data I / O interface block 135. Computing system 100 further includes control signal circuitry 140, which includes various types of circuit blocks, such as power circuits, clock circuits, bias circuits, and timing circuits, for providing power distribution signals, control signals, and clock signals to operate computing system 100.

[0016] In some embodiments, each RPU cell 110 of computing system 100 comprises a non-volatile resistive memory cell including an access transistor and a magnetic skyrmion resistive memory device that serves as the storage element of the non-volatile resistive memory cell. In some embodiments, RPU cell 110 is implemented using an exemplary non-volatile resistive memory cell framework, as described in further detail below in conjunction with FIG. 3. Furthermore, in some embodiments, RPU cell 110 is implemented with a magnetic skyrmion resistive memory device having one of the exemplary embodiments of a magnetic skyrmion resistive memory device framework, as shown generally in FIG. 4, 6, 7, 8, or 9, as described in further detail below.

[0017] In neuromorphic computing applications, RPU cells 110 comprise artificial synapses that provide weighted connections between pre-neurons and post-neurons. Multiple pre-neurons and post-neurons are connected via a 2D crossbar array of RPU cells 110, which, of course, represents a fully connected neural network. In some embodiments, computing system 100 is configured to perform DNN or CNN computations, and the conductance of each RPU cell 110 is represented by a matrix element, or weight W, that can be updated or accessed through operation of peripheral circuits 120 and 130. ij (where W ij(where σ denotes the weight value of the ith row and jth column in the array of RPU cells 110.) Typically, DNNs are trained using a simple stochastic gradient decent (SGD) method, in which an error gradient for each parameter is calculated using a backpropagation algorithm consisting of three iterative cycles: a forward cycle, a backward cycle, and a weight update cycle. Computing system 100 can be configured to perform all three cycles of the backpropagation process in parallel, potentially resulting in significant speedup for DNN training with low power and reduced computational resources. Computing system 100 can be configured to perform matrix-vector multiplication operations in parallel in the analog domain.

[0018] 1 as single lines for ease of illustration, it should be understood that each row and column control line may include two or more control lines connected to the RPU cells 110 in the respective row and column, depending on the implementation and specific architecture of the RPU cells 110. For example, in some embodiments, each row control line RL may include a single word line (WL) or a complementary pair of word lines for a given RPU cell 110, depending on the configuration of the RPU cell. Furthermore, each column control line CL may be composed of multiple control lines, including, for example, one or more source lines (SL) and one or more bit lines (BL).

[0019] Peripheral circuits 120 and 130 are connected to respective rows and columns in the 2D array of RPU cells 110 and comprise various circuit blocks configured to perform forward, backward, and weight update operations of the backpropagation process (for training a neural network), as well as vector-matrix multiplication functions, matrix-vector multiplication functions, and cross-product update operations to implement inference processes using the trained neural network. For example, in some embodiments, to support RPU cell read / sensing operations (e.g., reading the weight value of a given RPU cell 110), peripheral circuits 120 and 130 comprise pulse-width modulation (PWM) circuits and read pulse driver circuits that generate and apply PWM read pulses to RPU cells 110 in response to input vector values ​​(read input values) received during forward / reverse cycles.

[0020] More specifically, in some embodiments, peripheral circuits 120 and 130 include digital-to-analog (D / A) conversion circuitry configured to receive a digital input vector (applied to a row or column) and convert the digital input vector into an analog input vector value represented by an input voltage with a varying pulse width. In some embodiments, a time-encoding scheme is used where the input vector is represented by a fixed-amplitude Vin=1V pulse with an adjustable duration (e.g., the pulse duration is a multiple of 1 nanosecond and proportional to the value of the input vector). Input voltages applied to the rows (or columns) generate output vector values ​​represented by output currents, which are measured to read out the weights of RPU cells 110.

[0021] The peripheral circuits 120 and 130 receive the accumulated read current (I READ) and converts the integrated current to a digital value (read output value) for subsequent calculations. In particular, the currents generated by the RPU cells 110 are summed by column (or row), and this total current is integrated over a measurement time, tmeas, by current readout circuits in the peripheral circuits 120 and 130. The current readout circuits are comprised of a current integrator and an analog-to-digital (A / D) converter. In some embodiments, each current integrator is comprised of an operational amplifier that integrates the current output from a given column (or row) on a capacitor (or a differential current from a pair of RPU cells implementing negative and positive weights), and an analog-to-digital (A / D) converter that converts the integrated current (e.g., an analog value) to a digital value.

[0022] Additionally, the peripheral circuits 120 and 130 comprise voltage generators and driver circuits configured to generate programming voltages used during programming operations to adjust the conductance states of the magnetic skyrmion resistive memory devices implemented in the RPU cells. In some embodiments, the peripheral circuits 120 and 130 are configured to generate control signals and programming pulses on the word lines, bit lines, and source lines of the RPU system 100 to perform exemplary programming operations, as described in further detail below with reference to FIGS. 3, 4, and 5A.

[0023] The data I / O interfaces 125 and 135 are configured to interact with the digital processing cores, which are configured to handle input and output to the computing system 100 (neural cores) and route data between different RPU arrays. The data I / O interfaces 125 and 135 are configured to (i) receive external control signals and data from the digital processing cores and provide the received control signals and data to the peripheral circuits 120 and 130, and (ii) receive digital read output values ​​from the peripheral circuits 120 and 130 and send the digital read output values ​​to the digital processing cores for processing. In some embodiments, the digital processing cores implement nonlinear function circuits that calculate activation functions (e.g., sigmoid neuron functions, softmax, etc.) and other arithmetic operations on data provided to the next or previous layer of the neural network.

[0024] FIG. 2 schematically illustrates an exemplary configuration of an RPU system for performing in-memory computing operations, according to an exemplary embodiment of the present disclosure. In particular, FIG. 2 schematically illustrates an RPU computing system 200 comprised of a crossbar array of RPU cells 205 (or RPU array 205). In some embodiments, each RPU cell 210 in the RPU array 205 implements a magnetic skyrmion resistive memory device as the storage element of the RPU cell 210. In FIG. 2, each storage element of the RPU cell 210 is represented as a variable resistor with adjustable conductance G at the intersection of each row (R1, R2, ..., Rm) and column (C1, C2, ..., Cn). As shown in FIG. 2, the array of RPU cells 205 provides a matrix of conductance values ​​Gij that are mapped to weights, e.g., matrix values, of an artificial synaptic device, encoded by the conductance value Gij (where i represents the row index and j represents the column index) of each RPU cell 210.

[0025] 2 illustrates an exemplary configuration in which a multiplexer within the peripheral circuitry of computing system 200 operates to selectively connect line driver circuit 220 to row lines R1, R2, ..., Rn. Line driver circuit 220 is comprised of a plurality of digital-to-analog (DAC) circuit blocks 222-1, 222-2, ..., 222-m (collectively, DAC circuit blocks 222) connected to respective row lines R1, R2, ..., Rn. Additionally, a multiplexer within the peripheral circuitry of computing system 200 operates to selectively connect readout circuit 230 to column lines C1, C2, ..., Cn. Readout circuit 230 is comprised of a plurality of readout circuit blocks 230-1, 230-2, ..., 230-n connected to respective column lines C1, C2, ..., Cn. Each readout circuit block 230-1, 230-2, ..., 230-n is comprised of a respective current integrator circuit 232-1, 232-2, ..., 232-n and a respective analog-to-digital (ADC) circuit 234-1, 234-2, ..., 234-n. The current integrator circuit is comprised of a current integrator circuit block, each current integrator being comprised of an operational transconductance amplifier (OTA) that uses negative capacitive feedback to convert the input current (total column current) into an output voltage on the output node of the current integrator circuit, and each ADC circuit latches the output voltage produced at the output node of the respective current integrator circuit at the end of the integration period and quantizes this output voltage to generate a digital output signal.

[0026] Figure 2 shows how the matrix of weights (encoded by the conductance values ​​Gij) is fed into the digital input vector X = (x1, x2, …, x m ) and multiply it by the output vector Y=(y1, y2, …, y n , x 1 , x 2 , ..., x 3 ) of the input vector X. m are input to the respective DAC circuit blocks 222-1, 222-2, ..., 222-m, and are connected to the respective row lines R1, R2, ..., R m At the input to the analog voltages V1, V2, …, V mAnalog voltages V1, V2, ..., V m are the input vector elements x1, x2, ..., x m In some embodiments, DAC circuit blocks 222-1, 222-2, ..., 222-m each receive pulse-width modulated (PWM) read pulses V1, V2, ..., Vm applied to respective row lines R1, R2, ..., Rm. m The pulse width modulation circuit and the driver circuit are configured to generate

[0027] More specifically, in some embodiments, DAC circuit blocks 222-1, 222-2, ..., 222-m are configured to perform the digital-to-analog conversion process using a time encoding scheme in which an input vector is represented by fixed amplitude pulses (e.g., V = 1 V) of adjustable duration, where the pulse duration is a multiple of a pre-specified time period (e.g., 1 nanosecond) and is proportional to the value of the input vector. For example, suppose a digital input value of 0.5 can be represented by a 4 nanosecond voltage pulse, while a digital input value of 1 can be represented by an 80 nanosecond voltage pulse (e.g., a digital input value of 1 can be represented by an 80 nanosecond voltage pulse) ... meas (The resulting analog input voltages V1, V2, …, V can be encoded into analog voltage pulses with pulse durations equal to V1, V2, …, V2, as shown in Figure 2.) m (eg, PWM pulses) are applied to the array of RPU cells 205 via row lines R1, R2, . . . , Rm.

[0028] To perform matrix-vector multiplication, analog input voltages V1, V2, ..., Vm are applied to row lines R1, R2, ..., Rm, and corresponding read currents I are generated by each RPU cell 210. READ =V i ×G ij (based on Ohm's law) is generated, where V idenotes the analog input voltage applied to a given RPU cell 210 on a given row i, and Gij denotes the conductance value of a given RPU cell 210 (at a given row i and column j). As shown in FIG. 2, the read currents generated by the RPU cells 210 in each column j are summed together (based on Kirchhoff's current law) to produce respective currents I1, I2, ..., I at the output of each column C1, C2, ..., Cn. n In this way, the resulting column currents I1, I2, ..., I n indicates the result of a matrix vector multiplication operation.

[0029] The total read current I1, I2, ..., I obtained at the output of each column C1, C2, ..., Cn n are input to the respective read circuit blocks 230-1, 230-2, ..., 230-n of the read circuit 230. The total read currents I1, I2, ..., I n to generate respective output voltages, which are quantized by respective ADC circuits 234-1, 234-2, ..., 234-n to generate respective digital output signals y1, y2, ..., y3 of the resulting output vector Y (representing the result of the matrix-vector multiplication operation). n Generate.

[0030] 3 is a schematic diagram of an analog resistive memory cell implementing a magnetic skyrmion resistive memory device according to an exemplary embodiment of the present disclosure. In particular, FIG. 3 is a schematic diagram of a nonvolatile analog resistive memory cell 300 comprising an access transistor 310 and a magnetic skyrmion resistive memory device 320 (or magnetic skyrmion memristor device). The memory cell 300 is configured with a 1T-1R architecture, in which the transistor 310 operates as a select transistor for the memory cell 300, and the magnetic skyrmion resistive memory device 320 operates as a storage element for the memory cell 300. In some embodiments, the resistive memory device 320 includes a two-terminal programmable resistive memory element having a magnetic layer, wherein the resistive memory device 320 is programmable to have one of a plurality of different conductivity states, wherein the number n of conductance states is 4 or more (e.g., n≧4), or more preferably 100 or more conductance states, e.g., n≧100, and the number n can be adjusted by increasing or decreasing the number of magnetic skyrmions present in the magnetic layer.

[0031] As shown in FIG. 3 , the access transistor 310 (alternatively referred to herein as the select transistor 310) comprises a gate G terminal, a drain D terminal, and a source S terminal. The gate G terminal is coupled to a word line WL, the source S terminal is coupled to a source line SL, and the drain D terminal is coupled to a first terminal of the resistive memory device 320. The resistive memory device 320 has a second terminal coupled to a bit line BL. In this regard, the resistive memory device 320 is connected between the bit line BL and the drain D terminal of the access transistor 310. The memory cell 300 can be implemented as an RPU cell of the computing system 100 ( FIG. 1 ), for example, to implement an artificial neural network or a neuromorphic computing system. The resistive memory device 320 is configured to have an adjustable conductance state (or adjustable resistance state), which can be programmably adjusted within a range of different conductance levels to adjust the weight of the non-volatile analog resistive memory cell 300.

[0032] FIG. 4 schematically illustrates a magnetic skyrmion resistive memory device 400 according to an exemplary embodiment of the present disclosure. In some embodiments, FIG. 4 illustrates an exemplary embodiment of a resistive memory device 320 that can be implemented in the nonvolatile analog resistive memory cell 300 of FIG. 3. As shown schematically in FIG. 4, the magnetic skyrmion resistive memory device 400 includes a first electrode 402, a second electrode 404, and a magnetic tunnel junction (MTJ) structure 410 disposed between the first electrode 402 and the second electrode 404. The MTJ structure 410 includes a fixed magnetic layer 420, a tunnel barrier layer 430, and a free magnetic layer 440.

[0033] According to exemplary embodiments of the present disclosure, the free magnetic layer 440 is composed of at least one magnetic layer including a magnetic material capable of hosting a topological spin texture, such as a skyrmion, that is stable at room temperature and the operating temperature of the resistive memory device. In this context, a topological spin texture-hosting magnetic layer (e.g., a skyrmion-hosting magnetic layer) refers to a magnetic layer having a magnetic material that allows a stable topological spin texture (e.g., a magnetic skyrmion) to be realized (e.g., created, realized, existed, etc.) within the magnetic layer, e.g., due to the crystalline structure and magnetic properties of the magnetic material that enable the formation of a stable topological spin texture.

[0034] More specifically, as is known in the art, magnetic moments (spins) within magnetic materials can form various structures known as spin textures. In typical magnetic materials, the spins of adjacent atoms tend to align parallel or antiparallel to each other, resulting in ferromagnets or antiferromagnets, respectively. However, in some magnetic materials, such as chiral magnetic materials, there are specific types of physical interactions between spins due to specific crystalline or multilayer structures in which the spins are aligned in a topological spin texture. Magnetic skyrmions are a common type of topological spin texture (topologically stable spin texture) that contain non-collinear structures of magnetic moments with small, swirling magnetic structures whose constituent spins point in all directions and wrap around the surface of a unit sphere; i.e., the spin pattern of the magnetic skyrmion can be projected onto the sphere and becomes a pattern that wraps around the entire surface of the sphere. The magnetic skyrmion topology arises from competing magnetic interactions between the conventional Heisenberg direct exchange interaction (e.g., ferromagnetic exchange interaction) and an antisymmetric exchange interaction, termed the Dzyaloshinskii-Moriya (DM) interaction (or DMI), which causes the magnetic moments of the spin structures to orient at 90° to each other.

[0035] In magnetic skyrmions, the spin orientation gradually rotates from an upward direction at the edge of the spin texture to a downward direction at the center of the spin texture, or vice versa. More specifically, in magnetic skyrmions, the magnetization curves within the spin structure and reaches its maximum along the out-of-plane direction at the core and periphery of the spin structure, with the spin direction in the core region of the magnetic skyrmion opposing that in the peripheral region of the magnetic skyrmion. Skyrmions stabilized by DMI are commonly referred to as Bloch skyrmions or Néel skyrmions. The properties of magnetic skyrmions can be characterized by their helicity, polarity, and topological charge. In particular, helicity is defined as the angle of the global rotation of the magnetic skyrmion around the z-axis. For Néel skyrmions, the helicity is considered to be zero. The polarity property defines the magnetization direction at the core of the magnetic skyrmion, e.g., whether the magnetization points in the positive (p = 1) or negative (p = -1) z-direction at the core of the magnetic skyrmion. Topological charge describes how many times the magnetic moment of the spin texture wraps around the unit sphere in the mapping, and can be -1 or +1. In Bloch and Néel skyrmion structures, the topological charge and polarity are equal (Q = p), but the difference in helicity distinguishes Bloch and Néel skyrmion structures from each other. On the other hand, magnetic textures stabilized by DM interactions can also have opposite topological charge and polarity (Q = -p), such as antiskyrmions.

[0036] In some embodiments, the free magnetic layer 440 is composed of a chiral magnetic layer capable of hosting stable topological spin textures, such as magnetic skyrmions. Chiral magnetic materials are magnetic materials capable of stabilizing non-collinear magnetic moment configurations with fixed chirality (handedness) through physical antisymmetric exchange interactions (DM interactions). Specifically, magnetic skyrmions can be generated and hosted within chiral magnetic materials that exhibit helical magnetism due to DM interactions. As discussed above, magnetic skyrmions are topological spin textures that arise in magnetic fields. They can exist in different structures, termed helical (Bloch-type) or hedgehog (Néel-type) structures, which are stabilized by DM interactions. Their topological nature, small size (e.g., 1 nm to 300 nm), and low energy consumption make them promising candidates for highly energy-efficient data storage, processing, and transmission devices, as well as other spintronic devices.

[0037] The MTJ structure 410 comprises a magnetoresistive memory element that utilizes the spin-transfer torque (STT) phenomenon to change the magnetoresistive state of the MTJ structure 410 using a spin current. The STT MTJ structure 410 utilizes tunneling magnetoresistance (TMR) to store information. The basic structure of the MTJ structure 410 includes two thin magnetic layers separated by a thin insulating layer through which electrons can tunnel. The STT phenomenon is realized in the MTJ structure 410 in which the free magnetic layer 440 has a non-fixed magnetization and the fixed magnetic layer 420 (or reference layer) has a fixed magnetization. The MTJ structure 410 stores information by switching the magnetization state of the free magnetic layer 440. When the magnetization direction of the free magnetic layer 440 is parallel to the magnetization direction of the fixed magnetic layer 420 (referred to as the parallel (P) state), the MTJ structure 410 is in a "low resistance" state. Conversely, when the magnetization direction of the free magnetic layer 440 is antiparallel to the magnetization direction of the fixed magnetic layer 420 (referred to as the antiparallel (AP) state), the MTJ structure 410 is in a "high resistance" state. The tunneling current is typically high when the magnetic moments of the two magnetic layers 420 and 440 are parallel and low when the magnetic moments of the two magnetic layers 420 and 440 are antiparallel.

[0038] The spin-transfer torque phenomenon uses a spin-polarized current to have the effect of changing the magnetic orientation of the free magnetic layer 440. As is known in the art, charge carriers (e.g., electrons) have a property known as "spin," which is a small amount of angular momentum inherent to the carrier. While current is generally nonpolar (composed of 50% spin-up electrons and 50% spin-down electrons), a spin-polarized current has more spin-up or spin-down electrons. A spin-polarized current can be generated by passing a current through the fixed magnetic layer 420. The spin-polarized current has the effect of changing the magnetic orientation of the free magnetic layer 440.

[0039] In accordance with exemplary embodiments of the present disclosure, passing a spin-polarized current through the free magnetic layer 440, which is composed of a chiral magnetic layer, induces the creation or annihilation of magnetic skyrmions in the chiral magnetic layer. In conventional STT-MTJ devices, due to the strong magnetic anisotropy of the free magnetic layer, current-induced switching of this free magnetic layer results in two stable magnetization states (AP or P). However, by utilizing a layer of chiral magnetic material in the free magnetic layer 440, it is possible to induce multiple skyrmion states in the free magnetic layer 440 using a spin-polarized spin current, thereby tuning the magnetoresistance of the MTJ structure 410 so that the magnetic skyrmion resistive memory device 400 can be effectively used as a resistive memory element for neuromorphic computing.

[0040] The various layers and structures of the magnetic skyrmion resistive memory device 400 can be formed of materials suitable for a given application. For example, in some embodiments, the first electrode 402 and the second electrode 404 are formed of a suitable conductive material(s), such as tantalum, tantalum nitride, ruthenium, titanium, or the like. Furthermore, in some embodiments, the pinned magnetic layer 420 is composed of a layer of a magnetic material, such as cobalt (Co), iron (Fe), boron (B), or any combination thereof. For example, the pinned magnetic layer 420 can be formed of CoFeB or CoFe. In some embodiments, the tunnel barrier layer 420 is formed of a non-magnetic insulating material, such as magnesium oxide (MgO), aluminum oxide (AlO), or titanium oxide (TiO), or any other suitable material.

[0041] The free magnetic layer 440 may have a multilayer structure or a single layer structure. For example, the free magnetic layer 440 may be a multilayer structure composed of a first heavy metal layer, a second heavy metal layer, and a chiral magnetic layer disposed between the first and second heavy metal layers. In some embodiments, the first and second heavy metal layers have opposing DMIs and cooperate to enhance the overall DMI of the MTJ structure. In other embodiments, the free magnetic layer 440 includes a single chiral magnetic layer, such as a single non-centrosymmetric magnetic layer with a relatively strong DMI, such as FeCoSi or FeGe. As known in the art, a non-centrosymmetric magnetic layer is composed of a magnetic material that does not have an inversion center in its crystal structure. The free magnetic layer 440 may be formed of any suitable non-centrosymmetric magnetic layer capable of spontaneously forming magnetic skyrmions. Other exemplary embodiments for implementing magnetic skyrmion resistive memory devices with a free magnetic layer composed of a multilayer structure or a single layer structure including a chiral magnetic layer are described in further detail below in conjunction with FIGS. 6, 7, 8, and 9.

[0042] 4 illustrates an exemplary embodiment of a multistate resistive memory device implementing a free magnetic layer configured to host a topological spin texture, such as a magnetic skyrmion, it being understood that the state of the resistive memory device is modulated using a programming current to create or annihilate the topological spin texture present in the free magnetic layer 440. For purposes of illustration, a skyrmion-based resistive memory device is described herein, but it is understood that the free magnetic layer 440 can be implemented using any suitable magnetic material that can be configured to host one of various types of stable topological spin textures suitable for modulating the magnetoresistance of the MTJ structure 410 of the resistive memory device 400.

[0043] FIG. 4 illustrates a bidirectional charge current I that can be generated to flow through the magnetic skyrmion resistive memory device 400 and to (i) generate magnetic skyrmions in the free magnetic layer 440 during an enhancement programming operation (increasing the resistance of the resistive memory device 400 to a targeted resistance state), and (ii) annihilate magnetic skyrmions present in the free magnetic layer 440 during a depression programming operation (decreasing the resistance of the resistive memory device 400 to a targeted resistance state). + and I - In some embodiments, assuming that the magnetic skyrmion resistive memory device 400 is implemented in the memory cell 300 of FIG. 3, the first (top) electrode 402 would be coupled to a bit line BL and the second (bottom) electrode 404 would be coupled to the drain D terminal of the access transistor 310.

[0044] In such a configuration, an exemplary boost programming operation may include, for example, (i) applying a ground (GND) voltage level (e.g., 0V) to the source line SL, (ii) applying a positive voltage level to the word line WL sufficient to maintain the access transistor 310 in an active state (in saturation mode) during the boost programming operation, and (iii) applying a sequence of one or more positive voltage pulses to the bit line BL, thereby causing a positive current flow I through the resistive memory device 400 from the first electrode 402 to the second electrode 404. + As noted above, in some exemplary configurations, a positive current flow I from the fixed magnetic layer 420 to the free magnetic layer 440 occurs. + This generates a spin current in the free magnetic layer 440, which causes magnetic skyrmions to be generated.

[0045] On the other hand, an exemplary inhibit programming operation may involve, for example, (i) applying a ground (GND) voltage level (e.g., 0V) to the bit line BL, (ii) applying a positive voltage level to the word line WL sufficient to maintain the access transistor 310 in an active state (in saturation mode) during the inhibit programming operation, and (iii) applying a sequence of one or more positive voltage pulses to the source line SL, causing a negative current flow I through the resistive memory device 400 from the second electrode 404 to the first electrode 402. - As noted above, in some exemplary configurations, a negative current flow I from the free magnetic layer 440 to the fixed magnetic layer 420 occurs. - This causes the annihilation of magnetic skyrmions in the free magnetic layer 440.

[0046] To read the state of the magnetic skyrmion resistive memory device 400, a read operation can be performed by grounding the source line SL, applying a positive voltage level to the word line WL to activate the access transistor 310, and applying a read voltage signal to the bit line BL. The read voltage signal has a sufficient magnitude and duration (pulse width) to generate a read current on the bit line BL, the magnitude of which corresponds to the conductance state of the magnetic skyrmion resistive memory device 400 (or, more specifically, the magnetoresistance state of the MTJ structure 410) and is used to determine the conductance state. The magnitude of the read current is small enough to read the conductance state of the magnetic skyrmion resistive memory device 400 without causing any change in the conductance state of the magnetic skyrmion resistive memory device 400.

[0047] 5A schematically illustrates enhancement and suppression programming operations for generating and annihilating magnetic skyrmions in a magnetic skyrmion resistive memory device according to an exemplary embodiment of the present disclosure. More specifically, FIG. 5A schematically illustrates the gradual switching of the magnetic polarization states of the exemplary MTJ structure 410 of the resistive memory device 400 of FIG. 4 during enhancement and suppression programming operations using identical programming pulse sequences. FIG. 5A schematically illustrates different magnetic polarization states 500-1, 500-2, and 500-3 of the MTJ structure 410 based on the number of magnetic skyrmions present in the free magnetic layer 440.

[0048] 5A schematically illustrates an initial magnetic polarization state 500-1 of an MTJ structure 410 in which the pinned magnetic layer 420 and the free magnetic layer 440 have perpendicular magnetic anisotropy (PMA), in which the magnetic polarization vector 422 of the pinned magnetic layer 420 and the magnetic polarization vector 442 of the free magnetic layer 440 are oriented perpendicular to the plane of the pinned magnetic layer 420 and the free magnetic layer 440. The initial magnetic polarization state 500-1 of the MTJ structure 410 is shown schematically as a parallel (P) state (low resistance state) in which the magnetic polarization vector 442 of the free magnetic layer 440 is oriented in the same direction as the magnetic polarization vector 422 of the pinned magnetic layer 420.

[0049] 5A also schematically illustrates additional magnetic polarization states 500-2 and 500-3 of the MTJ structure 410, which are achieved by changing the number of magnetic skyrmions 505 present in the free magnetic layer 440 as a result of performing enhancement or suppression programming operations to create or annihilate magnetic skyrmions in the free magnetic layer 440. For illustrative purposes, magnetic polarization state 500-2 of the MTJ structure 410 is schematically illustrated as a magnetic polarization state in which the free magnetic layer 440 has one magnetic skyrmion 505, and magnetic polarization state 500-3 of the MTJ structure 410 is schematically illustrated as a magnetic polarization state in which the free magnetic layer 440 has two magnetic skyrmions 505. Although not specifically illustrated in FIG. 5A , additional magnetic polarization states of the MTJ structure 410 can be achieved by increasing the number of magnetic skyrmions 505 in the free magnetic layer 440 (e.g., to three or more).

[0050] Compared to the initial magnetic polarization state 500-1, the magnetic polarization state 500-2 of the MTJ structure 410 has a larger magnetoresistance as a result of the presence of at least one magnetic skyrmion 505 in the free magnetic layer 440. Similarly, compared to the magnetic polarization state 500-2, the magnetic polarization state 500-3 of the MTJ structure 410 has a larger magnetoresistance as a result of the presence of at least two magnetic skyrmions 505 in the free magnetic layer 440. As discussed above, increasing the number of magnetic skyrmions 505 in the free magnetic layer 440 serves to increase the magnetoresistance of the MTJ structure 410, thereby enabling the MTJ structure 410 to be programmed to have multiple resistance / conductance states to implement a multi-valued resistive memory device.

[0051] 5A schematically illustrates an enhancement programming operation performed by applying an enhancement programming pulse 510 to induce the formation of magnetic skyrmions 505 in the free magnetic layer 440 as a result of a current flow in a first direction through the MTJ structure 410. In particular, FIG. 5A illustrates the enhancement programming operation performed by applying an enhancement programming pulse 510 to the bit line BL (FIG. 3) while the source line SL is grounded, as described above, thereby inducing a positive current flow I through the resistive memory device 400 from the first electrode 402 to the second electrode 404. + A sequence of charging current pulses of the same amplitude +V can be generated to produce PP 10 shows a sequence of identical boost pulses with pulse width W and pulse width W.

[0052] For illustrative purposes, FIG. 5A shows an exemplary enhancement programming operation in which the number of skyrmions 505 generated in the free magnetic layer 440 increases with an increasing number of enhancement programming pulses (i.e., an increasing pulse count (PC)). In particular, as shown in FIG. 5A, magnetic polarization state 500-2 of the MTJ structure 410 is achieved after applying two programming pulses (e.g., PC=2) (starting from the initial magnetic polarization state 500-1) to generate at least one magnetic skyrmion 505 in the free magnetic layer 440. Furthermore, magnetic polarization state 500-3 of the MTJ structure 410 is achieved after applying two additional enhancement programming pulses (e.g., PC=4) (starting from the magnetic polarization state 500-2) to increase the number of magnetic skyrmions 505 in the free magnetic layer 440. 5A , increasing the number of magnetic skyrmions 505 in the free magnetic layer 440 (e.g., three or more) can induce additional magnetic polarization states in the MTJ structure 410, thereby increasing the magnetoresistance of the resistive memory device 400. Eventually, after applying a sufficient number of enhancement pulses, the multiple magnetic skyrmions 505 in the free magnetic layer 440 can be forced to combine to achieve an AP state, resulting in an AP state in which the magnetic polarization vector of the free magnetic layer 440 is oriented in a direction opposite to that of the magnetic polarization vector 422 of the fixed magnetic layer 420.

[0053] 5A also schematically illustrates a suppress programming operation performed by applying a suppress programming pulse 520 to annihilate the magnetic skyrmions 505 in the free magnetic layer 440 as a result of current flow in a second direction (opposite to the first direction of current flow that results in the formation of magnetic skyrmions) through the MTJ structure 410. In particular, FIG. 5A illustrates the suppress programming operation performed by applying a suppress programming pulse 520 to the source line SL (FIG. 3) while the bit line BL is grounded, as described above, thereby causing a negative current flow I from the second electrode 404 to the first electrode 402 through the resistive memory device 400. - , which can generate a sequence of charging current pulses with the same amplitude +V DP and a sequence of identical suppression pulses with pulse width W.

[0054] 5A illustrates an exemplary inhibitory programming operation in which the number of skyrmions 505 annihilated from the free magnetic layer 440 increases with an increasing number of inhibitory programming pulses (i.e., an increasing pulse count (PC)). In particular, as illustrated in FIG. 5A, the magnetic polarization state 500-3 of the MTJ structure 410 is achieved after applying a given number n of inhibitory programming pulses (e.g., PC=n) (starting from another magnetic polarization state of the MTJ structure 410 with a higher magnetoresistance, not shown) to induce the annihilation of one or more magnetic skyrmions 505 in the free magnetic layer 440, resulting in the magnetic polarization state 500-3 in which the free magnetic layer 440 contains two magnetic skyrmions 505. Furthermore, magnetic polarization state 500-2 of MTJ structure 410 is achieved after applying two more negative programming pulses (e.g., PC=n+2) (starting from magnetic polarization state 500-3) to annihilate and reduce the number of magnetic skyrmions 505 in the free magnetic layer, resulting in magnetic polarization state 500-2 in which the free magnetic layer 440 contains one magnetic skyrmion 505. Further negative programming pulses can be applied to achieve initial magnetic polarization state 500-1.

[0055] FIG. 5A illustrates exemplary enhancement / depression programming schemes using identical programming pulses to achieve linear bidirectional conductance tuning of a magnetic skyrmion resistive memory device. For example, FIG. 5A illustrates a linear enhancement programming scheme in which the number of skyrmions generated is linear with increasing pulse count, e.g., one skyrmion generated for two enhancement pulses, and a linear depression programming scheme in which the number of skyrmions annihilated is linear with increasing pulse count, e.g., one skyrmion annihilated for two depression pulses. It should be understood that the enhancement and depression programming operations illustrated in FIG. 5A are merely illustrative examples of the principles of programming operations for tuning the resistance states of a magnetic skyrmion resistive memory device, and that the linearity in tuning the conductance of such a resistive memory device varies depending on various factors, including, but not limited to, the magnitude and pulse width of the enhancement and depression programming pulses, the structural and electrical properties of the various components of the magnetic skyrmion resistive memory device, the dynamic range (e.g., number) of the conductance states of the magnetic skyrmion resistive memory device, etc. In this regard, it should be appreciated that the magnitude and pulse width of the enhancement and suppression programming pulses can be optimized to achieve the desired conductance modulation behavior required for a given application.

[0056] While FIG. 5A generally depicts magnetic skyrmions 505 as arrows whose magnetic polarization points in the opposite direction to the PMA polarization 442 of the free magnetic layer 440, the magnetic skyrmions 505 formed in the free magnetic layer 440 can have topological structures and distributions as shown in FIGS. 5B and 5C. In particular, FIGS. 5B and 5C illustrate exemplary structures of magnetic skyrmions generated in a layer of magnetic material with perpendicular magnetic anisotropy, according to exemplary embodiments of the present disclosure. FIG. 5B illustrates multiple magnetic skyrmions 505 formed in the free magnetic layer 440 with a PMA magnetic polarization. The magnetic skyrmions 505 are shown schematically as topological spin textures formed in various regions of the PMA vector field 442 of the free magnetic layer 440. The magnetic skyrmions 505 have a repulsive magnetic force, which keeps them separated once formed and allows them to dynamically move over regions of the free magnetic layer 440 during programming operations.

[0057] Furthermore, FIG. 5C illustrates an exemplary texture of a magnetic skyrmion 505 having a Néel-type (or hedgehog) structure of the PMA magnetic layer 440. As shown in FIG. 5C, the core region 505-1 of the magnetic skyrmion 505 is composed of a magnetic polarization vector oriented in a direction opposite (i.e., antiparallel) to the direction of the magnetic polarization vector in the PMA magnetic field 442 (FIG. 5B) surrounding the periphery of the magnetic skyrmion 505 and the free magnetic layer 440. More specifically, as shown schematically in FIG. 5C, the spin orientation gradually rotates from an upward direction (e.g., positive z-direction) at the periphery of the magnetic skyrmion 505 to a downward direction (e.g., negative z-direction) at the core 505-1 of the magnetic skyrmion 505. In the exemplary embodiment, the magnetic skyrmion has negative polarity (p=−1) (the core spin points in the negative z-direction) and a topological charge of Q=−1.

[0058] 5B and 5C illustrate exemplary topological spin textures having particular magnetic skyrmion structures in a magnetic layer having a PMA. However, it should be understood that resistive memory devices according to other embodiments of the present disclosure can be implemented using other suitable types of topological spin textures, such as biskyrmions, antiskyrmions, merons, spiral spin textures, helical spin textures, conical spin textures, and other types of stable topological spin textures that can be hosted in a free magnetic layer having a PMA configuration or an in-plane magnetic configuration and that can be created / annihilated using, for example, STT techniques.

[0059] FIG. 6 schematically illustrates a magnetic skyrmion resistive memory device according to another exemplary embodiment of the present disclosure. In particular, FIG. 6 schematically illustrates the magnetic skyrmion resistive memory device 600, including a first electrode 602, a second electrode 604, and an MTJ structure 610 disposed between the first electrode 602 and the second electrode 604. The MTJ structure 610 includes a fixed magnetic layer 620, a tunnel barrier layer 630, and a free magnetic layer 640. The free magnetic layer 640 is a multilayer structure including a first heavy metal layer 642, a chiral magnetic layer 644, and a second heavy metal layer 646. In some embodiments, the first and second heavy metal layers have opposing DMIs and cooperate to overall enhance the DMI of the free magnetic layer 640 of the MTJ structure 610.

[0060] In some embodiments, the first electrode 602, the second electrode 604, the fixed magnetic layer 620, and the tunnel barrier layer 630 are formed of materials that are the same as or similar to the corresponding elements of the resistive memory device 400 ( FIG. 4 ), as described above. In some embodiments, the first heavy metal layer 642 comprises platinum, the chiral magnetic layer 644 comprises a cobalt-iron-boron alloy, and the second heavy metal layer 646 comprises tantalum. In some embodiments, the first heavy metal layer 642 comprises platinum, the chiral magnetic layer 644 comprises a cobalt-iron-boron alloy, and the second heavy metal layer 646 comprises iridium. In some embodiments, the first heavy metal layer 642 comprises platinum, the chiral magnetic layer 644 comprises iron, and the second heavy metal layer 646 comprises iridium.

[0061] FIG. 7 schematically illustrates a magnetic skyrmion resistive memory device according to another exemplary embodiment of the present disclosure. In particular, FIG. 7 schematically illustrates a magnetic skyrmion resistive memory device 700 including a first electrode 702, a second electrode 704, and an MTJ structure 710 disposed between the first electrode 702 and the second electrode 704. The MTJ structure 710 includes a fixed magnetic layer 720, a tunnel barrier layer 730, and a free magnetic layer 740 that is a single chiral magnetic layer. In some embodiments, the free magnetic layer 740 includes a single non-centrosymmetric chiral magnetic layer with sufficiently strong DMI to form a stable magnetic skyrmion without the need for an additional layer (e.g., a heavy metal layer). In some embodiments, the single non-centrosymmetric chiral magnetic layer includes a cobalt-iron-silicon alloy, an iron-germanium alloy, or the like.

[0062] FIG. 8 schematically illustrates a magnetic skyrmion resistive memory device according to another exemplary embodiment of the present disclosure. In particular, FIG. 8 schematically illustrates the magnetic skyrmion resistive memory device 800, including a first electrode 802, a second electrode 804, and an MTJ structure 810 disposed between the first electrode 802 and the second electrode 804. The MTJ structure 810 includes a first polarizer layer 820 (e.g., a first pinned magnetic layer), a first insulating layer 822 (e.g., a silicon oxide layer), a first tunnel barrier layer 830, a free magnetic layer 840, a second tunnel barrier layer 850, a second polarizer layer 860 (e.g., a second pinned magnetic layer), and a second insulating layer 862. The free magnetic layer 840 is a multilayer structure including a first heavy metal layer 842, a chiral magnetic layer 844, and a second heavy metal layer 846. As mentioned above, in some embodiments, the first heavy metal layer 842 and the second heavy metal layer 846 have opposing DMIs and cooperate to overall enhance the DMI of the free magnetic layer 840 of the MTJ structure 810.

[0063] The exemplary skyrmion resistive memory device 800 is composed of a free magnetic layer 840 disposed between two fixed magnetic layers (e.g., a first polarizer layer 820 and a second polarizer layer 860). The first polarizer layer 820 and the second polarizer layer 860 facilitate enhancement and repression programming by generating a spin-polarized current to modulate the magnetic polarization of the chiral magnetic layer 844 and induce the formation or annihilation of magnetic skyrmions in the chiral magnetic layer 844. For example, when a programming current flows through the resistive memory device 800 from the first electrode 802 to the second electrode 804 during an enhancement programming operation, the first polarizer layer 820 generates a spin-polarized current that induces the formation of magnetic skyrmions in the chiral magnetic layer 844. On the other hand, when a programming current flows through the resistive memory device 800 from the second electrode 804 to the first electrode 802 during an inhibitory programming operation, the second polarizer layer 860 serves to generate a spin-polarized current that induces the annihilation of magnetic skyrmions in the chiral magnetic layer 844.

[0064] In some embodiments, as shown in FIG. 8 , the first polarizer layer 820 and the second polarizer layer 860 each have a footprint area that is smaller than the footprint areas of the other layers of the MTJ structure 810. The small lateral size (footprint) of the first polarizer layer 820 and the second polarizer layer 860 serves to locally increase the current density near the central region of the MTJ structure 810 aligned with the polarizer layers 820 and 860. As the current density increases above the skyrmion-generating threshold current, magnetic skyrmions are locally generated in the central region of the chiral magnetic layer 844 of the MTJ structure 810. Because magnetic skyrmions have a repulsive force between themselves, when successive enhancement programming pulses generate other magnetic skyrmions in the central region of the chiral magnetic layer 844 during the enhancement programming operation, the magnetic skyrmions near and in the central region of the chiral magnetic layer 844 are repelled by the surrounding regions of the chiral magnetic layer 844.

[0065] Similarly, during a suppression programming operation, increasing the current density above the skyrmion annihilation threshold current causes localized annihilation of magnetic skyrmions in the central region of the chiral magnetic layer 844 of the MTJ structure 810. Because magnetic skyrmions have a repulsive force among themselves, once the magnetic skyrmions present near and in the central region of the chiral magnetic layer 844 are annihilated during the suppression programming operation, the magnetic skyrmions in the peripheral regions of the chiral magnetic layer 844 are repelled by the central region of the chiral magnetic layer 844 and can be annihilated by successive suppression programming pulses. This structural configuration helps provide better control over the number of magnetic skyrmions generated or annihilated during a programming operation, while also improving the current density for programming using a given absolute current amount.

[0066] FIG. 9 schematically illustrates a magnetic skyrmion resistive memory device according to another exemplary embodiment of the present disclosure. In particular, FIG. 9 schematically illustrates the magnetic skyrmion resistive memory device 900, including a first electrode 902, a second electrode 904, and an MTJ structure 910 disposed between the first electrode 902 and the second electrode 904. The MTJ structure 910 includes a first polarizer layer 920 (e.g., a first pinned layer), a first insulating layer 922 (e.g., a silicon oxide layer), a first tunnel barrier layer 930, a free magnetic layer 940, a second tunnel barrier layer 950, a second polarizer layer 960 (e.g., a second pinned layer), and a second insulating layer 962. The free magnetic layer 940 includes a single non-centrosymmetric chiral magnetic layer with sufficiently strong DMI to form stable magnetic skyrmions without the need for an additional layer (e.g., a heavy metal layer). In some embodiments, as discussed above, the single non-centrosymmetric chiral magnetic layer 940 comprises a cobalt-iron-silicon alloy, an iron-germanium alloy, or the like.

[0067] FIG. 9 illustrates an exemplary embodiment of a magnetic skyrmion resistive memory device 900 with a single chiral magnetic layer 940 disposed between pinned magnetic layers (e.g., a first polarizer layer 920 and a second polarizer layer 960). As in the exemplary embodiment of FIG. 8, the first polarizer layer 920 and the second polarizer layer 960 serve to generate a spin-polarized current to modulate the magnetic polarization of the chiral magnetic layer 940 and induce the formation or annihilation of magnetic skyrmions in the chiral magnetic layer 940, thereby facilitating enhancement and repression programming. Furthermore, similar to the exemplary embodiment of FIG. 8, the small footprints of the polarizer layers 920 and 960 serve to locally increase the current density near the central region of the MTJ structure 910 aligned with the regions of the first polarizer layer 920 and the second polarizer layer 960, thereby facilitating the creation and annihilation of magnetic skyrmions near the chiral magnetic layer 940 and in the central region of the MTJ structure 910.

[0068] It should be appreciated that exemplary resistive memory devices (e.g., skyrmion-based resistive memory devices) as described herein can be readily implemented as storage elements in an RPU array of nonvolatile resistive memory cells of an RPU system such that the conductance states (e.g., synaptic weights) of the RPU array can be bidirectionally linearly tuned. The bidirectional linear tuning characteristic of skyrmion-based resistive memory devices enables the implementation of RPU memory cells with a 1T-1R architecture, as shown in FIG. 3. For example, an RPU system implementing a skyrmion-based resistive memory device as described herein can be utilized to support various types of neuromorphic computing applications (e.g., machine learning applications, image classification applications, neural network training applications, artificial intelligence applications, etc.) or can otherwise provide support for hardware-accelerated computing in conjunction with a digital processing system (e.g., a von Neumann architecture-based processor) utilizing the RPU system to perform in-memory calculations such as matrix-vector operations, vector-vector multiplication operations, data or image classification operations, or other types of in-memory operations requiring multiply-accumulate (MAC) operations that can be performed in the analog domain by hardware-accelerated computing using the RPU system. In such cases, the computing system can be implemented by integrating a digital processing core with a neuromorphic computing system (e.g., an RPU system).

[0069] In this regard, exemplary embodiments of the present disclosure may be systems, methods, or computer program products, or combinations thereof, incorporating any conceivable level of technical detail. The computer program product may include computer-readable storage medium(s) having computer-readable program instructions therein for causing a processor to perform aspects of the present invention.

[0070] A computer-readable storage medium may be a tangible device capable of retaining and storing instructions for use by an instruction execution device. A computer-readable storage medium may be, for example, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of computer-readable storage media includes portable computer diskettes, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disk read-only memory (CD-ROM), digital versatile disk (DVD), memory stick, floppy disk, mechanical coding devices such as punch cards or raised structures in grooves having instructions recorded thereon, and any suitable combination of the foregoing. As used herein, a computer-readable storage medium should not itself be construed as a transitory signal such as an electric wave or other freely propagating electromagnetic wave, an electromagnetic wave propagating through a waveguide or other transmission medium (e.g., light pulses through fiber optic cable), or an electrical signal transmitted over an electrical wire.

[0071] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to each computing / processing device, or can be downloaded to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network, or a wireless network, or a combination thereof. The network can include copper transmission cables, fiber optic transmission cables, wireless transmission cables, routers, firewalls, switches, gateway computers, or edge servers, or a combination thereof. A network adapter card or network interface within each computing / processing device receives and forwards the computer-readable program instructions from the network to store the computer-readable program instructions on a computer-readable storage medium within the respective computing / processing device.

[0072] Computer-readable program instructions for carrying out operations of the present invention may be either source code or object code written in any combination of one or more programming languages, including assembler instructions, instruction set architecture (ISA) instructions, machine language instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, configuration data for integrated circuits, or object-oriented programming languages ​​such as Smalltalk®, C++, etc., and procedural programming languages ​​such as the "C" programming language or similar programming languages. The computer-readable program instructions may execute entirely on the user's computer, partially on the user's computer as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., through the Internet using an Internet Service Provider). In some embodiments, computer-readable program instructions may be executed by electronic circuitry, including, for example, programmable logic circuitry, a field programmable gate array (FPGA), or a programmable logic array (PLA), by utilizing state information of the computer-readable program instructions to individualize the electronic circuitry to implement aspects of the present invention.

[0073] Aspects of the present invention are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0074] These computer-readable program instructions may be provided to a processor of a computer or other programmable data processing apparatus to produce a machine, such that the instructions, executed by the processor of the computer or other programmable data processing apparatus, create means for implementing the functions / acts specified in one or more blocks of the flowcharts and / or block diagrams. These computer-readable program instructions may also be stored in a computer-readable storage medium, capable of directing a computer, programmable data processing apparatus, or other device, or combination thereof, to function in a particular manner, such that a computer-readable storage medium having instructions stored therein comprises an article of manufacture containing instructions that implement aspects of the functions / acts specified in one or more blocks of the flowcharts and / or block diagrams.

[0075] The computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device, causing the computer, other programmable apparatus, or other device to perform a series of operational steps to produce a computer-implemented process, such that the instructions, which execute on the computer, other programmable data processing apparatus, or other device, implement the functions / operations specified in one or more blocks of the flowcharts and / or block diagrams.

[0076] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of executable implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of instructions, including one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the blocks may occur out of the order noted in the figures. For example, two blocks shown in succession may actually be completed as a single step, may be executed simultaneously, may be executed substantially simultaneously with partial or full time overlap, or the blocks may be executed in the reverse order depending on the functionality involved. It should also be noted that each block in the block diagrams and / or flowchart diagrams, and combinations of blocks in the block diagrams and / or flowchart diagrams, may be implemented by a dedicated hardware-based system that performs the specified functions or operations or executes a combination of dedicated hardware and computer instructions.

[0077] These concepts are described with reference to Figure 10, which schematically illustrates an exemplary architecture of a computing node capable of hosting a system configured to execute neuromorphic computing applications utilizing a hardware-accelerated computing RPU system in accordance with an exemplary embodiment of the present disclosure. Figure 10 illustrates a computing node 1000 including a computer system / server 1012 that is operable with numerous other general-purpose or special-purpose computing system environments or configurations. Examples of well-known computing systems, environments, or configurations, or combinations thereof, that may be suitable for use with the computer system / server 1012 include, but are not limited to, personal computer systems, server computer systems, thin clients, thick clients, handheld or laptop devices, multiprocessor systems, microprocessor-based systems, set-top boxes, programmable consumer electronics, network PCs, minicomputer systems, mainframe computer systems, and distributed cloud computing environments that include any of the above systems or devices.

[0078] The computer system / server 1012 may be described in the general context of computer system-executable instructions, such as program modules, being executed by a computer system. Generally, program modules may include routines, programs, objects, components, logic, data structures, etc. that perform particular tasks or implement particular abstract data types. The computer system / server 1012 may also be executed in a distributed cloud computing environment where tasks are performed by remote processing devices linked through a communications network. In a distributed cloud computing environment, program modules may be located in both local and remote computer system storage media, including memory storage devices.

[0079] 10, computer system / server 1012 within computing node 1000 is shown in the form of a general-purpose computing device. Components of computer system / server 1012 may include, but are not limited to, one or more processors or processing units 1016, a system memory 1028, and a bus 1018 that couples various system components, including the system memory 1028, to the processor 1016.

[0080] Bus 1018 represents one or more of any of several types of bus structures, including a memory bus or memory controller, a peripheral bus, an accelerated graphics port, and a processor or local bus using any of a variety of bus architectures, including, by way of example and not limitation, an Industry Standard Architecture (ISA) bus, a Micro Channel Architecture (MCA) bus, an Enhanced ISA (EISA) bus, a Video Electronics Standards Association (VESA) local bus, and a Peripheral Component Interconnect (PCI) bus.

[0081] The computer system / server 1012 typically includes a variety of computer system-readable media, which can be any available media that can be accessed by the computer system / server 1012 and includes both volatile and nonvolatile media, removable and non-removable media.

[0082] The system memory 1028 may include computer-system-readable media in the form of volatile memory, such as random access memory (RAM) 1030 and / or cache memory 1032. The computer system / server 1012 may further include other removable / non-removable, volatile / non-volatile computer system storage media. By way of example only, a storage system 1034 may be provided for reading from and writing to non-removable, non-volatile magnetic media (not shown, typically referred to as a "hard drive"). Although not shown, a magnetic disk drive may be provided for reading from and writing to removable, non-volatile magnetic disks (e.g., "floppy disks"), and an optical disk drive may be provided for reading from and writing to removable, non-volatile optical disks, such as CD-ROMs, DVD-ROMs, or other optical media. In such cases, each may be connected to the bus 1018 by one or more data media interfaces. As illustrated and described herein, memory 1028 may include at least one program product having a set (e.g., at least one) of program modules configured to perform the functions of embodiments of the present invention.

[0083] A program / utility 1040 having a set (at least one) of program modules 1042 may be stored in memory 1028, as well as, by way of example and not limitation, an operating system, one or more application programs, other program modules, and program data. Each of the operating system, one or more application programs, other program modules, and program data, or some combination thereof, may include an implementation of a networking environment. The program modules 1042 generally perform the functions and / or methodologies of embodiments of the present disclosure as described herein.

[0084] The computer system / server 1012 may also communicate with one or more external devices 1014, such as a keyboard, pointing device, display 1024, one or more devices that allow a user to interact with the computer system / server 1012, or any device (e.g., a network card, modem, etc.) that allows the computer system / server 1012 to communicate with one or more other computing devices, or a combination thereof. Such communication may occur via an input / output (I / O) interface 1022. Furthermore, the computer system / server 1012 may communicate with one or more networks, such as a local area network (LAN), a general wide area network (WAN), or a public network (e.g., the Internet), or a combination thereof, via a network adapter 1020. As shown, the network adapter 1020 communicates with other components of the computer system / server 1012 via a bus 1018. Although not shown, it should be understood that other hardware and / or software components may be used in conjunction with the computer system / server 1012. Examples include, but are not limited to, microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, SSD drives, and data archival storage systems.

[0085] Additionally, while this disclosure includes detailed descriptions of cloud computing, it should be understood that implementation of the teachings set forth herein is not limited to cloud computing environments. Rather, embodiments of the present invention may be implemented in conjunction with any other type of computing environment now known or later developed. For example, cloud services such as neuromorphic computing as a service or artificial intelligence as a service (AIaaS) may implement an RPU system utilizing the exemplary skyrmion-based resistive memory devices described herein.

[0086] Cloud computing is a service delivery model that enables opportunistic, on-demand network access to a shared pool of configurable computing resources (e.g., networks, network bandwidth, servers, processing, memory, storage, applications, virtual machines, and services) that can be rapidly provisioned and released with minimal administrative effort or interaction with a service provider. This cloud model can include at least five characteristics, at least three service models, and at least four deployment models.

[0087] The features are as follows:

[0088] On-Demand Self-Service: Cloud customers can unilaterally provision computing capacity, such as server time and network storage, automatically as needed without the need for human intervention with the service provider.

[0089] Pervasive Network Access: Functionality is available over the network and accessed through standard mechanisms that facilitate use by heterogeneous thin or thick client platforms (e.g., mobile phones, laptops, and PDAs).

[0090] Resource Pooling: A provider's computing resources are pooled to serve multiple consumers using a multi-tenant model that dynamically re-allocates and re-configures different physical and virtual resources on demand. Consumers generally have a location-independent feel in that they have no control or knowledge of the exact location of the resources provided, although it may be possible to specify location at a higher level of abstraction (e.g., country, state, or data center).

[0091] Rapid Elasticity: Capabilities can be rapidly and elastically provisioned, sometimes automatically, to rapidly scale out, and rapidly released to rapidly scale in. To the consumer, the capabilities available for provisioning often appear unlimited, and any amount can be purchased at any time.

[0092] Service Metering: Cloud systems employ metering capabilities to automatically control and optimize resource usage at a level of abstraction appropriate to the type of service (e.g., storage, processing, bandwidth, and active user accounts). Resource usage can be monitored, controlled, and reported, providing transparency to both providers and consumers of utilized services.

[0093] The service model is as follows:

[0094] Software as a Service (SaaS): The functionality offered to the consumer is the use of the provider's applications running on a cloud infrastructure. The applications are accessible from a variety of client devices through a thin-client interface such as a web browser (e.g., web-based email). The consumer does not manage or control the underlying cloud infrastructure, including the network, servers, operating systems, storage, or even individual application features, with the possible exception of limited user-specific application configuration settings.

[0095] Platform as a Service (PaaS): The capability offered to a customer is to deploy applications they create or acquire, written using programming languages ​​and tools supported by the provider, onto a cloud infrastructure. The customer does not manage or control the underlying cloud infrastructure, including the network, servers, operating systems, or storage, but does have control over the deployed applications and, in some cases, the application hosting environment configuration.

[0096] Infrastructure as a Service (laaS): The capability provided to the customer is to provision processing, storage, network, and other basic computing resources, upon which the customer can deploy and run any software, which may include operating systems and applications. The customer does not manage or control the underlying cloud infrastructure, but has control over the operating system, storage, deployed applications, and possibly limited control over selected network components (e.g., host firewalls).

[0097] The deployment model is as follows:

[0098] Private Cloud: This cloud infrastructure is operated solely for one organization. A private cloud may be managed by the organization or a third party and may exist on-premises or off-premises.

[0099] Community Cloud: This cloud infrastructure is shared by multiple organizations to support a specific community with shared concerns (e.g., mission, security requirements, policy, and compliance considerations). Community clouds may be managed by the organization or a third party and may exist on-premises or off-premises.

[0100] Public Cloud: This cloud infrastructure is available for use by the general public or large industry organizations and is owned by an organization that sells cloud services.

[0101] Hybrid Cloud: This cloud infrastructure is a composite of two or more clouds (private, community, or public) that maintain distinct entities but are bound together by standardized or proprietary technologies that allow for data and application portability (e.g., cloud bursting to balance load between clouds).

[0102] A cloud computing environment is a service-oriented environment with an emphasis on statelessness, loose coupling, modularity, and semantic interoperability. At the heart of cloud computing is an infrastructure that includes a network of interconnected nodes.

[0103] Referring now to FIG. 11 , an exemplary cloud computing environment 1100 is illustrated. As shown, the cloud computing environment 1100 includes one or more cloud computing nodes 1150, which enable communication between local computing devices used by cloud users, such as, for example, a personal digital assistant (PDA) or cellular phone 1154A, a desktop computer 1154B, a laptop computer 1154C, or an in-vehicle computer system 1154N, or combinations thereof. The nodes 1150 can communicate with each other. They may be physically or virtually organized into one or more networks (not shown), such as a private cloud, a community cloud, a public cloud, or a hybrid cloud, as described above, or combinations thereof. This enables the cloud computing environment 1100 to provide infrastructure, platform, and / or software as a service without requiring cloud users to maintain resources on their local computing devices. It will be understood that the types of computing devices 1154A-N shown in FIG. 11 are intended to be merely exemplary, and that the computing node 1150 and cloud computing environment 1100 can communicate with any type of computerized device over any type of network and / or network-addressable connection (e.g., using a web browser).

[0104] Referring now to Figure 12, a set of functional abstraction layers provided by cloud computing environment 1100 (Figure 11) is shown. It should be understood in advance that the components, layers, and functions shown in Figure 12 are intended to be merely exemplary, and embodiments of the present invention are not limited thereto. As shown, the following layers and corresponding functions are provided:

[0105] Hardware and software layer 1260 includes hardware and software components. Examples of hardware components include mainframe 1261, RISC (reduced instruction set computer) architecture-based server 1262, server 1263, blade server 1264, storage device 1265, and network and network components 1266. In some embodiments, software components include network application server software 1267 and database software 1268.

[0106] The virtualization layer 1270 provides an abstraction layer that can provide the following example virtual entities: virtual servers 1271, virtual storage 1272, virtual networks including virtual private networks 1273, virtual applications and virtual operating systems 1274, and virtual clients 1275.

[0107] In one embodiment, management layer 1280 may provide the functions described below. Resource provisioning 1281 provides dynamic procurement of computing and other resources used to execute tasks within the cloud computing environment. Metering and pricing 1282 provides cost tracking associated with the use of resources within the cloud computing environment and billing or invoicing for the consumption of these resources. In one embodiment, these resources may include application software licenses. Security provides identity verification for cloud users and tasks, as well as protection of data and other resources. User portal 1283 provides users and system administrators with access to the cloud computing environment. Service level management 1284 provides allocation and management of cloud computing resources to meet required service levels. Service level agreement (SLA) planning and fulfillment 1285 provides pre-allocation and procurement of cloud computing resources to anticipate future requirements in accordance with SLAs.

[0108] The workload layer 1290 provides examples of functionality for which a cloud computing environment may be used. Examples of workloads and functions that may be provided from this layer include mapping and navigation 1291, software development and lifecycle management 1292, virtual classroom education delivery 1293, data analytics processing 1294, transaction processing 1295, and various functions 1296 for supporting neuromorphic computing applications, including, but not limited to, machine learning applications, image classification applications, neural network training applications, artificial intelligence applications, etc., or otherwise providing support for hardware-accelerated computing using, for example, an RPU system composed of an array of non-volatile resistive memory cells implementing skyrmion-based resistive memory devices, according to exemplary embodiments of the present disclosure as described herein. Furthermore, in some embodiments, the hardware and software layer 1260 includes the computing systems 100 and 200 of FIGS. 1 and 2 for implementing or otherwise supporting various workloads and functions 1296 for performing such hardware-accelerated computing and analog in-memory computations.

[0109] Descriptions of various embodiments of the present disclosure have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the disclosed embodiments. Numerous modifications and variations will be apparent to those skilled in the art without departing from the scope of the described embodiments. The terms used herein have been selected to best explain the principles of the embodiments, practical applications or technical improvements to technology found in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. 1. A resistive memory device comprising: A device comprising a magnetic tunnel junction structure including a free magnetic layer, the free magnetic layer hosting a plurality of topological spin textures that are induced in response to programming pulses applied to the resistive memory device, the device comprising a magnetic material configurable to adjust the conductance state of the resistive memory device by increasing or decreasing the number of the topological spin textures present in the free magnetic layer.

2. The magnetic tunnel junction structure is a first pinned magnetic layer; a non-magnetic layer of an insulating material disposed between the first pinned magnetic layer and the free magnetic layer; The device of claim 1 , wherein the first pinned magnetic layer and the free magnetic layer have perpendicular magnetic anisotropy.

3. The device of claim 2 , wherein the magnetic tunnel junction structure further includes a second pinned magnetic layer, and the free magnetic layer is disposed between the first pinned magnetic layer and the second pinned magnetic layer.

4. 1. A resistive memory device comprising: a first pinned magnetic layer; a second pinned magnetic layer; and a free magnetic layer disposed between the first pinned magnetic layer and the second pinned magnetic layer; wherein the free magnetic layer comprises a magnetic material configurable to host a topological spin texture to tune the conductance state of the resistive memory device; The device, wherein the first pinned magnetic layer and the second pinned magnetic layer each have a footprint area that is smaller than a footprint area of ​​the free magnetic layer.

5. 5. The device of claim 2, wherein the free magnetic layer comprises a multilayer structure, the multilayer structure comprising a first heavy metal layer, a second heavy metal layer, and a chiral magnetic layer disposed between the first heavy metal layer and the second heavy metal layer.

6. 6. The device of claim 5, wherein the first heavy metal layer comprises platinum, the chiral magnetic layer comprises a cobalt-iron-boron alloy, and the second heavy metal layer comprises tantalum.

7. 1. A resistive memory device comprising: a magnetic tunnel junction structure including a free magnetic layer, the free magnetic layer comprising a magnetic material configurable to host a topological spin texture to tune a conductance state of the resistive memory device; the free magnetic layer includes a multilayer structure, the multilayer structure including a first heavy metal layer, a second heavy metal layer, and a chiral magnetic layer disposed between the first heavy metal layer and the second heavy metal layer; A device wherein the first heavy metal layer comprises platinum, the chiral magnetic layer comprises a cobalt-iron-boron alloy, and the second heavy metal layer comprises iridium.

8. 1. A resistive memory device comprising: a magnetic tunnel junction structure including a free magnetic layer, the free magnetic layer comprising a magnetic material configurable to host a topological spin texture to tune a conductance state of the resistive memory device; the free magnetic layer includes a multilayer structure, the multilayer structure including a first heavy metal layer, a second heavy metal layer, and a chiral magnetic layer disposed between the first heavy metal layer and the second heavy metal layer; The device, wherein the first heavy metal layer comprises platinum, the chiral magnetic layer comprises iron, and the second heavy metal layer comprises iridium.

9. The device of claim 1 or 4, wherein the free magnetic layer comprises a single non-centrosymmetric chiral magnetic layer.

10. 10. The device of claim 9, wherein the single non-centrosymmetric chiral magnetic layer comprises one of a cobalt-iron-silicon alloy and an iron-germanium alloy.

11. 9. The device of claim 1, 4, 7, or 8, wherein the topological spin texture comprises skyrmions.

12. 1. A device comprising an array of nonvolatile resistive memory cells, wherein at least one nonvolatile resistive memory cell comprises a resistive memory device, the resistive memory device comprising a magnetic tunnel junction structure including a free magnetic layer, the free magnetic layer hosting a plurality of topological spin textures induced in response to programming pulses applied to the resistive memory device, the free magnetic layer comprising a magnetic material configurable to adjust the conductance state of the resistive memory device by increasing or decreasing the number of the topological spin textures present in the free magnetic layer.

13. the magnetic tunnel junction structure of the resistive memory device comprising: a pinned magnetic layer; a non-magnetic layer of an insulating material disposed between the pinned magnetic layer and the free magnetic layer; The device of claim 12 , wherein the pinned and free magnetic layers have perpendicular magnetic anisotropy.

14. 13. The device of claim 12, wherein the free magnetic layer comprises a multilayer structure, the multilayer structure comprising a first heavy metal layer, a second heavy metal layer, and a chiral magnetic layer disposed between the first heavy metal layer and the second heavy metal layer.

15. The device of claim 12 , wherein the free magnetic layer comprises a single non-centrosymmetric chiral magnetic layer.

16. 16. The device of claim 12, wherein the device comprises a neuromorphic computing device, the array of non-volatile resistive memory cells comprises an array of artificial synaptic elements, and the at least one non-volatile resistive memory cell comprises a synaptic weight that is encodable by a conductance value of the resistive memory device of the at least one non-volatile resistive memory cell.

17. The device of claim 12 , wherein the topological spin texture comprises skyrmions.

18. Inducing a plurality of topological spin textures in a free magnetic layer of a magnetic tunnel junction structure; and tuning the conductance states of the resistive memory device by increasing or decreasing the number of the topological spin textures present in the free magnetic layer; applying one or more programming pulses to the resistive memory device, the free magnetic layer responding to the programming pulses to increase or decrease the number of the topological spin textures.

19. applying one or more programming pulses to the resistive memory device to configure one or more topological spin textures in the free magnetic layer to adjust the conductance state of the resistive memory device; applying one or more enhanced programming pulses to induce the formation of one or more topological spin textures in the free magnetic layer as a result of current flow in a first direction through the resistive memory device; applying one or more inhibiting programming pulses to cause annihilation of one or more topological spin textures present in the free magnetic layer as a result of current flow in a second direction through the resistive memory device opposite to the first direction; 20. The method of claim 18, comprising:

20. 20. The method of claim 18 or 19, wherein the topological spin texture comprises magnetic skyrmions and the free magnetic layer comprises a chiral magnetic layer.

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