GaN-on-Si epiwafer with strain-decoupled substack

Abstract

To provide a GaN-on-Si epi wafer suitable for manufacturing a group III-V nitride material-based photoelectronic device or an electronic device on an industrial scale and with high efficiency.SOLUTION: A GaN-on-Si epi wafer 100 comprises a substrate 102 including a substrate surface which is partially formed from silicon, and a self-organized template layer 110 is formed as a distortion separate layer. The self-organized template layer includes pits, and the pits have pit density of 1x107 cm-2 to 1x1011 cm-2. A distortion adjustment sub-stack 118 is disposed on the self-organized template layer and includes at least one GaN layer and at least one AlxGa1-xN intermediate layer (x≥0.5). The GaN layer has a thickness of 0.5 μm to 4.0 μm, the AlxGa1-xN intermediate layer has a thickness of 5 nm to 25 nm, and the GaN-on-Si epi wafer has a maximum warpage of 100 μm at room temperature.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to GaN-on-Si epi-wafers, particularly GaN-on-Si epi-wafers suitable for use in III-V nitride-based micro light-emitting diode (LED) technology and / or III-V nitride-based power electronics. Furthermore, the present invention relates to methods for manufacturing GaN-on-Si epi-wafers. The present invention further relates to micro LED structures, e.g., for use in displays. [Background technology]

[0002] III-V nitride compound semiconductors, such as GaN, InN, and AlN, are attracting interest for use in a variety of electronic and optoelectronic applications. To manufacture III-V nitride electronic and optoelectronic devices for commercial applications, III-V nitride active layers with high crystalline quality are often required. At the same time, the semiconductor industry is pursuing economic efficiency in terms of high die counts per wafer at high yields. Achieving this generally requires high uniformity in device performance. For example, III-V nitride microLED devices fabricated from large epitaxial wafers must have highly uniform emission wavelengths to achieve high yields.

[0003] Therefore, much development effort has been devoted to growing high crystalline quality III-V nitride layers on large diameter industry-standard silicon wafers, with the aim of integrating the superior electronic and optoelectronic functionality of III-V nitride materials into established Si processing technologies, for example in complementary metal-oxide semiconductor (CMOS) or bipolar CMOS (BiCMOS) manufacturing lines.

[0004] Patent Document 1 discloses a nitride semiconductor component comprising a substrate having a silicon surface, an aluminum-containing nitride nucleation layer on the silicon surface of the substrate, an aluminum-containing nitride buffer layer on the aluminum-containing nitride nucleation layer, a silicon nitride masking layer on the aluminum-containing nitride buffer layer, and a first gallium-containing nitride semiconductor layer on the silicon nitride masking layer. The first gallium-containing nitride semiconductor layer has a structure of coalesced crystallite growth islands. A layer plane at least 600 nm above the silicon nitride masking layer is at least 0.16 μm away from the silicon nitride masking layer. 2 The average surface area per crystal growth island is shown in Fig. 1. Adjacent to the first gallium-containing nitride semiconductor layer is an aluminum-containing nitride intermediate layer having a thickness in the range of 8 nm to 15 nm, and a stacked body formed by a second gallium-containing nitride semiconductor layer on the aluminum-containing nitride intermediate layer. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] International Publication No. 2007 / 096405 Summary of the Invention [Problem to be solved by the invention]

[0006] The present invention aims to provide a GaN-on-Si epitaxial wafer suitable for the efficient industrial-scale production of optoelectronic or electronic devices based on III-V nitride materials, and a method for producing such a GaN-on-Si epitaxial wafer. [Means for solving the problem]

[0007] According to the present invention, a GaN-on-Si epi-wafer is proposed, which comprises a layer stack along a stacking direction of the GaN-on-Si epi-wafer, including a substrate, a strain-decoupling sub-stack, and a strain-engineering sub-stack. The substrate has a lateral extent of 150 mm or more, preferably 150 mm to 450 mm, particularly 150 mm, 200 mm, or 300 mm, in at least one direction perpendicular to the stacking direction, and has a substrate surface facing along the stacking direction that is at least partially made of silicon. The strain-decoupling sub-stack is a self-assembling template layer disposed directly on the substrate, the self-assembling template layer containing pits, the pits having a size of 1x10 7 cm -2 ~1x10 11 cm -2 , preferably 1x10 8 cm -2 ~1x10 10 cm -2 , or 1x10 8 cm -2 ~3x10 9 cm -2 , especially 1x10 9 cm -2 ~3x10 9 cm -2 and a surface recovery layer comprising GaN disposed directly on the self-assembling template layer, the surface recovery layer having a substantially smooth surface pointing along the stacking direction. A strain-tuning substack is disposed on the surface recovery layer and comprises at least one GaN layer and at least one Al layer. x Ga 1-x The GaN layer has a thickness of 0.5 μm to 4.0 μm, preferably 0.5 μm to 2.0 μm, and the Al x Ga 1-x The N intermediate layer has a thickness of 5 nm to 25 nm, preferably 10 nm to 15 nm.

[0008] The proposed GaN-on-Si epi-wafer according to the present invention is characterized by a bow of at most 100 μm, preferably at most 50 μm, at room temperature.

[0009] The present invention recognizes that there is a steadily increasing demand for GaN-on-Si epi-wafers with large diameters greater than 150 mm, which allows for economical manufacturing and achieving high device yields in absolute and relative numbers. The present invention includes the recognition that achieving high manufacturing efficiency requires both high epi-wafer uniformity and extremely low room temperature bow. High uniformity is necessary to enable the epi-wafers to be fabricated into a large number of efficient electronic and optoelectronic devices with uniform electronic and optoelectronic properties. Extremely low room temperature epi-wafer bow is necessary to enable the application of standard processing techniques on the epi-wafers to fabricate electronic and optoelectronic devices on the epi-wafers.

[0010] The present invention further recognizes that epitaxial growth of III-V nitride layers on Si-containing substrates with high crystalline quality, excellent uniformity, and low warpage requires efficient strain accommodation due to the lattice mismatch between the Si crystal lattice and the III-V nitride crystal lattice. In particular, to obtain high crystalline quality III-V nitride layers deposited on Si-containing substrates, it is advantageous to grow the III-V nitride layers on a substantially strain-free surface. As used herein, "substantially strain-free" refers to the substantial absence of compressive or tensile strain in the respective layers. The advantage of growing III-V nitride layers on such a strain-free surface is that the substrate material does not induce strain in the III-V nitride layers, which can lead to relatively poor crystalline quality in the III-V nitride layers. However, poor crystalline quality generally translates to poor electronic and optoelectronic performance.

[0011] GaN-on-Si epitaxial wafers according to the present invention enable the epitaxial growth of high crystalline quality III-V nitride layers on large-diameter substrates, including Si, having diameters exceeding 150 mm. This is achieved in the present GaN-on-Si epitaxial wafers due to the controlled generation of strain within the layer stack as a result of specific interactions of the layers in the GaN-on-Si epitaxial wafer. In particular, the controlled generation of strain within the layer stack of the GaN-on-Si epitaxial wafer allows high crystalline quality III-V nitride layers to be deposited on a substantially strain-free, smooth surface.

[0012] These interactions include efficient decoupling of strain that normally results from the lattice mismatch between a Si-containing substrate and a III-V nitride layer deposited on the substrate. In particular, strain decoupling is achieved through the unique structure of the strain-decoupling substack, which comprises a self-assembled template layer disposed directly on the substrate and a surface recovery layer disposed directly on the self-assembled template layer.

[0013] The strain-detached substack is characterized by a self-assembled template layer with 1×10 pits distributed on the surface of the self-assembled template layer facing along the stacking direction, i.e., facing the surface recovery layer. 7 cm -2 ~1x10 11 cm -2The self-assembled template layer has a relatively high pit density. Although the self-assembled template layer is considered to have a relatively low crystalline quality due to the relatively high pit density, the pit density is quite high, and thus forms a self-assembled template for growing additional layers on the self-assembled template layer. During the fabrication of the self-assembled template layer, the pits are formed self-organized, since the positions at which the pits are formed are not predefined, for example, by a mask. That is, during the fabrication of the self-assembled template layer, the pits are formed at random positions favored by the growth conditions. In other words, the pits in the self-assembled template layer are formed self-organized without structural processing of the self-assembled template layer. Despite the self-assembled template layer having a high pit density and therefore a low crystalline quality, the self-assembled template layer is preferably a crystalline layer having a predominant crystalline structure, for example, a wurtzite structure, preferably wurtzite AlN.

[0014] The relatively high pit density in the self-assembled template layer contributes to efficient relaxation in the surface-recovered layer of strain resulting from lattice mismatch between the material of the self-assembled template layer and the material of the substrate. Efficient strain relaxation in the surface-recovered layer contributes to preventing strain propagation to the strain-tuned substack and providing a substantially strain-free, smooth surface for further growth of the strain-tuned substack and additional layers thereon (such as the active layer structure described in more detail below).

[0015] In particular, by growing a surface recovery layer on a self-assembled template layer having pits distributed on its surface, the surface recovery layer can be fabricated substantially without strain. This is achieved because the pits enable the initial pyramidal growth of the surface recovery layer, and pyramidal structures are formed between the pits on the surface of the self-assembled template layer. The pyramidal structures increase in volume at the side facets of the pyramidal shapes. This allows the pyramidal structures to grow on the pits and form the surface recovery layer. This initial growth of the pyramidal structures is referred to herein as the "pyramidal growth mode." The pyramidal growth mode has the special advantage that dislocations bend toward the side facets of the pyramidal shapes and stop propagating, or stop propagating along the stacking direction, resulting in a surface recovery layer with high crystal quality and no strain.

[0016] The surface recovery layer also has a substantially smooth surface facing along the stacking direction. The substantially smooth surface of the surface recovery layer is achieved, in particular, by changing the growth mode from the pyramidal growth mode to what is referred to herein as a "layer-by-layer growth mode." In the layer-by-layer growth mode, the surface recovery layer grows epitaxially along the stacking direction with a significantly reduced dislocation density. This provides a substantially smooth surface for growing the strain-tuning substack. The surface recovery layer has a relatively high crystalline quality at its smooth surface, with a reduced dislocation density, compared to, for example, the opposite surface forming the interface between the self-assembled template layer and the surface recovery layer. Therefore, the strain-tuning substack can be grown substantially strain-free on the substantially smooth surface with high crystalline quality.

[0017] When the surface recovery layer is grown on the self-assembled template layer, the material of the surface recovery layer can only cover the pits without filling them. Alternatively, when the surface recovery layer is grown on the self-assembled template layer, the material of the surface recovery layer can at least partially fill the pits and also cover them. Thus, after growing the surface recovery layer on the self-assembled template layer, the pits can either be at least partially filled with the material of the surface recovery layer or not filled with the material of the surface recovery layer.

[0018] Furthermore, the strain-tuning substack is disposed on a substantially smooth, strain-free base, allowing for particularly precise strain tuning with high uniformity in the strain-tuning substack. Thus, the presence of the self-assembled template layer and the surface recovery layer allows for the Al in the strain-tuning substack to be tuned with high uniformity. x Ga 1-x The ability of precise strain tuning by the N intermediate layer is further promoted. x Ga 1-x By using an N interlayer, it may be possible to compensate for the tensile strain with a compressive strain component in the GaN. Accurate and precisely controlled strain tuning allows for thick layer stacks and high crystalline quality GaN to be achieved.

[0019] An additional benefit of decoupling the strain-tuning substack from the strain normally induced by the substrate is that the curvature of the GaN-on-Si epitaxial wafer during fabrication can be more easily and precisely controlled. By precisely controlling the curvature of the GaN-on-Si epitaxial wafer during fabrication, particularly small bows of up to 100 μm at room temperature can be achieved, simultaneously achieving excellent emission wavelength uniformity when an active layer structure is added to the GaN-on-Si epitaxial wafer. Excellent emission wavelength uniformity of the active layer structure is achieved because controlling the curvature of the GaN-on-Si epitaxial wafer during fabrication ensures a uniform distribution of the surface temperature of the GaN-on-Si epitaxial wafer during fabrication while the active layer structure is being deposited on the GaN-on-Si epitaxial wafer. A uniform temperature distribution of the GaN-on-Si epitaxial wafer is advantageous for growing the active layer structure with uniform material distribution, which in turn is advantageous for excellent emission wavelength uniformity. For example, if the active layer structure comprises InGaN quantum wells, a uniform temperature distribution in the GaN-on-Si epi-wafer is advantageous for a uniform distribution of indium within the InGaN quantum wells.

[0020] As a result of the aforementioned interplay of layers in GaN-on-Si epi-wafers, the present GaN-on-Si epi-wafers provide a commercially attractive technology platform for a variety of applications in micro-LED technology and high-power electronics, where "epi-wafer" comprises a substrate and one or more layers epitaxially grown on the substrate.

[0021] The substrate itself does not necessarily have to be fabricated using epitaxy. The terms "wafer" and "substrate" are used interchangeably herein to refer to a semiconductor body having a surface usable for growing epitaxial layers thereon. While any suitable substrate, such as those described in various sections herein, can be used, the method of the present invention is particularly suited to fabricating GaN-on-Si epiwafers on silicon wafers with diameters of 150 mm or greater used in the semiconductor industry. Such wafers typically have a circular shape with one or more flat cut edge portions or notches to indicate the crystal orientation and doping of the surface and for alignment of the wafer during fabrication.

[0022] Thus, in the present GaN-on-Si epiwafer, pits extend from the interface between the self-assembling template layer and the surface recovery layer into the self-assembling template layer. Individual pits form recesses in the surface of the self-assembling template layer. The pits have a depth of at least 7 nm and can extend up to 50 nm or more into the self-assembling template layer. Some of the pits in the self-assembling template layer can extend completely through the self-assembling template layer along the thickness of the self-assembling template layer, i.e., from the interface between the self-assembling template layer and the surface recovery layer to the interface between the self-assembling template layer and the substrate. However, this may result from the growth parameter settings in a given individual reactor and does not form an essential feature of the present invention. The claimed method can include fabricating a self-assembling template layer having only pits that do not completely penetrate the self-assembling template layer to the substrate.

[0023] "Pit density" refers to the density of pits distributed on the surface or interface of a self-assembled template layer (especially when evaluating the density from cross-sectional images after growth). Pit density is defined as the number of pits present within a unit area of ​​a predefined surface.

[0024] "Bow" is the deviation of the center point of the midplane of an unclamped, free wafer from a reference plane, which is defined by the three corners of an equilateral triangle. Wafer bow can be measured in accordance with the "Test Method for Bow of Silicon Wafers" defined in standard ASTM F534-97.

[0025] "Room temperature" refers to the temperature in an everyday environment, and is generally in the range of 20°C to 30°C.

[0026] The smoothness of the surface of the surface recovery layer can be comparable to the smoothness of the substrate surface of the substrate. The smooth surface can be characterized, for example, by a reflectivity greater than 35%, for example, 35% to 50%, preferably 40% to 45%. The reflectivity can be measured, for example, using an in-situ monitoring method during MOCVD growth. The reflectivity can particularly refer to the ratio of reflected light to incident light. Additionally or alternatively, the smooth surface can be characterized by a surface roughness (e.g., root-mean-square roughness) of 1 nm or less, for example, 0.5 nm or less.

[0027] The Si-containing substrate may be a substrate composed entirely of Si. Alternatively, the Si-containing substrate may be a substrate having a Si crystal structure and / or a Si bulk lattice constant at least on the substrate surface facing along the stacking direction. For example, the Si-containing substrate may be a SiON substrate or an engineered substrate having a Si(111) substrate surface. Alternatively, the Si-containing substrate may be a silicon-on-insulator (SOI) substrate.

[0028] A preferred embodiment of the GaN-on-Si epitaxial wafer of the present invention will be described below.

[0029] Advantageously, strain decoupling of the strain-tuned substack from the substrate allows Al x Ga 1-x The N interlayer allows for reproducible strain tuning in the strain tuning substack during the fabrication of GaN-on-Si epiwafers. To achieve small bowing of GaN-on-Si epiwafers at room temperature, the Al x Ga 1-x The aluminum content in the N intermediate layer is preferably 50% or more. x Ga 1-x The thickness of the N intermediate layer is preferably 5 nm to 25 nm.

[0030] The substrate can have a thickness of at least 1 mm, preferably 1.2 mm to 1.6 mm. The use of a relatively thick substrate, especially a Si-containing substrate, can prevent plastic deformation of the Si-containing substrate during growth of the thick nitride layer stack, thereby achieving good crystalline quality of the GaN in the strain-tuned substack.

[0031] For example, a relatively thick GaN-on-Si epitaxial wafer can be thinned from the backside of the substrate to a SEMI-standard thickness for further use and acceptance by standard semiconductor processing lines. The "SEMI-standard thickness" is defined according to the standard wafer diameter: for 150 mm wafers, the SEMI-standard thickness is 675±20 μm or 625±15 μm; for 200 mm wafers, the SEMI-standard thickness is 725±20 μm; and for 300 mm wafers, the SEMI-standard thickness is 775±20 μm.

[0032] The GaN-on-Si epitaxial wafer preferably further comprises an active layer structure disposed on the strain-tuned substack. The active layer structure preferably comprises a multiple quantum well structure of a III-V nitride material, such as InGaN or GaN, configured to emit light under an applied operating voltage or optical excitation. Additionally or alternatively, the active layer structure may comprise a lasing structure configured to emit laser radiation. Additionally or alternatively, the active layer structure may comprise a transistor structure. The transistor structure may be a high electron mobility transistor (HEMT) structure. The transistor structure may be a vertical transistor structure, e.g., a vertical HEMT structure, in which layers are stacked along the stacking direction of the GaN-on-Si epitaxial wafer. Alternatively, the transistor structure may be a lateral transistor structure, e.g., a lateral HEMT structure, in which layers are arranged laterally parallel to the stacking direction of the GaN-on-Si epitaxial wafer. The GaN-on-Si epitaxial wafer having the active layer structure can be used to manufacture micro-LEDs. A multi-quantum well structure made of III-V nitride materials can include layers of p-doped III-V nitride material and n-doped III-V nitride material, and an active region containing several quantum wells that form a p-n junction. When an operating voltage is applied, electrons and holes recombine, emitting photons.

[0033] In particular, GaN-on-Si epitaxial wafers with active layer structures can be configured so that the multiple quantum well structures exhibit emission wavelength uniformity of ±3 nm or less, or ±1 nm or less, under application of an operating voltage or optical excitation, for example, with a UV laser. Emission wavelength uniformity of ±3 nm or less or ±1 nm or less can be achieved by precisely controlling the curvature of the GaN-on-Si epitaxial wafer during growth of the active layer structure to ensure uniform heat distribution across the surface of the GaN-on-Si epitaxial wafer.

[0034] Furthermore, the strain decoupling provided by the strain-decoupling substack allows the GaN in the strain-tuned substack of the GaN-on-Si epitaxial wafer to have relatively high crystal quality. Furthermore, efficient strain decoupling enables the GaN-on-Si epitaxial wafer to maintain a flat bow of up to 100 μm at room temperature even after thinning. Furthermore, despite the trade-off between epitaxial wafer flatness and high emission uniformity, strain decoupling and strain tuning contribute to achieving emission wavelength uniformity of ±3 nm or less, or ±1 nm or less. Wavelength uniformity of ±3 nm or less, or ±1 nm or less, refers to light emission from at least 80%, or even at least 90%, of the active layer structure of the GaN-on-Si epitaxial wafer. Based on GaN-on-Si epitaxial wafers with such active layer structures, microLEDs for use in display technology, for example, can be manufactured with high yields.

[0035] Thus, a particular advantage of the present GaN-on-Si epi-wafer is that, even after thinning, the GaN-on-Si epi-wafer has a maximum bow of 100 μm, e.g., less than 50 μm, at room temperature. Due to the high quality of the GaN in the strain-tuned substack and the maximum bow of 100 μm even after thinning of the GaN-on-Si epi-wafer, the present GaN-on-Si epi-wafer can be used to fabricate highly efficient micro-LEDs or high electron mobility transistors (HEMTs). Micro-LEDs fabricated from the present GaN-on-Si epi-wafer can have a relatively high external quantum efficiency (EQE) and a uniform emission wavelength, e.g., within ±1 nm.

[0036] The self-assembled template layer preferably has a thickness of 50 nm to 300 nm, preferably 100 nm to 200 nm. A thickness of 50 nm to 300 nm ensures sufficient strain decoupling between the Si-containing substrate and the strain-tuned substack so that the GaN in the strain-tuned substack has relatively high crystalline quality. Here, the term "high crystalline quality" refers to a dislocation density of 5x108 cm -2 This means that the pit density of the self-assembled template layer having a thickness of 50 nm to 300 nm is 1×10 or less on the template surface facing the stacking direction. 7 cm -2 ~1x10 11 cm -2 The self-assembling template layer can be fabricated using a method similar to that described above. In particular, a self-assembling template layer having a thickness of 50 nm to 300 nm is expected to be less susceptible to insufficient pit formation, for example, in terms of pit density and / or pit size. Preferably, the self-assembling template layer is an Al-containing nitride layer, more preferably an AlN layer. However, an Al-containing nitride self-assembling template layer can also contain additional elements adjacent to Al, such as additional group III elements, such as Ga. AlN is preferred because its columnar growth mode provides sufficient strain decoupling between the substrate and the strain-tuning substack. Another advantage of an AlN self-assembling template layer is that it prevents melt-back etching, i.e., a degrading chemical reaction between Ga and the Si substrate. However, if some melt-back etching is acceptable, the self-assembling template layer can also be an AlGaN layer.

[0037] The pits in the self-assembled template layer preferably have a pit size of 1 nm to 100 nm, preferably 10 nm to 50 nm, and particularly preferably 10 nm to 30 nm. The pit size refers to the lateral extent of the pit, for example, the opening in the template surface of the self-assembled template layer opposite the substrate, in the direction perpendicular to the stacking direction. To provide a self-assembled template containing pits that can be overgrown in a pyramidal growth mode, a pit size of 1 nm to 100 nm is preferred.

[0038] Pits in the self-assembled template layer may be formed, for example, due to columnar growth of the material of the self-assembled template layer (e.g., AlN). The columnar growth of the self-assembled template layer can be controlled by adjusting the growth conditions applied during the growth of the self-assembled template layer. It has been found that the columnar growth of the self-assembled template layer works particularly well when the self-assembled template layer is an Al-containing nitride layer, especially an AlN layer. This is because the surface mobility of Al atoms is relatively small compared to Ga atoms. Therefore, the presence of Al atoms in the self-assembled template layer, in particular, can influence the columnar growth of the self-assembled template layer and the 1x10 7 cm -2 ~1x10 11 cm -2 The columnar growth is self-organized without the involvement of structuring (e.g., masking), and therefore the pits are also formed in a self-organized manner during the columnar growth.

[0039] The pits in the self-assembled template layer preferably have an average pit distance between adjacent pits in the range of 200 nm to 2000 nm, preferably in the range of 200 nm to 1000 nm, e.g., 200 nm, 500 nm, 1000 nm, or 2000 nm. In particular, the pit distance between adjacent pits can be determined by measuring the distance from the center of one pit to the center of its directly adjacent pit. The average pit distance between adjacent pits can be calculated by determining the individual distances between adjacent pits and averaging the collected distances. An average pit distance between adjacent pits in the range of 200 nm to 2000 nm is preferred because it allows for a self-assembled template layer in which the pits can be overgrown by the epitaxially grown surface recovery layer.

[0040] During the fabrication of GaN-on-Si epiwafers, the pit density of the self-assembled template layer can be controlled as described below.

[0041] In some cases, a substrate having a Si-containing substrate surface facing along the stacking direction may be covered with a native oxide. Generally, the formation of the native oxide on the Si-containing substrate surface saturates after a certain time and reaches a uniform thickness. If the Si-containing substrate surface is covered with a native oxide, the Si-containing substrate surface can be first prepared by, if necessary, performing the following steps:

[0042] - providing a substrate having a Si-containing substrate surface facing the stacking direction, the substrate having a diameter of 150 mm or more, preferably 150 mm to 450 mm, the substrate surface being covered with a native oxide; - adapting at least one growth parameter in order to at least partially remove the native oxide.

[0043] The growth parameters that can be adapted to remove the native oxide can be the substrate temperature, reactor pressure, and / or reactor atmosphere. Furthermore, a time span can be selected to adapt the growth parameters to remove the native oxide. For example, the substrate temperature, reactor pressure, and / or atmosphere can be adjusted within a range in which the native oxide covering the Si-containing substrate surface is at least partially removed.

[0044] During oxide removal, the substrate exhibits concave bowing due to the temperature difference between the backside and frontside of the substrate, where the frontside is the substrate surface used to grow subsequent layers thereon. Thus, achieving a uniform temperature distribution at the frontside of the substrate may generally require more careful parameter adjustment, particularly when the substrate exhibits concave bowing during oxide removal.

[0045] The time and reactor conditions for oxide removal are preferably selected to substantially remove the native oxide. This can include complete removal of the native oxide. However, the native oxide may be only partially removed, with some of the previously covered surface still covered by the native oxide and other portions of the previously covered surface no longer covered by the native oxide. Only partially removing the native oxide can be advantageous because it avoids selecting a time for oxide removal that is too long, which would result in a rough Si-containing substrate surface due to etching of the substrate surface after oxide removal. A Si-containing substrate surface that is partially covered by the native oxide, i.e., incomplete oxide removal, can also be advantageous for the formation of pits in a subsequently grown self-assembled template layer.

[0046] Having a Si-containing substrate surface at least partially cleared of native oxide, a self-assembled template layer can be grown thereon, thereby controlling pit formation, for example, in the following manner.

[0047] Optionally, providing a wafer carrier for holding a wafer, the wafer carrier including a wafer carrier body having at least one carrier pocket for accommodating a wafer, the carrier pocket having a bottom surface and a support surface located a predefined vertical distance from the bottom surface, the support surface configured to support the wafer, the bottom surface having a convex shape or comprising a convex bottom surface portion that is curved upward when viewed in cross section.

[0048] Optionally, a substrate having a diameter of 150 mm or more, preferably 150 mm to 450 mm, is provided on a support surface of a carrier pocket of the wafer carrier, the substrate having a Si-containing substrate surface facing the stacking direction, the substrate surface being free of native oxide or only partially covered by native oxide.

[0049] - adapting at least one growth parameter for growing the self-assembled template layer;

[0050] As described above, the self-assembled template layer preferably includes a first sublayer that is an Al-containing layer (e.g., an Al layer). Therefore, to grow the self-assembled template layer, a gas containing the components of the self-assembled template layer is introduced into the reaction chamber through the gas inlet. Growth parameters that can be adjusted to grow the self-assembled template layer include the substrate temperature, reactor pressure, and reactor gas flow rate. In particular, growth parameters such as the substrate temperature and reactor pressure can be adjusted within a range that allows pits to form in the self-assembled template layer. The self-assembled template layer is preferably grown to a thickness of 50 nm to 300 nm, for example, 100 nm to 200 nm. Layer thicknesses of less than 50 nm may also be used.

[0051] By appropriately selecting growth parameters, the self-assembled template layer can be grown in a columnar mode, which may include the presence of portions on the substrate surface that prevent nucleation of the self-assembled template layer. The portions of the substrate surface that prevent nucleation of the self-assembled template layer may include remaining portions of an oxide layer and / or crystalline or other defects. Columnar growth is particularly efficient when using AlN for the self-assembled template layer. The present invention further recognizes that a relatively high substrate temperature is advantageous for forming pits as part of the crystalline self-assembled template layer. Furthermore, a relatively high substrate temperature is preferred because it allows the self-assembled template layer to grow as a crystalline layer. In contrast, prior art techniques generally attempt to grow AlN at low temperatures on Si-containing substrates.

[0052] The present invention further recognizes that pits can be used to form a self-assembling template for a layer (e.g., a surface recovery layer) grown on the self-assembling template layer. In the self-assembling template layer, one or more pits can extend from the template surface through the entire self-assembling template layer to the substrate surface of the substrate. The template surface of the self-assembling template layer thus provides a template similar to a mask whose holes can be overgrown. The pits are then covered by the overgrown subsequent layer. The pyramidal growth mode allows the subsequent surface recovery layer to be grown substantially strain-free, i.e., without compressive or tensile strain. Because the subsequent layer can be grown substantially strain-free, strain decoupling between the substrate and the strain-tuned substack can be achieved. Therefore, in the present GaN-on-Si epiwafer, it is preferable to have a relatively large number of pits, i.e., a relatively high pit density, in the self-assembling template layer to provide a self-assembling template. Therefore, having a self-assembling template layer with a relatively large number of pits eliminates the need for additional masking layers used in the prior art.

[0053] Advantageously, growing a surface recovery layer on a self-assembled template layer provides efficient strain decoupling between the substrate and the strain-tuning substack that follows the surface recovery layer along the stacking direction. The approach described herein contradicts the general prior art goal of improving the crystalline quality in a self-assembled template layer (e.g., an Al-containing layer) to achieve a subsequent III-V nitride layer with high crystalline quality.

[0054] In addition to the relatively high pit density, the self-assembled template layer of this GaN-on-Si epiwafer exhibits a pit density of 10 9 cm -2It is preferable that the total dislocation density is 10 or more. The total dislocation density is defined as the amount of all line defects at a specific interface in a crystalline solid. In the self-assembled template layer of the present GaN-on-Si epiwafer, the total dislocation density is 10 or more throughout the thickness of the self-assembled template layer. 9 cm -2 or more, i.e., the self-assembled template layer has a density of 10 9 cm -2 The self-assembled template layer has a total dislocation density of 10 9 cm -2 ~10 11 cm -2 Preferably, the self-assembled template layer has a total dislocation density of 1000 Å or less. The relatively high dislocation density in the self-assembled template layer contributes to strain decoupling between the strain-tuning substack and the substrate. As a result, at least partial decoupling can be achieved between the Si-containing substrate and the further layers of the GaN-on-Si epiwafer, particularly the GaN strain in the strain-tuning substack. Furthermore, some dislocations present in the self-assembled template layer may continue into the surface-recovered layer. In the surface-recovered layer, these dislocations may bend and / or disappear due to the formation of pyramidal structures during growth of the surface-recovered layer. This prevents these dislocations from propagating to the smooth surface of the surface-recovered layer, which forms the foundation for fabricating the strain-tuning substack.

[0055] In fabricating GaN-on-Si epiwafers, having a self-assembled template layer with relatively low crystalline quality, i.e., a high total dislocation density and preferably a high pit density, is in contrast to the general goal in the prior art, which attempts to grow a self-assembled template layer with the highest possible crystalline quality. Thus, having a self-assembled template layer with relatively low crystalline quality, such as that present in the GaN-on-Si epiwafers described herein, represents a paradigm shift.

[0056] Preferably, the self-assembled template layer contains at least 50%, at least 70%, or at least 90% of the linear defects with an angle between 0° and 20°, preferably substantially 0°, or between 0° and 2°, relative to the stacking direction. Having linear defects extending substantially in the same direction as the stacking direction enables efficient strain relaxation and, therefore, strain decoupling between the substrate and the strain-tuned substack. In particular, efficient strain relaxation is achieved because dislocations extending substantially parallel to the stacking direction penetrate into the surface-recovered layer. In the surface-recovered layer, these dislocations bend and / or annihilate, thereby reducing the dislocation density in the surface-recovered layer along the stacking direction. It is particularly preferred that the surface-recovered layer contain dislocations bending at an angle between 15° and 45° relative to the interface formed between the self-assembled template layer and the surface-recovered layer. Therefore, it is considered advantageous for the linear defects in the self-assembled template layer to extend along the stacking direction, which is in contrast to the commonly-targeted goal of improving the crystalline quality of the corresponding layer in state-of-the-art GaN-on-Si epitaxial wafers.

[0057] The strain-tuned substack consists of a single GaN layer and a single Al x Ga 1-x N intermediate layer only, and GaN layer or Al x Ga 1-x However, the strain-tuned substack can start with either the GaN layer or the AlN intermediate layer. x Ga 1-x N intermediate layer sequence, or Al x Ga 1-x It may be advantageous to include at least two repetitions of the N intermediate layer and GaN layer sequence (x≧0.5). Increasing the number of repetitions allows for more precise and individual control of the strain in the strain-tuning substack. For example, the Al present in the strain-tuning substack may be x Ga 1-xEach of the N intermediate layers can have different thicknesses and / or Al contents in order to ensure an efficient strain balance adjustment in the GaN layer of the strain adjustment sub-stack. Thereby, the crystal quality of the GaN layer of the strain adjustment sub-stack can be further improved. Furthermore, it can be expected that the crystal quality will be further improved each time. Thereby, the growth of the GaN layer of the strain adjustment sub-stack can be continued until it has sufficient crystal quality for a particular application. Also, further repetitions can be grown until the crystal quality of each repeated GaN layer no longer changes. Thereafter, the GaN-on-Si epiwafer can be thinned from the back side for further use down to the GaN layer of the GaN-on-Si epiwafer showing the required crystal quality.

[0058] The self-organizing template layer comprises a first sub-layer which is an AlN layer and a second sub-layer which is directly disposed on the first sub-layer and contains Al x Ga 1-x GaN (0 < x < 1). In particular, the self-organizing template layer can comprise a second sub-layer which is a Ga-containing nitride layer. However, the second sub-layer can also be an AlN layer, a GaN layer, or an AlGaN layer. By using the second sub-layer, a further improved separation between the substrate and the strain adjustment sub-stack can be achieved. In particular, by using the second sub-layer, it is possible to finely adjust the size and density of the pits generated in the self-organizing template layer. Thereby, the uniformity of the pits can be improved. As a result, an improved template surface for growing the surface recovery layer can be provided.

[0059] Thus, when present, the second sub-layer also has a density of 1x10 7 cm -2 ~1x10 11 cm -2 , preferably 1x10 8 cm -2 ~1x10 10 cm -2 or 1x10 8 cm-2 ~3x10 9 cm -2 , especially, 1x10 9 cm -2 ~3x10 9 cm -2 and / or an average pit distance between adjacent pits in the range of 200 nm to 2000 nm, preferably in the range of 200 nm to 1000 nm, e.g., 200 nm, 500 nm, 1000 nm, or 2000 nm, and / or a pit size of 1 nm to 100 nm, preferably 10 nm to 50 nm, particularly 10 nm to 30 nm. Thus, if present, the second sublayer provides a template surface for the self-assembled template layer on its surface opposite the substrate for growing the surface recovery layer. If present, the second sublayer is grown on the first sublayer, which already has pits, and the second sublayer itself provides a template surface for growing the surface recovery layer on top of it.

[0060] In particular, if the first sublayer is made of AlN, it may be advantageous to make the second sublayer of AlGaN because the lattice constant of AlGaN is close to that of the GaN in the surface recovery layer. Therefore, the second sublayer can be considered to act as a bridge between the lattice constant of the AlN in the first sublayer and the GaN in the surface recovery layer. This improves the crystal quality of the surface recovery layer, resulting in improved smoothness of the surface of the surface recovery layer oriented in the stacking direction.

[0061] The second sublayer may have a total thickness of 50 nm to 150 nm. The surface recovery layer may consist solely of GaN. However, the surface recovery layer may also contain other group III metals, such as Al or In, or may be a ternary or quaternary alloy. However, the lattice constant of the surface recovery layer preferably deviates by 5% or less, e.g., 3% or less, or 1% or less, from the lattice constant of bulk GaN, which is a = 3.189 Å and c = 5.178 Å at 300 K.

[0062] With regard to the above objectives directed to a method for manufacturing a GaN-on-Si epi-wafer, a method for manufacturing a GaN-on-Si epi-wafer is proposed, which includes the following steps:

[0063] - providing a wafer carrier for holding a wafer, the wafer carrier comprising a wafer carrier body having at least one carrier pocket for accommodating a wafer, the carrier pocket having a bottom surface and a support surface located at a predefined vertical distance from the bottom surface, the support surface being configured to support the wafer, the bottom surface having a convex shape or comprising an upwardly curved convex bottom surface portion when viewed in cross section; - placing a substrate having a diameter of 150 mm or more, preferably 150 mm to 450 mm, in at least one direction perpendicular to the stacking direction, in particular a diameter of 150 mm, 200 mm, 300 mm, 450 mm or 500 mm, and having a substrate surface facing along the stacking direction that is at least partly made of silicon, on a support surface of a carrier pocket of a wafer carrier; - Self-assembling template layer is 1x10 7 cm -2 ~1x10 11 cm -2 , preferably 1x10 8 cm -2 ~1x10 10 cm -2 , or 1x10 8 cm -2 ~3x10 9 cm -2 , especially 1x10 9 cm -2 ~3x10 9 cm -2 fabricating a strain-decoupled substack by directly epitaxially growing a self-assembled template layer on a substrate having pits at a pit density of 0.1 μm and directly epitaxially growing a surface recovery layer comprising GaN on the self-assembled template layer, such that the surface recovery layer has a substantially smooth surface facing along the stacking direction; - controlling the curvature of the GaN-on-Si epiwafer by epitaxially growing at least one strain-tuning substack on the surface recovery layer, the strain-tuning substack comprising at least one GaN layer and at least one Al layer; x Ga 1-x and an N intermediate layer (x≧0.5), the GaN layer having a thickness of 0.5 μm to 4.0 μm, preferably 0.5 μm to 2.0 μm, and an Al x Ga 1-x the N intermediate layer has a thickness of 5 nm to 25 nm, preferably 10 nm to 15 nm; - Allowing the GaN-on-Si epi-wafer to cool to room temperature.

[0064] The method according to the present invention can be used to produce the above-described GaN-on-Si epi-wafer according to the present invention.

[0065] The method according to the invention can be carried out using, for example, a molecular beam epitaxy (MBE) or metalorganic vapor phase epitaxy (MOVPE) apparatus, or any other suitable crystal growth apparatus, such as a chemical vapor deposition (CVD) apparatus.

[0066] The predefined vertical distance from the bottom surface to the support surface can be between 0.05 mm and 1 mm, for example between 1 mm and 0.25 mm.

[0067] The growth of the surface recovery layer can include different growth modes characterized by different growth parameter values, for example, applied pressure, gas flow ratio, and growth temperature. These growth modes can include pyramidal growth mode, layer-by-layer growth mode, and transient growth mode that occurs when changing growth parameters to change from pyramidal growth mode to layer-by-layer growth mode. However, the transient growth mode itself can be applied for a predefined time span, if necessary. However, the transient growth can be short, such that the growth of the surface recovery layer substantially includes only pyramidal growth mode and layer-by-layer growth mode.

[0068] Generally, it is preferable to first grow a surface recovery layer on the self-assembled template layer in a pyramidal growth mode. In this mode, pyramidal structures are formed on the template surface of the self-assembled template layer, and the pyramidal structures increase in size by growing on their side facets. This results in overgrowth of pits. In fact, the pit-containing self-assembled template layer particularly promotes the formation of pyramidal structures and growth on their side facets in the pyramidal growth mode. The formation of pyramidal structures can be promoted by dislocations in the GaN of the surface recovery layer propagating along the growth direction. This pyramidal growth causes dislocations to bend toward the side facets of the pyramidal structures and / or stop propagating along the stacking direction. In fact, in the pyramidal growth mode, dislocations can bend and annihilate when they encounter other existing dislocations. This allows the formation of a substantially smooth surface of the surface recovery layer that is substantially strain-free and aligned with the stacking direction.

[0069] The growth of the surface recovery layer involves pyramidal growth, but in the layer-by-layer growth mode, the surface recovery layer grows specifically along the stacking direction. A transitional growth mode can be applied between the pyramidal growth mode and the layer-by-layer growth mode for a specific time span. In the transitional growth mode, the surface recovery layer grows both horizontally and along the stacking direction, i.e., there are horizontal and vertical growth components. In the layer-by-layer growth mode, the surface recovery layer grows substantially along the stacking direction, thereby forming a substantially smooth surface of the surface recovery layer. When the pyramidal growth mode and the layer-by-layer growth mode are applied to fabricate the surface recovery layer, the surface recovery layer can be substantially strain-free. Therefore, a strain-tuned substack can be fabricated on the surface recovery layer that is decoupled from the strain induced by the substrate.

[0070] In this method, the curvature of the GaN-on-Si epiwafer can be controlled by, for example, adjusting the degree of strain decoupling of the strain-tuned substack from the Si-containing substrate by appropriately adapting growth parameters when growing the self-assembled template layer. In this method, it is particularly preferred that the curvature of the GaN-on-Si epiwafer substantially corresponds to the shape of the bottom surface, which is convex or has a convex bottom portion. This allows a substantially constant distance between the GaN-on-Si epiwafer and the bottom surface of the carrier pocket to be maintained during growth of the strain-tuned substack, and particularly during growth of the active layer structure grown on the strain-tuned substack. Establishing a substantially constant distance between the GaN-on-Si epiwafer and the bottom surface of the carrier pocket during growth of the strain-tuned substack, and particularly the active layer structure, is advantageous because it allows the strain-tuned substack and the active layer structure to be grown at a substantially uniform growth temperature along the GaN-on-Si epiwafer. This uniform growth temperature, in turn, can be advantageous for achieving uniform electronic and / or optoelectronic properties of the GaN-on-Si epiwafer.

[0071] The curvature of the GaN-on-Si epitaxial wafer is, for example, x Ga 1-x The amount of Al in the N intermediate layer and / or Al x Ga 1-x The thickness of the N intermediate layer can be adjusted to control the amount of tensile strain that is compensated for by the compressive strain component in the GaN, which in turn affects the curvature of the GaN-on-Si epitaxial wafer. Therefore, in this method, the curvature of the GaN-on-Si epitaxial wafer is controlled by strain tuning in the strain-tuning substack. To tune the strain, Al x Ga 1-x N The Al content of the intermediate layer, or Al x Ga 1-x The thickness of the N interlayer or the growth temperature can be adjusted. The Al content, thickness, or growth temperature can be adjusted by in-line process control. Also, the Al content of the strain-tuned substack can be adjusted by in-line process control. x Ga 1-x Before actually growing the N intermediate layer, the Al content or thickness or growth temperature can also be controlled as part of planned adjustments in the programmed process flow.

[0072] Therefore, in this method, controlling the curvature of the GaN-on-Si epiwafer can further include adjusting growth parameters, such as the Al content described above, to achieve a convex curvature in which the normal (i.e., vertical) distance between the bottom of the carrier pocket and the GaN-on-Si epiwafer is substantially constant across the wafer diameter. A substantially constant distance between the bottom of the carrier pocket and the GaN-on-Si epiwafer is preferably achieved at the growth temperature, particularly during growth of the active layer structure.

[0073] By controlling the curvature of the GaN-on-Si epitaxial wafer so that the distance to the bottom surface of the carrier pocket is substantially constant, the bowing of the GaN-on-Si epitaxial wafer, particularly during the growth of the active layer structure, can be substantially matched to the curvature of the bottom surface of the carrier pocket. This allows for a uniform temperature distribution to be established between the GaN-on-Si epitaxial wafer and the carrier pocket. This uniform temperature distribution has the advantage that the crystalline layers of the GaN-on-Si epitaxial wafer are grown under uniform growth conditions. Such uniform growth conditions are particularly desirable for the fabrication of the active layer structure, which is sensitive to temperature changes.

[0074] Furthermore, thermal stress within the GaN-on-Si epiwafer, which may be caused by temperature differences within the GaN-on-Si epiwafer, can be reduced. This allows the active layer structure to be grown on the strain-tuned sub-stack with a relatively uniform heat distribution between the bottom surface of the carrier pocket and the GaN-on-Si epiwafer. This has the advantage of allowing the active layer structure to be grown relatively uniformly. For example, if the active layer structure includes one or more InGaN quantum wells for light emission, the relatively uniform growth conditions, particularly in terms of heat distribution, allow for relatively uniform incorporation of In into the InGaN quantum wells. In particular, properly grown GaN-on-Si epiwafers are suitable for the fabrication of microLEDs with excellent emission wavelength uniformity of ±3 nm or less, or ±1 nm or less. The self-assembled template layer is preferably grown to have a first sub-layer that is an Al-containing layer. The strain-uncoupling layer can be formed solely by the first sub-layer. However, optionally, the method can further include growing an Al-containing layer on the first sub-layer before growing the surface recovery layer and the strain-uncoupling sub-stack on the strain-uncoupling layer. x Ga 1-xN, where 0≦x≦1, where the strain-decoupling layer comprises the first sublayer and the second sublayer. The use of the second sublayer can achieve further improved strain decoupling between the substrate and the strain-tuning substack. The use of the second sublayer can also improve the uniformity of pits produced by growing the self-assembled template layer.

[0075] When the second sublayer is grown as part of a self-assembling template layer, the method further preferably involves growing the second sublayer on top of the first sublayer along the stacking direction by using the pits in the first sublayer as a self-assembling template. The second sublayer itself contains pits with a pit density comparable to that of the first sublayer. In this case, the pits in the second sublayer can also be used as a self-assembling template for growing a surface recovery layer on top of the self-assembling template layer.

[0076] Preferably, in the method, after cooling to ambient room temperature, the GaN-on-Si epi-wafer has a bow of at most 100 μm at ambient room temperature. To achieve a bow of at most 100 μm at ambient room temperature, the GaN layer of the strain-tuned substack is doped with Al. x Ga 1-x It is advantageous to apply sufficient compressive strain by the N intermediate layer to compensate for the tensile strain. This is particularly true for AlN layers with a thickness of 5 nm to 25 nm. x Ga 1-x This is possible with an N intermediate layer (x≧0.5). For example, Al x Ga 1-xThe Al content and thickness of the N interlayer can be selected taking into account the thermal expansion mismatch between GaN and Si. For this purpose, it is particularly advantageous to consider the total thickness of the GaN layer and the substrate. For example, the GaN layer of the strain-tuned substack can be grown at a thickness that allows for strain balancing to compensate for thermal expansion during growth, achieving a high-crystal-quality GaN layer in the strain-tuned substack. Suitable thicknesses can range from 500 nm to several micrometers (e.g., 2 μm or 3 μm).

[0077] The method can further include thinning the GaN-on-Si epi-wafer, starting from the backside of the substrate, to a thickness specified by SEMI standards for a given wafer diameter. Thinning to a SEMI-standard thickness is particularly feasible because the strain-tuning substack is decoupled from substrate-induced strain due to lattice mismatch to the epilayers grown on top of the substrate. A particular advantage of decoupling is that even after thinning to a SEMI-standard thickness, bow of up to 100 μm can be maintained at ambient room temperature. As a result, the thinned GaN-on-Si epi-wafer, which can consist only of an active layer structure having a SEMI-standard thickness, is suitable for further processing, such as micro LEDs or transistors, in a standard semiconductor processing line.

[0078] Preferably, the method further comprises epitaxially growing an active layer structure on the strain-tuned substack at a predefined growth temperature, the active layer structure comprising a multiple quantum well structure of III-V nitride material and configured to emit light under an applied operating voltage or under optical excitation. An n-type doped GaN layer below the multiple quantum well structure is preferably grown on the strain-tuned substack, e.g., as part of the active layer structure.

[0079] As part of the method, microLED structures can be fabricated from a GaN-on-Si epitaxial wafer having an active layer structure. This can include thinning the GaN-on-Si epitaxial wafer, starting from the substrate, down to the n-type doped GaN layer beneath the multi-quantum well structure of III-V nitride materials. For example, the GaN-on-Si epitaxial wafer can be thinned to a SEMI standard thickness. Thinning can be performed while the GaN-on-Si epitaxial wafer is mounted on a mechanical support.

[0080] The present invention further relates to a micro LED structure comprising an active layer structure including a multiple quantum well structure of III-V nitride material configured to emit light under an applied operating voltage or under optical excitation, wherein the multiple quantum well structure exhibits an emission wavelength uniformity of ±3 nm or less, or ±1 nm or less, under an applied operating voltage or under optical excitation.

[0081] Thus, a micro-LED structure can be fabricated by creating a GaN-on-Si epi-wafer with an active layer structure on top of the strain-tuned substack as described above, thinning the GaN-on-Si epi-wafer starting from the backside of the substrate down to the n-type doped GaN layer underneath the multiple quantum well structure of III-V nitride material, and cutting or etching the micro-LED structure from the thinned GaN-on-Si epi-wafer.

[0082] It is to be understood that the above-mentioned aspects, in particular the GaN-on-Si epi-wafer of claim 1 and the method of claim 11, have similar and / or identical preferred embodiments, in particular as defined in the dependent claims.

[0083] It is further to be understood that a preferred embodiment of the invention can also be any combination of the dependent claims or above embodiments with the respective independent claim.

[0084] These and other aspects of the present invention will become apparent from and elucidated by the following description of the embodiments taken in conjunction with the drawings. [Brief explanation of the drawings]

[0085] [Figure 1] 1 shows a GaN-on-Si epiwafer that can be used to fabricate micro LED structures or power electronic structures. [Figure 2] A self-assembled template layer made of AlN is shown. [Figure 3] GaN-on-Si epi-wafer with active layer structure. [Figure 4] 2 shows a GaN-on-Si epi-wafer similar to that of FIG. 3, but with a GaN layer disposed between a surface recovery layer and an AlGaN intermediate layer. [Figure 5] 1 shows a strain-decoupled substack in a schematic cross-sectional view. [Figure 6] 1 shows an atomic force microscopy (AFM) image of the outer surface of the self-assembled template layer along the stacking direction of a GaN-on-Si epitaxial wafer. [Figure 7] This shows the a) reflectivity change and b) curvature change during the fabrication of a GaN-on-Si epiwafer. [Figure 8] A GaN-on-Si epi-wafer is shown in cross section. [Figure 9] 1 shows a schematic and exemplary illustration of pyramidal GaN structures formed on a self-assembled template upon initiating growth of a surface recovery layer. [Figure 10] 1 shows a flow diagram illustrating a method for manufacturing a GaN-on-Si epi-wafer. [Figure 11] The wafer carrier is shown schematically in a cross-sectional side view, with the wafer carrier having a carrier pocket with a bottom surface having a convex shape. [Figure 12] The wafer carrier is shown schematically in a cross-sectional side view, with the wafer carrier having a carrier pocket with a bottom surface presenting a substantially planar flat. [Figure 13] 1 shows a wafer carrier schematically in a cross-sectional side view, the wafer carrier having a carrier pocket with an M-shaped bottom surface. [Figure 14] The wafer carrier is shown schematically in a top view, with a carrier pocket having a support surface formed by an outer rim surrounding a bottom surface. [Figure 15] The wafer carrier is shown schematically in a top view, with the wafer carrier having a carrier pocket with triangular support posts that provide respective portions of a support surface. [Figure 16] The wafer carrier is shown schematically in a top view, having a carrier pocket with rectangular support posts that provide respective portions of a support surface. DETAILED DESCRIPTION OF THE INVENTION

[0086] FIG. 1 illustrates a GaN-on-Si epi wafer 100 that can be used to fabricate micro LED structures or power electronic structures such as HEMTs. The GaN-on-Si epi wafer 100 includes a substrate 102 made of silicon. The substrate 102 has a circular bottom area with a diameter of 300 mm. However, in alternative embodiments of the GaN-on-Si epi wafer 100, the substrate 102 can have a diameter of 150 mm or greater, preferably 150 mm to 450 mm, where the substrate 102 preferably has a standard diameter for semiconductor technology, such as 150 mm, 200 mm, 300 mm, or 450 mm. In some embodiments, the substrate 102 does not have a circular bottom area, but rather has a quadratic or polygonal bottom area.

[0087] Although the substrate 102 does not need to be made entirely of silicon, it is preferable that at least the substrate surface 106 along the stacking direction 108 of the GaN-on-Si epi-wafer 100 be at least partially made of silicon. For example, the portion of the substrate surface 106 that is not made of silicon can be made of SiO, SiON, or SiO.

[0088] The substrate 102 has a thickness of 1 mm along the stacking direction 108. However, it may be advantageous to use a substrate that is thicker than 1 mm, for example, 1.2 mm to 1.6 mm. By using a relatively thick substrate of 1 mm or more, it may be possible to prevent plastic deformation of the substrate 102 when growing layers on it.

[0089] Disposed on the substrate surface 106 of the substrate 102 is a strain-release substack 111 comprising a self-assembling template layer 110 and a surface recovery layer 114. The self-assembling template layer 110 is made of AlN and contains a plurality of pits and dislocations. In particular, the self-assembling template layer 110 has a 1×10 lattice structure at its template surface 112. 8 cm -2 and pits with a density of 1x10 10 cm -2The self-assembled template layer 110 has a relatively high pit density and dislocations with a total dislocation density of 100 . The dislocations are distributed throughout the volume of the self-assembled template layer 110. Due to the relatively high pit density and relatively high total dislocation density, the self-assembled template layer 110 has a relatively low crystalline quality. This low crystalline quality, in combination with the surface recovery layer 114, is intended to and results in decoupling of strain resulting from the lattice mismatch between the silicon substrate 102 and the crystalline layers deposited on top of the strain-decoupling substack 111 along the stacking direction 108. The strain induced by the silicon substrate 102 is relaxed in the surface recovery layer 114, which is substantially strain-free due to the presence of pits and dislocations in the self-assembled template layer 110. A high pit density alone is sufficient to achieve sufficient strain decoupling. However, a high total dislocation density in addition to this can further improve strain decoupling.

[0090] The pits in the self-assembled template layer 110 provide self-assembled templates 112 for growing the next crystalline layer following the self-assembled template layer 110 along the stacking direction 108. When growing a layer on the self-assembled template 112, the pits formed on the surface of the self-assembled template layer oriented along the stacking direction 108 can be overgrown so that the pits are covered. By overgrowing the pits, efficient strain relaxation is achieved in the surface recovery layer 114, thereby isolating the subsequent crystalline layer along the stacking direction 108 from the strain induced by the substrate 102.

[0091] As described above, the surface recovery layer 114 is disposed on the self-assembling template layer 110. The surface recovery layer 114 was deposited on the self-assembling template layer 110 by overgrowing the pits in the self-assembling template 112 provided by the self-assembling template layer 110. Due to the pits in the self-assembling template layer 110, the surface recovery layer first grows by forming pyramidal structures in a pyramidal growth mode, so that the surface recovery layer overgrows the pits, thereby bending dislocations toward the side facets of the pyramids. This mechanism enables efficient strain relaxation, such that the surface recovery layer 114 is substantially unstrained and provides a smooth surface for growing subsequent crystalline layers. In particular, the smooth surface 116 of the surface recovery layer oriented along the stacking direction 108 is substantially free of pits. For example, a substantially smooth surface 116 having a reflectivity of more than 35%, e.g., 40% or more, can be achieved by first applying a pyramidal growth mode, which involves the formation of pyramidal-shaped GaN structures that promote dislocation bending and annihilation, and then applying a layer-by-layer growth mode to form a substantially smooth surface 116.

[0092] On the surface recovery layer 114, and therefore on the substantially smooth surface 116, a GaN layer 120 having a thickness of 3 μm and an Al layer having a thickness of 10 nm are formed. 0.6 Ga 0.4 A strain-tuned substack 118 is deposited, comprising an AlN interlayer 122. 0.6 Ga 0.4 The aluminum content of the N intermediate layer 122 may be different from 60%, and may be 50% or more. Furthermore, the thickness of 10 nm may be selected to be smaller or larger, in particular between 5 nm and 25 nm. 0.6 Ga 0.4 By varying the aluminum content and / or thickness of the N interlayer 122, it is possible to tune the strain in the strain-tuned substack 118. 0.6 Ga 0.4The use of the N intermediate layer 122 can reduce the strain in the strain-tuned substack 118, which allows the growth of a high crystalline quality GaN layer 120 having a thickness of 500 nm or, for example, a few micrometers, e.g., up to 2 μm or up to 5 μm, along the stacking direction. 0.6 Ga 0.4 By using the N intermediate layer 122, the tensile strain caused by the thermal expansion mismatch between GaN and Si can be compensated for by the compressive strain component in the GaN layer 120, thereby improving the crystal quality of the GaN layer 120.

[0093] In the strain-tuned substack 118, Al 0.6 Ga 0.4 The N intermediate layer 122 is deposited directly on the smooth surface 116 of the surface recovery layer 114. The GaN layer 120 is deposited along the stacking direction 108 of the GaN-on-Si epitaxial wafer 100 by 0.6 Ga 0.4 The Al intermediate layer 122 is connected to the AlN intermediate layer 122. 0.6 Ga 0.4 It is also possible for the strain-tuned substack 118 to start with the GaN layer 120 , such that the N intermediate layer 122 is deposited on top of the GaN layer 120 along the stacking direction 108 .

[0094] The strain-tuning substack 118 is made of Al 0.6 Ga 0.4 Further repetitions of the N intermediate layer 122 and the GaN layer 120 may be provided. 0.6 Ga 0.4Including additional repetitions of the N intermediate layer 122 and the GaN layer 120 can be advantageous because the crystalline quality of each GaN layer may improve with each repetition. Therefore, the number of repetitions can be selected so that the topmost GaN layer along the stacking direction 108 has the desired crystalline quality. In these additional repetitions, the Al content and thickness of the intermediate layer may vary from repetition to repetition. Including additional repetitions can be advantageous because each subsequent repetition generally results in a relatively thicker GaN layer. The thicker the GaN layer, the better its crystalline quality. Therefore, growing a relatively thick GaN layer is often desirable to achieve improved crystalline quality. Typical thicknesses of the GaN layers in the repetitions are between 0.5 μm and 5 μm.

[0095] The strain-tuning substack 118 can be grown on the substantially smooth surface 116 provided by the substantially strain-free surface recovery layer 114, allowing for particularly precise strain tuning by the intermediate layer 122. Thus, the strain-decoupling substack 111, which provides strain decoupling via a relatively high pit density in the self-assembling template layer 110, and the subsequent strain relaxation in the surface recovery layer 114 formed by overgrowing the self-assembling template 112 of the self-assembling template layer 110, facilitates efficient and precise strain balancing in the strain-tuning substack 118. Strain balancing in the strain-tuning substack 118 can include inducing compressive strain in the GaN layer by the intermediate layer 122, enabling growth of a GaN layer of relatively high crystalline quality in the strain-tuning substack 118.

[0096] Furthermore, precise strain tuning by decoupling the strain from the substrate allows the GaN-on-Si epitaxial wafer 100 to have a warpage of less than 100 μm at room temperature, such as less than 80 μm or even less than 50 μm at room temperature. With a flat warpage of up to 100 μm at room temperature, the GaN-on-Si epitaxial wafer 100 is particularly suitable for fabricating multiple quantum well structures of III-V nitride materials suitable for producing micro-LEDs with emission wavelength uniformity of ±3 nm or less, or even ±1 nm or less. Due to its relatively large diameter of 300 mm, or even up to 450 nm or 500 mm, the GaN-on-Si epitaxial wafer 100 can be used to economically fabricate micro-LED structures with high emission wavelength uniformity.

[0097] 2 shows a self-assembled template layer 200 made of AlN, which can form the self-assembled template layer in the GaN-on-Si epi-wafer described with reference to FIG.

[0098] The self-assembled template layer 200 has a surface area of ​​1×10 7 cm -2 ~1x10 11 cm -2The pits 208 have a pit density of 100 nm to 100 nm, particularly 10 nm to 50 nm, in a direction perpendicular to the stacking direction 206 of the GaN-on-Si epitaxial wafer. In particular, the pits in the self-assembling template layer 200 have an average distance of 200 nm to 2000 nm in a direction perpendicular to the stacking direction 206, which is particularly advantageous for providing a self-assembling template. The pits 208 provide a self-assembling template, with the template surface 210 of the self-assembling template layer 200 oriented along the stacking direction 206. When the pits 208 are overgrown in a pyramidal structure in the pyramidal growth mode of the surface recovery layer, the pits can be covered without being filled with material. Alternatively, the pits 208 can be at least partially filled and covered when overgrown. This allows the surface recovery layer to be grown without distortion and with a smooth surface for further growth of subsequent crystal aylets.

[0099] In addition to the pits 208, the self-assembled template layer 200 has a thickness of 10 9 cm -2 The self-assembled template layer 200 includes a plurality of dislocations 212 having a total dislocation density of at least 100 Å. At least 70% of the dislocations 212 include line defects with an angle of 0 to 5 degrees relative to the stacking direction 206. The dislocations 210 are distributed throughout the volume of the self-assembled template layer 200, while the pits 208 extend from the template surface 210 into the volume of the self-assembled template layer 200.

[0100] FIG. 3 shows a GaN-on-Si epi-wafer 300 having an active layer structure 302 which can be an LED structure with a multiple quantum well structure or a high power electronics structure.

[0101] Along the stacking direction 304 of the GaN-on-Si epi-wafer 300, the GaN-on-Si epi-wafer 300 includes a silicon substrate 306 having a thickness of 1.2 mm and a diameter of 150 mm. However, the silicon substrate 306 may have a thickness of 1 mm to 1.6 mm and a diameter greater than 150 mm, such as 200 mm, 300 mm, or 450 mm. On top of the silicon substrate 306 is a strain-uncoupling substack 311 including a self-assembled template layer 308, which is an Al-containing layer containing a plurality of pits 310, and a surface recovery layer 312. The self-assembled template layer 308 with pits 310 serves to uncouple strain resulting from the lattice mismatch between the silicon substrate 306 and an additional nitride layer deposited on the strain-uncoupling substack 311. The pits 310 in the self-assembled template layer 308 form a self-assembled template on the template surface facing along the stacking direction 304 for growing the surface recovery layer 312 made of GaN. The use of the surface recovery layer 312 can significantly reduce the number of dislocations and pits along the stacking direction, thereby providing a substantially smooth surface 314 that is used as a growth surface for growing a strain-tuned substack 316 on top of the surface recovery layer 312.

[0102] The strain-tuned substack 316 provides a high-quality GaN layer 318 that can be used to fabricate microLED structures with a relatively high emission wavelength uniformity of ±3 nm or less across the GaN-on-Si epiwafer 300. The high-quality GaN layer 318 can also be used to fabricate high-power electronic structures, such as HEMT structures. To obtain the high-quality GaN layer 318, an AlGaN intermediate layer 320 is deposited on the surface recovery layer 312. By adjusting the Al content and / or thickness of the intermediate layer 320, the strain in the strain-tuned substack 316 can be tuned to improve the crystalline quality of the GaN layer 318. It is also possible to grow the GaN layer 318 directly on the surface recovery layer 312, and then grow the intermediate layer 320 on top of the GaN layer 318. In this case, it is preferable that an additional GaN layer be deposited on the intermediate layer 320 and used to fabricate the active layer structure 302.

[0103] 4 shows a GaN-on-Si epi-wafer 400 having a GaN layer 404 disposed between a surface recovery layer 406 and an AlGaN intermediate layer 408. The GaN-on-Si epi-wafer 400 shown in FIG. 4 includes, along a stacking direction 402 of the GaN-on-Si epi-wafer 400, a silicon substrate 403 that can be configured in accordance with the substrate 306 of the GaN-on-Si epi-wafer 300 described with reference to FIG. 3.

[0104] As the strain decoupling substack 311 of the GaN-on-Si epiwafer 300, the strain decoupling substack 411 includes a self-assembling template layer 410 for decoupling strain and a surface recovery layer 412. The self-assembling template layer 410 includes pits 415 that contribute to decoupling the strain tuning substack 414 from the strain induced by the substrate 403. The self-assembling template layer 410 provides a self-assembling template 406 for growing the surface recovery layer 412 on the self-assembling template layer 410.

[0105] As previously described, a first high-crystalline-quality GaN layer 404 is provided on the substantially smooth surface 413 provided by the surface recovery layer 412. The first high-crystalline-quality GaN layer 404 is part of a strain-tuned substack 414 that further includes an AlGaN intermediate layer 408 and a second high-crystalline-quality GaN layer 416. By depositing the first GaN layer 404 on the surface recovery layer 406 and below the AlGaN intermediate layer 408, the crystalline quality of the second GaN layer 416 can be further improved by precise strain tuning achieved by appropriately selecting the Al content and thickness of the AlGaN intermediate layer 408. An active layer structure 418 is present on the second high-crystalline-quality GaN layer 416, enabling, for example, a micro LED structure with improved emission wavelength uniformity or a high-power electronics structure such as a HEMT structure.

[0106] 5 shows a schematic cross-sectional view of a strain-decoupling substack 500, which comprises a self-assembled template layer 504 of AlN disposed on a silicon substrate 506. A surface recovery layer 508 of GaN is disposed on top of the self-assembled template layer 504.

[0107] Pits 510 are present in self-assembled template layer 504. Furthermore, self-assembled template layer 504 has a high dislocation density of dislocations 512 that extend substantially vertically through self-assembled template layer 504 and penetrate into surface recovery layer 508. In surface recovery layer 508, the total dislocation density is significantly reduced compared to self-assembled template layer 504. In fact, dislocations 502 bend and disappear, i.e., dislocation annihilation occurs, in surface recovery layer 508. As a result, surface recovery layer 508 has significantly improved crystalline quality compared to the relatively poor crystalline quality throughout self-assembled template layer 504.

[0108] The surface recovery layer 508 can be made of GaN. The surface recovery layer 508 is substantially strain-free, providing a smooth surface 506 for fabricating the strain-tuned substack. The strain-tuned substack can include, along a stacking direction 508 of the self-assembled template layer 504, a first AlGaN intermediate layer, followed by a first GaN layer, followed by a second AlGaN intermediate layer, a second GaN layer, a third AlGaN intermediate layer, and a third GaN layer. The first, second, and third intermediate layers can have different thicknesses of 5 nm to 25 nm and different aluminum contents of at least 50%. The thicknesses of the first, second, and third GaN layers can increase along the stacking direction. Similarly, the crystalline quality of the first, second, and third GaN layers can increase along the stacking direction 508.

[0109] FIG. 6 shows an atomic force microscope (AFM) image 600 of the template surface of a self-assembling template layer 602 oriented along the stacking direction of a GaN-on-Si epitaxial wafer. The self-assembling template layer 602 is made of AlN. As can be seen from the AFM image 600, a plurality of pits 604 are distributed on the template surface of the self-assembling template layer. The pits 604 are formed by holes having a depth of at least 7 nm into the self-assembling template layer 602. In the AFM image 600 of the self-assembling template layer 602, the pits 604 are represented by relatively dark spots having a diameter of 10 nm to 100 nm. In the AFM image 600 of the self-assembling template layer 602, the pits 604 are approximately 10 nm deep. 9 cm -2 The pit density can be obtained by counting the pits per unit area. The average distance between pits is approximately 500 nm, which can be derived by determining the distance between adjacent pits and averaging the distances. In this example, the average distance is approximately 500 nm, as indicated by the open circles 610 superimposed on excerpt 600. Some pits 608 may be connected at the template surface of self-assembled template layer 602.

[0110] The distribution and size of the pits can be controlled by adjusting the oxide removal conditions in the reactor for removing the native oxide covering the Si-containing surface of the substrate and by adjusting the growth conditions during the growth of the self-assembled template layer. In particular, adjusting the oxide removal conditions to be relatively uniform results in a relatively uniform surface condition of the Si-containing surface of the substrate. The self-assembled template layer is then grown on the Si-containing surface of the substrate by columnar growth. Thus, the growth conditions for growing the self-assembled template layer can be controlled to achieve uniform growth, thereby forming pits in the self-assembled template layer with a relatively uniform distribution.

[0111] Oxide removal has been shown to work particularly well in an H2 atmosphere. Conditions for native oxide removal can be applied for several minutes. For example, if too short a treatment time is selected, the native oxide may not be sufficiently removed, preventing further growth on the substrate. However, if too long a treatment time is selected, the H2 etching may affect the Si-containing surface after the oxide has been removed, resulting in a rough substrate surface.

[0112] It has been shown that in order to grow a self-assembled template layer with a high pit density, it is advantageous not to completely remove the oxide, but to still have some native oxide present on the surface of the substrate, so that the formation of pits in the self-assembled template layer can be achieved, particularly by columnar growth.

[0113] The self-assembled template layer is preferably grown to a thickness of 50 nm to 300 nm, e.g., 100 nm to 200 nm. The columnar growth of the AlN self-assembled template layer can be promoted by only partially removed native oxide on the substrate surface and by defects that prevent nucleation. For example, native oxide and defects can prevent the AlN from completely overgrowing the self-assembled template layer, resulting in the formation of pits in the self-assembled template layer. A particular advantage of the growth conditions just described is that the self-assembled template layer is crystalline rather than amorphous and can be fabricated at relatively high substrate temperatures above 1000°C.

[0114] Figure 7 shows, in the upper part, Figure 7a), the change in reflectivity during the fabrication of a GaN-on-Si epi-wafer 800, a portion of which is shown schematically in Figure 8. Figure 7 also shows, in the lower part, Figure 7b), the change in curvature during the fabrication of a GaN-on-Si epi-wafer 800.

[0115] As can be seen in FIG. 7a), the reflectivity of the substrate 700 exceeds 40%. The reflectivity then drops to approximately 10% for the self-assembled template layer 702, which is believed to be due to the poor crystalline quality of the self-assembled template layer 702, which contains multiple pits and defects. The decoupling of strain from the substrate 700 achieved by the self-assembled template layer 702 ultimately enables the recovery of good crystalline quality in the surface recovery layer 704, which has a substantially smooth surface with surface quality comparable to that of the substrate 700, as seen in portion 701. The surface recovery layer 704 comprises a pyramidal-shaped GaN layer 706 grown in a pyramidal growth mode. In the pyramidal growth mode, the growth of the surface recovery layer 704 begins with the formation of pyramidal-shaped GaN structures 900, as shown in FIG. 9. These pyramidal-shaped GaN structures 900 are formed on the self-assembled template provided by the pits in the self-assembled template layer 702. In the pyramidal growth mode, the pyramidal GaN structures 900 of the pyramidal-formed GaN layer 706 overgrow the pits of the self-assembled template. The pyramidal growth mode of the first GaN 706 of the surface recovery layer 704 promotes bending of dislocations 902 toward the inclined facets 904 of the pyramidal GaN structures 900. As a result, the dislocation density can be significantly reduced in the surface recovery layer 704 along the stacking direction 711 of the GaN-on-Si epitaxial wafer 800. As a result, the layer-by-layer formed GaN layer 708 grown in the layer-by-layer growth mode of the surface recovery layer 704 has significantly reduced pit density and provides a recovered, smooth surface, as indicated by the red circle 701. To change from the pyramidal growth mode to the layer-by-layer growth mode, the growth parameters are appropriately controlled to suit the layer-by-layer growth.

[0116] As just described, after growing the pyramidal-shaped GaN layer 706 of the surface recovery layer 704, the layer-by-layer-formed GaN layer 708 of the surface recovery layer 704 is grown in a layer-by-layer growth mode. By growing the layer-by-layer-formed GaN layer 708, the smooth surface is significantly restored as shown by the dashed line 709, and the surface recovery layer 704 is restored to a substantially smooth surface with a reflectivity of over 40% as shown by the red circle 701.

[0117] An intermediate layer 710 of AlGaN is deposited on the smooth surface of the surface recovery layer 704 and is used to induce compressive strain in a GaN layer 712 that is part of the strain-tuned substack of the GaN-on-Si epiwafer 800.

[0118] As can be seen from Figure 7b, compressive strain is not induced during the growth of the surface recovery layer 704, as indicated by the horizontal dashed line 714. However, compressive strain is induced in the GaN layer 712, as indicated by the dashed line 716. By inducing compressive strain in the GaN layer 712, it is possible to achieve a relatively large bow during the growth of an active layer structure on the strain-tuned substack of the GaN-on-Si epitaxial wafer. During the growth of the active layer structure, the large bow has the advantage of enabling a uniform temperature distribution between the substrate and the bottom surface of the carrier pocket holding the substrate. For this purpose, the carrier pocket preferably has a convex bottom surface or a bottom surface with an upwardly curved convex bottom portion when viewed in cross section. This allows a substantially constant distance to be established between the bottom surface of the carrier pocket and the GaN-on-Si epitaxial wafer with a large bow. The uniform temperature distribution is advantageous for growing high-quality active layer structures, for example, quantum wells made of III-V nitride materials such as InGaN. In particular, InGaN is more sensitive to temperature changes than GaN, so establishing a uniform temperature distribution can result in uniform quantum wells made from III-V nitride materials with superior performance.

[0119] As a further advantage, despite the relatively large warpage of the GaN-on-Si epitaxial wafer during growth of the active layer structure, after cooling, the GaN-on-Si epitaxial wafer has a relatively small warpage of up to 100 μm at room temperature, especially due to strain decoupling, even after thinning. Therefore, the GaN-on-Si epitaxial wafer can be thinned to a SEMI-standard thickness and further processed into electronic or optoelectronic devices from the active layer structure with uniform electronic and / or optoelectronic properties. In particular, due to the relatively flat warpage of the GaN-on-Si epitaxial wafer 800 at room temperature even after thinning, the GaN-on-Si epitaxial wafer 800 is particularly suitable for providing an active layer structure for realizing a microLED structure that emits light with relatively good emission wavelength uniformity of ±3 nm or less for further processing in standard semiconductor processing lines.

[0120] 10 is a flow diagram showing a method for manufacturing a GaN-on-Si epitaxial wafer. By carrying out the method described below, it is possible to obtain a GaN-on-Si epitaxial wafer such as that described with reference to FIG.

[0121] The method includes providing a wafer carrier configured to hold a wafer (step S1). The wafer carrier is provided in a reactor chamber. The wafer carrier includes a wafer carrier body having at least one carrier pocket configured to accommodate a wafer. The carrier pocket has a support surface for holding the wafer and a bottom surface below the wafer, the bottom surface having a convex shape or including a convex bottom surface portion. In particular, the bottom surface is at least partially curved upward toward the wafer supported by the support surface.

[0122] A substrate having a circular bottom area with a diameter of 300 mm is placed on the support surface of the carrier pocket (step S2). Alternatively, the carrier pocket may be designed to hold a substrate having a diameter of 150 mm or more, preferably 150 mm to 450 mm. The bottom area of ​​the wafer does not necessarily have to be circular. The carrier pocket may also be designed to accommodate substrates having a non-circular bottom area, for example, a quadratic or hexagonal bottom area.

[0123] A strain-uncoupled substack is fabricated on the substrate, which includes growing a self-assembled template layer by epitaxy (Step S3). The self-assembled template layer is made of AlN and has a thickness of 1×10 7 cm -2 ~1x10 11 cm -2 The self-assembling template layer is grown to have pits with a pit density of 1000 nm. The self-assembling template layer serves, among other things, to decouple the strain induced by the substrate and provide a self-assembling template through the pits. Prior to growing the self-assembling template layer on the substrate, native oxide can be at least partially removed from the surface of the substrate. The self-assembling template layer is preferably grown to a thickness of 50 nm to 300 nm, more preferably 100 nm to 200 nm.

[0124] A surface recovery layer is epitaxially grown on the self-assembled template provided by the pits in the self-assembled template layer as part of the strain-uncoupling substack (step S4). A pyramidal GaN layer of the surface recovery layer is grown by first adopting a pyramidal growth mode. Therefore, the pyramidal growth mode is particularly applicable to first growing the surface recovery layer on the self-assembled template of the self-assembled template layer. In the pyramidal growth mode, the surface recovery layer is initiated by forming pyramidal structures, which grow in size, thereby filling or overgrowing the pits in the self-assembled template layer without filling them. This causes dislocations present in the pyramidal GaN structures to bend toward the tilted facets and annihilate. As a result of the dislocation bending and annihilation, the total dislocation density of the surface recovery layer is reduced to 10 9 cm -2 The total dislocation density of the self-assembled template layer is significantly reduced compared to the total dislocation density of the self-assembled template layer, which is of the same order of magnitude as the substrate. Then, by appropriately controlling the growth parameters, the pyramidal growth mode is changed to a transitional growth mode, in which the surface recovery layer grows horizontally and vertically. Then, by again appropriately controlling the growth parameters, the growth of the surface recovery layer is changed to a layer-by-layer growth mode. This achieves surface recovery, resulting in a substantially smooth surface of the surface recovery layer, characterized by, for example, a reflectivity comparable to that of the substrate.

[0125] Thus, by providing a self-assembled template layer with a high pit density, it is possible to first overgrow the pits with pyramidal structures. Overgrowth with pyramidal structures bends dislocations and / or prevents them from propagating further along the stacking direction. As a result, a layer-by-layer growth mode can be used to heal the surface of the surface-healed layer, providing a smooth, substantially strain-free surface for growing the strain-tuned substack. Thus, the interplay of pit formation, pit overgrowth, and dislocation lateral bending can provide a smooth, strain-free surface for growing additional crystalline layers that are decoupled from substrate-induced strain.

[0126] A strain-tuning substack is then grown by epitaxy on the substantially smooth and strain-free surface of the surface recovery layer (step S5). The strain-tuning substack comprises a GaN layer having a thickness of 1.5 μm to 4.0 μm and an Al layer having a thickness of 5 nm to 25 nm. x Ga 1-x and an N intermediate layer (x≧0.5). By adjusting the Al content and thickness of the intermediate layer, it is possible to control the curvature of the GaN-on-Si epiwafer. Control of the curvature of the GaN-on-Si epiwafer is particularly possible by adjusting the Al content and thickness of the intermediate layer, which affects the amount of compressive strain induced in the GaN layer of the strain-tuned substack.

[0127] To fabricate a micro LED structure from a GaN-on-Si epitaxial wafer, an active layer structure can first be grown on the strain-tuned substack (optional step S6). To fabricate the active layer structure, growth parameters are controlled to result in a relatively large bow of the GaN-on-Si epitaxial wafer. This large bow enables the fabrication of a uniform, high-quality active layer structure. The active layer structure preferably comprises a multiple quantum well structure of III-V nitride materials and is configured to emit light under an applied operating voltage.

[0128] After the strain-tuning substack is grown, the GaN-on-Si epitaxial wafer is cooled to ambient temperature (step S7). The resulting GaN-on-Si epitaxial wafer has a flat bow of up to 100 μm and is suitable for fabricating micro LED structures comprising multiple quantum well structures of III-V nitride materials configured to emit light under an applied operating voltage. In particular, properly fabricated micro LED structures can have an emission wavelength uniformity of ±3 nm or less.

[0129] To fabricate a micro-LED structure from the GaN-on-Si epi-wafer with the active layer structure, the GaN-on-Si epi-wafer is thinned starting from the backside of the substrate down to the n-type doped GaN layer below the active layer structure (optional step S8). Due to strain decoupling, the GaN-on-Si epi-wafer maintains a flat bow of up to 100 μm even after thinning, allowing it to be used in standard semiconductor processing lines for manufacturing electronic and / or optoelectronic devices.

[0130] FIG. 11 schematically illustrates a wafer carrier 1100 in a cross-sectional side view. The wafer carrier 1100 includes a carrier pocket 1102. The carrier pocket 1102 is configured to accommodate wafers having a diameter of 300 mm. Alternatively, the carrier pocket 1102 may be configured to accommodate wafers having a diameter of 150 mm or greater, e.g., 150 mm to 450 mm, particularly 150 mm, 200 mm, 300 mm, or 450 mm. The carrier pocket 1102 is configured to accommodate wafers having a thickness of 1 mm or greater, e.g., 1 mm to 1.5 mm. To this end, the carrier pocket 1102 includes a support surface 1108 for supporting the wafer. As seen in the cross-sectional side view, the carrier pocket 1102 has a bottom surface 1104 having a convex shape that curves upward toward the support surface 1108.

[0131] The wafer carrier 1100 is shown in operation, i.e., with a GaN-on-Si epi-wafer 1106 placed in the carrier pocket 1102. The GaN-on-Si epi-wafer 1106 is positioned on a support surface 1108. The GaN-on-Si epi-wafer 1106 is configured as described with reference to FIG. 1 and, at its current growth stage, does not have an active layer structure disposed on top of a strain-tuned substack. At the growth stage illustratively shown in FIG. 11, the GaN-on-Si epi-wafer 1106 has a convex bow. The bottom surface 1104 has a convex shape configured such that the distance 1112 between the GaN-on-Si epi-wafer 1106 and the bottom surface 1104 of the carrier pocket 1102 is substantially constant at a predefined bow of the GaN-on-Si epi-wafer 1106. In other words, at the predefined bow of the GaN-on-Si epi-wafer 1106, the curvature of the GaN-on-Si epi-wafer 1106 substantially corresponds to the convex shape of the bottom surface 1104. This is advantageous because it allows the active layer structure to be grown on the strain-tuned sub-stack with uniform heat distribution below the GaN-on-Si epi-wafer. In particular, growth conditions are controlled to maintain the predefined bow of the GaN-on-Si epi-wafer 1106 during growth of the active layer structure on the strain-tuned sub-stack. When the GaN-on-Si epi-wafer 1106 has a predefined bow, the vertical distance from the bottom surface to the support surface is preferably 0.05 mm to 1 mm, e.g., 1 mm to 0.25 mm, along the diameter of the GaN-on-Si epi-wafer 1106.

[0132] This allows for at least similar growth conditions to be established along the diameter of the GaN-on-Si epi-wafer 1106, thereby enabling the growth of a uniform active layer structure, such as that described with reference to FIG. 3 or FIG. 4 . An active layer structure grown with uniform thermal distribution beneath the GaN-on-Si epi-wafer 1106 can have substantially uniform electronic and / or optoelectronic properties along the diameter of the GaN-on-Si epi-wafer 1106. Electronic or optoelectronic devices, such as micro-LEDs, can be manufactured with high yields from such active layer structures. For example, the GaN-on-Si epi-wafer 1106 can produce micro-LEDs that exhibit excellent emission wavelength uniformity of ±3 nm or better, or ±1 nm or better.

[0133] FIG. 12 shows a schematic cross-sectional side view of a wafer carrier 1200. The wafer carrier 1200 has a carrier pocket 1202. The wafer carrier 1200 is configured similarly to the wafer carrier 1100 described with reference to FIG. 11, except for the bottom surface 1204 of the carrier pocket 1202. The bottom surface 1204 of the carrier pocket 1202 is not uniformly curved like the bottom surface 1104 of the carrier pocket 1102, but has a convexly curved outer edge 1214 surrounding a substantially planar flat portion 1216 located in the center of the bottom surface 1204. The substantially planar flat portion 1216 is parallel to the support surface 1208 of the carrier pocket 1202.

[0134] Such a wafer carrier 1200 may be useful for growing an active layer structure on a strain-tuned substack of a GaN-on-Si epiwafer 1206, which also exhibits a convexly curved outer edge 1218 surrounding a substantially planar plateau 1220 located in the center of the GaN-on-Si epiwafer 1206. A corresponding situation is illustratively shown in Figure 12, in which the wafer carrier 1200 is positioned on a support surface 1208 of a carrier pocket and employed for growing an active layer structure on the strain-tuned substack of the GaN-on-Si epiwafer 1206. As can be seen from Figure 12, growth conditions are controlled so that the distance 1212 between the GaN-on-Si epiwafer 1206 and the bottom surface 1204 of the carrier pocket 1202 is substantially constant.

[0135] 13 shows a schematic cross-sectional side view of a wafer carrier 1300. The wafer carrier 1300 has a carrier pocket 1302 with an M-shaped bottom surface 1304. The M-shaped bottom surface 1304 thus includes a convex edge 1314 that surrounds a concave central portion 1316 of the bottom surface 1304.

[0136] Similar to wafer carrier 1100 in FIG. 11 and wafer carrier 1200 in FIG. 12 , wafer carrier 1300 is also shown in operation, i.e., with a GaN-on-Si epi-wafer 1306 positioned on support surface 1308 of carrier pocket 1302. Growth conditions are controlled so that GaN-on-Si epi-wafer 1306 also has an M-shaped curvature, with a convex outer edge 1318 surrounding a concave central portion 1320. Such an M-shape can occur during growth due to gravity, particularly when using GaN-on-Si epi-wafers 1306 with large diameters, e.g., 300 mm or greater. During growth of the active layer structure on the strain-tuned substack of GaN-on-Si epi-wafer 1306, growth conditions can be controlled so that distance 1312 between GaN-on-Si epi-wafer 1306 and bottom surface 1304 of carrier pocket 1302 is substantially constant along the diameter of GaN-on-Si epi-wafer 1306.

[0137] The wafer carriers 1100, 1200, 1300 described with reference to Figures 11, 12, and 13, respectively, can be used in the method described with reference to Figure 10 for manufacturing GaN-on-Si epi-wafers.

[0138] 14, 15, and 16 schematically illustrate wafer carriers 1400, 1550, and 1600, respectively, in top view. Wafer carrier 1400 has a carrier pocket 1402 with a support surface 1408 formed by an outer edge surrounding bottom surface 1404. Wafer carrier 1500 has a carrier pocket with triangular support posts 1508 that each provide a portion of the support surface surrounding bottom surface 1504. The number of triangular support posts 1508 can be four, as in this example, but generally can be three or more. Wafer carrier 1600 has a carrier pocket 1602 with rectangular support posts 1608 that each provide a portion of the support surface surrounding bottom surface 1604. The number of rectangular support posts 1608 can be four, as in this example, but generally can be three or more. Support surfaces implemented as outer edges 1408 as in wafer carrier 1400, or as triangular support posts 1508 as in wafer carrier 1500, or as rectangular support posts 1608 as in wafer carrier 1600, can be used to implement support surfaces 1108, 1208, and 1308, respectively, in each of wafer carriers 1100, 1200, and 1300.

[0139] Those skilled in the art will understand and effect other variations to the disclosed embodiments, from a study of the drawings, the disclosure, and the appended claims, in practicing the claimed invention.

[0140] In the claims, the word "comprising" does not exclude other elements or steps and the indefinite article "a" or "an" does not exclude a plurality.

[0141] Any reference signs in the claims should not be construed as limiting the scope of the invention.

Claims

1. A GaN-on-Si epi-wafer forming a layer stack along a stacking direction comprising: a substrate having a diameter of at least 150 mm in at least one direction perpendicular to said stacking direction and a substrate surface along said stacking direction at least partly made of silicon; a strain-decoupling substack, a self-assembled template layer disposed directly on the substrate, the self-assembled template layer comprising pits, the pits having a size of 1×10 ７ cm －２ ~1 x 10 １１ cm －２ a self-assembled template layer having a pit density of a surface recovery layer comprising GaN, disposed directly on the self-assembled template layer, the surface recovery layer having a smooth surface oriented along the stacking direction; a strain decoupling substack comprising: - arranged on said surface recovery layer and comprising at least one GaN layer and at least one Al ｘ Ga １－ｘ A strain-tuned substack comprising an N intermediate layer, where x≧0.5, the GaN layer having a thickness of 0.5 μm to 4.0 μm, and the Al ｘ Ga １－ｘ a strain-tuned substack, wherein the N interlayer has a thickness of 5 nm to 25 nm; It is equipped with - the GaN-on-Si epi-wafer has a warpage of at most 100 μm at room temperature; GaN-on-Si epitaxial wafer.

2. 10. The GaN-on-Si epi-wafer of claim 1, further comprising an active layer structure disposed on the strain-tuned substack, the active layer structure comprising a multiple quantum well structure of III-V nitride material configured to emit light under an applied operating voltage or under optical excitation, and / or a lasing structure configured to emit laser radiation, and / or a transistor structure.

3. 3. The GaN-on-Si epitaxial wafer according to claim 2, wherein the multiple quantum well structure exhibits an emission wavelength uniformity of ±3 nm or less, or ±1 nm or less, under application of an operating voltage or under optical excitation.

4. The self-assembled template layer has a thickness of 10 ９ cm －２ 2. The GaN-on-Si epi-wafer according to claim 1, having a total dislocation density of at least 1000 nm.

5. 2. The GaN-on-Si epiwafer of claim 1, wherein the self-assembled template layer contains at least 50%, at least 70%, or at least 90% of line defects having an angle in the range of 0° to 20°, or 0° to 2°, relative to the stacking direction.

6. The strain-tuning substack comprises the GaN layer and the Al ｘ Ga １－ｘ N intermediate layer, or the Al ｘ Ga １－ｘ 2. The GaN-on-Si epitaxial wafer according to claim 1, comprising at least two repetitions of the layer sequence of an N intermediate layer and a GaN layer, where x≧0.

5.

7. 2. The GaN-on-Si epi-wafer of claim 1, wherein the smooth surface of the surface recovery layer has a reflectivity of 35% or more.

8. 2. The GaN-on-Si epi-wafer of claim 1, wherein the surface recovery layer includes dislocations that bend at an angle of 15° to 45° relative to the interface formed between the self-assembled template layer and the surface recovery layer.

9. 2. The GaN-on-Si epi-wafer of claim 1, wherein the pits in the self-assembled template layer have a pit size between 1 nm and 100 nm.

10. 10. The GaN-on-Si epiwafer of claim 1 or claim 9, wherein the pits in the self-assembled template layer have an average pit distance between adjacent pits in the range of 200 nm to 2000 nm.

11. 1. A method for manufacturing a GaN-on-Si epi-wafer, said method comprising the steps of: - providing a wafer carrier for holding a substrate, said wafer carrier comprising a wafer carrier body having at least one carrier pocket for accommodating a substrate, said carrier pocket comprising: - the bottom surface, a support surface located at a predefined vertical distance from said bottom surface, said support surface being configured to support said substrate; and The bottom surface has a convex shape or includes a bottom surface portion that is convex and curved upward when viewed in cross section. Steps and - placing a substrate on the support surface of a carrier pocket of the wafer carrier, the substrate having a diameter of 150 mm or more in at least one direction perpendicular to a deposition direction of subsequent epitaxial layer growth and a substrate surface along said deposition direction that is at least partly made of silicon; - creating a strain-decoupled substack, - the self-assembled template layer is formed such that the self-assembled template layer is 1×10 ７ cm －２ ~1 x 10 １１ cm －２ epitaxially growing a silicon nitride film directly on the substrate to have a pit density of epitaxially growing a surface recovery layer comprising GaN on the self-assembled template layer until the surface recovery layer has a smooth surface oriented along the stacking direction; and - controlling the curvature of the GaN-on-Si epi-wafer by epitaxially growing a strain-tuning sub-stack on top of said surface recovery layer using at least one predefined growth temperature, said strain-tuning sub-stack comprising at least one GaN layer and at least one Al ｘ Ga １－ｘ N intermediate layer, x≧0.5, the GaN layer has a thickness of 0.5 μm to 4.0 μm, ｘ Ga １－ｘ the N intermediate layer having a thickness of 5 nm to 25 nm; - cooling the GaN-on-Si epi-wafer to ambient room temperature; A method comprising:

12. controlling the curvature of the GaN-on-Si epi-wafer includes controlling the Al so that a convex curvature is achieved in which a normal distance between the bottom surface of the carrier pocket and the GaN-on-Si epi-wafer is constant across a diameter of the GaN-on-Si epi-wafer at a growth temperature. ｘ Ga １－ｘ The method of claim 11 , further comprising adjusting the Al content or thickness of the N intermediate layer.

13. 13. The method of claim 12, further comprising epitaxially growing an active layer structure on the strain-tuned substack, the active layer structure comprising a multiple quantum well structure of a III-V nitride material and configured to emit light under an applied operating voltage or optical excitation.

14. 14. The method of claim 13, wherein growing the active layer structure comprises growing an n-type doped GaN layer and growing the multiple quantum well structure on the n-type doped GaN layer, and fabricating a micro LED structure from the GaN-on-Si epi-wafer comprises thinning the GaN-on-Si epi-wafer starting from a backside of the substrate to the n-type doped GaN layer below the multiple quantum well structure.

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