Semiconductor Devices

Abstract

The present invention provides a semiconductor device which has a novel configuration. This semiconductor device comprises: a first substrate which is provided with a first peripheral circuit that has a function of driving a first memory cell; and a first memory cell layer which comprises a second substrate and a first element layer that comprises the first memory cell. The first memory cell comprises a first transistor and a first capacitor. The first transistor has a semiconductor layer which contains a metal oxide in a channel formation region. The first memory cell layer is superposed on the first substrate so as to be perpendicular or generally perpendicular to a surface of the first substrate. The second substrate comprises a circuit for writing or reading data to / from the first memory cell. The first peripheral circuit and the first memory cell are electrically connected to each other via a first through electrode that is provided in the second substrate and the first element layer.

Description

[Technical Field]

[0001] This specification describes semiconductor devices and the like.

[0002] In this specification, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. It also refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, or an electronic component that houses a chip in a package are examples of semiconductor devices. Furthermore, memory devices, display devices, light-emitting devices, lighting devices, electronic devices, etc. are themselves semiconductor devices and may include semiconductor devices. [Background technology]

[0003] Metal oxides have attracted attention as semiconductors that can be used in transistors. Transistors having a metal oxide semiconductor in a channel formation region (hereinafter sometimes referred to as "oxide semiconductor transistors" or "OS transistors") have been reported to have extremely low off-state current (e.g., Non-Patent Documents 1 and 2). Various semiconductor devices using OS transistors have been manufactured (e.g., Non-Patent Documents 3 and 4).

[0004] The manufacturing process of OS transistors can be incorporated into a conventional CMOS process for Si transistors. For example, Patent Document 1 discloses a configuration in which multiple layers of memory cell arrays having OS transistors are stacked on a substrate on which Si transistors are provided. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] US Patent Application Publication No. 2012 / 0063208 [Non-patent literature]

[0006] [Non-Patent Document 1] S. Yamazaki et al., “Properties of crystalline In-Ga-Zn-oxide semiconductor and its transistor characteristics,” Jpn.J.Appl.Phys., vol.53, 04ED18 (2014). [Non-patent document 2] K. Kato et al., “Evaluation of Off-State Current Characteristics of Transistor Using Oxide Semiconductor Material, Indium-Gallium-Zinc Oxide,” Jpn.J.Appl.Phys., vol. 51, 021201 (2012). [Non-patent document 3] S. Amano et al., “Low Power LC Display Using In-Ga-Zn-Oxide TFTs Based on Variable Frame Frequency,” SID Symp. Dig. Papers, vol. 41, pp. 626-629 (2010). [Non-patent document 4] T. Ishizu et al., “Embedded Oxide Semiconductor Memories: A Key Enabler for Low-Power ULSI,” ECS Tran., vol.79, pp.149-156 (2017). Summary of the Invention [Problem to be solved by the invention]

[0007] An object of one embodiment of the present invention is to provide a semiconductor device or the like having a novel structure. Another object of one embodiment of the present invention is to provide a semiconductor device or the like having a novel structure that can reduce manufacturing costs in a semiconductor device that functions as a memory device utilizing an extremely small off-state current. Another object of one embodiment of the present invention is to provide a semiconductor device or the like having a novel structure that has excellent low power consumption in a semiconductor device that functions as a memory device utilizing an extremely small off-state current. Another object of one embodiment of the present invention is to provide a semiconductor device or the like having a novel structure that can reduce the size of a semiconductor device that functions as a memory device utilizing an extremely small off-state current. Another object of one embodiment of the present invention is to provide a semiconductor device or the like having a novel structure that has excellent reliability and exhibits small fluctuations in the electrical characteristics of a transistor in a semiconductor device that functions as a memory device utilizing an extremely small off-state current.

[0008] The description of multiple problems does not preclude the existence of each other's problems. One embodiment of the present invention does not necessarily solve all of the problems exemplified. Furthermore, problems other than those listed will become apparent from the description in this specification, and such problems may also be problems of one embodiment of the present invention. [Means for solving the problem]

[0009] One embodiment of the present invention is a semiconductor device having a first substrate on which a first peripheral circuit having a function of driving a first memory cell is provided, a second substrate, and a first element layer having the first memory cell, wherein the first memory cell has a first transistor and a first capacitor, the first transistor has a semiconductor layer having a metal oxide in a channel formation region, the first memory cell layer is stacked on the first substrate in a direction perpendicular or approximately perpendicular to a surface of the first substrate, and the first peripheral circuit and the first memory cell are electrically connected via a first through electrode provided in the second substrate and the first element layer.

[0010] One embodiment of the present invention is a semiconductor device including: a first substrate provided with a first peripheral circuit having a function of driving a first memory cell; a second substrate; and a first element layer having the first memory cell, wherein the first memory cell has a first transistor and a first capacitor, the first transistor having a semiconductor layer having a metal oxide in a channel formation region, the first memory cell layer being stacked on the first substrate in a direction perpendicular or approximately perpendicular to a surface of the first substrate, the second substrate having an amplifier circuit for writing or reading data in the first memory cell, and the first peripheral circuit and the first memory cell being electrically connected via a first through electrode provided in the second substrate and the first element layer.

[0011] In one aspect of the present invention, the semiconductor device preferably has a first memory cell layer including a plurality of first element layers stacked in a direction perpendicular or approximately perpendicular to the surface of the first substrate.

[0012] In one aspect of the present invention, a semiconductor device is preferred which includes a first substrate provided with a second peripheral circuit having a function of driving a second memory cell, and a third substrate provided with a second memory cell layer having a second element layer having the second memory cell, wherein the first memory cell layer is provided between the first substrate and the second memory cell layer, the second memory cell has a second transistor and a second capacitor, the second transistor has a semiconductor layer having silicon in a channel formation region, and the second peripheral circuit and the second memory cell are electrically connected via second through electrodes provided in the second substrate, the third substrate, the first element layer, and the second element layer.

[0013] In one embodiment of the present invention, the semiconductor device preferably has a first substrate including a CPU, and a second memory cell having a function of retaining data retained by the CPU.

[0014] In one embodiment of the present invention, a semiconductor device is preferred which includes a first substrate provided with a second peripheral circuit having a function of driving the second memory cell, a third substrate, and a second memory cell layer having a second element layer having the second memory cell, wherein the first memory cell layer is provided between the first substrate and the second memory cell layer, the second memory cell has third to fifth transistors and a third capacitor, the third to fifth transistors have a semiconductor layer having a metal oxide in a channel formation region, and the second peripheral circuit and the second memory cell are electrically connected via second through electrodes provided in the second substrate, the third substrate, the first element layer, and the second element layer.

[0015] In one embodiment of the present invention, the metal oxide is a semiconductor device containing In, Ga, and Zn.

[0016] Other aspects of the present invention will be described in the following embodiments and in the drawings. [Effects of the Invention]

[0017] One embodiment of the present invention can provide a semiconductor device or the like having a novel structure. Alternatively, one embodiment of the present invention can provide a semiconductor device or the like having a novel structure that can reduce manufacturing costs in a semiconductor device that functions as a memory device utilizing an extremely small off-state current. Alternatively, one embodiment of the present invention can provide a semiconductor device or the like having a novel structure that has excellent low power consumption in a semiconductor device that functions as a memory device utilizing an extremely small off-state current. Alternatively, one embodiment of the present invention can provide a semiconductor device or the like having a novel structure that can reduce the size of the semiconductor device that functions as a memory device utilizing an extremely small off-state current. Alternatively, one embodiment of the present invention can provide a semiconductor device or the like having a novel structure that has excellent reliability and exhibits small fluctuations in the electrical characteristics of a transistor in a semiconductor device that functions as a memory device utilizing an extremely small off-state current.

[0018] The description of multiple effects does not preclude the existence of other effects. Furthermore, one embodiment of the present invention does not necessarily have all of the exemplified effects. Furthermore, problems, effects, and novel features of one embodiment of the present invention other than those described above will become apparent from the description and drawings of this specification. [Brief explanation of the drawings]

[0019] 1A to 1C are diagrams showing configuration examples of a semiconductor device. 2A and 2B are diagrams showing an example of the configuration of a semiconductor device. 3A to 3C are diagrams showing configuration examples of a semiconductor device. 4A and 4B are diagrams illustrating an example of the configuration of a semiconductor device. 5A to 5D are diagrams showing configuration examples of a semiconductor device. 6A and 6B are diagrams illustrating an example of the configuration of a semiconductor device. 7A to 7C are diagrams showing configuration examples of a semiconductor device. 8A and 8B are diagrams illustrating an example of the configuration of a semiconductor device. 9A and 9B are diagrams illustrating an example of the configuration of a semiconductor device. 10A to 10C are diagrams showing configuration examples of a semiconductor device. FIG. 11 is a diagram illustrating a configuration example of a semiconductor device. FIG. 12 is a diagram illustrating a configuration example of a semiconductor device. 13A and 13B are diagrams illustrating an example of the configuration of a semiconductor device. FIG. 14 is a diagram illustrating a configuration example of a semiconductor device. FIG. 15 is a diagram illustrating a configuration example of a semiconductor device. 16A and 16B are diagrams illustrating an example of the configuration of a semiconductor device. 17A and 17B are diagrams illustrating an example of the configuration of a semiconductor device. FIG. 18 is a schematic cross-sectional view showing a configuration example of a semiconductor device. FIG. 19 is a schematic cross-sectional view showing a configuration example of a semiconductor device. FIG. 20 is a block diagram illustrating a configuration example of a semiconductor device. FIG. 21 is a conceptual diagram showing a configuration example of a semiconductor device. 22A and 22B are schematic diagrams illustrating an example of an electronic component. FIG. 23 is a diagram illustrating an example of an electronic device. DETAILED DESCRIPTION OF THE INVENTION

[0020] The following describes an embodiment of the present invention. However, one embodiment of the present invention is not limited to the following description, and it will be readily understood by those skilled in the art that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, one embodiment of the present invention should not be interpreted as being limited to the description of the embodiment shown below.

[0021] In this specification, the ordinal numbers "first," "second," and "third" are used to avoid confusion between components. Therefore, they do not limit the number of components. Furthermore, they do not limit the order of the components. For example, a component referred to as "first" in one embodiment of this specification may be a component referred to as "second" in another embodiment or in the claims. For example, a component referred to as "first" in one embodiment of this specification may be omitted in another embodiment or in the claims.

[0022] In the drawings, the same elements or elements having similar functions, elements made of the same material, or elements formed at the same time may be given the same reference numerals, and repeated description thereof may be omitted.

[0023] In this specification, for example, the power supply potential VDD may be abbreviated to potential VDD, VDD, etc. This also applies to other components (for example, signals, voltages, circuits, elements, electrodes, wiring, etc.).

[0024] Furthermore, when the same symbol is used for multiple elements, and particularly when it is necessary to distinguish between them, the symbol may be accompanied by an identifying symbol such as "_1", "_2", "[n]", or "[m,n]". For example, the second wiring GL is written as wiring GL[2].

[0025] (Embodiment 1) 1A to 1C , a configuration example of a semiconductor device according to one embodiment of the present invention will be described. Note that the semiconductor device is a device utilizing semiconductor characteristics, such as a circuit including a semiconductor element (a transistor, a diode, a photodiode, or the like) or a device having the circuit. The semiconductor device described in this embodiment functions as a memory device using a transistor with extremely low off-state current.

[0026] FIG. 1A is a schematic cross-sectional view of a semiconductor device described in this embodiment.

[0027] 1A includes a peripheral circuit 20 provided on a substrate 25, and memory cell layers 31_1 to 31_N each including a plurality of memory cells 40_1 to 40_N (N is an integer) that form a memory cell array. The memory cell layers 31_1 to 31_N may be collectively referred to as a memory cell layer 30.

[0028] Although the substrate 25 on which the peripheral circuit 20 is provided is described as a silicon substrate, this embodiment is not limited to this. The silicon substrate refers to a substrate using silicon as a semiconductor material, for example, a substrate made of single crystal silicon. The substrate is not limited to silicon, and may be made of materials such as Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), etc.

[0029] The peripheral circuit 20 includes circuits for outputting signals for driving the memory cells 40_1 to 40_N, such as a row driver and a column driver, etc. The peripheral circuit 20 may also be called a control circuit, a drive circuit, or a circuit.

[0030] A row driver is a circuit that outputs signals to word lines to drive memory cells. Word lines transmit word signals to memory cells. A row driver is sometimes called a word line side drive circuit. The row driver includes a decoder circuit and a buffer circuit for selecting a word line according to a specified address. A column driver is a circuit that outputs signals to bit lines to drive memory cells, outputs data to be written to the memory cells, and amplifies data read from the memory cells to the bit lines. The bit lines transmit data to the memory cells. A column driver is sometimes called a bit line side drive circuit. The column driver includes a sense amplifier, a precharge circuit, a decoder circuit for selecting a bit line according to a specified address, and so on.

[0031] It is preferable that the peripheral circuit 20 drives the memory cells 40_1 to 40_N at high speed. Therefore, it is preferable that the peripheral circuit 20 has transistors that operate at high speed. The transistors included in the peripheral circuit 20 are preferably transistors with excellent field-effect mobility and whose channel formation region has silicon (Si transistors).

[0032] Each of the memory cell layers 31_1 to 31_N has an element layer 51 and a substrate 52. The element layer 51 is a layer having elements such as transistors and capacitors. Memory cells 40_1 to 40_N are provided in the element layer 51 of each of the memory cell layers 31_1 to 31_N. Although two memory cells 40_1 to 40_N are illustrated in the element layer 51, three or more memory cells may actually be provided.

[0033] The memory cell layers 31_1 to 31_N are stacked in a direction perpendicular or approximately perpendicular to the surface of the substrate 25. In other words, the element layer 51 and the substrate 52 are stacked in a direction perpendicular or approximately perpendicular to the surface of the substrate 25. This configuration allows for an increase in the number of memory cells 40_1 to 40_N arranged per unit area, thereby increasing memory density. In the cross-sectional view of FIG. 1A, the direction perpendicular or approximately perpendicular to the surface of the substrate 25 is defined as the z-axis direction in order to explain the arrangement of each component. For ease of understanding, the z-axis direction may be referred to as the direction perpendicular to the surface of the substrate 25 in the specification. Note that "approximately perpendicular" refers to an arrangement at an angle of 85 degrees or more and 95 degrees or less.

[0034] The through electrodes 54 provided in the memory cell layers 31_1 to 31_N and the metal bumps 53 provided between the through electrodes 54 function as wiring for electrically connecting the peripheral circuit 20 and the memory cells 40_1 to 40_N. The through electrodes 54 and the metal bumps 53 functioning as wiring can be provided in a direction perpendicular or approximately perpendicular to the surface of the substrate 25, thereby shortening the distance between the peripheral circuit 20 and the memory cells 40_1 to 40_N. The through electrodes 54 and the metal bumps 53 can function as bit lines for writing or reading data to or from the memory cells 40_1 to 40_N, or as word lines for selecting the memory cells 40_1 to 40_N.

[0035] 1B schematically illustrates data signals Data between the peripheral circuit 20 and the memory cells 40_1 to 40_N. The semiconductor device 10A in FIG. 1A can be configured to input and output data signals Data between the peripheral circuit 20 and the memory cells 40_1 to 40_N via through electrodes 54 provided in an element layer 51 and a substrate 52, and metal bumps 53 provided between the through electrodes 54. As described above, the through electrodes 54 and metal bumps 53 functioning as wiring can shorten the distance between the peripheral circuit 20 and the memory cells 40_1 to 40_N. Therefore, the peripheral circuit 20 can input and output data signals Data not only between the memory cell layer 31_1 in the lower layer, but also between the memory cell layer 31_N in the upper layer.

[0036] The through electrodes 54 provided to penetrate the substrate 52 and the element layer 51 of the memory cell layers 31_1 to 31_N can be formed using through electrode technology such as TSV (Through Silicon Via). The through electrodes 54 provided to penetrate each of the memory cell layers 31_1 to 31_N can be connected via metal bumps 53 (also called microbumps) provided between the memory cell layers 31_1 to 31_N. The through electrodes 54 of each of the memory cell layers 31_1 to 31_N may be connected using Cu-Cu bonding instead of using the metal bumps 53. Cu-Cu bonding is a technology that achieves electrical conductivity by connecting Cu (copper) pads together. Alternatively, the through electrodes 54 may be directly connected to each other without using Cu (copper) pads.

[0037] FIG. 1C illustrates a circuit configuration of a memory cell applicable to the memory cells 40_1 to 40_N. The memory circuit 40p illustrated in FIG. 1C includes a transistor 41 and a capacitor 42. One of the source and the drain of the transistor 41 is connected to a wiring BL. The gate of the transistor 41 is connected to a wiring WL. The other of the source and the drain of the transistor 41 is connected to the capacitor 42.

[0038] The transistor 41 is preferably an OS transistor. An OS transistor has an extremely low off-state current. Therefore, charge corresponding to data written to the memory cells 40_1 to 40_N can be held in the capacitor 42 for a long time. That is, data once written in the memory cells 40_1 to 40_N can be held for a long time. Therefore, the frequency of data refresh can be reduced, and the power consumption of the semiconductor device of one embodiment of the present invention can be reduced.

[0039] The memory circuit 40p including the transistor 41 can be called a dynamic oxide semiconductor random access memory (DOSRAM) that uses an OS transistor as a memory. Because it can be configured with one transistor and one capacitor, high-density memory can be achieved. Furthermore, the use of an OS transistor can extend the data retention period.

[0040] Although the transistor 41 is illustrated as a transistor having a top-gate structure or a bottom-gate structure without a back gate electrode, the structure of the transistor 41 is not limited thereto. The transistor 41 preferably has a back gate electrode. The threshold voltage of the transistor 41 can be controlled by controlling the potential applied to the back gate electrode. This can increase the on-current and decrease the off-current of the transistor 41, for example.

[0041] The memory cells 40_1 to 40_N using OS transistors can be freely arranged in an element layer having OS transistors, which facilitates integration, thereby increasing the number of memory cells arranged per unit area and increasing memory density.

[0042] Furthermore, OS transistors have superior electrical characteristics to Si transistors in high-temperature environments. Specifically, they have a large on-current / off-current ratio even at high temperatures of 125°C to 150°C, enabling them to perform favorable switching operations. Furthermore, OS transistors operate favorably at temperatures ranging from -40°C to 190°C. In other words, OS transistors have excellent heat resistance. This is superior to the heat resistance of phase-change memory (PCM) (-40°C to 150°C), resistance random access memory (ReRAM) (-40°C to 125°C), and magnetoresistive random access memory (MRAM) (-40°C to 105°C).

[0043] Although the configuration in which the memory cell layer 30 is bonded to the substrate 25 using the metal bumps 53 and the through electrodes 54 has been described with reference to FIG. 1A, other configurations may also be used.

[0044] 2A and 2B, a configuration will be described in which the electrodes of the peripheral circuit 21 included in the substrate 25 and the electrodes of the element layer 51 included in the memory cell layer 30 are connected by the through electrodes 54. In FIG.

[0045] 2A is a schematic cross-sectional view of a memory cell layer 31 applicable to the memory cell layers 31_1 to 31_N in FIG. 1A. 2A illustrates an element layer 51 provided in contact with a substrate 52. 2A also illustrates a bonding layer 57 on the element layer 51.

[0046] The element layer 51 includes an OS transistor M OS , and electrode M Cu Electrode M Cu is an electrode that is connected when forming the through electrode 54. Cu When copper (Cu) is used as the electrode M, it is effective to cover the electrode surface with gold (Au) in order to prevent the surface from being oxidized when forming the through electrode 54.Cu It is also possible to use a conductor other than copper as the insulating layer.

[0047] The bonding layer 57 is made of silicon oxide (SiO ), which flattens the bonding surface with the substrate 25 and allows hydroxyl groups on the bonding layer 57 and the surface of the substrate 25 to form bonds with each other. X ) is suitable. Silicon oxide (SiO X ) is preferable because it can improve the flatness of the surface compared to silicon nitride (SiN) etc. Note that the layer formed on the surface of the substrate 25 and the bonding layer 57 are each made of silicon oxide (SiO X ) and the flatness of the silicon oxide is improved, the hydroxyl groups (OH groups) on the surface of the silicon oxide formed on the surface of the substrate 25 and the hydroxyl groups (OH groups) on the surface of the silicon oxide of the bonding layer 57 are bonded by van der Waals forces, and subsequent heat treatment may generate Si-O-Si bonds and HO molecules.

[0048] 2B is a cross-sectional view showing a case where the memory cell layer 31 of FIG. 2A is attached face-down to the substrate 25 (face-down bonding). The substrate 25 is a substrate for the Si transistor M Si , and electrode M Cu The through electrodes 54 provided in the element layer 51 and the substrate 52 are connected to the electrodes M of the memory cells 40. Cu and the electrode M of the peripheral circuit 21. Cu and is provided to connect.

[0049] By improving the flatness of the bonding layer 57, the bonding between the substrate 25 and the memory cell layer 31 can be performed within a range of 350°C to 450°C as an upper limit, without exposing them to high temperatures of 1000°C or higher. In other words, the bonding between the substrate 25 and the memory cell layer 31 can be performed without exposing them to high temperatures. Therefore, the deterioration of the OS transistor M caused by exposing the element layer 51 to high temperatures can be prevented. OSIn addition, since the Si transistor is not exposed to high temperatures when bonding the substrate 25 and the memory cell layer 31, copper wiring can be used.

[0050] The above-described bonding of the substrate 25 and the memory cell layer 31 is effective not only for bonding the memory cell layer 31 having an OS transistor, but also for bonding the memory cell layer having a Si transistor. Since the bonding temperature can be set within a range of 350° C. to 450° C., it is also possible to alternately bond the memory cell layers having Si transistors and the memory cell layers having OS transistors.

[0051] In one embodiment of the present invention, OS transistors with extremely low off-state current are used as transistors provided in each element layer. Therefore, the frequency of refreshing data stored in a memory cell can be reduced, resulting in a semiconductor device with low power consumption. OS transistors can be stacked and can be repeatedly fabricated in the vertical direction using the same manufacturing process, thereby reducing manufacturing costs. In another embodiment of the present invention, transistors constituting a memory cell can be arranged vertically rather than planarly, thereby improving memory density and miniaturizing the device. Furthermore, OS transistors exhibit less fluctuation in electrical characteristics than Si transistors even under high-temperature conditions. Therefore, a semiconductor device can function as a highly reliable memory device with less fluctuation in the electrical characteristics of the transistors when stacked and integrated.

[0052] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments.

[0053] (Embodiment 2) In this embodiment, a configuration example of a semiconductor device according to one embodiment of the present invention will be described, which is different from that of Embodiment 1. Note that the detailed description of the same part as in Embodiment 1 will be omitted as the description therein is incorporated by reference.

[0054] FIG. 3A is a schematic cross-sectional view of a semiconductor device described in this embodiment. A semiconductor device 10B shown in FIG. 3A has another memory cell layer 60 above the memory cell layer 30 described in the first embodiment. The other memory cell layer 60 has, as an example, memory cell layers 61_1 and 61_N (memory cell layers 61_1 and 61_2 are shown) in which memory cells 70_1 and 70_N (memory cells 70_1 and 70_2 are shown). In FIG. 3A, a substrate 25 has a peripheral circuit 21 in addition to the peripheral circuit 20.

[0055] The peripheral circuit 21 includes circuits such as a row driver and a column driver for outputting signals for driving the memory cells 70_1 to 70_N. It is preferable that the peripheral circuit 21 drives the memory cells 70_1 to 70_N at high speed. Therefore, it is preferable that the peripheral circuit 21 has transistors that operate at high speed. It is preferable that the transistors included in the peripheral circuit 21 are transistors (Si transistors) that have excellent field-effect mobility and have silicon in their channel formation regions. The peripheral circuit 21 may also be called a control circuit, a drive circuit, or a circuit.

[0056] Each of the memory cell layers 61_1 to 61_N includes an element layer 62 and a substrate 63. The memory cell layers 61_1 to 61_N are stacked in a direction perpendicular or approximately perpendicular to the surface of the substrate 25. This configuration allows the number of memory cells 70_1 to 70_N arranged per unit area to be increased, thereby increasing memory density. In the schematic cross-sectional view shown in FIG. 3A, the z-axis direction, which is perpendicular or approximately perpendicular to the surface of the substrate 25, is defined in order to explain the arrangement of each component.

[0057] A portion of the through electrodes 54 provided in the memory cell layers 31_1 to 31_N, a through electrode 54A provided in the memory cell layers 61_1 to 61_N, and a portion of the metal bump 53 provided between the through electrodes 54A and the through electrodes 54 function as wiring for electrically connecting the peripheral circuit 21 and the memory cells 70_1 to 70_N. The through electrodes 54, the through electrodes 54A, and the metal bump 53 functioning as wiring can be provided in a direction perpendicular or approximately perpendicular to the surface of the substrate 25, thereby shortening the distance between the peripheral circuit 21 and the memory cells 70_1 to 70_N. The through electrodes 54, the through electrodes 54A, and the metal bump 53 can function as bit lines for writing or reading data to or from the memory cells 70_1 to 70_N, or as word lines for selecting the memory cells 70_1 to 70_N.

[0058] FIG. 3B illustrates a circuit configuration of a memory cell applicable to the memory cells 70_1 to 70_N. The memory circuit 70p illustrated in FIG. 3B includes transistors 71 to 73 and a capacitor 74. One of the source or the drain of the transistor 71 is connected to a wiring BL. The gate of the transistor 71 is connected to a wiring WL. The other of the source or the drain of the transistor 71 is connected to the gate of a transistor 72 and the capacitor 74. The other of the source or the drain of the transistor 72 is connected to a wiring BL. The other of the source or the drain of the transistor 72 is connected to one of the source or the drain of a transistor 73. The gate of the transistor 73 is connected to a wiring RL that supplies a read signal.

[0059] 3B illustrates a wiring BL shared between writing and reading data, different wirings may be used as the wiring BL. For example, the transistors 71 and 72 may be connected to different wirings BL (a wiring RBL for reading data and a wiring WBL for writing data). Although the memory circuit in FIG. 3B illustrates a memory circuit having three transistors, the transistor 73 may be omitted, and the memory circuit may have two transistors.

[0060] The transistor 71 is preferably an OS transistor. OS transistors have extremely low off-state current. Therefore, charge corresponding to data written to the memory cells 70_1 to 70_N can be retained in the gate of the transistor 72 and the capacitor 74 for a long time. In other words, data once written in the memory cells 70_1 to 70_N can be retained for a long time. That is, the memory circuit 70p has nonvolatile characteristics. In this specification, a memory cell configured with the memory circuit 70p having an OS transistor is referred to as a nonvolatile oxide semiconductor random access memory (NOSRAM). Since NOSRAM rewrites data by charging and discharging a capacitor, in principle, there is no limit to the number of rewrites, and data can be written and read with low energy. Furthermore, the simple circuit configuration of the memory cell facilitates large capacity. Therefore, NOSRAM is a memory with large capacity, low power consumption, and high rewrite endurance.

[0061] NOSRAM can store data in three or more levels, allowing it to store a larger amount of data per memory cell than DOSRAM. Furthermore, NOSRAM can read written data nondestructively, making it suitable for long-term data retention. Meanwhile, DOSRAM destructively reads written data, making it suitable for use in memory hierarchies with high write and read frequencies. Therefore, it is preferable to position the memory cell layer 30, which has DOSRAM memory cells, closer to the substrate 25 than the memory cell layer 60, which has NOSRAM memory cells. In other words, it is preferable to position the memory cell layer 30 between the substrate 25 and the memory cell layer 60.

[0062] The data stored in the memory cells can be transferred to the NOSRAM as needed depending on the operating conditions. For example, as shown in FIG. 3C, the data signal Data stored in the memory cells 40_1 to 40_N can be transferred to the memory cells 70_1 and 70_2 via the peripheral circuits 20 and 21.

[0063] In one embodiment of the present invention, OS transistors with extremely low off-state current are used as transistors provided in each element layer. Therefore, the frequency of refreshing data stored in a memory cell can be reduced, resulting in a semiconductor device with low power consumption. OS transistors can be stacked and can be repeatedly fabricated in the vertical direction using the same manufacturing process, thereby reducing manufacturing costs. In another embodiment of the present invention, transistors constituting a memory cell can be arranged vertically rather than planarly, thereby improving memory density and miniaturizing the device. Furthermore, OS transistors exhibit less fluctuation in electrical characteristics than Si transistors even under high-temperature conditions. Therefore, a semiconductor device can function as a highly reliable memory device with less fluctuation in the electrical characteristics of the transistors when stacked and integrated.

[0064] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments.

[0065] (Embodiment 3) In this embodiment, a configuration example of a semiconductor device according to one aspect of the present invention will be described, which is different from that of Embodiments 1 and 2. Note that detailed description of the same parts as those of Embodiments 1 and 2 will be omitted, as the description thereof is incorporated herein by reference.

[0066] 4A is a schematic cross-sectional view of a memory cell layer 31A applicable to a semiconductor device of one embodiment of the present invention. The memory cell layer 31A illustrated in FIG. 4A has a configuration in which a plurality of memory cells 40_1 in the element layer 51 are stacked in the z-axis direction in the memory cell layer 31_1 described in Embodiment 1 or 2. Note that while FIG. 4A illustrates the memory cell layer 31_1, the same applies to the memory cell layers 31_2 to 31_N. Note that a wiring connecting the memory cells 40_1 to each other in the element layer 51 may be referred to as a wiring LBL (local bit line). The wiring LBL is a wiring made of a conductor provided between layers of the element layer 51, unlike the through electrode 54 described in the above embodiment.

[0067] Fig. 4B is a cross-sectional view of a semiconductor device according to the present embodiment. The semiconductor device 10C shown in Fig. 4B has a configuration in which the configuration of the memory cell layer 31A described in Fig. 4A is applied to each of the memory cell layers 31_1 to 31_N. This configuration increases the number of memory cells per unit area and reduces the number of metal bumps 53 and through electrodes 54, thereby reducing manufacturing costs and increasing memory density.

[0068] In one embodiment of the present invention, OS transistors with extremely low off-state current are used as transistors provided in each element layer. Therefore, the frequency of refreshing data stored in a memory cell can be reduced, resulting in a semiconductor device with low power consumption. OS transistors can be stacked and can be repeatedly fabricated in the vertical direction using the same manufacturing process, thereby reducing manufacturing costs. In another embodiment of the present invention, transistors constituting a memory cell can be arranged vertically rather than planarly, thereby improving memory density and miniaturizing the device. Furthermore, OS transistors exhibit less fluctuation in electrical characteristics than Si transistors even under high-temperature conditions. Therefore, a semiconductor device can function as a highly reliable memory device with less fluctuation in the electrical characteristics of the transistors when stacked and integrated.

[0069] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments.

[0070] (Fourth embodiment) In this embodiment, a structural example of a semiconductor device according to one embodiment of the present invention will be described, which is different from those in Embodiments 1 to 3. Note that the description overlapping with those in Embodiments 1 to 3 will be incorporated and will not be described in detail again.

[0071] FIG. 5A is a schematic cross-sectional view of a memory cell layer 31B applicable to a semiconductor device of one embodiment of the present invention. The memory cell layer 31B illustrated in FIG. 5A has a configuration in which a peripheral circuit 20_1 (peripheral circuits 20_1 to 20_N) capable of performing part of the functions of the peripheral circuit 20 in the memory cell layer 31_1 (memory cell layers 31_1 to 31_N) described in any of Embodiments 1 to 3 is provided on a substrate 52. Note that while FIG. 5A illustrates an example in which the configuration is applied to the memory cell layer 31_1, the same applies to the memory cell layers 31_2 to 31_N. Note that a wiring connecting the peripheral circuit 20_1 provided on the substrate 52 to the memory cell 40_1 in the element layer 51 may be referred to as a wiring LBL (local bit line). The wiring LBL is a wiring made of a conductor provided between the substrate 52 and the element layer 51, similar to the wiring LBL described in Embodiment 3. The peripheral circuit 20_1 (peripheral circuits 20_1 to 20_N) can be a circuit such as a sense amplifier having a function of amplifying a signal in order to perform a part of the function of the peripheral circuit 20, for example, to write or read data.

[0072] Fig. 5B is a cross-sectional view of a semiconductor device according to the present embodiment. A semiconductor device 10D shown in Fig. 5B has a configuration in which the configuration of the memory cell layer 31B described in Fig. 5A is applied to the memory cell layers 31_1 to 31_N.

[0073] When the number of memory cell layers 31_1 to 31_N is, for example, 100 or more, the distance between the uppermost memory cell layer and the peripheral circuit 20 may be short. In this case, by providing a data amplification function in the peripheral circuits 20_1 to 20_N, it becomes possible to input and output data between the uppermost memory cell layer and the peripheral circuit 20. For example, as shown in FIG. 5C , by configuring the peripheral circuits 20_1 to 20_N to amplify the data signals Data held in the memory cells 40_1 to 40_N, it becomes possible to input and output data between the memory cells 40_1 to 40_N and the peripheral circuit 20 without a large difference in data write speed and data read speed.

[0074] 5A, a configuration may be adopted in which a plurality of memory cells 40_1 are stacked in the z-axis direction in the element layer 51. In the memory cell layer 31C shown in FIG. 5D, a peripheral circuit 20_1 is provided on the substrate 52, and a plurality of memory cells 40_1 are stacked in the z-axis direction in the element layer 51.

[0075] Although the configuration in which the memory cell layer 31B is bonded to the substrate 25 by the metal bumps 53 and the through electrodes 54 has been described with reference to FIG. 5B, other configurations may also be used.

[0076] 6A and 6B, a configuration will be described in which a through electrode 54 connects an electrode of peripheral circuit 21 included in substrate 25 to an electrode of substrate 52 included in memory cell layer 31B.

[0077] Fig. 6A is a schematic cross-sectional view of a memory cell layer 31B applicable to the memory cell layers 31_1 to 31_N in Fig. 5A. Fig. 6A illustrates an element layer 51 provided in contact with a substrate 52. Fig. 6A also illustrates a bonding layer 57 on the element layer 51.

[0078] The element layer 51 includes an OS transistor M OS It has.

[0079] The peripheral circuit 20 applicable to the peripheral circuits 20_1 to 20_N includes a Si transistor M Si and electrode M Cu Electrode M Cu is an electrode that is connected when forming the through electrode 54. Cu When copper (Cu) is used as the electrode M, it is effective to cover the electrode surface with gold (Au) in order to prevent the surface from being oxidized when forming the through electrode 54. Cu It is also possible to use a conductor other than copper as the insulating layer.

[0080] The bonding layer 57 is made of silicon oxide (SiO ), which flattens the bonding surface with the substrate 25 and allows hydroxyl groups on the bonding layer 57 and the surface of the substrate 25 to form bonds with each other. X ) is suitable.

[0081] 6B is a cross-sectional view showing a case where the memory cell layer 31B of FIG. 6A is attached face-down to the substrate 25 (face-down bonding). The substrate 25 is a substrate for attaching the Si transistor M Si , and electrode M Cu The through electrodes 54 provided in the element layer 51 and the substrate 52 are connected to the electrodes M of the peripheral circuit 20. Cu and the electrode M of the peripheral circuit 21. Cu and is provided to connect.

[0082] By improving the flatness of the bonding layer 57, the bonding between the substrate 25 and the memory cell layer 31B can be performed within a range of 350°C to 450°C as an upper limit, without exposing them to high temperatures of 1000°C or higher. In other words, the bonding between the substrate 25 and the memory cell layer 31B can be performed without exposing them to high temperatures. Therefore, the deterioration of the OS transistor M caused by exposing the element layer 51 to high temperatures can be prevented. OS In addition, since the Si transistor is not exposed to high temperatures when bonding the substrate 25 and the memory cell layer 31B, copper wiring can be used.

[0083] The above-described bonding of the substrate 25 and the memory cell layer 31B is effective not only when bonding a memory cell layer 31B having an OS transistor and a Si transistor, but also when bonding a memory cell layer having only Si transistors, such as a memory cell layer having memory cells of a DRAM, etc. Since the bonding temperature can be set within a range of 350° C. to 450° C. as an upper limit, it is also possible to alternately bond memory cell layers having Si transistors and memory cell layers having OS transistors and Si transistors.

[0084] In one embodiment of the present invention, OS transistors with extremely low off-state current are used as transistors provided in each element layer. Therefore, the frequency of refreshing data stored in a memory cell can be reduced, resulting in a semiconductor device with low power consumption. OS transistors can be stacked and can be repeatedly fabricated in the vertical direction using the same manufacturing process, thereby reducing manufacturing costs. In another embodiment of the present invention, transistors constituting a memory cell can be arranged vertically rather than planarly, thereby improving memory density and miniaturizing the device. Furthermore, OS transistors exhibit less fluctuation in electrical characteristics than Si transistors even under high-temperature conditions. Therefore, a semiconductor device can function as a highly reliable memory device with less fluctuation in the electrical characteristics of the transistors when stacked and integrated.

[0085] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments.

[0086] (Embodiment 5) In this embodiment, a structural example of a semiconductor device according to one embodiment of the present invention will be described, which is different from those in Embodiments 1 to 4. Note that the detailed description of the same parts as those in Embodiments 1 to 4 will be omitted as they are incorporated herein.

[0087] 7A is a cross-sectional view of a semiconductor device according to the present embodiment. A memory cell layer 80 shown in FIG. 7A includes a DRAM (Dynamic Random Access Memory) having a Si transistor provided on a substrate 84. In FIG. 7A, the substrate 84 includes a peripheral circuit 81, a transistor 82, and a capacitor 83. The peripheral circuit 81 may also be referred to as a control circuit, a drive circuit, or a circuit. The transistor 82 and the capacitor 83 correspond to elements constituting a memory cell of the DRAM.

[0088] 7B is a cross-sectional view of a semiconductor device according to the present embodiment. Semiconductor device 10E shown in FIG. 7B includes memory cell layer 80, as described in FIG. 7A, above memory cell layer 30 described in the first embodiment. Memory cell layer 80 is shown as a single layer, but may be multi-layered. In FIG. 7B, substrate 25 includes peripheral circuit 22 in addition to peripheral circuit 20.

[0089] The peripheral circuit 22 includes circuits such as row drivers and column drivers for outputting signals to drive DRAM memory cells, which are composed of transistors 82 and capacitors 83 included in the memory cell layer 80. The peripheral circuit 22 preferably has transistors that operate at high speed. The transistors included in the peripheral circuit 22 are preferably transistors (Si transistors) that have excellent field-effect mobility and have silicon in their channel formation regions. The peripheral circuit 22 may also be referred to as a control circuit, a drive circuit, or a circuit.

[0090] The through electrodes 54 provided in the memory cell layers 31_1 to 31_N, a portion of the through electrodes 54B provided in the memory cell layer 80, and a portion of the metal bumps 53 provided between the through electrodes 54B and the through electrodes 54 function as wiring for electrically connecting the peripheral circuit 22 to a DRAM memory cell configured by a transistor 82 and a capacitor 83. The through electrodes 54, the through electrodes 54B, and the metal bumps 53 functioning as wiring can be provided in a direction perpendicular or approximately perpendicular to the surface of the substrate 25, thereby shortening the distance between the peripheral circuit 22 and the DRAM memory cell configured by the transistor 82 and the capacitor 83. The through electrodes 54, the through electrodes 54B, and the metal bumps 53 can function as bit lines for writing or reading data to or from the DRAM memory cell configured by the transistor 82 and the capacitor 83, or as word lines for selecting the DRAM memory cell configured by the transistor 82 and the capacitor 83.

[0091] 7B illustrates a configuration in which memory cell layer 80 having DRAM memory cells is bonded to memory cell layer 30 having DOSRAM memory cells bonded to substrate 25, but other configurations are also possible. In FIG. 7C, a configuration in which memory cell layer 30 having DOSRAM memory cells is bonded to memory cell layer 80 having DRAM memory cells, multiple layers of which are bonded to substrate 25. Furthermore, the memory cell layer provided on memory cell layer 80 may be a memory cell layer having NOSRAM memory cells instead of the memory cell layer having DOSRAM memory cells, or a memory cell layer in which a memory cell layer having NOSRAM memory cells and a memory cell layer having DOSRAM memory cells are stacked may be provided on memory cell layer 30.

[0092] DRAMs with Si transistors have a higher data transfer rate than DOSRAMs with OS transistors. Meanwhile, DOSRAMs with OS transistors can reduce the frequency of data refresh compared to DRAMs with Si transistors, which is effective in reducing power consumption. To achieve both high data transfer rate and low power consumption, the semiconductor device 10E with DRAM shown in this embodiment has a configuration in which the state of memory cells that hold data can be switched between multiple states depending on the data access state.

[0093] For example, Figure 8A shows mode D1, which stores data in DRAM, and modes DOS1 and DOS2, which store data in DOSRAM. Modes DOS1 and DOS2 have different data refresh frequencies, and mode DOS2 can further reduce power consumption by lowering the data refresh frequency compared to mode DOS1. By switching between the modes shown in Figure 8A depending on the data access status, it is possible to achieve both high data transfer speeds and low power consumption.

[0094] FIG. 8B also illustrates mode NOS1, which retains data in NOSRAM, in addition to mode D1, which retains data in DRAM, and modes DOS1 and DOS2, which retain data in DOSRAM, as shown in FIG. 8A. The memory cell layer containing NOSRAM may be provided above memory cell layer 30. Unlike DOSRAM, NOSRAM allows non-destructive readout, so when data access is low, it is effective to switch to mode NOS1, which retains data in NOSRAM. By switching between the modes shown in FIG. 8B depending on the data access status, it is possible to achieve both high data transfer speeds and low power consumption.

[0095] Here, Figure 9A illustrates a Si transistor included in the DRAM memory cell described in Figure 8A. Figure 9A shows a cross-sectional schematic diagram of a transistor 82 and a capacitor 83. The transistor 82 illustrated in Figure 9A includes a gate electrode GE embedded in a silicon substrate, a source electrode SE provided on the source side of the transistor 82, and a drain electrode DE provided on the drain side of the transistor 82. The capacitor 83 provided in the upper layer of the transistor 82 is illustrated as a capacitor with a so-called three-dimensional structure, which is provided by forming a deep hole.

[0096] 9B illustrates an OS transistor included in the memory cell of the DOSRAM described in FIG. 1C of the first embodiment. FIG. 9B shows a cross-sectional view of a transistor 41 and a capacitor 42. The transistor 41 illustrated in FIG. 9B includes a gate electrode GE provided in a region overlapping with the semiconductor layer SEM on the substrate, a source electrode SE provided on the source side of the transistor 41, and a drain electrode DE provided on the drain side of the transistor 41. The capacitor 42 provided above the transistor 41 is a so-called three-dimensional capacitor provided by forming a deep hole.

[0097] In the OS transistor of the DOSRAM, the capacitor 42 has a three-dimensional structure, but other structures are also possible. Because the off-state current of the OS transistor is extremely low, the capacitance of the capacitor can be estimated to be small. Therefore, a two-dimensional capacitor can also be used, as shown in FIG. 10A.

[0098] The off-state current of a Si transistor included in a DRAM is higher than that of an OS transistor. Therefore, in order to reduce the off-state current of a Si transistor, the channel length (L in FIG. 9A ) needs to be increased. CH ) must be long. Therefore, the transistor 82 must be provided extending in the z-axis direction, which makes it difficult to thin the substrate. In addition, the capacitance of the capacitor 83 must be large to hold the charge. Therefore, the height of the capacitor 83 (H in FIG. 9A) must be large. CAP83Therefore, in the memory cell layer having the DRAM with the Si transistor, the thickness T D becomes larger (memory cell layer 80 in FIG. 10B).

[0099] On the other hand, as described in the first embodiment, the off-state current of the OS transistor included in the DOSRAM is extremely low. Therefore, in order to reduce the off-state current, the channel length (L in FIG. 9B ) is increased by, for example, extending the transistor in the z-axis direction. CH ) does not need to be long. Therefore, the transistor 41 can make the substrate 52 in the z-axis direction thinner. In addition, the height of the capacitor 42 (H in FIG. 9B) can be made shorter to increase the capacitance of the capacitor 42. CAP42 Therefore, in the memory cell layer having the DOSRAM with the OS transistor, the thickness T DOS Therefore, in a memory cell layer having DOSRAM, the thickness of each layer can be made smaller than that of a memory cell layer having DRAM, in a configuration in which memory cell layers are stacked and bonded together.

[0100] In one embodiment of the present invention, OS transistors with extremely low off-state current are used as transistors provided in each element layer. Therefore, the frequency of refreshing data stored in a memory cell can be reduced, resulting in a semiconductor device with low power consumption. OS transistors can be stacked and can be repeatedly fabricated in the vertical direction using the same manufacturing process, thereby reducing manufacturing costs. In another embodiment of the present invention, transistors constituting a memory cell can be arranged vertically rather than planarly, thereby improving memory density and miniaturizing the device. Furthermore, OS transistors exhibit less fluctuation in electrical characteristics than Si transistors even under high-temperature conditions. Therefore, a semiconductor device can function as a highly reliable memory device with less fluctuation in the electrical characteristics of the transistors when stacked and integrated.

[0101] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments.

[0102] (Embodiment 6) In this embodiment, a structural example of a semiconductor device according to one embodiment of the present invention will be described, which has a different structure from those in Embodiments 1 to 5. Note that the description overlapping with those in Embodiments 1 to 5 will be incorporated and will not be described in detail again.

[0103] 11 is a schematic cross-sectional view of a semiconductor device described in this embodiment. The semiconductor device 10E_PU shown in Fig. 11 has a configuration in which the peripheral circuit 22 in the substrate 25 described in the fifth embodiment is replaced with a CPU 110.

[0104] The data held by the CPU 110 can be held in a DRAM memory cell configured of memory cells 40_1 to 40_N, a transistor 82, and a capacitor 83. The data held by the CPU 110 can also be configured to be held in a memory cell having an OS transistor with a circuit configuration different from that of the memory cells 40_1 to 40_N.

[0105] The CPU 110 inputs and outputs signals at high speed, and generates a lot of heat due to the current flowing through it. If a DRAM is attached to the CPU, this heat can make it difficult to retain data.

[0106] As shown in FIG. 11 , in the configuration of this embodiment, a memory cell layer 80 having a DRAM can be provided via a memory cell layer 30 having memory cells 40_1 to 40_N each having an OS transistor. Since the OS transistor has a large ratio of on-current to off-current even in a high-temperature environment, it can perform a good switching operation. In addition, the memory cell layer 80 having a DRAM can be provided away from the CPU 110 via the memory cell layer 30 having memory cells 40_1 to 40_N each having an OS transistor. Therefore, a semiconductor device can be provided that combines the characteristics of both a memory device utilizing an extremely small off-current and a memory device capable of high-speed operation, has small fluctuations in the electrical characteristics of the transistors, and is highly reliable.

[0107] Next, a description will be given of an example configuration of the CPU 110. In this embodiment, a description will be given of the CPU 110 having a CPU core capable of power gating.

[0108] 12 shows an example configuration of the CPU 110. The CPU 110 has a CPU core 200, an L1 (level 1) cache memory device (L1 Cache) 202, an L2 cache memory device (L2 Cache) 203, a bus interface unit (Bus I / F) 205, power switches 210 to 212, and a level shifter (LS) 214. The CPU core 200 has a flip-flop 220.

[0109] The CPU core 200, the L1 cache memory device 202, and the L2 cache memory device 203 are interconnected by a bus interface unit 205.

[0110] The PMU 193 generates a clock signal GCLK1 and various PG (power gating) control signals in response to interrupt signals (Interrupts) input from the outside and signals such as the SLEEP1 signal issued by the CPU 110. The clock signal GCLK1 and the PG control signals are input to the CPU 110. The PG control signals control the power switches 210 to 212 and the flip-flop 220.

[0111] Power switches 210 and 211 control the supply of voltages VDDD and VDD1 to a virtual power line V_VDD (hereinafter referred to as a V_VDD line), respectively. A power switch 212 controls the supply of a voltage VDDH to a level shifter (LS) 214. A voltage VSSS is input to the CPU 110 and PMU 193 without passing through a power switch. A voltage VDDD is input to the PMU 193 without passing through a power switch.

[0112] The voltages VDDD and VDD1 are drive voltages for the CMOS circuit. The voltage VDD1 is lower than the voltage VDDD and is the drive voltage in the sleep state. The voltage VDDH is the drive voltage for the OS transistors and is higher than the voltage VDDD.

[0113] Each of the L1 cache memory device 202, the L2 cache memory device 203, and the bus interface unit 205 has at least one power domain that can be power-gated. Each power domain that can be power-gated has one or more power switches. These power switches are controlled by a PG control signal.

[0114] The flip-flop 220 is used as a register. A backup circuit is provided in the flip-flop 220. The flip-flop 220 will be described below.

[0115] 13A shows an example of the circuit configuration of a flip-flop 220. The flip-flop 220 has a scan flip-flop 221 and a backup circuit 222. The scan flip-flop 221 is provided on the substrate 25 in FIG. 11, and the backup circuit 222 can be provided in the same layer as the memory cell layer 30.

[0116] The scan flip-flop 221 has nodes D1, Q1, SD, SE, RT, CK, and a clock buffer circuit 221A.

[0117] Node D1 is a data input node, node Q1 is a data output node, and node SD is an input node for scan test data. Node SC is an input node for signal SCE. Node CK is an input node for clock signal GCLK1. Clock signal GCLK1 is input to clock buffer circuit 221A. The analog switch of scan flip-flop 221 is connected to nodes CK1 and CKB1 of clock buffer circuit 221A. Node RT is an input node for a reset signal.

[0118] The signal SCE is a scan enable signal and is generated by the PMU 193. The PMU 193 generates signals BK and RC. The level shifter 214 level-shifts the signals BK and RC to generate signals BKH and RCH. The signal BK is a backup signal, and the signal RC is a recovery signal.

[0119] The circuit configuration of the scan flip-flop 221 is not limited to that shown in Fig. 13A, and any flip-flop available in a standard circuit library can be applied.

[0120] The backup circuit 222 includes nodes SD_IN and SN11, transistors M11 to M13, and a capacitive element C11.

[0121] The node SD_IN is an input node for scan test data and is connected to the node Q1 of the scan flip-flop 221. The node SN11 is a storage node of the backup circuit 222. The capacitive element C11 is a storage capacitor for storing the voltage of the node SN11.

[0122] The transistor M11 controls the conduction state between the node Q1 and the node SN11. The transistor M12 controls the conduction state between the node SN11 and the node SD. The transistor M13 controls the conduction state between the node SD_IN and the node SD. The on / off of the transistors M11 and M13 is controlled by a signal BKH, and the on / off of the transistor M12 is controlled by a signal RCH.

[0123] The transistors M11 to M13 are OS transistors, similar to the transistors included in the memory cell layer 31. The transistors M11 to M13 are illustrated as having back gates. The back gates of the transistors M11 to M13 are connected to a power supply line that supplies a voltage VBG1.

[0124] At least the transistors M11 and M12 are preferably OS transistors. The OS transistors have an extremely small off-state current, which prevents a voltage drop at the node SN11. Furthermore, the backup circuit 222 consumes almost no power to retain data, making it nonvolatile. Because data is rewritten by charging and discharging the capacitive element C11, the backup circuit 222 is theoretically capable of writing and reading data without any restrictions on the number of times it can be rewritten, and with low energy consumption.

[0125] It is highly preferable that all transistors in the backup circuit 222 are OS transistors. As shown in Fig. 13B, the backup circuit 222 can be stacked on a scan flip-flop 221 made up of a silicon CMOS circuit.

[0126] Since the backup circuit 222 has an extremely small number of elements compared to the scan flip-flop 221, stacking the backup circuit 222 does not require changing the circuit configuration and layout of the scan flip-flop 221. In other words, the backup circuit 222 is a highly versatile backup circuit. Furthermore, since the backup circuit 222 can be provided in the region where the scan flip-flop 221 is formed, even if the backup circuit 222 is incorporated, the area overhead of the flip-flop 220 can be reduced to zero. Therefore, providing the backup circuit 222 in the flip-flop 220 enables power gating of the CPU core 200. Because little energy is required for power gating, the CPU core 200 can be power gated with high efficiency.

[0127] By providing the backup circuit 222, a parasitic capacitance due to the transistor M11 is added to the node Q1, but since it is small compared to the parasitic capacitance due to the logic circuit connected to the node Q1, it does not affect the operation of the scan flip-flop 221. In other words, even if the backup circuit 222 is provided, the performance of the flip-flop 220 does not substantially deteriorate.

[0128] For example, a clock gating state, a power gating state, or a sleep state can be set as the low power consumption state of the CPU core 200. The PMU 193 selects the low power consumption mode of the CPU core 200 based on an interrupt signal, a signal SLEEP1, etc. For example, when transitioning from a normal operating state to a clock gating state, the PMU 193 stops generating the clock signal GCLK1.

[0129] For example, when transitioning from a normal operating state to a hibernation state, the PMU 193 performs voltage and / or frequency scaling. For example, when performing voltage scaling, the PMU 193 turns off the power switch 210 and turns on the power switch 211 to input the voltage VDD1 to the CPU core 200. The voltage VDD1 is a voltage that does not cause data to be lost in the scan flip-flop 221. When performing frequency scaling, the PMU 193 reduces the frequency of the clock signal GCLK1.

[0130] When the CPU core 200 is transitioned from the normal operation state to the power gating state, an operation is performed to back up the data of the scan flip-flop 221 to the backup circuit 222. When the CPU core 200 is returned from the power gating state to the normal operation state, an operation is performed to recover the data of the backup circuit 222 to the scan flip-flop 221.

[0131] 14 shows an example of a power gating sequence of the CPU core 200. In FIG. 14, t1 to t7 represent time. Signals PSE0 to PSE2 are control signals for the power switches 210 to 212, and are generated by the PMU 193. When the signal PSE0 is "H" / "L", the power switch 210 is on / off. The same applies to the signals PSE1 and PSE2.

[0132] Before time t1, the state is normal operation. The power switch 210 is on, and the voltage VDDD is input to the CPU core 200. The scan flip-flop 221 performs normal operation. At this time, the level shifter 214 does not need to operate, so the power switch 212 is off, and the signals SCE, BK, and RC are "L". Since the node SC is "L", the scan flip-flop 221 stores the data of the node D1. In the example of FIG. 14, at time t1, the node SN11 of the backup circuit 222 is "L".

[0133] At operation time t1, the PMU 193 stops the clock signal GCLK1 and sets the signals PSE2 and BK to "H." The level shifter 214 becomes active and outputs the signal BKH at "H" to the backup circuit 222.

[0134] The transistor M11 of the backup circuit 222 turns on, and the data at the node Q1 of the scan flip-flop 221 is written to the node SN11 of the backup circuit 222. If the node Q1 of the scan flip-flop 221 is "L", the node SN11 remains "L", and if the node Q1 is "H", the node SN11 becomes "H".

[0135] The PMU 193 sets the signals PSE2 and BK to "L" at time t2, and sets the signal PSE0 to "L" at time t3. At time t3, the state of the CPU core 200 transitions to the power gating state. Note that the signal PSE0 may also fall at the same timing as the signal BK falls.

[0136] The operation during power gating will be described. When the signal PSE0 goes to "L", the voltage of the V_VDD line drops, and the data at node Q1 is lost. Node SN11 continues to hold the data at node Q1 at time t3.

[0137] The operation during recovery will be explained below. At time t4, the PMU 193 sets the signal PSE0 to "H", transitioning from the power gating state to the recovery state. Charging of the V_VDD line begins, and when the voltage on the V_VDD line reaches VDDD (time t5), the PMU 193 sets the signals PSE2, RC, and SCE to "H".

[0138] Transistor M12 turns on, and the charge of capacitive element C11 is distributed between node SN11 and node SD. If node SN11 is "H," the voltage of node SD rises. Since node SC is "H," the data of node SC is written to the input latch circuit of scan flip-flop 221. When clock signal GCLK1 is input to node CK at time t6, the data of the input latch circuit is written to node Q1. In other words, the data of node SN11 has been written to node Q1.

[0139] At time t7, the PMU 193 sets the signals PSE2, SCE, and RC to "L," and the recovery operation ends.

[0140] The backup circuit 222 using OS transistors consumes low dynamic and static power, making it highly suitable for normally-off computing. A CPU 110 including a CPU core 200 with a backup circuit 222 using OS transistors can be called an NoffCPU (registered trademark). The NoffCPU has nonvolatile memory and can stop power supply when operation is not required. Even if the flip-flop 220 is installed, it is possible to minimize the degradation of CPU core 200 performance and the increase in dynamic power.

[0141] The CPU core 200 may have multiple power domains that can be power-gated. Each of the multiple power domains is provided with one or more power switches for controlling the input of voltage. The CPU core 200 may also have one or more power domains in which power gating is not performed. For example, a power domain in which power gating is not performed may be provided with a power gating control circuit for controlling the flip-flop 220 and the power switches 210 to 212.

[0142] The application of the flip-flop 220 is not limited to the CPU 110. In the CPU 110, the flip-flop 220 can be applied to a register provided in a power domain that is capable of power gating.

[0143] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments.

[0144] (Embodiment 7) In this embodiment, a structural example of a semiconductor device according to one embodiment of the present invention will be described, which has a different structure from those in Embodiments 1 to 5. Note that the description overlapping with those in Embodiments 1 to 5 will be incorporated and will not be described in detail again.

[0145] 15 is a cross-sectional view of a semiconductor device according to the present embodiment. The semiconductor device 10F shown in FIG. 15 has a configuration in which through electrodes 54 are provided in a state in which a plurality of memory cell layers 31_1 to 31_N, each of which is described in FIG. 1A, are stacked. That is, in the semiconductor device 10F shown in FIG. 15, the memory cells 40_1 and 40_2 included in the memory cell layer 31_1 and the memory cell layer 31_2 can be connected by the through electrodes 54 without the intervention of the metal bumps 53. This configuration increases the number of memory cells per unit area and reduces the number of metal bumps 53 and through electrodes 54, thereby reducing manufacturing costs and increasing memory density.

[0146] In one embodiment of the present invention, OS transistors with extremely low off-state current are used as transistors provided in each element layer. Therefore, the frequency of refreshing data stored in a memory cell can be reduced, resulting in a semiconductor device with low power consumption. OS transistors can be stacked and can be repeatedly fabricated in the vertical direction using the same manufacturing process, thereby reducing manufacturing costs. In another embodiment of the present invention, transistors constituting a memory cell can be arranged vertically rather than planarly, thereby improving memory density and miniaturizing the device. Furthermore, OS transistors exhibit less fluctuation in electrical characteristics than Si transistors even under high-temperature conditions. Therefore, a semiconductor device can function as a highly reliable memory device with less fluctuation in the electrical characteristics of the transistors when stacked and integrated.

[0147] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments.

[0148] (Embodiment 8) In this embodiment mode, modifications of circuits applicable to the semiconductor devices described in any of Embodiments 1 to 6 will be described with reference to FIGS. 16A and 16B. FIG.

[0149] FIG. 16A illustrates a configuration example of a semiconductor device having a memory cell layer stacked on a substrate, the semiconductor device including an amplifier circuit capable of amplifying a data signal held in the memory cell.

[0150] 16A is a block diagram of a memory cell layer 31 applicable to the memory cell layers 31_1 to 31_N described in Embodiment 1. The memory cell layer 31 has an amplifier circuit 49 between a peripheral circuit 20 provided on a substrate 52 and a plurality of memory cells 40 provided in the element layer 51.

[0151] In the schematic diagram shown in Figure 16A, the z-axis direction is defined to explain the arrangement of each component. For ease of understanding, the z-axis direction may be referred to as the direction perpendicular to the surface of the substrate 52 in the specification. In Figure 16A, in the element layer 51 provided on the substrate 52, the amplifier circuit 49 and the multiple memory cells 40 are provided by stacking transistors in the z-axis direction.

[0152] The amplifier circuit 49 is provided between the wiring LBL for connecting multiple memory cells 40 together and the wiring GBL for connecting the peripheral circuit 20 and the circuit above it. The amplifier circuit 49 has a circuit that has the function of amplifying the potential of the wiring LBL connected to the memory cell 40 and transmitting it to the wiring GBL connected to the peripheral circuit 20, and the function of transmitting the potential of the peripheral circuit 20 to the wiring LBL connected to the memory cell 40. The wiring GBL is sometimes called a global bit line. The wiring LBL is sometimes called a local bit line. The wiring LBL and the wiring GBL function as bit lines for writing or reading data to or from the memory cell. In the drawings, the wiring LBL and the wiring GBL may be illustrated with thick lines or dotted thick lines to improve visibility.

[0153] 16B shows an example of the circuit configuration of the amplifier circuit 49. The amplifier circuit 49 includes transistors 91 to 94. The transistors 91 to 94 can each be formed using an OS transistor, and are illustrated as n-channel transistors.

[0154] The transistor 91 controls the potential of the wiring GBL to correspond to the potential of the wiring LBL during a period when data is read from the memory cell 40. The transistor 92 receives a selection signal MUX at its gate and functions as a switch whose on / off state between its source and drain is controlled in accordance with the selection signal MUX. The transistor 93 receives a write control signal WE at its gate and functions as a switch whose on / off state between its source and drain is controlled in accordance with the write control signal WE. The transistor 94 receives a read control signal RE at its gate and functions as a switch whose on / off state between its source and drain is controlled in accordance with the read control signal RE. The source side of the transistor 94 is supplied with a fixed ground potential GND.

[0155] A semiconductor device according to one embodiment of the present invention can be manufactured by repeatedly providing transistors in a vertical direction on a substrate using the same manufacturing process. In one embodiment of the present invention, OS transistors constituting memory cells are arranged vertically rather than planarly, thereby improving memory density and miniaturizing the device. The memory cell layer 31 includes an amplifier circuit 49, which connects the wiring LBL to the gate of the transistor 91. Therefore, a slight potential difference in the wiring LBL can be used to read out a data signal to the wiring GBL.

[0156] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments.

[0157] (Embodiment 9) In this embodiment, an example of an integrated circuit (referred to as an IC chip) having semiconductor devices 10A to 10F is shown. The semiconductor device 10 can be made into a single IC chip by mounting multiple dies on a packaging substrate. Figures 17A and 17B show an example of the configuration.

[0158] The cross-sectional schematic diagram of an IC chip 100A shown in FIG. 17A includes a substrate 25 on a package substrate 101. For example, the IC chip 100A includes a memory cell layer in which four memory cell layers 31_1 and 31_4 are stacked on the substrate 25. The package substrate 101 is provided with solder balls 102 for connecting the IC chip 100A to a printed circuit board or the like. The memory cell layers 31_1 to 31_4 can be stacked by repeatedly forming OS transistors in an element layer 51 in contact with a substrate 52. Peripheral circuits provided on the silicon substrate can be connected to the memory cells and other circuits of the memory cell layers 31_1 to 31_4 through through electrodes 54, such as TSVs (Through Silicon Vias), that penetrate the substrate 52 and element layer 51 of each layer. The layers can be electrically connected through the through electrodes 54 that penetrate each layer and metal bumps 53 (also called microbumps) that are provided between the layers.

[0159] As another example, the cross-sectional schematic diagram of an IC chip 100B shown in FIG. 17B has a substrate 25 on a package substrate 101, and as an example, has a memory cell layer in which four memory cell layers 31_1 and 31_4 are stacked on the substrate 25. A peripheral circuit (not shown) provided on the substrate 25 and each circuit of the memory cells (not shown) having the memory cell layers 31_1 and 31_4 are bonded together using electrodes 55 and 56 provided on the substrate 52 and element layer 51 of each layer. Cu-Cu bonding can be used as a technique for electrically bonding different layers using the electrodes 55 and 56. Cu-Cu bonding is a technique for achieving electrical conduction by connecting Cu (copper) pads together.

[0160] (Embodiment 10) An example of a schematic cross-sectional view of a semiconductor device according to one embodiment of the present invention will be described below.

[0161] FIG. 18 is a diagram showing an example of a semiconductor device in which memory units 470 (memory units 470_1 to 470_m: m is an integer equal to or greater than 2; FIG. 18 illustrates the case where m=2) are stacked on an element layer 411 having circuits provided in a semiconductor substrate 311. The element layer 411 having circuits provided in the semiconductor substrate 311 corresponds to the substrate 25 having the peripheral circuits 21 and the like described in any of the above embodiments 1 to 6. The memory units 470 correspond to the memory cell layer 31 having the memory cells 40 described in any of the above embodiments 1 to 6.

[0162] 18 illustrates an example in which an element layer 411 and a plurality of memory units 470 are stacked on the element layer 411. The plurality of memory units 470 include transistor layers 413 (transistor layers 413_1 to 413_m) corresponding to the respective memory units 470 and a plurality of memory device layers 415 (memory device layers 415_1 to 415_n: n is an integer of 2 or more) on the respective transistor layers 413, which are provided on a substrate 450. Note that, in each memory unit 470, an example in which the transistor layer 413 is provided on the substrate 450 and the memory device layer 415 is provided on the transistor layer 413 is illustrated, but this embodiment is not limited to this. Alternatively, a plurality of memory device layers 415 may be provided on the substrate 450 and the transistor layer 413 may be provided on the plurality of memory device layers 415, or the memory device layers 415 may be provided above and below the transistor layer 413 on the substrate 450. The transistor layer 413 corresponds to a layer having transistors included in the amplifier circuit 49 or the like described in Embodiment 8. The memory device layer 415 corresponds to a layer having transistors included in the memory cell 40 or the like described in Embodiments 1 to 6.

[0163] The materials contained in the semiconductor substrate 311 and the substrate 450 may be selected from the group consisting of Si, Ge, SiGe, GaAs, GaAlAs, GaN, and InP.

[0164] The element layer 411 includes the transistor 300 provided over the semiconductor substrate 311 and can function as a circuit (sometimes referred to as a peripheral circuit) of the semiconductor device. Examples of the circuit include a column driver, a row driver, a column decoder, a row decoder, a sense amplifier, a precharge circuit, an amplifier circuit, a word line driver circuit, an output circuit, and a control logic circuit.

[0165] The transistor layer 413 includes a transistor 200T and can function as a circuit that controls each memory unit 470. The memory device layer 415 includes a memory device 420. The memory device 420 shown in this embodiment includes a transistor and a capacitor.

[0166] The value of m is not particularly limited, but is 2 or more and 100 or less, preferably 2 or more and 50 or less, and more preferably 2 or more and 10 or less. The value of n is not particularly limited, but is 2 or more and 100 or less, preferably 2 or more and 50 or less, and more preferably 2 or more and 10 or less. The product of m and n is 4 or more and 256 or less, preferably 4 or more and 128 or less, and more preferably 4 or more and 64 or less.

[0167] 18 is a cross-sectional view of a transistor 200T included in the memory unit and a transistor included in the memory device 420 in the channel length direction.

[0168] 18 , a transistor 300 is provided on a semiconductor substrate 311, and a transistor layer 413 and a memory device layer 415 included in a memory unit 470 are provided on the transistor 300. A transistor 200T included in the transistor layer 413 and a memory device 420 included in the memory device layer 415 within one memory unit 470 are electrically connected by a plurality of conductors 424. The transistor 300 and the transistor 200T included in the transistor layer 413 in each memory unit 470 are electrically connected by conductors 426, 427, and 430. Furthermore, the conductor 426 is preferably electrically connected to the transistor 200T via a conductor 428 electrically connected to any one of the source, drain, and gate of the transistor 200T. The conductor 424 is preferably provided in each layer of the memory device layer 415. The conductor 427 is provided on the top layer of each memory unit 470 and is electrically connected to the conductor 426 and the conductor 430 .

[0169] The material contained in the conductor 426, the conductor 427, and the conductor 430 can be selected from Cu, W, Ti, Ta, and Al.

[0170] 18 shows an example in which the substrate 450 of the memory unit 470 is provided on the transistor 300 side, but the present embodiment is not limited to this. As shown in FIG. 19, the memory unit 470 may be provided so that the memory device layer 415 is provided on the transistor 300 side.

[0171] In FIG. 18, electrical conductor 426 is provided through memory device layer 415 , and electrical conductor 430 is provided through memory device layer 415 , transistor layer 413 , and substrate 450 .

[0172] 19, conductor 426 is provided to penetrate through substrate 450 and transistor layer 413, and conductor 430 is provided to penetrate through substrate 450, transistor layer 413, and memory device layer 415.

[0173] To prevent leakage between the conductors 426 and 430, it is preferable that an insulator be provided on each side.

[0174] As will be described in detail later, an insulator that suppresses the permeation of impurities such as water or hydrogen or oxygen is preferably provided on the side surfaces of the conductor 424 and the conductor 426. As such an insulator, for example, silicon nitride, aluminum oxide, or silicon nitride oxide can be used.

[0175] The memory device 420 has a transistor and a capacitance on its side, and the transistor can have a structure similar to that of the transistor 200T included in the transistor layer 413.

[0176] Here, in the transistor 200T, a metal oxide functioning as an oxide semiconductor (hereinafter also referred to as an oxide semiconductor) is preferably used for a semiconductor including a region where a channel is formed (hereinafter also referred to as a channel formation region).

[0177] As the oxide semiconductor, for example, a metal oxide such as In-M-Zn oxide (wherein the element M is one or more elements selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc.) may be used. Alternatively, as the oxide semiconductor, indium oxide, In-Ga oxide, or In-Zn oxide, that is, an oxide semiconductor containing In, Ga, and Zn, may be used. Note that an oxide semiconductor with a high indium content can increase the on-state current, field-effect mobility, and the like of a transistor.

[0178] The transistor 200T using an oxide semiconductor for a channel formation region has extremely low leakage current in an off-state, and therefore can provide a low-power semiconductor device. Furthermore, since an oxide semiconductor can be deposited by a sputtering method or the like, it can be used for the transistor 200T that constitutes a highly integrated semiconductor device.

[0179] On the other hand, the electrical characteristics of a transistor using an oxide semiconductor tend to fluctuate due to impurities and oxygen vacancies in the oxide semiconductor, and the transistor tends to have normally-on characteristics (characteristics in which a channel exists and current flows through the transistor even when no voltage is applied to the gate electrode).

[0180] Therefore, it is preferable to use an oxide semiconductor having a low impurity concentration and a low density of defect states. Note that in this specification and the like, an oxide semiconductor having a low impurity concentration and a low density of defect states is referred to as a highly purified intrinsic or substantially highly purified intrinsic.

[0181] Therefore, it is preferable to reduce the impurity concentration in the oxide semiconductor as much as possible. Note that examples of impurities in the oxide semiconductor include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0182] In particular, hydrogen as an impurity contained in oxide semiconductors creates oxygen vacancies (V O In addition, defects in which hydrogen enters the oxygen vacancy (hereinafter referred to as V O H.) may generate carrier electrons. In addition, some of the hydrogen may react with oxygen, which bonds with metal atoms, generating carrier electrons.

[0183] Therefore, a transistor using an oxide semiconductor containing a large amount of hydrogen is likely to have normally-on characteristics. Furthermore, since hydrogen in an oxide semiconductor is easily moved by stress such as heat or an electric field, the reliability of the transistor may be reduced if the oxide semiconductor contains a large amount of hydrogen.

[0184] Therefore, the oxide semiconductor used in the transistor 200T is preferably a high-purity intrinsic oxide semiconductor in which impurities such as hydrogen and oxygen vacancies are reduced.

[0185] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments.

[0186] (Embodiment 11) In this embodiment, details of the peripheral circuit 20 having a circuit for driving the memory cell array including the memory cells 40 in the semiconductor device 10 described in any of the first to sixth embodiments will be described.

[0187] 20 is a block diagram showing an example of the configuration of a semiconductor device functioning as a memory device. The semiconductor device 10s includes a peripheral circuit 20 and a memory cell array 40MA. The peripheral circuit 20 includes a row decoder 571, a word line driver circuit 572, a column driver 575, an output circuit 573, and a control logic circuit 574.

[0188] The column driver 575 includes a column decoder 581, a precharge circuit 582, an amplifier circuit 583, and a write circuit 584. The precharge circuit 582 has a function of precharging the wiring BL and the like. The amplifier circuit 583 has a function of amplifying a data signal read from the wiring BL. The amplified data signal is output to the outside of the semiconductor device 10s via the output circuit 573 as a digital data signal RDATA.

[0189] The semiconductor device 10s is supplied with a low power supply voltage (VSS), a high power supply voltage (VDD) for the peripheral circuit 20, and a high power supply voltage (VIL) for the memory cell array 40MA from the outside as power supply voltages.

[0190] Furthermore, control signals (CE, WE, RE), an address signal ADDR, and a data signal WDATA are input from the outside to the semiconductor device 10s. The address signal ADDR is input to a row decoder 571 and a column decoder 581, and WDATA is input to a write circuit 584.

[0191] The control logic circuit 574 processes external input signals (CE, WE, RE) to generate control signals for the row decoder 571 and column decoder 581. CE is a chip enable signal, WE is a write enable signal, and RE is a read enable signal. The signals processed by the control logic circuit 574 are not limited to these, and other control signals may be input as needed. For example, a control signal for determining a defective bit may be input, and a data signal read from the address of a specific memory cell may be identified as a defective bit.

[0192] It should be noted that the above-mentioned circuits and signals can be appropriately selected or omitted as required.

[0193] Generally, various storage devices (memories) are used in semiconductor devices such as computers depending on the application. Figure 21 shows various storage devices by layer. The higher the layer, the faster the access speed required, while the lower the layer, the larger the storage capacity and recording density required. Figure 21 shows, from the top layer, memories embedded as registers in arithmetic processing units such as CPUs, SRAM (Static Random Access Memory), DRAM (Dynamic Random Access Memory), and 3D NAND memory.

[0194] The memory embedded as a register in a CPU or other processing unit is frequently accessed by the processing unit because it is used to temporarily store the results of calculations. Therefore, a faster operating speed is required than a larger memory capacity. Registers also have the function of storing setting information for the processing unit.

[0195] SRAM is used, for example, in caches. Caches have the function of storing a copy of the information stored in main memory. By storing copies of frequently used data in the cache, access speed to the data can be increased.

[0196] DRAM is used, for example, as main memory. Main memory has the function of storing programs, data, etc. read from storage. The recording density of DRAM is approximately 0.1 to 0.3 Gbit / mm 2 is.

[0197] 3D NAND memory is used, for example, in storage. Storage has the function of storing data that needs to be stored for a long period of time, or various programs used by processing units. Therefore, storage requires a large memory capacity and high recording density rather than an operating speed. The recording density of memory devices used in storage is approximately 0.6 to 6.0 Gbit / mm 2 is.

[0198] A semiconductor device functioning as a memory device according to one embodiment of the present invention has high operating speed and can retain data for a long period of time. The semiconductor device according to one embodiment of the present invention can be suitably used as a semiconductor device located in a boundary region 901 including both a layer where a cache is located and a layer where a main memory is located. The semiconductor device according to one embodiment of the present invention can also be suitably used as a semiconductor device located in a boundary region 902 including both a layer where a main memory is located and a layer where a storage is located.

[0199] (Embodiment 12) This embodiment mode will show examples of electronic components and electronic devices in which the semiconductor device or the like described in the above embodiment mode is incorporated.

[0200] <Electronic components> First, an example of an electronic component incorporating the semiconductor device 10 and the like will be described with reference to FIGS. 22A and 22B.

[0201] 22(A) shows a perspective view of an electronic component 700 and a substrate (mounting substrate 704) on which the electronic component 700 is mounted. The electronic component 700 shown in FIG. 22(A) has a semiconductor device 10 in which a memory cell layer 30 is stacked on a silicon substrate 25 in a mold 711. The semiconductor devices 10A to 10F described in the first embodiment can be used as the semiconductor device 10. In order to show the inside of the electronic component 700, part of it is not shown in FIG. 22A. The electronic component 700 has lands 712 on the outside of the mold 711. The lands 712 are electrically connected to electrode pads 713, and the electrode pads 713 are electrically connected to the semiconductor device 10 by wires 714. The electronic component 700 is mounted on, for example, a printed circuit board 702. A plurality of such electronic components are combined and electrically connected on the printed circuit board 702 to complete the mounting substrate 704.

[0202] 22B shows a perspective view of electronic component 730. Electronic component 730 is an example of a SiP (System in Package) or MCM (Multi Chip Module). Electronic component 730 has an interposer 731 provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and multiple semiconductor devices 10 provided on interposer 731.

[0203] The electronic component 730 shows an example in which the semiconductor device 10 is used as a high bandwidth memory (HBM). The semiconductor device 735 can be an integrated circuit (semiconductor device) such as a CPU, a GPU, or an FPGA.

[0204] The package substrate 732 can be a ceramic substrate, a plastic substrate, a glass epoxy substrate, or the like. The interposer 731 can be a silicon interposer, a resin interposer, or the like.

[0205] The interposer 731 has multiple wirings and functions to electrically connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 731 also functions to electrically connect the integrated circuits provided on the interposer 731 to electrodes provided on the package substrate 732. For these reasons, the interposer is sometimes called a "rewiring substrate" or "intermediate substrate." In some cases, through electrodes are provided in the interposer 731, and the integrated circuits and the package substrate 732 are electrically connected using the through electrodes. In addition, with a silicon interposer, TSVs (Through Silicon Vias) can also be used as through electrodes.

[0206] It is preferable to use a silicon interposer as the interposer 731. Since a silicon interposer does not require the provision of active elements, it can be manufactured at a lower cost than an integrated circuit. On the other hand, since the wiring formation of a silicon interposer can be performed using a semiconductor process, it is easy to form fine wiring that is difficult to form with a resin interposer.

[0207] HBM requires many interconnects to achieve a wide memory bandwidth. Therefore, the interposer that implements HBM requires fine and high-density interconnects. Therefore, it is preferable to use a silicon interposer for implementing HBM.

[0208] Furthermore, SiP, MCM, etc. that use silicon interposers are less likely to experience a decrease in reliability due to differences in the expansion coefficient between the integrated circuit and the interposer. Furthermore, because the silicon interposer has a highly flat surface, poor connections between the integrated circuit mounted on the silicon interposer and the silicon interposer are less likely to occur. Silicon interposers are particularly preferable for 2.5D packages (2.5-dimensional packaging), which place multiple integrated circuits side-by-side on an interposer.

[0209] A heat sink (heat sink) may be provided on top of the electronic component 730. When a heat sink is provided, it is preferable to align the height of the integrated circuit provided on the interposer 731. For example, in the electronic component 730 shown in this embodiment, it is preferable to align the height of the semiconductor device 10 with that of the semiconductor device 735.

[0210] Electrodes 733 may be provided on the bottom of package substrate 732 in order to mount electronic component 730 on another substrate. FIG. 22B shows an example in which electrodes 733 are formed of solder balls. By providing solder balls in a matrix on the bottom of package substrate 732, BGA (Ball Grid Array) mounting can be achieved. Electrodes 733 may also be formed of conductive pins. By providing conductive pins in a matrix on the bottom of package substrate 732, PGA (Pin Grid Array) mounting can be achieved.

[0211] The electronic component 730 can be mounted on other substrates using various mounting methods, including but not limited to BGA and PGA, such as a staggered pin grid array (SPGA), a land grid array (LGA), a quad flat package (QFP), a quad flat J-leaded package (QFJ), or a quad flat non-leaded package (QFN).

[0212] <Electronic equipment> Next, an example of an electronic device equipped with the above electronic component will be described with reference to FIG.

[0213] The robot 7100 includes an illuminance sensor, a microphone, a camera, a speaker, a display, various sensors (infrared sensors, ultrasonic sensors, acceleration sensors, piezoelectric sensors, optical sensors, gyro sensors, etc.), a movement mechanism, etc. The electronic component 730 includes a processor and the like, and has the function of controlling these peripheral devices. For example, the electronic component 730 has the function of storing data acquired by the sensors.

[0214] The microphone has a function of detecting acoustic signals such as the user's voice and environmental sounds. The speaker has a function of emitting audio signals such as voice and warning sounds. The robot 7100 can analyze the audio signals input via the microphone and emit the necessary audio signals from the speaker. The robot 7100 can communicate with the user using the microphone and speaker.

[0215] The camera has a function of capturing images of the surroundings of the robot 7100. The robot 7100 also has a function of moving using a movement mechanism. The robot 7100 can capture images of the surroundings using the camera and analyze the images to detect the presence or absence of obstacles when moving.

[0216] The flying object 7120 has a propeller, a camera, a battery, etc., and has the function of flying autonomously. The electronic component 730 has the function of controlling these peripheral devices.

[0217] For example, image data captured by a camera is stored in the electronic component 700. The electronic component 730 can analyze the image data and detect the presence or absence of obstacles when moving. The electronic component 730 can also estimate the remaining battery charge from changes in the battery's storage capacity.

[0218] The cleaning robot 7140 has a display on its top surface, multiple cameras on its sides, a brush, operation buttons, various sensors, etc. Although not shown, the cleaning robot 7140 is equipped with tires, a suction port, etc. The cleaning robot 7140 can move on its own, detect dirt, and suck up the dirt from the suction port provided on its bottom surface.

[0219] For example, electronic component 730 can analyze images captured by the camera to determine whether there are obstacles such as walls, furniture, steps, etc. Furthermore, if image analysis detects an object that may become tangled in the brush, such as a wire, it can stop the brush from rotating.

[0220] The automobile 7160 has an engine, tires, brakes, a steering device, a camera, etc. For example, the electronic component 730 performs control to optimize the driving state of the automobile 7160 based on data such as navigation information, speed, engine condition, gear selection state, and frequency of brake use. For example, image data captured by a camera is stored in the electronic component 700.

[0221] The electronic component 700 and / or the electronic component 730 can be incorporated into a TV device 7200 (television receiver), a smartphone 7210, a PC (personal computer) 7220, 7230, a game console 7240, a game console 7260, etc.

[0222] For example, the electronic component 730 built into the TV device 7200 can function as an image engine. For example, the electronic component 730 performs image processing such as noise reduction and resolution up-conversion.

[0223] The smartphone 7210 is an example of a portable information terminal. The smartphone 7210 includes a microphone, a camera, a speaker, various sensors, and a display unit. These peripheral devices are controlled by the electronic component 730.

[0224] PC 7220 and PC 7230 are examples of a notebook PC and a desktop PC, respectively. A keyboard 7232 and a monitor device 7233 can be connected to PC 7230 wirelessly or via a wired connection. Game console 7240 is an example of a portable game console. Game console 7260 is an example of a desktop game console. A controller 7262 is connected to game console 7260 wirelessly or via a wired connection. Electronic component 700 and / or electronic component 730 can also be incorporated into controller 7262.

[0225] This embodiment mode can be implemented in appropriate combination with any of the structures described in other embodiment modes.

[0226] <Additional notes regarding the present specification etc.> The above-described embodiments and the respective components in the embodiments will be described below with additional notes.

[0227] The configurations shown in each embodiment can be combined with the configurations shown in other embodiments as appropriate to form one aspect of the present invention. Furthermore, when multiple configuration examples are shown in one embodiment, the configuration examples can be combined as appropriate.

[0228] In addition, the content (or even a part of the content) described in one embodiment can be applied to, combined with, or replaced with another content (or even a part of the content) described in that embodiment, and / or with the content (or even a part of the content) described in one or more other embodiments.

[0229] The contents described in the embodiments refer to the contents described in each embodiment using various figures or the contents described using text in the specification.

[0230] Furthermore, a figure (or even a part thereof) described in one embodiment can be combined with another part of that figure, another figure (or even a part thereof) described in that embodiment, and / or a figure (or even a part thereof) described in one or more other embodiments to form even more figures.

[0231] In addition, in the block diagrams in this specification, components are classified by function and shown as independent blocks. However, in actual circuits, it is difficult to separate components by function, and there may be cases where a single circuit is involved in multiple functions, or where a single function is involved across multiple circuits. Therefore, the blocks in the block diagrams are not limited to the components described in the specification, but may be rephrased appropriately depending on the situation.

[0232] In addition, in the drawings, the size, layer thickness, or region is shown at an arbitrary size for convenience of explanation. Therefore, it is not necessarily limited to the scale. Note that the drawings are shown schematically for clarity, and are not limited to the shapes or values ​​shown in the drawings. For example, it is possible to include variations in signal, voltage, or current due to noise, or variations in signal, voltage, or current due to timing deviations.

[0233] In this specification and the like, when describing the connection relationship of a transistor, the terms "one of the source or drain" (or first electrode or first terminal) and "the other of the source or drain" (or second electrode or second terminal) are used. This is because the source and drain of a transistor vary depending on the structure or operating conditions of the transistor. Note that the source and drain of a transistor can be appropriately referred to as source (drain) terminal, source (drain) electrode, or the like depending on the situation.

[0234] Furthermore, the terms "electrode" and "wiring" used in this specification and elsewhere do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring," and vice versa. Furthermore, the terms "electrode" and "wiring" also include cases where multiple "electrodes" and "wirings" are integrally formed.

[0235] Furthermore, in this specification and the like, voltage and potential can be interchanged as appropriate. Voltage refers to the potential difference from a reference potential. For example, if the reference potential is a ground voltage (earth voltage), voltage can be interchanged with potential. Ground potential does not necessarily mean 0 V. Note that potential is relative, and the potential applied to wiring, etc. may change depending on the reference potential.

[0236] In this specification and the like, terms such as "film" and "layer" can be interchangeable depending on the circumstances. For example, the term "conductive layer" can be changed to the term "conductive film." Or, for example, the term "insulating film" can be changed to the term "insulating layer."

[0237] In this specification, a switch refers to a device that has the function of controlling whether a current flows by being in a conductive state (on state) or a non-conductive state (off state), or a device that has the function of selecting and switching a path for a current to flow.

[0238] In this specification, the channel length refers to, for example, in a top view of a transistor, a region where a semiconductor (or a portion in the semiconductor through which current flows when the transistor is on) and a gate overlap, or a distance between a source and a drain in a region where a channel is formed.

[0239] In this specification, the channel width refers to, for example, the length of the region where the semiconductor (or the portion in the semiconductor through which current flows when the transistor is on) and the gate electrode overlap, or the length of the portion where the source and drain face each other in the region where the channel is formed.

[0240] In this specification, "A and B are connected" includes not only a direct connection between A and B, but also an electrical connection between A and B. Here, "A and B are electrically connected" means that when an object having some kind of electrical effect exists between A and B, it enables the exchange of electrical signals between A and B. [Explanation of symbols]

[0241] 10A: semiconductor device, 20: peripheral circuit, 25: substrate, 30: memory cell layer, 31_1: memory cell layer, 31_2: memory cell layer, 31_N: memory cell layer, 40_1: memory cell, 40_2: memory cell, 40_N: memory cell, 40p: memory circuit, 40: memory cell, 41: transistor, 42: capacitor

Claims

1. a first substrate provided with a first peripheral circuit having a function of driving the first memory cells and a second peripheral circuit having a function of driving the second memory cells; a first memory cell layer having a second substrate and a first element layer having the first memory cells; a second memory cell layer having a third substrate and a second element layer having the second memory cells; the first memory cell layer is provided between the first substrate and the second memory cell layer; the first memory cell includes a first transistor and a first capacitor; the second memory cell includes a second transistor and a second capacitor; the first transistor has a semiconductor layer having a metal oxide in a channel formation region; the second transistor has a semiconductor layer having silicon in a channel formation region; the first memory cell layer is stacked on the first substrate in a direction perpendicular or substantially perpendicular to a surface of the first substrate; the first peripheral circuit and the first memory cell are electrically connected via first through electrodes provided in the second substrate and the first element layer; A semiconductor device, wherein the second peripheral circuit and the second memory cell are electrically connected via second through electrodes provided in the second substrate, the third substrate, the first element layer, and the second element layer.

2. a first substrate provided with a first peripheral circuit having a function of driving the first memory cells and a second peripheral circuit having a function of driving the second memory cells; a first memory cell layer having a second substrate and a first element layer having the first memory cells; a second memory cell layer having a third substrate and a second element layer having the second memory cells; the first memory cell layer is provided between the first substrate and the second memory cell layer; the first memory cell includes a first transistor and a first capacitor; the second memory cell includes a second transistor and a second capacitor; the first transistor has a semiconductor layer having a metal oxide in a channel formation region; the second transistor has a semiconductor layer having silicon in a channel formation region; the first memory cell layer is stacked on the first substrate in a direction perpendicular or substantially perpendicular to a surface of the first substrate; the second substrate has an amplifier circuit for writing or reading data in the first memory cell; the first peripheral circuit and the first memory cell are electrically connected via first through electrodes provided in the second substrate and the first element layer; A semiconductor device, wherein the second peripheral circuit and the second memory cell are electrically connected via second through electrodes provided in the second substrate, the third substrate, the first element layer, and the second element layer.

3. In claim 1 or 2, The semiconductor device, wherein the first memory cell layer has a plurality of the first element layers stacked in a direction perpendicular or substantially perpendicular to a surface of the first substrate.

4. In claim 1 or 2, the first substrate has a CPU, The second memory cell has a function of retaining data retained by the CPU.

5. In claim 1 or 2, The metal oxide includes In, Ga, and Zn.

Images