High aspect ratio dielectric etching using chlorine.

Abstract

Various embodiments herein relate to methods and apparatus for etching recessed features on semiconductor substrates. The techniques described herein can be used to form high-quality recessed features with substantially vertical profiles, low bowing, low twist, and highly circular features. These high-quality results can be achieved with high selectivity and relatively high etch rates. In various embodiments, the etching involves exposing the substrate to a plasma generated from a process gas containing a chlorine source, a carbon source, a hydrogen source, and a fluorine source. The chlorine source may have specific properties. In some cases, specific chlorine sources may be used. The etching is typically performed at low temperatures, e.g., about 25°C or below.

Description

[Background technology]

[0001] Related Applications A PCT application has been filed concurrently herewith as part of this application. Each application identified in the concurrently filed PCT application to which this application claims benefit or priority is incorporated herein by reference in its entirety for all purposes.

[0002] One process frequently employed during the manufacture of semiconductor devices is the formation of etched cylinders or other recessed features in dielectric materials. The dielectric materials often include alternating / repeating layers in which the recessed features are formed. One example of a situation in which such a process may be performed is in memory applications such as 3D NAND. As the semiconductor industry develops and device dimensions decrease, it becomes increasingly difficult to etch such recessed features in a uniform manner, especially for high aspect ratio features with narrow widths and / or large depths.

[0003] The background art description provided herein is intended to provide a general context for the present disclosure. Work by the presently named inventors, to the extent described in this background art section, as well as aspects of the description that may not qualify as prior art at the time of filing, are not admitted, expressly or impliedly, as prior art against the present disclosure. Summary of the Invention

[0004] Various embodiments herein relate to methods and apparatus for etching recessed features on a semiconductor substrate. For example, in one aspect of the disclosed embodiments, a method for etching recessed features on a substrate is provided, the method including: (a) providing a substrate on a substrate support in a reaction chamber, the substrate having a stack thereon, the stack including one or more layers of a first material and one or more layers of a second material alternating with each other, the stack including a silicon-containing material, the substrate further including a patterned mask layer disposed over the stack; (b) flowing a process gas into the reaction chamber to generate a plasma from the process gas, the process gas including: (i) (1) a chlorine source including chlorine gas (Cl), (2) a chlorine source including hydrogen chloride (HCl), (3) a chlorine source including only carbon and chlorine, (ii) a carbon source; (iii) a fluorine source; and (iv) a hydrogen source; and (c) exposing the substrate to a plasma to etch recessed features in the stack on the substrate, the recessed features being etched through one or more of the layers of the first material and one or more of the layers of the second material, wherein the substrate support is maintained at a cryogenic temperature during etching.

[0005] In certain embodiments, the first material comprises silicon nitride and the second material comprises silicon oxide. In some such embodiments, the stack may further comprise one or more layers of a third material alternating with one or more layers of the first material comprising silicon nitride and one or more layers of the second material comprising silicon oxide. The third material may, in various embodiments, comprise polysilicon. In some implementations, the first material comprises silicon nitride and the second material comprises polysilicon.

[0006] In various embodiments, the chlorine source may include one or more specific reactants. For example, the chlorine source may include Cl. In some cases, the chlorine source may include CCl and / or CCl. In some cases, the chlorine source may include C x H y Cl z where x>0, y>0, and z>0. For example, the chlorine source may include CH2Cl2 and / or C2H2Cl2. In some embodiments, the chlorine source includes at least one species selected from the group consisting of CCl4, CH2Cl2, C2H2Cl2, CHCl3, CH3Cl, C2H5Cl, C2H4Cl2, C2H3Cl3, C2H3Cl, C2Cl2, ClCN, CH2BrCl, C2H2BrCl, and C2H4BrCl.

[0007] In some embodiments, the chlorine source may have specific properties. For example, the chlorine source may include molecules containing only carbon and chlorine. In some cases, the chlorine source may include molecules containing only carbon, hydrogen, and chlorine. In some cases, the chlorine source may include molecules containing only carbon, hydrogen, bromine, and chlorine. In some cases, the chlorine source may include molecules containing only chlorine, carbon, and nitrogen.

[0008] Certain process conditions may be controlled during etching. In some embodiments, the substrate support is maintained at a cryogenic temperature of between about −40° C. and −10° C. during etching. In these or other embodiments, the plasma may be a capacitively coupled plasma generated at an RF power of between about 10 and 100 kW.

[0009] Other species present in the process gas may include specific reactants and / or properties. For example, in some cases, the hydrogen source may be H, CH, or x F y (where 1≦x≦4 and x+y=4), C x H y F z(where z>0), and combinations thereof. In some such embodiments, the hydrogen source comprises H2. In these or other embodiments, the fluorine source comprises NF3, CH x F y (where 0≦x≦3 and x+y=4), C x F y (where y ≥ x), C x H y F z (where z>0), and combinations thereof. In these or other embodiments, the carbon source may comprise at least one substance selected from the group consisting of CH x F y (where 0≦x≦4 and x+y=4), C x F y (where y ≥ x), C x H y F z (where z>0), and combinations thereof. In certain embodiments, the process gas includes at least one of Cl2, H2, NF3, CH2F2, CF4, and at least one of HBr and CF3I.

[0010] In some cases, etching may be performed in a manner that achieves a particular result. For example, the formed recessed features may have a 3σ twist of about 10 nm or less. In these or other embodiments, the formed recessed features may have a depth of at least about 4000 nm. In these or other embodiments, the formed recessed features may have an ellipticity of about 1.15 or less. In these or other embodiments, the formed recessed features may have a maximum critical dimension of about 115 nm or less and / or a max-bottom CD of about 40 nm or less.

[0011] In another aspect of the disclosed embodiment, an apparatus for etching recessed features on a substrate is provided, the apparatus comprising: (a) a reaction chamber; (b) a substrate support disposed within the reaction chamber; (c) a plasma generator configured to generate a plasma in the reaction chamber; (d) one or more inlets to the reaction chamber; and (e) a controller, the controller configured to (i) provide a substrate on the substrate support within the reaction chamber; (ii) flow a process gas into the reaction chamber to generate a plasma from the process gas, the process gas comprising: (1) (a) the chlorine source comprises chlorine gas (Cl); (b) the chlorine source comprises hydrogen chloride (HCl); (c) the chlorine source comprises molecules containing only carbon and chlorine; (d) the chlorine source comprises a molecule containing only carbon, hydrogen, and chlorine. (e) the chlorine source includes molecules containing only carbon, hydrogen, bromine, and chlorine; and / or (f) the chlorine source includes molecules containing only chlorine, carbon, and nitrogen; (2) a carbon source; (3) a fluorine source; and (4) a hydrogen source; and (iii) exposing the substrate to a plasma to etch recessed features into a stack on the substrate, the stack including one or more alternating layers of a first material including a silicon-containing material and one or more layers of a second material, the recessed features being etched through one or more of the layers of the first material and one or more of the layers of the second material, and the substrate support being maintained at a cryogenic temperature during etching.

[0012] In various embodiments, an apparatus may be configured to cause any of the methods claimed or otherwise described herein to be performed.

[0013] These and other aspects are further described below with reference to the drawings. [Brief explanation of the drawings]

[0014] [Figure 1] FIG. 1 shows a flow chart illustrating a method for etching recessed features in a stack including dielectric materials, according to various embodiments.

[0015] [Figure 2A] FIG. 2A illustrates a reaction chamber that can be used to perform the techniques described herein according to certain embodiments. [Figure 2B] FIG. 2B illustrates a reaction chamber that can be used to perform the techniques described herein according to certain embodiments. [Figure 2C] FIG. 2C illustrates a reaction chamber that can be used to perform the techniques described herein according to certain embodiments.

[0016] [Figure 3] FIG. 3 illustrates a semiconductor process cluster architecture that may be used to implement the techniques described herein in accordance with certain embodiments.

[0017] [Figure 4] FIG. 4 is a schematic diagram of a computer system that may be used in implementing an embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0018] In the following description, numerous specific details are set forth in order to provide a thorough understanding of the presented embodiments. The disclosed embodiments may be practiced without some or all of these specific details. In other instances, well-known process operations are not described in detail so as not to unnecessarily obscure the disclosed embodiments. While the disclosed embodiments will be described in conjunction with specific embodiments, it will be understood that they are not intended to be limited to the disclosed embodiments.

[0019] The fabrication of certain semiconductor devices involves etching features in a stack of materials using a plasma-based etching process. In various embodiments herein, the stack of materials includes alternating / repeating layers of dielectric materials. In many cases, at least one of the layers in the stack is or includes silicon nitride. In one example, the stack includes alternating layers of silicon oxide and silicon nitride. In another example, the stack includes alternating layers of silicon oxide, silicon nitride, and polysilicon. In another example, the stack includes alternating layers of silicon nitride and polysilicon. Additional layers may be present depending on the particular application.

[0020] The features etched into dielectric materials may be cylinders, trenches, or other concave features. As the aspect ratios of such features continue to increase, several problems arise, including (1) feature twist, (2) feature non-circularity, (3) aspect ratio-dependent etch rates, (4) bowed etch profiles, (5) poor mask selectivity, and (6) low etch rates. Twist refers to a random deviation between the intended bottom position of a feature and the actual final bottom position of the feature (e.g., the final position of the feature corresponds to the position of the bottom of the feature after etching the feature). For example, in some cases, cylindrical features are intended to be etched in a regular array. Twist is understood to exist when some or all of the features randomly deviate from this array at their bottoms.

[0021] Feature non-circularity refers to the deviation of the bottom hole shape from a circular hole shape. This problem is relevant when etching circular features, such as cylinders, where a circular bottom for the concave feature is desired. When the bottom hole shape deviates from a circular shape, it often resembles an ellipse, a triangle, or an irregular polygon. In many cases, such non-circular shapes are undesirable.

[0022] Aspect ratio dependent etch rate refers to the problem of the etch rate slowing as the aspect ratio of a feature increases. In other words, the further a feature is etched into the dielectric material, the slower the etching process becomes. This is problematic because it can lead to reduced throughput and a corresponding increase in processing costs.

[0023] A bowed etch profile refers to the tendency of a feature to be etched laterally into a dielectric layer such that the final profile bows outward excessively somewhere along the depth of the feature. In other words, the actual maximum critical dimension of the feature exceeds the desired maximum critical dimension of the feature, which can compromise the integrity of the structure being formed and / or limit the electrical performance of the final device.

[0024] Poor mask selectivity becomes a problem when an etching process removes too much of the mask, leaving either no mask at all at the end of the process, or an insufficient amount of mask remaining to adequately transfer the pattern from the mask to the dielectric film(s). One common result of poor mask selectivity is degradation of the feature profile near the top of recessed features.

[0025] A low etch rate refers to an etch rate that is slower than desired for a particular application. A low etch rate is problematic because it leads to long etch times, reduced throughput, and higher processing costs.

[0026] Unfortunately, techniques that ameliorate some of these problems often exacerbate others. Therefore, these problems must be balanced against one another when designing an etching operation. For example, conventional, commercially practiced dielectric etch processes often result in substantial bowing. To address the bowing problems associated with conventional, commercially practiced dielectric etch processes, cryogenic etch processes have been developed in recent years. Such cryogenic processes are defined as processes in which the substrate support is cooled to a temperature of about 25° C. or less, and in some cases, about 0° C. or less. Advantageously, cryogenic processes also result in relatively high etch rates and relatively low bowing. However, these cryogenic processes substantially exacerbate problems associated with feature twist and non-circularity. Previously, such trade-offs have been difficult to avoid.

[0027] The techniques described herein may be used to etch recessed features in dielectric materials without some or all of the problems identified above. In other words, the disclosed techniques may be used to etch recessed features in dielectric materials with little or no twist, reasonably circular features, acceptable aspect ratio dependent etch rates, acceptable bow shapes, sufficient mask selectivity, and sufficient etch rates.

[0028] In various embodiments herein, a specific set of reactants is used. The reactants include a chlorine source, a carbon source, a fluorine source, and a hydrogen source. Examples of chlorine sources include Cl2, HCl, CCl4, C x H y Cl z (where z>0). C x H y Cl z Specific examples of materials include, but are not limited to, chloroform (CHCl) and methylene chloride (CHCl). In some embodiments, the chlorine source is CH y Cl z or C2H y Clz In various embodiments, the chlorine source does not include fluorine or other non-chlorine halogens.

[0029] Examples of carbon sources include CH x F y (where 0≦x≦4 and x+y=4), C x F y (where y≧x), and C x H y F z (where z>0), or combinations thereof. Examples of fluorine sources include, but are not limited to, CH x F y (where 0≦x≦3 and x+y=4), C x F y (where y ≥ x), C x H y F z (where z>0), and NF. Examples of hydrogen sources include, but are not limited to, hydrogen (H), CH x F y (where 1≦x≦4 and x+y=4), and C x H y F z (where z>0). In some embodiments, the reactants may further comprise one or more non-fluorine and non-chlorine halogen sources, examples of which include, but are not limited to, HBr, I2, and CF3I. Chlorine sources, as well as carbon sources, work in combination with the reactants to generate abundant H and F radicals, resulting in the exceptional etching results described herein.

[0030] In some embodiments, the reactants are Cl, H, NF, and CH x F y where 0≦x≦4 and x+y=4. In some embodiments, the reactants include Cl2, H2, NF3, CH2F2, CF4, and at least one of HBr and CF3I. Various other combinations of reactants are possible and are considered within the scope of the disclosed embodiments.

[0031] The substrate may be maintained at a cryogenic temperature during etching. This temperature control may be achieved by controlling the temperature of a substrate support on which the substrate is placed during etching. In certain embodiments, the substrate support is maintained at a cryogenic temperature of about 25° C. or below, or about 15° C. or below, or about 0° C. or below. In some cases, the substrate support may be maintained at a cryogenic temperature as low as about −40° C., as low as about −70° C., or even lower. In some embodiments, the substrate support may be maintained at a cryogenic temperature of about −30° C. to −10° C. Operating at a relatively low etching temperature can provide benefits associated with low-temperature etching, such as low bowing, relatively high etching rates, and low aspect-ratio dependent etching rates. Advantageously, including chlorine gas as a reactant reduces or eliminates problems associated with low-temperature etching, such as twist and non-circularity.

[0032] Although chlorine gas is commonly used to etch other materials such as polysilicon, aluminum, and other metals and metal-containing compounds, it has not typically been used to etch silicon-containing dielectric materials such as silicon oxide and silicon nitride. Previously, chlorine gas exhibited very poor etching results when used to etch these silicon-containing dielectric materials. However, the inventors have discovered that using chlorine gas in combination with specific reactants at specific temperatures significantly reduces the aforementioned problems related to twist and non-circularity. Unexpectedly, these problems are reduced without exacerbating aspect ratio-dependent etch rates, bowing, mask selectivity, and other problems related to etch rates.

[0033] Without being bound by theory or mechanism of action, it is believed that embodiments herein reduce the twist and non-circularity problems typically associated with low-temperature etching by avoiding excessive deposition of plasma species and / or etching byproducts on the sidewalls of high-aspect-ratio recessed features. Because chlorine gas has previously shown poor etching results when used to etch silicon-containing dielectrics, it is believed that the primary function of chlorine gas may not be to etch the silicon-containing material itself, but rather to control the degree to which species present in the reaction chamber adhere to the sidewalls of growing features. Such surface chemical interactions were unexpected.

[0034] One application of the disclosed method is in the context of forming DRAM devices. In this case, features may be etched primarily in silicon oxide, with one, two, or more layers of silicon nitride, for example. In one example, a substrate includes a silicon oxide layer sandwiched between two silicon nitride layers, the silicon oxide layer being about 400-1800 nm thick, and one or more of the silicon nitride layers being about 20-600 nm thick. The etched feature may be a cylinder having a final depth of about 1-3 μm, e.g., about 1.5-2 μm. The cylinder may have a width of about 10-50 nm, e.g., about 15-30 nm. After the cylinder is etched, a capacitor memory cell can be formed within it.

[0035] Another application of the disclosed method is in the context of forming vertical NAND (VNAND, also known as 3D NAND) devices. In this case, the material from which features are etched may have a repeating layer structure. For example, the material may include alternating layers of silicon oxide and silicon nitride. The repeating layer structure includes pairs or repeating groups of materials. In various cases, the number of pairs or repeating groups may be about 10 to 500 (e.g., about 20 to 1000 individual layers). Based on current device dimensions, oxide layers may have thicknesses of about 20 to 50 nm, e.g., about 30 to 40 nm. Nitride or polysilicon layers may have thicknesses of about 20 to 50 nm, e.g., about 30 to 40 nm. Features etched into the layer stack may have depths of about 2 to 15 μm, e.g., about 5 to 9 μm. The features may have widths of about 20 to 450 nm, e.g., about 50 to 100 nm.

[0036] The details of dimensions / parameters provided herein, such as high aspect ratio, thickness, width, and depth, are for illustrative and explanatory purposes only, and it will be understood that different dimensions / parameters may also be applicable or used based on the disclosure provided herein.

[0037] FIG. 1 is a flowchart illustrating a method for etching a stack including dielectric materials, according to various embodiments herein. The method begins at operation 101, where a substrate is received in a reaction chamber. The reaction chamber is an etch chamber configured to etch semiconductor substrates. The substrate received in the reaction chamber includes a stack of materials thereon. The stack of materials includes one or more layers of silicon nitride. In addition to silicon nitride, the stack of materials may include one or more layers of silicon oxide and / or one or more layers of polysilicon. Specific combinations of stack materials are described above. A patterned mask layer is provided over the stack. The pattern provided in the mask layer defines the locations of recessed features to be formed in the stack.

[0038] Next, in operation 103, a process gas (which may be a mixture of gases combined before or after delivery to the reaction chamber) is flowed into the reaction chamber and a plasma is generated from the process gas. The process gas includes a chlorine source, a carbon source, a fluorine source, and a hydrogen source, as further described above. The process gas may also include one or more inert gases.

[0039] In certain embodiments, specific conditions may be used to generate the plasma. Often, the plasma is a capacitively coupled plasma. The plasma may be generated at an RF power between about 5 and 200 kW, e.g., about 10 and 100 kW, or in some embodiments, about 10 and 65 kW. In some cases, dual-frequency RF may be used to generate the plasma. Thus, RF power may be provided at two or more frequency components, e.g., a first frequency component at about 400 kHz and a second frequency component at about 60 MHz. Different powers may be provided at each frequency component. For example, the first frequency component (e.g., about 400 kHz) may be provided at a power between about 10 and 40 kW, e.g., about 25 kW, and the second frequency component (e.g., about 60 MHz) may be provided at a different power, e.g., between about 0.5 and 8 kW, e.g., about 4 kW. These power levels assume that the RF power is delivered to a single 300 mm wafer. The power level can be adjusted linearly based on the substrate area for additional substrates and / or substrates of other sizes (thereby maintaining a uniform power density delivered to the substrate). In other cases, a triple-frequency RF power may be used to generate the plasma. In some cases, the applied RF power may be pulsed at a repetition rate of 1 to 50,000 Hz. The RF power may be pulsed between two non-zero values ​​(e.g., between a higher and a lower power state) or between zero and a non-zero value (e.g., between an off state and an on state). When the RF power is pulsed between two non-zero values, the power noted above relates to the higher power state, and the lower power state may correspond to an RF power of approximately 600 W or less. The maximum ion energy at the substrate may be relatively high, for example, approximately 1 to 10 kV. The maximum ion energy is determined by the applied RF power in combination with the RF excitation frequency, electrode size, electrode configuration, chamber geometry, and plasma interaction details.

[0040] The pressure within the reaction chamber may be about 5-100 mTorr, and in some cases about 15-50 mTorr. As noted above, the substrate may be maintained at a cryogenic temperature by maintaining the substrate support at a desired temperature. Examples of temperatures are described above.

[0041] In some cases, the process gas (or one or more species therein) may be flowed into the reaction chamber at a specific flow rate. For example, in some cases, chlorine gas (Cl2) or other chlorine source may be provided to the reaction chamber at a flow rate of about 10-100 sccm. If hydrogen gas (H2) is used, it may be provided to the reaction chamber at a flow rate of about 20-500 sccm. If NF3 is used, it may be provided to the reaction chamber at a flow rate of about 5-100 sccm. CH x F y The total flow rate of the species may be about 10-300 sccm. If CH2F2 is used, it may be provided to the reaction chamber at a flow rate of about 10-300 sccm. If CF4 is used, it may be provided to the reaction chamber at a flow rate of about 5-100 sccm. If HBr is used, it may be provided to the reaction chamber at a flow rate of about 5-100 sccm. If CF3I is used, it may be provided to the reaction chamber at a flow rate of about 5-50 sccm.

[0042] Returning to FIG. 1 , the method continues at operation 105, where the substrate is exposed to the plasma for a time sufficient to etch a recessed feature in the stack of materials. The feature is etched through at least one silicon nitride layer in the stack. In some cases, the substrate may be exposed to the plasma for a duration of approximately 2000-3000 seconds. In some cases, process parameters such as power, pressure, and gas flow are adjusted in a series of recipe steps. A patterned mask layer protects the underlying stack material where the patterned mask layer is present. This ensures that the recessed feature is formed in the patterned opening in the mask layer where the recessed feature is desired.

[0043] In another embodiment, another method for etching recessed features on a substrate is provided. In this embodiment, the substrate includes at least a first silicon-containing layer and a patterned mask layer disposed on the stack. A process gas is flowed into a reaction chamber. The process gas includes a chlorine source selected from molecules containing only carbon and chlorine, or molecules containing only carbon, hydrogen, and chlorine, or molecules containing only carbon, hydrogen, bromine, and chlorine, or molecules containing only chlorine, carbon, and nitrogen. In some embodiments, the chlorine source is carbon tetrachloride (CCl4), dichloroacetylene (C2Cl2), cyanogen chloride (ClCN), bromochloromethane (CH2BrCl), 1-bromo-2-chloroethane (C2H4BrCl), dichloromethane (CH2Cl2), the isomers of dichloroethylene (C2H2Cl2) 1,1-dichloroethylene, trans-1,2-dichloroethylene, and cis-1,2-dichloroethylene, chloroform (CHCl3), chloromethane (CH3Cl), chloroethylene, The process gas further comprises a carbon source, a fluorine source, and a hydrogen source. The process gas further comprises at least one chlorine source selected from the group consisting of chloroethane (C2H5Cl), 1,2-dichloroethane or 1,1-dichloroethane (C2H4Cl2), 1,1,1-trichloroethane and 1,1,2-trichloroethane, which are isomers of trichloroethane (C2H3Cl3), vinyl chloride (C2H3Cl), bromochloromethane (CH2BrCl), cis- and trans-1-bromo-2-chloroethylene (C2H2BrCl), and 1-bromo-1-chloroethane (C2H4BrCl). A plasma is generated from the process gas. The substrate is exposed to the plasma to etch recessed features in a stack on the substrate, the recessed features being etched through at least the first silicon-containing layer, and the substrate support is maintained at a cryogenic temperature of about 25°C or less during etching. In some embodiments, the chlorine source molecule is also a carbon source. In other embodiments, the molecule that is the carbon source does not contain chlorine and is different from the molecule that is the chlorine source. In various embodiments, the chlorine source, carbon source, fluorine source, and hydrogen source are all different molecules.

[0044] Twist-reduced etching may be achieved by providing a chlorine-containing source that includes at least one of: (1) molecules containing only carbon and chlorine, or (2) molecules containing only carbon, hydrogen, and chlorine, or (3) molecules containing only carbon, hydrogen, bromine, and chlorine, or (4) molecules containing only chlorine, carbon, and nitrogen. To provide a chlorine source with multiple Cl atoms and sufficient vapor pressure to allow simple incorporation into typical gas delivery equipment, in some embodiments, the chlorine source is at least one of C2Cl2, CH2Cl2, and trans-1,2-C2H2Cl2.

[0045] Device 2A-2C illustrate an embodiment of an adjustable gap capacitively coupled confined RF plasma reactor 200 that can be used to perform the etching operations described herein. As shown, a vacuum chamber 202 includes a chamber housing 204 that encloses an interior space that houses a lower electrode 206. At the top of the chamber 202, an upper electrode 208 is vertically spaced from the lower electrode 206. The upper electrode 208 may be used as a plasma generator. The planar surfaces of the upper electrode 208 and the lower electrode 206 are substantially parallel and perpendicular to the vertical direction between the electrodes. Preferably, the upper electrode 208 and the lower electrode 206 are circular and coaxial with the vertical axis. The lower surface of the upper electrode 208 faces the upper surface of the lower electrode 206. The opposing, spaced-apart electrode surfaces define an adjustable gap 210 therebetween. During operation, the lower electrode 206 is supplied with RF power by a matching RF power source 220. RF power is supplied to the lower electrode 206 via an RF supply conduit 222, an RF strap 224, and an RF power member 226. A ground shield 236 may surround the RF power member 226 to provide a more uniform RF field to the lower electrode 206. A wafer may be inserted through a wafer port 282, which provides an entrance for the wafer. The wafer is supported in a gap 210 above the lower electrode 206 for processing, and process gases (including, for example, chlorine gas or other chlorine sources, and other reactants described herein) are supplied to the gap 210 and excited into a plasma state by RF power. The upper electrode 208 may be powered or may be grounded.

[0046] 2A-2C, the lower electrode 206 is supported on a lower electrode support plate 216. An insulator ring 214 interposed between the lower electrode 206 and the lower electrode support plate 216 insulates the lower electrode 206 from the support plate 216.

[0047] RF bias housing 230 supports lower electrode 206 on RF bias housing bowl 232. Bowl 232 is connected by arm 234 of RF bias housing 230 to conduit support plate 238 through an opening in chamber wall plate 218. In a preferred embodiment, RF bias housing bowl 232 and RF bias housing arm 234 are integrally formed as one component, although arm 234 and bowl 232 can also be two separate components bolted or joined together.

[0048] The RF bias housing arm 234 includes one or more hollow passages for passing RF power and equipment, such as gas coolant, liquid coolant, RF energy, lift pin control cables, and electrical monitoring and operating signals, from outside the vacuum chamber 202 to the interior of the vacuum chamber 202 in the space behind the lower electrode 206. The RF supply conduit 222 is insulated from the RF bias housing arm 234, which provides a return path for RF power to the RF power source 220. An equipment conduit 240 provides passage for equipment components. The gap 210 is preferably surrounded by a containment ring assembly or shroud (not shown). The interior of the vacuum chamber 202 is maintained at a low pressure by connection to a vacuum pump via a vacuum portal 280.

[0049] The conduit support plate 238 is attached to an actuation mechanism 242. The actuation mechanism 242, such as a servomechanical motor or a stepper motor, is attached to a vertical linear bearing 244 by a screw gear 246, such as a ball screw, and a motor for rotating the ball screw. During operation to adjust the size of the gap 210, the actuation mechanism 242 moves along the vertical linear bearing 244. FIG. 2A illustrates an arrangement in which the actuation mechanism 242 is in a high position relative to the linear bearing 244, resulting in a small gap 210a. FIG. 2B illustrates an arrangement in which the actuation mechanism 242 is in an intermediate position relative to the linear bearing 244. As shown, the lower electrode 206, RF bias housing 230, conduit support plate 238, and RF power supply 220 are all moved low relative to the chamber housing 204 and upper electrode 208, resulting in a medium-sized gap 210b.

[0050] 2C illustrates a large gap 210c when the actuation mechanism 242 is in a low position relative to the linear bearing. Preferably, the upper electrode 208 and the lower electrode 206 remain coaxial during gap adjustment, and the facing surfaces of the upper and lower electrodes across the gap remain parallel.

[0051] This embodiment allows for the adjustment of the gap 210 between the bottom electrode 206 and the top electrode 208 in the CCP chamber 202 during multi-step process recipes (such as BARC, HARC, and STRIP) to maintain uniform etching across large diameter substrates, such as 300 mm wafers or flat panel displays. In particular, the chamber relates to a mechanical arrangement that allows the linear motion necessary to provide an adjustable gap between the bottom electrode 206 and the top electrode 208.

[0052] 2A illustrates a laterally deflected bellows 250 sealed at its proximal end to a conduit support plate 238 and at its distal end to a stepped flange 228 of a chamber wall plate 218. The inner diameter of the stepped flange defines an opening 212 in the chamber wall plate 218 through which an RF bias housing arm 234 passes. The distal end of the bellows 250 is secured by a clamp ring 252.

[0053] The laterally deflected bellows 250 provides a vacuum seal while simultaneously allowing vertical movement of the RF bias housing 230, conduit support plate 238, and actuation mechanism 242. The RF bias housing 230, conduit support plate 238, and actuation mechanism 242 may also be referred to as a cantilever assembly. Preferably, the RF power supply 220 moves with the cantilever assembly and is attachable to the conduit support plate 238. Figure 2B shows the bellows 250 in a neutral position when the cantilever assembly is in the middle position. Figure 2C shows the laterally deflected bellows 250 when the cantilever assembly is in the low position.

[0054] A labyrinth seal 248 provides a particle barrier between the bellows 250 and the interior of the plasma processing chamber housing 204. A fixed shield 256 is fixedly attached to the inner wall of the chamber housing 204 at the chamber wall plate 218 to provide a labyrinth groove 260 (slot) within which a movable shield plate 258 moves vertically to accommodate vertical movement of the cantilever assembly. An outer portion of the movable shield plate 258 remains within the slot at all vertical positions of the lower electrode 206.

[0055] In the illustrated embodiment, the labyrinth seal 248 includes a fixed shield 256 attached to the inner surface of the chamber wall plate 218 around the periphery of the opening 212 in the chamber wall plate 218, which defines a labyrinth groove 260. A movable shield plate 258 is attached to and extends radially from the RF bias housing arm 234, which passes through the opening 212 in the chamber wall plate 218. The movable shield plate 258 extends into the labyrinth groove 260, spaced a first gap from the fixed shield 256 and a second gap from the inner surface of the chamber wall plate 218, to allow vertical movement of the cantilever assembly. The labyrinth seal 248 prevents the migration of particles dislodged from the bellows 250 into the vacuum chamber interior 205 and prevents radicals from the process gas plasma from migrating to the bellows 250, where the radicals may form deposits that are subsequently dislodged.

[0056] 2A shows the movable shield plate 258 in a higher position within the labyrinth groove 260 above the RF bias housing arm 234 when the cantilever assembly is in a high position (small gap 210a). FIG. 2C shows the movable shield plate 258 in a lower position within the labyrinth groove 260 above the RF bias housing arm 234 when the cantilever assembly is in a low position (large gap 210c). FIG. 2B shows the movable shield plate 258 in a neutral or intermediate position within the labyrinth groove 260 when the cantilever assembly is in an intermediate position (medium gap 210b). While the labyrinth seal 248 is shown as symmetrical with respect to the RF bias housing arm 234, in other embodiments the labyrinth seal 248 may be asymmetrical with respect to the RF bias housing arm 234.

[0057] FIG. 3 illustrates a semiconductor process cluster architecture with various modules interfacing with a vacuum transfer module 338 (VTM). The arrangement of transfer modules for "transferring" substrates between multiple storage facilities and processing modules is sometimes referred to as a "cluster tool architecture" system. An airlock 330, also known as a load lock or transfer module, is shown within the VTM 338 with four processing modules 320a-320d, which may be individually optimized to perform various manufacturing processes. By way of example, processing modules 320a-320d may be implemented to perform substrate etching, deposition, ion implantation, substrate cleaning, sputtering, and / or other semiconductor processes, as well as laser metrology and other defect detection and identification methods. One or more of the processing modules (any of 320a-320d) may be implemented as disclosed herein, i.e., to etch recessed features in substrates. The airlock 330 and processing modules 320a-320d may also be referred to as "stations." Each station has a facet 336 that connects the station to the VTM 338. Inside the facet, sensors 1-18 are used to detect the passage of substrate 326 as it moves between the respective stations.

[0058] A robot 322 transfers substrates between stations. In one embodiment, the robot may have one arm, and in another embodiment, the robot may have two arms, each arm having an end effector 324 that grasps the substrate for transfer. A front-end robot 332 may be used to transfer substrates from cassettes or front-opening unified pods (FOUPs) 334 in a load port module (LPM) 342 to the airlock 330 in an atmospheric transfer module (ATM) 340. A module center 328 in a process module 320a-320d may be one location for placing substrates. An aligner 344 in the ATM 340 may be used for substrate alignment.

[0059] In an example processing method, a substrate is placed in one of the FOUPs 334 within the LPM 342. The front-end robot 332 transfers the substrate from the FOUP 334 to the aligner 344, which allows the substrate 326 to be properly centered before etching, deposition, or other processing occurs thereon. After alignment, the substrate is moved by the front-end robot 332 to the airlock 330. The airlock module has the ability to match the environment between the ATM and the VTM, so the substrate can be moved between the two pressure environments without damage. From the airlock module 330, the substrate is moved by the robot 322 through the VTM 338 and into one of the processing modules 320a-320d, such as processing module 320a. To accomplish this substrate transfer, the robot 322 uses an end effector 324 on each of its arms. In processing module 320a, the substrate undergoes etching as described. The robot 322 then moves the substrate out of the processing module 320a and to its next desired location.

[0060] It should be noted that the computer controlling the movement of the substrate may be part of the cluster architecture, may be located outside the cluster architecture on the manufacturing floor, or may be at a remote location and connected to the cluster architecture via a network.

[0061] In some embodiments, the controller is part of an apparatus or system, which may be part of the examples described above. Such systems may include semiconductor processing equipment, including one or more processing tools, one or more chambers, one or more processing platforms, and / or specific processing components (such as a wafer pedestal, gas flow system, etc.). These systems may be integrated with electronics for controlling their operation before, during, and after processing of semiconductor wafers or substrates. The electronics may also be referred to as a "controller," and the controller may control various components or subparts of one or more systems. Depending on the processing requirements and / or type of system, the controller may be programmed to control any of the processes disclosed herein, including delivery of process gases, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, radio frequency (RF) generator settings, RF matching circuit settings, frequency settings, flow rate settings, liquid delivery settings, position and motion settings, wafer transfer into and out of the tool, and wafer transfer into and out of other transfer tools and / or load locks connected or interfaced with the particular system.

[0062] Broadly speaking, a controller may be defined as an electronic device having various integrated circuits, logic, memory, and / or software that receive instructions, issue instructions, control operations, enable cleaning operations, enable endpoint measurements, etc. Integrated circuits may include chips in the form of firmware that store program instructions, digital signal processors (DSPs), chips defined as application-specific integrated circuits (ASICs), and / or one or more microprocessors or microcontrollers that execute program instructions (e.g., software). Program instructions may be instructions communicated to the controller in the form of various individual settings (or program files) that define operational parameters for performing a particular process on or for a semiconductor wafer or for a system. The operational parameters, in some embodiments, may be part of a recipe defined by a process engineer to accomplish one or more processing steps during the manufacture of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or dies of a wafer.

[0063] In some embodiments, the controller may be part of or connected to a computer that is integrated into, connected to, or otherwise networked to the system, or a combination thereof. For example, the controller may be all or part of a “cloud,” i.e., fab host computer system, enabling remote access to wafer processing. The computer may enable remote access to the system to monitor the current progress of a manufacturing operation, examine the history of past manufacturing operations, examine trends or performance criteria from multiple manufacturing operations, modify parameters of a current process, configure processing steps to track a current process, or initiate a new process. In some examples, a remote computer (e.g., a server) can provide process recipes to the system over a network, which may include a local network or the Internet. The remote computer may include a user interface that allows entry or programming of parameters and / or settings, which are then communicated from the remote computer to the system. In some examples, the controller receives instructions in the form of data specifying parameters for each of the processing steps to be performed during one or more operations. It should be understood that the parameters may be specific to the type of process being performed and the type of tool the controller is configured to interface with or control. Thus, as described above, the controller may be distributed, such as by including one or more individual controllers networked together and operating toward a common purpose, such as the processes and controls described herein. One example of a distributed controller for such purposes is one or more integrated circuits on the chamber that are located remotely (e.g., at the platform level or as part of a remote computer) and communicate with one or more integrated circuits that cooperatively control the processes in the chamber.

[0064] Examples of systems may include, but are not limited to, a plasma etch chamber or module, a deposition chamber or module, a spin rinse chamber or module, a metal plating chamber or module, a cleaning chamber or module, a bevel edge etch chamber or module, a physical vapor deposition (PVD) chamber or module, a chemical vapor deposition (CVD) chamber or module, an atomic layer deposition (ALD) chamber or module, an atomic layer etch (ALE) chamber or module, an ion implantation chamber or module, a track chamber or module, and any other semiconductor processing system that may be associated with or used in the fabrication and / or manufacturing of semiconductor wafers.

[0065] As described above, depending on one or more process steps being performed by the tool, the controller may communicate with one or more other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, nearby tools, tools located throughout the factory, a main computer, another controller, or tools used to transport materials to and from tool locations and / or load ports of wafers within a semiconductor fabrication factory.

[0066] The various hardware and method embodiments described above may be used in conjunction with lithographic patterning tools or processes, for example, for the fabrication or manufacture of semiconductor devices, displays, LEDs, solar panels, etc. Typically, although not necessarily, such tools / processes are used or performed together in a common manufacturing facility.

[0067] Lithographic patterning of films typically involves some or all of the following steps, each of which can be achieved using several possible tools: (1) applying a photoresist onto a workpiece, e.g., a substrate having a silicon nitride film formed thereon, using a spin-on or spray-on tool; (2) curing the photoresist using a hotplate, furnace, or other suitable curing tool; (3) exposing the photoresist to visible, ultraviolet, or X-ray light using a tool such as a wafer stepper; (4) developing the resist and selectively removing and thereby patterning the resist using a tool such as a wet bench or spray developer; (5) transferring the resist pattern to an underlying film or workpiece using a dry or plasma-assisted etching tool; and (6) removing the resist using a tool such as an RF or microwave plasma resist stripper. In some embodiments, an ashing hard mask layer (e.g., an amorphous carbon layer) and other suitable hard masks (e.g., an antireflective layer) may be deposited before applying the photoresist.

[0068] In this application, the terms “semiconductor wafer,” “wafer,” “substrate,” “wafer substrate,” and “partially fabricated integrated circuit” are used interchangeably. Those skilled in the art will understand that the term “partially fabricated integrated circuit” can refer to a silicon wafer during any of the many stages of integrated circuit fabrication on a silicon wafer. Wafers or substrates used in the semiconductor device industry typically have diameters of 200 mm, 300 mm, or 450 mm. The above detailed description assumes that the embodiments are implemented on a wafer. However, the embodiments are not so limited. Workpieces may be of various shapes, sizes, and materials. In addition to semiconductor wafers, other workpieces that may utilize the disclosed embodiments include various articles such as printed circuit boards, magnetic recording media, magnetic recording sensors, mirrors, optical elements, micromechanical devices, and the like.

[0069] Unless otherwise defined with respect to a particular parameter, the terms "about" and "approximately" as used herein are intended to mean ±10% with respect to the associated value.

[0070] It is understood that the configurations and / or approaches described herein are exemplary in nature and are susceptible to numerous variations, and therefore, these specific embodiments or examples should not be considered in a limiting sense. The specific routines or methods described herein may represent one or more of any number of processing strategies. As such, various illustrated acts may be performed in the illustrated order, in other orders, in parallel, or in some cases omitted. Similarly, the order of operations described above may be varied. Certain references are incorporated herein by reference. It is understood that any disclaimer or disclaimer made in such references does not necessarily apply to the embodiments described herein. Similarly, features described in such references as required may be omitted herein. The subject matter of the present disclosure includes all novel and non-obvious combinations and combinations of the various processes, systems, and configurations, and other features, functions, acts, and / or properties disclosed herein, and any and all equivalents thereof.

[0071] experiment Experimental results demonstrate that the disclosed method can be used to etch dielectric-containing stacks on substrates with improved results compared to previous etching methods. In particular, the disclosed method can be used to achieve the benefits associated with low-temperature etching (e.g., little or no bowing, low aspect ratio dependent etch rates, and high etch rates) without the problems typically associated with low-temperature etching (e.g., twisting and non-circularity of the resulting features). These results were achieved in the context of successful 3D NAND applications (e.g., 3D NAND applications within acceptable specifications / tolerances, as described below). These results demonstrate significant improvements over both traditional commercially practiced etching methods and newer cryogenic etching methods.

[0072] Table 1 below shows experimental results for three different etching processes. Processes A and B were cryogenic etching processes without chlorine gas or other chlorine sources, while Process C was a cryogenic etching process using chlorine gas according to an embodiment of the present disclosure. [Table 1]

[0073] As used herein, CD refers to the critical dimension of a feature (e.g., width in a direction parallel to the surface of the substrate) at a particular location within the feature. "Max-bottom CD" refers to the difference between the maximum critical dimension of a feature and the critical dimension at the bottom of the feature. Selectivity refers to the ratio of the etch rate of the material to be removed to the etch rate of the mask material. For example, if the material to be removed is etched at a rate of 200 nm / min and the mask is etched at a rate of 50 nm / min, the selectivity is calculated as 200 / 50, sometimes reported as 4:1 or more simply 4. Twist refers to the degree to which a feature deviates from the desired array pattern. Twist reported herein is "3σ twist" (e.g., 3 sigma twist), which is calculated as three times the standard deviation of the distance between holes at the bottom of the feature. Because twist is an undesirable feature, it is desirable to have as low a 3σ twist as possible. Ovality is the degree to which the bottom of a cylindrical feature deviates from a perfect circle to an ellipse, and is calculated as the ratio of the major axis to the minor axis when an ellipse is fitted to the shape of the hole at the bottom. A perfectly circular feature has an ellipse ratio of 1.0. Since circular features are often desired (for example, when etching a cylinder), an ellipse ratio closer to 1.0 is preferable.

[0074] The results in Table 1 demonstrate that the disclosed techniques can be used to significantly improve problems associated with twist and non-circularity of etched features. The inclusion of chlorine gas at low etching temperatures achieves the benefits of a low temperature etching regime without the twist and non-circularity problems typically observed with such low temperature etches. These results represent a significant improvement over results previously obtained.

[0075] In certain embodiments herein, the features formed may meet certain specifications that define a successful process for 3D NAND applications. For example, the features may have a 3σ twist of about 20 nm or less, or about 15 nm or less, or about 10 nm or less, or about 8 nm or less. This low degree of twist may be achieved over an etch depth of at least about 3500 nm, or at least about 4000 nm, or at least about 8000 nm. The features may have an ellipticity of about 1.15 or less, or about 1.05 or less. The features may be etched at a rate of at least about 125 nm / min, or at least about 175 nm / min. The features may have a max-bottom CD of about 70 nm or less, in some cases about 50 nm or less, or about 40 nm or less. The features may be etched with a selectivity of about 3 or greater. Any or all of these characteristics may be present in certain embodiments.

[0076] FIG. 4 is a high-level block diagram illustrating a computer system 400 suitable for implementing a controller used in various embodiments. The computer system 400 may also be used to control the RF plasma reactor 200 of FIGS. 2A-2C. Computer systems may take many physical forms, ranging from integrated circuits, printed circuit boards, and small handheld devices to large supercomputers. The computer system 400 includes one or more processors 402 and may further include an electronic display device 404 (e.g., for displaying graphics, text, and other data), a main memory 406 (e.g., random access memory (RAM)), a storage device 408 (e.g., a hard disk drive), a removable storage device 410 (e.g., an optical disk drive), a user interface device 412 (e.g., a keyboard, touch screen, keypad, mouse, or other pointing device), and a communications interface 414 (e.g., a wireless network interface). The communications interface 414 allows software and data to be transferred between the computer system 400 and external devices over a link. The system may also include a communication infrastructure 416 (eg, a communication bus, crossover bar, or network) to which the aforementioned devices / modules are connected.

[0077] Information transferred via communications interface 414 may be in the form of signals, such as electronic, electromagnetic, optical, or other signals, receivable by communications interface 414 over a communications link carrying the signals, which may be implemented using wire or cable, fiber optics, telephone lines, cellular phone links, wireless links, and / or other communications channels. Using such communications interfaces, it is contemplated that one or more processors 402 may receive information from a network or output information to a network in the course of performing the method steps described above. Furthermore, method embodiments may be performed solely by the processor or may be performed over a network, such as the Internet, in conjunction with a remote processor that shares some of the processing.

[0078] The term "non-transitory computer-readable medium" is used generally to refer to main memory, secondary storage, removable storage, and storage devices such as hard disks, flash memory, disk drive memory, CD-ROMs, and other forms of persistent memory used to store computer code or computer-executable instructions, and should not be construed to cover transitory subject matter such as carrier waves or signals. Examples of computer code include machine code and computer-executable instructions that may be stored on a computer-readable medium, such as that produced by a compiler, and files containing higher-level code that are executed by a computer using an interpreter. Computer-readable medium may also be computer code embodied in a carrier wave and transmitted by a computer data signal representing a sequence of instructions executable by a processor.

[0079] The computer-readable medium may include computer-executable instructions for providing a substrate on a substrate support, flowing a process gas into a reaction chamber, generating a plasma from the process gas, and exposing the substrate to the plasma.

[0080] conclusion Although the foregoing embodiments have been described in some detail for purposes of clarity of understanding, it will be apparent that certain changes and modifications may be practiced within the scope of the appended claims. It should be noted that there are many alternative ways of implementing the processes, systems, and apparatus of the present embodiments. Accordingly, the present embodiments are to be considered as illustrative and not restrictive, and the present embodiments are not to be limited to the details given herein.

Claims

1. 1. A method of etching a recessed feature on a substrate, comprising: a. providing the substrate on a substrate support in a reaction chamber, the substrate having a stack thereon, the stack comprising one or more layers of a first material alternating with one or more layers of a second material, the stack comprising a silicon-containing material, the substrate further comprising a patterned mask layer disposed over the stack; b. flowing a process gas into the reaction chamber and generating a plasma from the process gas, the process gas comprising: i. a chlorine source comprising molecules containing only carbon, hydrogen, bromine, and chlorine, or molecules containing only chlorine, carbon, and nitrogen; ii. a carbon source; iii. a fluorine source; iv. a hydrogen source; Including, exposing the substrate to the plasma to etch a recessed feature in the stack on the substrate, the recessed feature being etched through one or more of the layers of the first material and one or more of the layers of the second material, and the substrate support being maintained at a cryogenic temperature during etching.

2. 10. The method of claim 1, wherein the first material comprises silicon nitride and the second material comprises silicon oxide.

3. 3. The method of claim 2, wherein the stack further comprises one or more layers of a third material alternating with the one or more layers of the first material comprising silicon nitride and the one or more layers of the second material comprising silicon oxide.

4. The method of claim 3 , wherein the third material comprises polysilicon.

5. 10. The method of claim 1, wherein the first material comprises silicon nitride and the second material comprises polysilicon.

6. 6. The method according to claim 1, wherein the chlorine source is ClCN, CH 2 BrCl, C 2 H 2 BrCl, and C 2 H 4 BrCl.

7. The method of any of claims 1 to 5, wherein the substrate support is maintained at a cryogenic temperature between -40°C and -10°C during etching.

8. 6. The method according to any one of claims 1 to 5, wherein the plasma is a capacitively coupled plasma generated at an RF power between 10 and 100 kW.

9. 6. The method of claim 1, wherein the hydrogen source is H 2 , C.H. x F y (where 1≦x≦4 and x+y=4), C x H y F z (where z>0), and combinations thereof.

10. 6. The method of claim 1, wherein the hydrogen source is H 2 A method comprising:

11. 6. The method of claim 1, wherein the fluorine source is NF 3 , C.H. x F y (where 0≦x≦3 and x+y=4), C x F y (where y≧x), C x H y F z (where z>0), and combinations thereof.

12. 6. The method according to claim 1, wherein the carbon source is CH x F y (where 0≦x≦4 and x+y=4), C x F y (where y≧x), C x H y F z (where z>0), and combinations thereof.

13. 6. The method according to claim 1, wherein the process gas is H 2 , N.F. 3 , C.H. 2 F 2 , C.F. 4 , and HBr and CF 3 The method includes at least one of I.

14. 6. The method of claim 1, wherein the recessed features formed have a 3σ twist of 10 nm or less.

15. 6. The method of claim 1, wherein the recessed features formed have a depth of at least 4000 nm.

16. The method of any of claims 1 to 5, wherein the formed recessed features have an ellipticity of 1.15 or less.

17. The method of any preceding claim, wherein the recessed features formed have a maximum critical dimension of 115 nm or less and / or a max-bottom CD of 40 nm or less.

18. 1. An apparatus for etching a recessed feature on a substrate, comprising: a. a reaction chamber; b. a substrate support disposed within the reaction chamber; c. a plasma generator configured to generate a plasma within the reaction chamber; d. one or more inlets to the reaction chamber; e. A controller and wherein the controller i. providing the substrate on the substrate support in the reaction chamber; ii. flowing a process gas into the reaction chamber to generate the plasma from the process gas, the process gas comprising:

1. A chlorine source comprising a molecule containing only carbon, hydrogen, bromine, and chlorine, or a molecule containing only chlorine, carbon, and nitrogen; 2. a carbon source; 3. a fluorine source; 4. Hydrogen source and Including, exposing the substrate to the plasma to etch the recessed feature into a stack on the substrate, the stack including one or more alternating layers of a first material including a silicon-containing material and one or more layers of a second material, the recessed feature being etched through one or more of the layers of the first material and one or more of the layers of the second material, and the substrate support being maintained at a cryogenic temperature during etching; 2. An apparatus configured to cause a

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