Multiplier operation method, operation device, electronic device, and storage medium

Abstract

To provide an operation method of a multiplier, operation apparatus, electronic device, and storage medium which realize multiplication operations with multiple precision, and reduce hardware resource consumption and hardware area.SOLUTION: A method includes the steps of: determining a plurality of input data groups of a multiplier and an encoding manner for the multiplier; determining at least one low-order bit input data group in the plurality of input data groups; determining a carry compensation term corresponding to the at least one low-order bit input data group based on the at least one low-order bit data group and the encoding manner; determining a target partial product array based on the carry compensation term corresponding to the at least one low-order bit input data group and the plurality of input data groups; and determining a multiplication operation result for each input data group based on the target partial product array.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] This application claims priority to a Chinese patent application bearing application number 202310468468.2, filed on April 27, 2023, the entire contents of which are incorporated herein by reference.

[0002] The present disclosure relates to the technical field of data processing, and more particularly to a multiplier operation method, an operation device, an electronic device, and a storage medium. [Background technology]

[0003] In a microprocessor chip, the multiplier is the core of digital signal processing. Optimizing the speed and area of ​​the multiplier is very important to the overall performance of the microprocessor. In addition, the variety of the multiplier's calculation precision is also very important to the performance of the microprocessor, since it determines the range of algorithms that the microprocessor can process.

[0004] To solve the above problems, the present disclosure provides a multiplier operation method, an operation device, an electronic device, and a storage medium, thereby realizing multi-precision multiplication operations and reducing hardware resource consumption and hardware area. Summary of the Invention [Problem to be solved by the invention]

[0005] Generally, one multiplier performs multiplication operations with one precision. In a related solution, multiple multipliers are combined to perform multiplication operations with precisions other than the one precision, thereby achieving multi-precision multiplication operations. However, combining multiple multipliers has the problem of consuming a large amount of hardware resources and incurring a large area overhead. [Means for solving the problem]

[0006] A multiplier operation method according to a first aspect of the present disclosure includes the steps of determining a plurality of input data groups of the multiplier and an encoding method for the multiplier, determining at least one lower-order bit input data group among the plurality of input data groups, determining a carry compensation term corresponding to the at least one lower-order bit input data group based on the at least one lower-order bit data group and the encoding method, determining a target partial product array based on the carry compensation term corresponding to the at least one lower-order bit input data group and the plurality of input data groups, and determining a multiplication operation result for each input data group based on the target partial product array.

[0007] An arithmetic device according to a second aspect of the present disclosure includes a compensation determination module, a partial product sequencing module, and a partial product processing module, wherein the compensation determination module is for determining a plurality of input data groups of a multiplier and an encoding method of the multiplier, determining at least one lower-order input data group among the plurality of input data groups, and determining a carry compensation term corresponding to the at least one lower-order input data group based on the at least one lower-order data group and the encoding method.

[0008] The partial product sequencing module is for determining a target partial product sequencing based on the carry compensation terms corresponding to at least one lower-order bit input data group determined by the compensation determination module and the plurality of input data groups, and the partial product processing module is for determining a multiplication operation result for each input data group based on the target partial product sequencing determined by the partial product sequencing module.

[0009] A computer-readable storage medium according to a third aspect of the present disclosure stores a computer program for executing the multiplier operation method according to the first aspect described above.

[0010] An electronic device according to a fourth aspect of the present disclosure includes a processor and a memory storing instructions executable by the processor, the processor reading the executable instructions from the memory and executing the instructions to implement the multiplier calculation method according to the first aspect.

[0011] A fifth aspect of the present disclosure provides a computer program product, and when computer program instructions in the computer program product are executed by a processor, the multiplier operation method according to the first aspect above is performed. [Effects of the Invention]

[0012] According to the multiplier operation method, device, electronic device, and storage medium disclosed herein, when a carry compensation term corresponding to at least one lower-order input data group is added to a target partial product array (PPA), the target PPA includes not only the sub-PPAs corresponding to each lower-order input data group but also the carry compensation terms corresponding to each lower-order input data group. Furthermore, during the accumulation process of the target PPA, the carry compensation terms corresponding to each lower-order input data group in the target PPA can offset the carries occurring when the sub-PPAs corresponding to the lower-order input data group are accumulated, and the carries occurring when the sub-PPAs corresponding to each lower-order input data group are accumulated do not affect the results of the multiplication operation of the upper-order input data group corresponding to each lower-order input data group. This ensures the accuracy of the results of the multiplication operation of the upper-order input data group corresponding to each lower-order input data group among multiple input data groups. Furthermore, since the results of the multiplication operation of at least one lower-order input data group among the multiple input data groups are also accurate, the results of the multiplication operation of each input data group are accurate, thereby realizing multi-precision multiplication operations. Furthermore, the multiplier calculation method according to the present disclosure does not require combining multiple multipliers, and can realize multi-precision multiplication calculations with a single multiplier, thereby reducing hardware resource consumption and hardware area. [Brief explanation of the drawings]

[0013] [Figure 1] 1 is a first schematic flowchart of a multiplier operation method according to the present disclosure. [Figure 2] FIG. 1 is a schematic diagram of a target PPA corresponding to one input data group according to the present disclosure. [Figure 3] FIG. 10 is a schematic diagram of a target PPA corresponding to multiple input data groups according to the present disclosure. [Figure 4] 10 is a second schematic flowchart of a multiplier operation method according to the present disclosure. [Figure 5] 10 is a third schematic flowchart of a multiplier operation method according to the present disclosure. [Figure 6] 4 is a fourth schematic flowchart of a multiplier operation method according to the present disclosure. [Figure 7] 5 is a fifth schematic flowchart of a multiplier operation method according to the present disclosure. [Figure 8] 1 is a first structural schematic diagram of an electronic device according to the present disclosure. [Figure 9] 10 is a schematic diagram of another target PPA corresponding to multiple input data groups according to the present disclosure. [Figure 10] 1 is a schematic flow chart illustrating a method for performing a multiplier operation on multiple input data groups according to the present disclosure. [Figure 11] 10 is a schematic flow chart illustrating another method for performing a multiplier operation on multiple input data groups according to the present disclosure. [Figure 12] 1 is a first structural schematic diagram of a computing device according to the present disclosure; [Figure 13] FIG. 2 is a second structural schematic diagram of a computing device according to the present disclosure. [Figure 14] FIG. 10 is a third structural schematic diagram of a computing device according to the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0014] In order to explain the present disclosure, the embodiments of the present disclosure will be described in detail below with reference to the drawings. The described embodiments are not all of the embodiments of the present disclosure, but are merely a part of the embodiments of the present disclosure, and the present disclosure is not limited to the exemplary embodiments.

[0015] The relative arrangement of parts and steps, formulas, and numerical values ​​described in this example do not limit the scope of the present disclosure unless otherwise stated.

[0016] Hereinafter, the terms "first" and "second" are for descriptive purposes only and are not intended to denote or imply relative importance, nor do they encompass the number of technical features shown. Thus, a feature with "first" or "second" may expressly or imply the inclusion of one or more of the relevant feature. In the description of this disclosure, unless otherwise stated, "plurality" means two or more than two. "A and / or B" includes including only A, including only B, and a combination of A and B. (Application Summary)

[0017] To achieve multi-precision multiplication, related solutions may use one multiplier to calculate one low-precision multiplication, or may use a combination of multiple multipliers to calculate high-precision multiplication. Specifically, the related solutions propose the following: two high-precision data are each divided into lower-bit data and upper-bit data, and multiple multipliers capable of performing low-precision multiplication are used to calculate the multiplication result of the two lower-bit data, the multiplication result of the lower-bit data and the upper-bit data, and the multiplication result of the two upper-bit data, respectively. The multiplication results of the multiple multipliers are then accumulated according to weights to obtain the multiplication result of two high-precision data. The low-precision multiplication and high-precision multiplication are achieved using the low-precision multipliers.

[0018] For example, take the int16 multiplicand A and multiplier B as an example, and multiplicand A=a 15 a 14 …a1a0, multiplier B=b15 b 14 ...b1b0. In a related solution, the multiplicand A is a set of two int8 data (i.e., A H , A L ), and the multiplier B is also divided into two int8 data (B H , B L ), where A=A H ×2 8 +A L , A H =a 15 a 14 …a9a8, A L =a7a6...a1a0. B=B H ×2 8 +B L , B H =b 15 b 14 …b9b8, B L =b7b6...b1b0. And the related solution is to use four multipliers that can perform int8 multiplication operations to H and B H The result of the multiplication with A H and B L The result of the multiplication with A L and B H The result of the multiplication with A L and B L The multiplication results of multiplicand A and multiplier B are calculated, and the four multiplication results are accumulated according to the weights to obtain the multiplication result of multiplicand A and multiplier B. The multiplication result of multiplicand A and multiplier B is shown in the following equation (1).

[0019] A×B=A H ×B H ×2 16 +(A H ×B L +A L ×B H )×2 8 +A L ×B L (1)

[0020] The related solution combines four int8 multipliers to realize int16 multiplication operations.

[0021] Although the above-mentioned related solutions can realize multi-precision multiplication operations such as low precision and high precision, to realize high precision multiplication operations, multiple low precision multipliers must be combined, and the use of multiple multipliers has problems such as high hardware resource consumption and large area overhead. (Example System)

[0022] The multiplier calculation method according to the embodiments of the present disclosure is widely used in multiple scenarios, such as real-time image processing and digital signal processing.

[0023] The multiplication operation method of the multiplier according to the embodiments of the present disclosure can be performed by an electronic device or a computing device, which can be provided in the electronic device and can be a part of the electronic device (e.g., a CPU, a microprocessor chip, or a multiplier). (Exemplary Method)

[0024] 1 is a schematic flowchart of a multiplier calculation method according to an exemplary embodiment of the present disclosure. The multiplier calculation method according to this embodiment can be applied to electronic devices, and as shown in FIG. 1, can include the following steps S101 to S105.

[0025] In step S101, a plurality of input data groups of the multiplier and the encoding method of the multiplier are determined.

[0026] The electronic device may include a multiplier that performs a multiplication operation on two data. The electronic device may receive a plurality of input data groups, send the plurality of input data groups to the multiplier, and then have the multiplier perform an arithmetic operation on the plurality of input data groups. Here, each of the plurality of input data groups may include one multiplier and one multiplicand. The multiplier and the multiplicand may be signed or unsigned numbers.

[0027] In some embodiments, the maximum data bit width that can be implemented by a multiplier in an electronic device is N, and the multiplier can perform multiplication operations of multiple data bit widths (which can be called multi-precision multiplication operations). All of the multiple data bit widths that the multiplier can implement are smaller than N. That is, the multiplier can calculate a multiplication operation of two data pieces with a data bit width of N, and a multiplication operation of two data pieces with a data bit width of at least one of the data pieces being a different data bit width. The different data bit width is smaller than N, where N is a positive integer (e.g., 32, 16, or 8).

[0028] In some embodiments, the electronic device may receive multiple groups of input data entered by a user, or may generate multiple groups of input data.

[0029] For example, a plurality of input data groups acquired by the electronic device can be divided into one multiplier (which can be referred to as a first multiplier) and one multiplicand (which can be referred to as the first multiplicand). The first multiplier is composed of a plurality of second multipliers. The first multiplicand is composed of a plurality of second multiplicands. The plurality of second multipliers and the plurality of second multiplicands correspond one-to-one, and one second multiplier and its corresponding one second multiplicand constitute one input data group. Here, the data bit width of the first multiplier and the data bit width of the first multiplicand are both equal to or less than N. The data bit width of the second multiplier is equal to or less than the data bit width of the first multiplicand, and the data bit width of the second multiplicand is equal to or less than the data bit width of the first multiplicand.

[0030] In some embodiments, the electronic device receives a plurality of input data groups, and the data bit widths of the second multiplier and the second multiplicand included in each of the plurality of input data groups may be the same or different. If the data bit widths of the second multiplier and the second multiplicand in any one of the input data groups are different, the electronic device can pre-process the input data group to obtain a pre-processed input data group, and then update any one of the input data groups to the pre-processed input data group. Here, the data bit widths of the second multiplier and the second multiplicand in the pre-processed input data group are the same, and the magnitudes of the values ​​of the input data group before and after pre-processing are the same (including the magnitudes of the values ​​of the second multiplier before and after pre-processing being the same, and the magnitudes of the values ​​of the second multiplicand before and after pre-processing being the same).

[0031] Further, the electronic device can obtain updated input data groups and continue to execute S102 on the updated input data groups, wherein the second multiplier and the second multiplicand included in each of the updated input data groups have the same data bit width.

[0032] For example, one input data group includes one multiplier with a data bit width of 8 bits (bit) and one multiplicand with a data bit width of 16 bits, and the electronic device can pre-process the multiplier in the input data group to obtain a multiplier with a data bit width of 16 bits. The pre-processing includes adding an 8-bit number to bits higher than the most significant bit of the multiplier, and all of the 8-bit number are 0.

[0033] In the embodiment of the present disclosure, an input data group in which the included second multiplier and second multiplicand have the same data bit width will be taken as an example to describe the operation method of the multiplier according to the embodiment of the present disclosure.

[0034] In some embodiments, the data bit widths of different input data groups in the plurality of input data groups may be the same or different. The data bit width of each input data group may refer to the data bit width of the second multiplier included in the input data group, or may refer to the data bit width of the second multiplicand included in the input data group. For example, the plurality of input data groups may include two 8-bit input data groups. As another example, the plurality of input data groups may include one 8-bit input data group and one 16-bit input data group.

[0035] In some embodiments, the electronic device may pre-store the encoding scheme of the multiplier, for example, the encoding scheme of the multiplier may be radix-4 Booth encoding or radix-8 Booth encoding.

[0036] The operating principle of a multiplier to calculate the result of multiplication of one multiplier and one multiplicand is as follows: The first digit of the multiplier is multiplied by all the digits in the multiplicand to generate a set of product terms corresponding to the first digit; the second digit of the multiplier is multiplied by all the digits in the multiplicand to generate a set of product terms corresponding to the second digit; and similar processes are carried out for the other digits of the multiplier. The product terms (which can be considered multiple sets of product terms) corresponding to all the digits in the multiplier are then arranged to obtain a partial product array (PPA). The process of "arranging product terms corresponding to all the digits in the multiplier" involves shifting the set of product terms corresponding to the second digit one place to the left compared to the set of product terms corresponding to the first digit, shifting the set of product terms corresponding to the third digit one place to the left compared to the set of product terms corresponding to the second digit, and similar processes are carried out for the other product terms. Finally, the partial product array is accumulated to obtain the result of the multiplication operation between the multiplier and the multiplicand.

[0037] Here, both the multiplier and the multiplicand can be binary numbers. If the single digit of the multiplier is 1, the set of product terms corresponding to this single digit is the multiplicand. If the single digit of the multiplier is 0, the set of product terms corresponding to this single digit are all 0.

[0038] Booth coding also transforms the multiplier to reduce the number of non-zero values ​​contained in the transformed multiplier, thereby reducing the number of partial products and the size of the PPA. In other words, multipliers in electronic devices use Booth coding to accelerate the generation of PPAs. Different radix Booth codings also reduce the number of partial products that can be reduced. For example, radix-4 Booth coding (i.e., radix-4 Booth coding) can reduce the number of rows of partial products contained in a PPA by half, while radix-8 Booth coding (i.e., radix-8 Booth coding) can reduce the number of rows of partial products contained in a PPA by approximately one-third.

[0039] For example, the multiplier A of int16, which is signed data, 16 and int16 multiplicand B 16 For example, the electronic device uses radix-4 Booth coding to generate a multiplier A 16 and multiplicand B 16 As shown in Figure 2, all black dots in the PPA shown in Figure 2 represent product terms, and s represents the multiplier A 16 is the sign bit obtained by Booth coding, and e is the multiplier A 16 indicates the sign bit of a set of product terms corresponding to the value of each bit of , and ￣e indicates the value obtained by inverting e in the first row of the PPA. All s values ​​in Figure 2 are either 1 or 0, and the s values ​​in different rows of the PPA may be the same or different. All e values ​​in Figure 2 are either 1 or 0, and the e values ​​in different rows of the PPA may be the same or different.

[0040] int16 multiplier A 16 and multiplicand B 16For the PPA generated by the electronic device using base 4-Booth coding, the number of rows of product terms included in the PPA is 8. The electronic device employs 4-Booth coding to reduce the number of rows of product terms included in the PPA from 16 to 8.

[0041] In step S102, at least one lower-order bit input data group from among the plurality of input data groups is determined.

[0042] The electronic device can determine at least one least significant bit input data group from the plurality of input data groups based on the position of each input data group in the plurality of input data groups, where the at least one least significant bit input data group includes an input data group other than the most significant bit input data group in the plurality of input data groups, and the most significant bit input data group is an input data group located at the most significant bit among the plurality of input data groups.

[0043] In some embodiments, the position of each input data group in the plurality of input data groups can be the number of each input data group in the plurality of input data groups (e.g., first, second, third, etc.). The number of each input data group in the plurality of input data groups indicates the order of bits that the input data group occupies in the plurality of input data groups. The smaller the number of each input data group in the plurality of input data groups, the lower the bit that the input data group occupies in the plurality of input data groups.

[0044] For example, the first multiplier A has a data bit width of 32 bits. 32 and the first multiplicand B, whose data bit width is 32 bits. 32 For example, let us consider multiple input data groups including A and B. 32 =a 31 a 30 …a1a0, B 32 =b 31 b 30 ...b1b0. First multiplier A 32includes a plurality of second multipliers, each of which has a data bit width of 16 bits. 16-1 , the second multiplier A whose data bit width is 8 bits 8-2 and a second multiplier A whose data bit width is 8 bits. 8-3 A 16-1 =a 15 a 14 …a1a0, A 8-2 =a 23 a 22 …a 17 A 16 , A 8-3 =a 31 a 30 …a 25 a 24 A in multiple input data groups 16-1 , A 8-2 and A 8-3 number (i.e., the first multiplier A 32 A in 16-1 , A 8-2 and A 8-3 The numbers are 1st, 2nd and 3rd respectively.

[0045] First multiplier B 32 includes a plurality of second multiplicands, each of which has a data bit width of 16 bits. 16-1 , the second multiplicand B whose data bit width is 8 bits 8-2 and a second multiplicand B whose data bit width is 8 bits. 8-3 B 16-1 =b 15 b 14 …b1b0, B 8-2 =b 23 b 22 …b 17 b 16 , B 8-3 =b 31 b 30 …b 25 b 24 B in multiple input data groups 16-1 , B 8-2 and B 8-3 number (i.e., the first multiplicand B 32B in 16-1 , B 8-2 and B 8-3 The numbers are 1st, 2nd and 3rd respectively.

[0046] Here, the first multiplier A 32 and the first multiplicand B 32 and a second multiplier A is applied to at least one lower-order bit input data group. 16-1 and the second multiplicand B 16-1 and a second multiplier A 8-2 and the second multiplicand B 8-2 and another lower-order bit input data group constituted by:

[0047] In some embodiments, in addition to acquiring the multiple input data groups, the electronic device can acquire an input signal, where the input signal indicates the data bit width of each input data group included in the multiple input data groups (which can be said to be the data precision of each input data group). The input signal can include multiple sets of numerical values, where the multiple sets of numerical values ​​occupy different bits in the input signal, and the positions of the numerical values ​​of each set in the input signal are the same as the positions of the input data groups corresponding to each set of numerical values ​​in the multiple input data groups (e.g., the numbers of each set of numerical values ​​in the input signal are the same as the numbers of the input data groups corresponding to each set of numerical values ​​in the multiple input data groups). Furthermore, the electronic device can determine the positions of each input data group in the multiple input data groups based on the input signal.

[0048] Here, each set of values ​​may include one or more values, and each set of values ​​may indicate the data bit width of one input data group corresponding to the corresponding set of values.

[0049] Exemplarily, the input signal dxlp may be data with a data bit width of 8 bits, where dxlp = d7d6...d1d0. The values ​​of the first and second bits of the input signal dxlp (i.e., the value d1d0) indicate the data bit width of the first input data group in the plurality of input data groups. The values ​​of the third and fourth bits of the input signal dxlp (i.e., the value d3d2) indicate the data bit width of the second input data group in the plurality of input data groups. The values ​​of the fifth and sixth bits of the input signal dxlp (i.e., the value d5d4) indicate the data bit width of the third input data group in the plurality of input data groups. The values ​​of the seventh and eighth bits of the input signal dxlp (i.e., the value d7d6) indicate the data bit width of the fourth input data group in the plurality of input data groups.

[0050] Here, the value indicating the data bit width of one input data group in the input signal dxlp may be the same as or different from this data bit width. For example, d1d0=01 indicates that the data bit width of the first input data group in the multiple input data groups is 8 bits. As another example, d7d6=00 indicates that the data bit width of the fourth input data group in the multiple input data groups is 0 bits, which indicates that the multiple input data groups do not include a fourth input data group.

[0051] In the above example, the input signal dxlp was described as an example in which two bits of the input signal dxlp indicate the data bit width of one input data group, but the data bit width of one input data group can also be indicated by other numbers of multiple bits in the input signal dxlp (e.g., three bits, four bits, etc.), and the greater the number of multiple bits, the greater the variety of data group widths of one input data group indicated by the multiple bits.

[0052] In step S103, a carry compensation term corresponding to the at least one lower-order bit input data group is determined based on the at least one lower-order bit input data group and the encoding method.

[0053] In a process in which the electronic device calculates a multiplication operation result of multiple input data groups using one multiplier, PPAs corresponding to the multiple input data groups can be obtained. The PPA can include sub-PPAs (sub-PPAs corresponding to each lower-order bit input data group) corresponding to each input data group, and the sub-PPA corresponding to each input data group is a PPA obtained by multiplying the input data groups. A carry occurs when the sub-PPAs corresponding to each lower-order bit input data group in the multiple input data groups are accumulated, and this carry affects the multiplication operation result of one upper-order bit input data group corresponding to each lower-order bit input data group. Therefore, the electronic device determines a carry compensation term corresponding to at least one lower-order bit input data group in the multiple input data groups. The carry compensation term corresponding to each lower-order bit input data group offsets the carry when the sub-PPAs corresponding to that lower-order bit input data group are accumulated.

[0054] Here, the bits occupied by one upper bit input data group corresponding to each lower bit input data group in the plurality of input data groups are higher than the bits occupied by the lower bit input data group in the plurality of input data groups, and the bits occupied by the upper bit input data group in the plurality of input data groups are adjacent to the bits occupied by the lower bit input data group in the plurality of input data groups. 16-1 and the second multiplicand B 16-1 The second multiplier A is input to one upper input data group corresponding to one lower bit input data group configured by 8-2 and the second multiplicand B 8-2 Includes:

[0055] The carry compensation term corresponding to each lower-order bit input data group is used to offset a carry when the sub-PPA corresponding to that lower-order bit input data group is accumulated, and the sub-PPA corresponding to that lower-order bit input data group depends on the second multiplier and second multiplicand included in that lower-order bit input data group and the encoding method of the multiplier used to generate the sub-PPA. Thus, the electronic device can determine the carry compensation term corresponding to each lower-order bit input data group based on each lower-order bit input data group and the encoding method of the multiplier.

[0056] For example, the plurality of lower-order bit input data groups include a first multiplier A of int16, which is all signed data. 16 and the first multiplicand B of int16 16 contains the first multiplier A 16 contains two second multipliers (i.e., second multiplier A 8-1 and the second multiplier A 8-1 ) and the first multiplicand B 16 contains two second multiplicands (i.e., second multiplicand B 8-1 and the second multiplicand B 8-1 ) is included, A 8-1 =a7a6…a1a0, A 8-2 =a 15 a 14 …a9a8, B 8-1 =b7b6…b1b0, B 8-2 =b 15 b 14 …b9b8. A 8-1 and A 8-2 and the first multiplier A 16 The numbers in are the first and second places, respectively. B 8-1 and B 8-2 and the first multiplicand B 16 The numbers in are the first and second digits, respectively. The second multiplier A 8-1 and the second multiplicand B 8-1 The input data group (which can be said to be the first input data group) is composed of the second multiplier A 8-2 and the second multiplicand B 8-2The first-order input data group is the lower-order bit input data group, and the upper-order bit input data group corresponding to the first-order input data group is the second-order input data group.

[0057] The electronics uses radix-4 Booth coding to generate the first multiplier A 16 and the first multiplicand B 16 A PPA (which may be referred to as an initial PPA) can be generated based on the first and second input data groups. The initial PPA includes a sub-PPA corresponding to the first input data group and a sub-PPA corresponding to the second input data group.

[0058] 3, the sub-PPA corresponding to the first-order input data group includes all product terms indicated by black dots in rows 1 to 4 and all sign bits in rows 1 to 4. All sign bits in rows 1 to 4 include s0, e0, ̂e0, and 1. Here, s0 is the second multiplier A 8-1 is the sign bit obtained by Booth encoding, and e0 is the second multiplier A 8-1 indicates the sign bit of a set of product terms corresponding to the value of each bit of , and ￣e0 indicates the value obtained by inverting e0 in the first row of the PPA. All s0 values ​​in Figure 3 are either 1 or 0, and the values ​​of s0 in different rows of the PPA may be the same or different. All e0 values ​​in Figure 3 are either 1 or 0, and the values ​​of e0 in different rows of the PPA may be the same or different.

[0059] Referring to Figure 3, the sub-PPA corresponding to the second-order input data group includes all product terms indicated by black dots in rows 5 to 8 and all sign bits in rows 5 to 8. All sign bits in rows 5 to 8 include s1, e1, ̂ e1, and 1. Here, s1 is the second multiplier A 8-2 is the sign bit obtained by Booth encoding, and e1 is the second multiplier A 8-2indicates the sign bit of a set of product terms corresponding to the value of each bit of , and ￣e1 indicates the value obtained by inverting e1 in the fifth row of the PPA. All s1 values ​​in Figure 3 are either 1 or 0, and the values ​​of s1 in different rows of the PPA may be the same or different. All e1 values ​​in Figure 3 are either 1 or 0, and the values ​​of e1 in different rows of the PPA may be the same or different.

[0060] Furthermore, the second multiplier A 8-1 and the second multiplicand B 8-1 For a lower-order bit input data group constituted by: and, the electronic device can determine a carry compensation term corresponding to the lower-order bit input data group. The carry compensation term corresponding to the lower-order bit input data group offsets a carry when the sub-PPA corresponding to the lower-order bit input data group is accumulated.

[0061] In step S104, a target partial product array is obtained based on a carry compensation term corresponding to at least one lower-order bit input data group and the plurality of input data groups.

[0062] The electronic device can generate an initial PPA using multiple input data groups, and combine this initial PPA with a carry compensation term corresponding to at least one lower-bit input data group to obtain a target partial product array (i.e., a target PPA).

[0063] For example, the electronic device may 16 and the first multiplicand B 16 and generate an initial PPA using the second multiplier A. 8-1 and the second multiplicand B 8-1 A carry compensation term corresponding to the lower bit input data group composed of the first multiplier A and the second multiplier B is added to obtain the target PPA shown in FIG. 3. 8-1 and the second multiplicand B 8-1 and the carry compensation term corresponding to the lower-order input data group constituted by

[0064] Second multiplier A 8-1 and the second multiplicand B 8-1 The position of the carry when the sub-PPAs corresponding to the lower bit input data groups, which are configured as follows, are accumulated is at the position of the carry compensation term E shown in FIG. 3. The carry compensation term E can offset the carry when the sub-PPAs corresponding to the lower bit input data groups are accumulated, and the carry when the sub-PPAs corresponding to the lower bit input data groups are accumulated is offset by the carry compensation term E when the sub-PPAs corresponding to the lower bit input data groups are accumulated. 8-2 and the second multiplicand B 8-2 This ensures the accuracy of the multiplication result of the upper-bit input data group. In addition, since the multiplication result of the lower-bit input data group is also accurate, the multiplication result of each input data group is accurate, and multi-precision multiplication can be realized.

[0065] In step S105, the multiplication operation result for each input data group is determined based on the target partial product array.

[0066] The electronic device can accumulate the target PPA to obtain an accumulated result. The accumulated result can be constructed by combining the multiplication operation results of each input data group, and the position of the multiplication operation result of each input data group in the accumulated result (e.g., the number of the multiplication operation result of each input data group in the accumulated result) is the same as the position of each input data group in the multiple input data groups (e.g., the number of each input data group in the multiple input data groups).

[0067] The data bit width of the multiple input data groups is different from the data bit width of the accumulation result, for example, the data bit width of the multiple input data groups is 16, and the data bit width of the accumulation result corresponding to the multiple input data groups is 32. Therefore, it can be seen that the bits occupied by each input data group in the multiple input data groups are different from the bits occupied by the multiplication operation result of that input data group in the accumulation result.

[0068] For example, the number of a certain input data group among the plurality of input data groups is number 1, and the input data group is located from bit 1 to bit 16 among the plurality of input data groups. The number of the multiplication operation result of the input data group in the accumulation result is also number 1, but the multiplication operation result of the input data group is located from bit 1 to bit 32 in the accumulation result.

[0069] When the electronic device adds a carry compensation term corresponding to at least one lower-order input data group to the target PPA, the target PPA includes not only the sub-PPAs corresponding to each lower-order input data group but also the carry compensation terms corresponding to each lower-order input data group. Furthermore, when the electronic device accumulates the target PPA, the carry compensation terms corresponding to each lower-order input data group in the target PPA can offset the carries occurring when the sub-PPAs corresponding to the lower-order input data group are accumulated, and the carries occurring when the sub-PPAs corresponding to each lower-order input data group are accumulated do not affect the results of the multiplication operation of the upper-order input data group corresponding to each lower-order input data group. This ensures the accuracy of the results of the multiplication operation of the upper-order input data group corresponding to each lower-order input data group among the multiple input data groups. Furthermore, because the results of the multiplication operation of at least one lower-order input data group among the multiple input data groups are also accurate, the results of the multiplication operation of each input data group are accurate, thereby realizing multi-precision multiplication operations. Furthermore, the multiplier calculation method according to the present disclosure does not require combining multiple multipliers, and can realize multi-precision multiplication calculations with a single multiplier, thereby reducing the consumption of hardware resources and the hardware area.

[0070] In addition, in the process of using multiple low-precision multipliers to achieve high-precision multiplication in the above-mentioned related solutions, the multiple multiplication results output from the multiple multipliers need to be accumulated according to weights to obtain high-precision multiplication results. In the process of accumulating multiple multiplication results according to weights, it is necessary to shift the multiplication results with different weights (for example, in the related solutions, A H ×B H Shift the multiplication result of A H ×B H ×2 16 Get A H ×B L Shift the multiplication result of A H ×B L ×2 8 Get AL ×B H Shift the multiplication result of A L ×B H ×2 8 (Acquire high-precision multiplication results). The shift operation in the related solution increases the time required to obtain high-precision multiplication results. In the embodiments of the present disclosure, the electronic device can obtain the multiplication results (including high-precision multiplication results) of each input data group by simply accumulating the target PPA, eliminating the need for shift operations and reducing the time required to obtain the multiplication results (including high-precision multiplication results) of each input data group.

[0071] In some embodiments, the maximum data bit width that the multiplier in the electronic device can implement is N, so after determining the multiple input data groups, the electronic device can determine whether the sum of the data bit widths of the input data groups is less than or equal to N (i.e., less than or equal to N), and if the sum of the data bit widths of the input data groups is less than or equal to N, the electronic device can continue to execute the calculation method on the multiple input data groups, and if the sum of the data bit widths of the input data groups is greater than N, the electronic device can terminate the process.

[0072] Illustratively, step S102 in the multiplier operation method according to an embodiment of the present disclosure may include determining at least one lower-bit input data group among the plurality of input data groups according to the sum of the data bit widths of the input data groups being less than or equal to N.

[0073] The electronic device can perform a multiplication operation on one input data group whose data bit width is less than N bits using one multiplier whose maximum possible data bit width is N bits, and can also perform multiplication operations on multiple input data groups whose total data bit width is less than N bits.

[0074] In some embodiments, in order to offset the carry when the sub-PPAs corresponding to each lower-bit input data group are accumulated, it is necessary to set the compensation position of the carry compensation term corresponding to each lower-bit input data group based on the position of the carry when the sub-PPAs corresponding to each lower-bit input data group are accumulated, and to set the compensation value of the carry compensation term corresponding to each lower-bit input data group based on the numerical value of the carry when the sub-PPAs corresponding to each lower-bit input data group are accumulated.

[0075] As shown in FIG. 4, in addition to the embodiment shown in FIG. 1, step S103 in the multiplier calculation method according to the embodiment of the present disclosure may include the following steps S201 to S202.

[0076] In step S201, a position of a carry compensation term corresponding to at least one lower-order bit input data group is determined based on the encoding method, the data bit width of at least one lower-order bit input data group, and the position of the at least one lower-order bit input data group among the multiple input data groups.

[0077] The electronic device can determine the number of rows of the sub-PPA corresponding to each lower-order bit input data group based on the encoding method of the multiplier, the data bit width of the second multiplier included in each lower-order bit input data group (i.e., the data bit width of each lower-order bit input data group), and the position of each lower-order bit input data group among the multiple input data groups.The electronic device then determines the compensation position of the carry compensation term corresponding to each lower-order bit input data group based on the number of rows of the sub-PPA corresponding to each lower-order bit input data group.

[0078] In some embodiments, the electronic device determines the position of the last row of the sub-PPA corresponding to each of the at least one lower-order bit input data group based on the encoding method of the multiplier, the data bit width of the at least one lower-order bit input data group, and the position of the at least one lower-order bit input data group among the plurality of input data groups, and the position of the last row of the sub-PPA corresponding to each lower-order bit input data group is the position of the carry compensation term corresponding to that lower-order bit input data group.As shown in Figure 5, in addition to the embodiment shown in Figure 4 above, step S201 in the operation method of the multiplier according to this embodiment can include the following steps S301 to S302.

[0079] In step S301, the position of the last row of the sub partial product array corresponding to at least one lower-order bit input data group is determined based on the encoding method, the data bit width of at least one lower-order bit input data group, and the position of at least one lower-order bit input data group among the multiple input data groups.

[0080] Here, the position of the last row of the sub-PPA corresponding to each lower-order bit input data group can refer to the row number of the last row of that sub-PPA in the PPA corresponding to multiple input data groups.

[0081] In some embodiments, the position of each input data group in the plurality of input data groups may refer to the number of each input data group in the plurality of input data groups. Further, the electronic device determines a bit position of the at least one lower-order bit input data group in the plurality of input data groups based on a data bit width of the at least one lower-order bit input data group and the position of the at least one lower-order bit input data group in the plurality of input data groups, and determines a position of a last row of the sub-PPA corresponding to each lower-order bit input data group based on an encoding scheme of the multiplier and the bit position of the at least one lower-order bit input data group in the plurality of input data groups.

[0082] Here, the plurality of input data groups may include a first multiplier and a first multiplicand, and each lower-order bit input data group may include a second multiplier and a second multiplicand. The bit position that each lower-order bit input data group occupies in the plurality of input data groups may refer to the bit position that the second multiplier occupies in the first multiplier, or may refer to the bit position that the second multiplicand occupies in the first multiplicand.

[0083] Illustratively, the plurality of input data groups are 32 and the first multiplicand B 32 and at least one lower-order bit input data group among the plurality of input data groups is provided with the second multiplier A 16-1 and the second multiplicand B 16-1 The first lower-order bit input data group is composed of the second multiplier A 8-2 and the second multiplicand B 8-2 and a second lower-order bit input data group consisting of: and the first lower-order bit input data group consisting of: and the second ...

[0084] Here, the bit position that the first lower-order bit input data group occupies in the plurality of input data groups is determined by the second multiplier A 16-1is the first multiplier A 32 or the bit position occupied in the second multiplicand B 16-1 is the first multiplicand B 32 The bit position that the second least significant bit input data group occupies in the plurality of input data groups may refer to the bit position that the second least significant bit input data group occupies in the second multiplier A 8-2 is the first multiplier A 32 or the bit position occupied in the second multiplicand B 8-2 is the first multiplicand B 32 It may also refer to the bit position occupied in

[0085] Furthermore, taking as an example that the encoding method of the multiplier is radix-4 Booth encoding, the electronic device can determine, based on the radix-4 Booth encoding and the bit positions occupied by the first least significant input data group in the multiple input data groups being bits 1 to 16, that the position of the last row of the sub-PPA corresponding to the first least significant input data group is row 8. Similarly, based on the radix-4 Booth encoding and the bit positions occupied by the second least significant input data group in the multiple input data groups being bits 17 to 24, the electronic device can determine that the position of the last row of the sub-PPA corresponding to the second least significant input data group is row 12.

[0086] In step S302, a compensation position of a carry compensation term corresponding to at least one lower-order bit input data group is determined based on the position of the last row of the sub partial product array corresponding to at least one lower-order bit input data group.

[0087] The electronic device can determine that the position of the last row of the sub-PPA corresponding to each lower-order bit input data group is the compensation position of the carry compensation term corresponding to that lower-order bit input data group. For example, if the position of the last row of the sub-PPA corresponding to the first lower-order bit input data group is row 8, the compensation position of the carry compensation term corresponding to the first lower-order bit input data group is row 8 of the PPA corresponding to the multiple input data groups. As another example, if the position of the last row of the sub-PPA corresponding to the second lower-order bit input data group is row 12, the compensation position of the carry compensation term corresponding to the second lower-order bit input data group is row 12 of the PPA corresponding to the multiple input data groups.

[0088] The carry when the sub-PPA corresponding to each lower-order bit input data group is accumulated is located in the last row of the sub-PPA. Therefore, the compensation position of the carry compensation term corresponding to the lower-order bit input data group is set to the last row of the sub-PPA so that the carry compensation term corresponding to the lower-order bit input data group can offset the carry when the sub-PPA corresponding to the lower-order bit input data group is accumulated.

[0089] In step S202, a compensation value of a carry compensation term corresponding to at least one lower-order bit input data group is determined based on the value of the sign bit of each data in at least one lower-order bit input data group.

[0090] The electronic device can determine a compensation value of a carry compensation term corresponding to each lower-order bit input data group based on a numerical value of a sign bit of each data in each lower-order bit input data group, where each lower-order bit input data group can include a second multiplier and a second multiplicand, and the numerical value of the sign bit of each data in each lower-order bit input data group can include a numerical value of a sign bit of the second multiplier and a numerical value of a sign bit of the second multiplicand.

[0091] Illustratively, each data (e.g., the second multiplier or the second multiplicand) in each lower-order bit input data group may include a sign bit, and the value of the sign bit indicates the sign type of each data. For example, if the value of the sign bit included in the second multiplier is 1, it indicates that the sign type of the second multiplier is a negative number. As another example, if the value of the sign bit included in the second multiplier is 0, it indicates that the sign type of the second multiplier is a positive number.

[0092] In some embodiments, the electronic device can determine a compensation value for a carry compensation term corresponding to each lower-order input data group based on the numerical value of the sign bit of each data included in that lower-order input data group. As shown in Fig. 5, in addition to the embodiment shown in Fig. 4 above, step S202 in the multiplier operation method according to this embodiment can include the following steps S303 to S304.

[0093] In step S303, an XNOR operation is performed on the numerical values ​​of the sign bits of the multiplier and multiplicand in each lower-order bit input data group to determine the numerical value after the XNOR operation.

[0094] Each lower-order bit input data group includes one multiplier (i.e., the second multiplier) and one multiplicand (i.e., the second multiplicand). The electronic device can perform an XNOR operation on the value of the sign bit of the second multiplier and the value of the sign bit of the second multiplicand to determine a value after the XNOR operation. Here, the value of the sign bit included in the second multiplier indicates the type of sign of the second multiplier. The value of the sign bit included in the second multiplicand indicates the type of sign of the second multiplicand.

[0095] For example, the value of the sign bit included in the second multiplier is 0 or 1. The value of the sign bit included in the second multiplicand is 0 or 1. The value after the XNOR operation is 0 or 1. Here, the type of sign indicated by 0 is a positive number, and the type of sign indicated by 1 is a negative number.

[0096] For example, when an electronic device performs an XNOR operation on 0 and 1, the resulting number after the XNOR operation is 0. As another example, when an electronic device performs an XNOR operation on 1 and 1, the resulting number after the XNOR operation is 1. As yet another example, when an electronic device performs an XNOR operation on 0 and 0, the resulting number after the XNOR operation is 1.

[0097] In some embodiments, the sign of the value obtained after the XNOR operation of each lower order input data group is the opposite of the sign of the result of the multiplication operation of that lower order input data group.

[0098] For example, if the sign of the second multiplier indicated by the value of the sign bit of the second multiplier included in the lower-bit input data group is positive, and the sign of the second multiplicand indicated by the value of the sign bit of the second multiplicand included in this lower-bit input data group is positive, the electronic device performs an XNOR operation on the value of the sign bit of the second multiplier and the value of the sign bit of the second multiplicand to determine a value after the XNOR operation. As a result, the sign of the value after the XNOR operation is negative, and the sign of the multiplication result corresponding to the lower-bit input data group is positive. This indicates that the sign of the value after the XNOR operation is opposite to the sign of the multiplication result corresponding to this lower-bit input data group.

[0099] As another example, if the sign of the second multiplier indicated by the value of the sign bit of the second multiplier included in the lower-bit input data group is positive, and the sign of the second multiplicand indicated by the value of the sign bit of the second multiplicand included in this lower-bit input data group is negative, the electronic device performs an XNOR operation on the value of the sign bit of the second multiplier and the value of the sign bit of the second multiplicand to determine a value after the XNOR operation. As a result, the sign of the value after the XNOR operation is positive, and the sign of the multiplication operation result corresponding to the lower-bit input data group is negative. This indicates that the sign of the value after the XNOR operation is opposite to the sign of the multiplication operation result corresponding to this lower-bit input data group.

[0100] In step S304, a compensation value for a carry compensation term corresponding to at least one lower-order bit input data group is determined based on the numerical value after the XNOR operation.

[0101] The electronic device can determine that the numerical value obtained after the XNOR operation of each lower-order bit input data group is the compensation value of the carry compensation term corresponding to that lower-order bit input data group. For example, if the numerical value obtained after the XNOR operation of the lower-order bit input data group is 0, the electronic device can determine that the compensation value of the carry compensation term corresponding to that lower-order bit input data group is 0. As another example, if the numerical value obtained after the XNOR operation of the lower-order bit input data group is 1, the electronic device can determine that the compensation value of the carry compensation term corresponding to that lower-order bit input data group is 1.

[0102] Since electronic devices typically calculate PPAs using binary numbers corresponding to multiple input data groups, the numerical value in the sub-PPA corresponding to each lower-order input data group is either 0 or 1, and the carry when the sub-PPAs corresponding to each lower-order input data group are accumulated is also either 0 or 1. The sign value of the multiplication result of each lower-order input data group indicates the sign of the multiplication result of that lower-order input data group, and the sign value is either 0 or 1. The sign indicated by the inverse of the sign value (e.g., the inverse of 0 is 1, and the inverse of 1 is 0) is the opposite of the sign of the multiplication result corresponding to the lower-order input data group, and the inverse of the sign value can cancel out the carry when the sub-PPAs corresponding to the lower-order input data group are accumulated. The sign indicated by the value after the XNOR operation corresponding to the lower-order input data group is also the opposite of the sign of the multiplication result corresponding to the lower-order input data group, so the value after the XNOR operation is the same as the inverse of the sign value, and similarly, the value after the XNOR operation can cancel out the carry when the sub-PPAs corresponding to the lower-order input data group are accumulated.

[0103] Here, when the first multiplier and the second multiplicand included in the plurality of input data groups are both binary numbers, the binary numbers corresponding to the plurality of input data groups are the first multiplier and the second multiplicand. When the first multiplier and the second multiplicand included in the plurality of input data groups are not binary numbers, the electronic device can convert the first multiplier and the second multiplicand, respectively, to obtain a converted first multiplier and a converted second multiplicand. The converted first multiplier and the converted second multiplicand are both binary numbers, and the binary numbers corresponding to the plurality of input data groups include the converted first multiplier and the converted second multiplicand.

[0104] In another embodiment, the electronic device can determine a code value indicating the type of sign of the multiplication operation result of each lower-order bit input data group based on the numerical value of the sign bit of each data included in each lower-order bit input data group, and determine a compensation value for the carry compensation term corresponding to that lower-order bit input data group based on this code value. As shown in Fig. 6, in addition to the embodiment shown in Fig. 4 above, step S202 in the operation method of the multiplier according to this embodiment can include the following steps S401 to S402.

[0105] In step S401, the sign value of the multiplication result of the multiplier and the multiplicand is determined based on the value of the sign bit of the multiplier and the multiplicand in each lower-order bit input data group.

[0106] The electronic device can determine the sign value of the multiplication result of the second multiplier and the second multiplicand (i.e., the sign value of the multiplication result of that lower-bit input data group) based on the numerical value of the sign bit of the second multiplier and the numerical value of the sign bit of the second multiplicand included in each lower-bit input data group.

[0107] For example, if the value of the sign bit included in the second multiplier is 0 and the value of the sign bit included in the second multiplicand is 0, the code value of the multiplication result of the second multiplier and the second multiplicand is 0. As another example, if the value of the sign bit included in the second multiplier is 0 and the value of the sign bit included in the second multiplicand is 1, the code value of the multiplication result of the second multiplier and the second multiplicand is 1. As yet another example, if the value of the sign bit included in the second multiplier is 1 and the value of the sign bit included in the second multiplicand is 1, the code value of the multiplication result of the second multiplier and the second multiplicand is 0. Here, the type of code indicated by the numerical value 0 is a positive number, and the type of code indicated by the numerical value 1 is a negative number.

[0108] In step S402, the sign value of the multiplication result is inverted to obtain the compensation value of the carry compensation term corresponding to each lower-order bit input data group.

[0109] For example, a sign value of 0 of the multiplication result of the lower-order input data group indicates that the sign of the multiplication result is a positive number, and the electronic device can determine that the compensation value of the carry compensation term corresponding to the lower-order input data group is 1. As another example, a sign value of 1 of the multiplication result of the lower-order input data group indicates that the sign of the multiplication result is a negative number, and the electronic device can determine that the compensation value of the carry compensation term corresponding to the lower-order input data group is 0.

[0110] The sign value of the multiplication operation result of each lower-order bit input data group indicates the sign type of the multiplication operation result of that lower-order bit input data group, and the sign value is 0 or 1. The sign type indicated by the inverted value of the sign value is the opposite of the sign type of the multiplication operation result corresponding to that lower-order bit input data group, and the inverted value of the sign value can offset the carry when the sub-PPA corresponding to that lower-order bit input data group is accumulated. Thus, the electronic device can determine the inverted value of the sign value as the compensation value of the carry compensation term corresponding to the lower-order bit input data group, and the compensation value of the carry compensation term corresponding to the lower-order bit input data group can offset the carry when the sub-PPA corresponding to the lower-order bit input data group is accumulated.

[0111] In some embodiments, the electronic device obtains a carry compensation term corresponding to at least one lower-order bit input data group, then generates an initial PPA based on the multiple input data groups, and adds the carry compensation term to the initial PPA to obtain a target PPA. As shown in Fig. 7, in addition to the embodiment shown in Fig. 4 above, step S104 in the multiplier operation method according to this embodiment can include the following steps S501 to S503.

[0112] In step S501, each input data group is encoded using an encoding method corresponding to the data bit width of each input data group to obtain encoded data corresponding to each input data group.

[0113] Since the electronic device calculates the multiplication result of each input data group, the electronic device separately encodes (e.g., Booth encodes) each input data group to obtain coded data corresponding to each input data group, where the coded data corresponding to each input data group may be multiple sets of product terms.

[0114] For details about multiple sets of product terms, see the description of multiple sets of product terms in the above embodiment.

[0115] For example, the plurality of input data groups may include one input data group having a data bit width of n1 bits and one input data group having a data bit width of n2 bits, and the electronic device may employ n1-bit Booth encoding to encode the input data group having a data bit width of n1 bits, and employ n2-bit Booth encoding to encode the input data group having a data bit width of n2 bits.

[0116] Furthermore, when the encoding method of the multiplier is radix-4 Booth encoding, the electronic device can employ n1-bit radix-4 Booth encoding to encode an input data group having a data bit width of n1 bits, and employ n2-bit radix-4 Booth encoding to encode an input data group having a data bit width of n2 bits.

[0117] In some embodiments, the electronic device sets the multiplier through the selector to adopt an encoding method corresponding to the data bit width of each input data group, and encodes each input data group through the set multiplier to obtain encoded data corresponding to each input data group.

[0118] In step S502, an initial partial product array including sub partial product arrays corresponding to each input data group is generated based on the coded data corresponding to each input data group.

[0119] The electronic device generates a sub-PPA corresponding to each input data group using the coded data corresponding to each input data group, and generates an initial PPA corresponding to the multiple input data groups based on the sub-PPA corresponding to each input data group, where the sub-PPAs corresponding to different input data groups occupy different columns in the initial PPA.

[0120] In some embodiments, the coded data corresponding to each input data group can be multiple sets of product terms, and the electronics can arrange the multiple sets of product terms to obtain a sub-PPA corresponding to each input data group.

[0121] For details about the electronic device arranging multiple sets of product terms, please refer to the explanation in the above embodiment regarding "arranging product terms corresponding to all the numerical values ​​included in the multiplier," and therefore, the explanation will be omitted here.

[0122] In step S503, a carry compensation term is added to the initial partial product array based on the compensation position and compensation value of the carry compensation term corresponding to at least one lower-order bit input data group to obtain a target partial product array.

[0123] The electronic device can add a carry compensation term corresponding to at least one lower-order bit input data group to the initial PPA to obtain the target PPA.

[0124] In some embodiments, the initial PPA includes sub-PPAs corresponding to at least one lower-order bit input data group. The carry position corresponding to each lower-order bit input data group is the position of the last row of the sub-PPA corresponding to that lower-order bit input data group. Furthermore, the electronics adds a compensation value for the carry compensation term corresponding to that lower-order bit input data group to the last row of the sub-PPA corresponding to that lower-order bit input data group, so as to add the carry compensation term corresponding to that lower-order bit input data group to the initial PPA based on the position of the last row of the sub-PPA corresponding to that lower-order bit input data group. The electronics adds the carry compensation term corresponding to the at least one lower-order bit input data group to the initial PPA to obtain the target PPA.

[0125] For example, the electronic device can set a target most significant bit in the last row of the sub-PPA corresponding to each lower-bit input data group to the compensation value of the carry compensation term corresponding to that lower-bit input data group, where the target most significant bit is a bit located higher than the positions of the partial products and the sign bit in the last row of the sub-PPA corresponding to the lower-bit input data group.

[0126] In the embodiment of the present disclosure, instead of encoding multiple input data groups as a whole, each input data group is encoded separately to obtain encoded data corresponding to each input data group. Furthermore, the electronic device can use the encoded data corresponding to each input data group to generate sub-PPAs corresponding to each input data group, and then generate an initial PPA including the sub-PPAs corresponding to each input data group. Based on the initial PPA, a multiplication operation result for each input data group can be obtained.

[0127] In some embodiments, the electronic device can accumulate the target PPA to obtain a multiplication operation result for each input data group, or the electronic device can compress the target PPA to obtain compressed data, and accumulate the compressed data to obtain a multiplication operation result for each input data group.

[0128] Illustratively, the process of the electronic device compressing the target PPA and obtaining the multiplication result of each input data group will be described below. Specifically, as shown in FIG. 7, in addition to the embodiment shown in FIG. 4, step S105 in the multiplier operation method according to this embodiment can include the following steps S504 to S505.

[0129] In step S504, the target partial product array is compressed using a Wallace tree compressor to obtain compressed data.

[0130] The electronic device may use a Wallace tree compressor (also called a Wallace tree multiplier) to compress the target PPA to obtain compressed data. The compressed data may include two sets of numbers, which are a product accumulation value of the target PPA and a carry value of the target PPA, respectively.

[0131] In step S505, the compressed data is accumulated to obtain the multiplication operation result for each input data group.

[0132] The electronic device can accumulate two sets of values ​​included in the compressed data to obtain an accumulation result. The accumulation result includes the multiplication operation results of each input data group. The data bit width of the accumulation result is 2N.

[0133] The electronic device compresses the target PPA through a Wallace tree compressor to obtain compressed data. The amount of data contained in the compressed data is smaller than the amount of data contained in the target PPA. This improves the accumulation speed of the compressed data and allows the multiplication operation results of each input data group to be obtained quickly.

[0134] Illustratively, with reference to Fig. 8, an operation method of a multiplier according to an embodiment of the present disclosure will be described using the electronic device shown in Fig. 8 as an example. The electronic device shown in Fig. 8 includes one multiplier with a data bit width of N, a Wallace tree compressor, and an adder, and the operation method performed by the electronic device can include the following steps:

[0135] In step 1, the electronic device obtains a plurality of input data groups, an input signal dlxp, and an encoding method of the multiplier.

[0136] For example, the input data groups include a first multiplier A N and the first multiplicand B N The input signal dlxp indicates the data bit width of each input data group, and specifically, the input signal dlxp indicates that the data bit width of the input data group ranked first among the multiple input data groups (abbreviated as the first-rank input data group) is n1 bits, the data bit width of the input data group ranked second (abbreviated as the second-rank input data group) is n2 bits, ..., the data bit width of the input data group ranked m-th (abbreviated as the m-th rank input data group) is n m The multiplier is coded using Booth coding. m is a positive integer.

[0137] In step 2, the electronic device uses a multiplier to encode each input data group using an encoding method corresponding to the data bit width of each input data group to obtain encoded data corresponding to each input data group.

[0138] In step 2, the electronic device encodes the first input data group using n1-bit Booth coding, encodes the second input data group using n2-bit Booth coding, ..., and n mThe method includes: encoding the m-th input data group by employing bit Booth encoding to obtain encoded data corresponding to the first input data group, encoded data corresponding to the second input data group, ..., and encoded data corresponding to the m-th input data group.

[0139] In step 3, the electronic device generates a sub-PPA corresponding to each input data group using the coded data corresponding to each input data group through a multiplier, and generates initial PPAs corresponding to the multiple input data groups based on the sub-PPAs corresponding to each input data group, where the sub-PPAs corresponding to each input data group include a sub-PPA corresponding to the first input data group (i.e., PPA1), a sub-PPA corresponding to the second input data group (i.e., PPA2), ..., and a sub-PPA corresponding to the m-th input data group (i.e., PPA m ) is included.

[0140] For example, referring to FIGS. 8 and 9, the data bit width of the first input data group is n1 bits, the data bit width of the second input data group is n2 bits, ..., and the data bit width of the m-th input data group is n m For example, if the bits are all 8 and the encoding method of the multiplier is radix-4 Booth encoding, the electronic device can obtain sub-PPAs corresponding to each input data group shown in FIG. 9, including a sub-PPA corresponding to the first input data group (i.e., PPA1), a sub-PPA corresponding to the second input data group (i.e., PPA2), ..., and a sub-PPA corresponding to the m-th input data group (i.e., PPA m ) is included.

[0141] For details of PPA1 shown in FIG. 9, please refer to the description of the sub-PPA corresponding to the first input data group shown in FIG. 3 in the above embodiment. For details of PPA2 shown in FIG. 9, please refer to the description of the sub-PPA corresponding to the second input data group shown in FIG. 3 in the above embodiment. mFor details of the above, please refer to the description of the sub-PPA corresponding to the m-th input data group shown in FIG. 3 in the above embodiment, and therefore the description thereof will be omitted here.

[0142] In step 4, the electronic device determines, through a multiplier, a carry compensation term corresponding to the at least one lower-order bit input data group based on the at least one lower-order bit input data group and the encoding scheme, and adds the carry compensation term corresponding to the at least one lower-order bit input data group to the initial PPA to obtain a target PPA, where the at least one lower-order bit input data group includes a first-order input data group, a second-order input data group, a

[0143] For example, referring to FIGS. 8 and 9, the carry compensation terms determined by the electronic device corresponding to at least one lower-order bit input data group include a carry compensation term E1 corresponding to the first-order input data group, a carry compensation term E2 corresponding to the second-order input data group, ..., and a carry compensation term E3 corresponding to the (m-1)th-order input data group. m-1 Further, the electronic device can obtain a target PPA as shown in FIG.

[0144] In step 5, the electronics compresses the target PPA through a Wallace tree compressor to obtain compressed data.

[0145] In step 6, the electronic device accumulates the compressed data through an adder to obtain a multiplication result for each input data group. Here, the data bit width of the multiplication result obtained by the electronic device accumulating the compressed data is 2N. The accumulation result includes the multiplication result for each input data group. For example, the multiplication result for the first input data group is a value represented by 2×n1 bits from the 1st bit in the accumulation result, and the multiplication result for the second input data group is a value represented by 2×n1+1 bits to the 2×n2th bit in the accumulation result.

[0146] For example, referring to FIG. 10, a first multiplier A of int16 shown in FIG. 10 is applied to a plurality of input data groups. 16 and the first multiplicand B of int16 16 For example, electronic devices include B 16 ×A 16 Calculate the first multiplier A 16 and the first multiplicand B 16 are both signed data, and the first multiplier A 16 The second multiplier A shown in Figure 10 8-1 and the second multiplier A 8-2 and the first multiplicand B 16 The second multiplicand B shown in FIG. 8-1 and the second multiplicand B 8-2 A 16 =(0010101100110001)2, and A 8-1 =(00110001)2, and A 8-2 =(00101011)2, and A 8-1 The decimal number shown is 49, and A 8-2 The decimal number shown is 43. 16 =(0000001010001010)2, and B 8-1 =(10001010)2, and B 8-2 =(00000010)2, and B 8-1 The decimal number shown is -118, and B 8-2 The decimal value indicated by is 2.

[0147] FIG. 10 shows simplified binary numbers, for example (0010101100110001)2 is simplified to 0010101100110001, and (00110001)2 is simplified to 00110001.

[0148] First, the second multiplier A 8-1 and the second multiplicand B 8-1 The data bit width of the first input data group is 8 bits, and the second multiplier A 8-2 and the second multiplicand B 8-2and the data bit width of the second-rank input data group is 8 bits, the electronic device employs 8-bit radix-4 Booth encoding to encode the first-rank input data group to obtain coded data corresponding to the first-rank input data group, and employs 8-bit radix-4 Booth encoding to encode the second-rank input data group to obtain coded data corresponding to the second-rank input data group.

[0149] Next, the electronic device can generate a sub-PPA (i.e., PPA1) corresponding to the first input data group based on the encoded data corresponding to the first input data group, and generate a sub-PPA (i.e., PPA2) corresponding to the second input data group based on the encoded data corresponding to the second input data group.

[0150] Then, when the first-order input data group is a lower-order bit input data group, the electronic device can determine the carry compensation term E1 corresponding to the first-order input data group. The electronic device's determination of the carry compensation term E1 corresponding to the first-order input data group includes the following steps: 8-1 The sign bit of the second multiplicand B in the first input data group is 0. 8-1 If the sign bit of B is 1, the electronic device 8-1 and the second multiplier A 8-1 It is possible to determine that the sign value of the multiplication result is 1, invert the sign value of this multiplication result to obtain the compensation value of the carry compensation term E1 corresponding to the first-place input data group as 0, and then determine that the position of the last row of the sub-PPA corresponding to the first-place input data group (i.e., the fourth row of PPA1) is the compensation position of the carry compensation term E1 corresponding to the first-place input data group.

[0151] 10, and based on this target PPA, the electronic device can determine the multiplication result C1 of the first-place input data group and the multiplication result C2 of the second-place input data group. Here, C1=(1110100101101010)2, and the decimal number represented by C1 is -5728, and -5728 is B 8-1 and A 8-1 (i.e., the product of -118 and 49). C2 = (0000000001010110)2, and the decimal number represented by C2 is 86, which is equal to B 8-2 and A 8-2 (i.e., 2 multiplied by 43).

[0152] For details of the sign bits (including s0, e0, e0, s1, e1, and 1) shown in FIG. 10, please refer to the explanation of the sign bits (including s0, e0, e0, s1, e1, and 1) shown in FIG. 3 in the above embodiment, and therefore the explanation will be omitted here.

[0153] For example, referring to FIG. 11, a first multiplier A of int16 shown in FIG. 11 is applied to a plurality of input data groups. 16 and the first multiplicand B of int16 16 For example, electronic devices include B 16 ×A 16 Calculate the first multiplier A 16 and the first multiplicand B 16 are all signed data, and the first multiplier A 16 The second multiplier A shown in FIG. 8-1 and the second multiplier A 8-2 and the first multiplicand B 16 The second multiplicand B shown in FIG. 8-1 and the second multiplicand B 8-2 A 16 =(1000101000110000)2, and A 8-1 =(00110000)2, and A 8-2 =(10001010)2, and A 8-1 The decimal number shown is 48, and A 8-2The decimal value shown is -118. 16 =(0110110100101000)2, and B 8-1 =(00101000)2, and B 8-2 =(01101101)2, and B 8-1 The decimal number shown is 40, and B 8-2 The decimal number represented by is 109.

[0154] FIG. 11 shows simplified binary numbers, for example (1000101000110000)2 is simplified to 1000101000110000, and (00110000)2 is simplified to 00110000.

[0155] 11 is a lower-order bit input data group, the electronic device can determine the carry compensation term E1 corresponding to the first-order input data group. The electronic device's determination of the carry compensation term E1 corresponding to the first-order input data group includes the following steps: 8-1 The sign bit of the second multiplicand B in the first input data group is 0. 8-1 If the sign bit of B is 0, the electronic device 8-1 and the second multiplier A 8-1 It is determined that the sign value of the multiplication result is 0, the sign value of this multiplication result is inverted to obtain the compensation value of the carry compensation term E1 corresponding to the first-place input data group as 1, and it is then determined that the position of the last row of the sub-PPA corresponding to the first-place input data group (i.e., the fourth row of PPA1) is the compensation position of the carry compensation term E1 corresponding to the first-place input data group.

[0156] 11, and based on this target PPA, the electronic device can determine the multiplication result C1 of the first-place input data group and the multiplication result C2 of the second-place input data group. Here, C1=(0000011110000000)2, and the decimal number represented by C1 is 1920, and 1920 is B 8-1 and A 8-1 (i.e., the product of 40 and 48). C2 = (1100110111000010)2, and the decimal number represented by C2 is -12862, which is B 8-1 and A 8-1 (i.e., 109 multiplied by -118).

[0157] The process by which an electronic device performs the multiplication operation method of a multiplier on a plurality of input data groups shown in FIG. 11 is similar to the process by which an electronic device performs the multiplication operation method of a multiplier on a plurality of input data groups shown in FIG. 10, and therefore the description thereof will be omitted here. (Exemplary Device)

[0158] When functional modules are divided corresponding to respective functions, an embodiment of the present disclosure further provides a computing device. Figure 12 is a structural schematic diagram of a computing device according to an embodiment of the present disclosure. The computing device 600 includes a compensation determination module 601, a partial product sequence determination module 602, and a partial product processing module 603.

[0159] Here, the compensation determination module 601 is for determining a plurality of input data groups of a multiplier and an encoding method of the multiplier, determining at least one lower-order bit input data group in the plurality of input data groups, and determining a carry compensation term corresponding to the at least one lower-order bit input data group based on the at least one lower-order bit data group and the encoding method.

[0160] The partial product sequence determination module 602 is for determining a target partial product sequence based on a carry compensation term corresponding to at least one lower-bit input data group determined by the compensation determination module 601 and a plurality of input data groups.

[0161] The partial product processing module 603 is for determining the multiplication operation result of each input data group based on the target partial product sequence determined by the partial product sequence determination module 602 .

[0162] 12 and 13, the compensation determination module 601 includes a compensation position determination unit 6011 and a compensation value determination unit 6012. Here, the compensation position determination unit 6011 is for determining a position of a carry compensation term corresponding to at least one lower-order bit input data group based on the encoding scheme, the data bit width of the at least one lower-order bit input data group, and the position of the at least one lower-order bit input data group among the plurality of input data groups. The compensation value determination unit 6012 is for determining a compensation value of the carry compensation term corresponding to the at least one lower-order bit input data group based on the value of a sign bit of each data in the at least one lower-order bit input data group.

[0163] In some embodiments, the compensation position determination unit 6011 determines the position of the last row of the sub-partial product array corresponding to at least one lower-bit input data group based on the encoding scheme, the data bit width of the at least one lower-bit input data group, and the position of the at least one lower-bit input data group in the multiple input data groups, and determines the position of the carry compensation term corresponding to the at least one lower-bit input data group based on the position of the last row of the sub-partial product array corresponding to the at least one lower-bit input data group.

[0164] In some embodiments, the compensation value determination unit 6012 performs an XNOR operation on the numerical values ​​of the sign bits of the multiplier and the multiplicand in each lower-bit input data group to determine a numerical value after the XNOR operation, and determines a compensation term value of the carry compensation term corresponding to each lower-bit input data group based on the numerical value after the XNOR operation.

[0165] In some embodiments, the compensation value determination unit 6012 determines the sign value of the multiplication result of the multiplier and the multiplicand based on the value of the sign bit of the multiplier and the multiplicand in each lower-bit input data group, and inverts this sign value to obtain the compensation term value of the carry compensation term corresponding to each lower-bit input data group.

[0166] 12 and 13, the partial product sequencing module 602 includes an encoding unit 6021 and a partial product sequencing unit 6022. The encoding unit 6021 encodes each input data group using an encoding scheme corresponding to the data bit width of the input data group to obtain coded data corresponding to the input data group. The partial product sequencing unit 6022 generates an initial partial product array including sub-partial product arrays corresponding to the input data group based on the coded data corresponding to the input data group, and adds a carry compensation term to the initial partial product array based on the compensation position and compensation value of the carry compensation term corresponding to at least one lower-bit input data group to obtain a target partial product array.

[0167] In some embodiments, the compensation determination module 601 determines at least one lower-bit input data group among the plurality of input data groups according to the sum of the data bit widths of the input data groups being less than or equal to the maximum data bit width that the multiplier can implement.

[0168] 12 and 13, the partial product processing module 603 includes a partial product compression unit 6031 and an accumulation unit 6032. Here, the partial product compression unit 6031 is for compressing the target partial product array using a Wallace tree compressor to obtain compressed data. The accumulation unit 6032 is for accumulating the compressed data to obtain a multiplication operation result for each input data group.

[0169] The beneficial technical effects corresponding to the exemplary embodiments of the present apparatus can be referred to the corresponding beneficial technical effects in the exemplary method section above, and therefore will not be described here. (Example Electronic Devices)

[0170] FIG. 14 is a structural diagram of an electronic device according to an embodiment of the present disclosure, in which an electronic device 10 includes at least one processor 11 and a memory 12.

[0171] The processor 11 may be a central processing unit (CPU) or other type of processing unit having data processing and / or instruction execution capabilities, and may control other components within the electronic device 10 to perform desired functions.

[0172] The memory 12 may include one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory. Non-volatile memory may include, for example, read-only memory (ROM), a hard disk, flash memory, etc. The computer-readable storage medium may store one or more computer program instructions, and the processor 11 may execute the one or more program instructions to implement the multiplier operation method and / or other desired functions according to the above-described embodiments of the present disclosure.

[0173] In one example, electronic device 10 may further include input devices 13 and output devices 14 connected to each other via a bus system and / or other form of connection (not shown).

[0174] The input device 13 may include, for example, a keyboard, a mouse, and the like.

[0175] The output device 14 can output various information to the outside, and can include, for example, a display, a speaker, a printer, a communication network, and remote output devices connected thereto.

[0176] For simplicity, Fig. 14 shows only some of the components of the electronic device 10 that are relevant to the present disclosure, and omits components such as buses and input / output interfaces. In addition, the electronic device 10 may further include any appropriate components depending on specific application conditions. Exemplary Computer Program Products and Computer-Readable Storage Media

[0177] In addition to the above-described methods and apparatuses, embodiments of the present disclosure may provide a computer program product including computer program instructions that, when executed by a processor, cause the processor to perform steps in the multiplier operation methods according to the embodiments described in the "Exemplary Method" section above.

[0178] The computer program product may have program code for carrying out operations of embodiments of the present disclosure written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java, C++, and common procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user computing device, partially on the user device, as a separate software package, partially on the user computing device and partially on a remote computing device, or entirely on the remote computing device or a server.

[0179] Furthermore, an embodiment of the present disclosure may further provide a computer-readable storage medium having stored thereon computer program instructions that, when executed by a processor, cause the processor to perform steps in the multiplier operation method according to each embodiment described in the "Exemplary Method" section above.

[0180] The computer-readable storage medium may be any combination of one or more readable media. The readable medium may be a readable signal medium or a readable storage medium. The readable storage medium may include, but is not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples (non-exhaustive list) of readable storage media include an electrical connection having one or more conductors, a mobile hard drive, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above.

[0181] Although the basic principles of the present disclosure have been described above with reference to specific embodiments, the benefits, advantages, and effects mentioned in the present disclosure are merely illustrative and not limiting, and are not necessarily possessed by each embodiment of the present disclosure. Furthermore, the specific details of the above disclosure are merely illustrative and easy-to-understand functions and are not limiting, and the above details do not necessarily limit the present disclosure to those realized by the above specific details.

[0182] Those skilled in the art can make various modifications and variations to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is intended to include these modifications and variations.

Claims

1. determining a plurality of input data groups for a multiplier and an encoding scheme for said multiplier; determining at least one least significant bit input data group from the plurality of input data groups; determining a carry compensation term corresponding to at least one group of least significant input data based on the at least one group of least significant input data and the encoding scheme; obtaining a target partial product array based on a carry compensation term corresponding to the at least one lower-order bit input data group and the plurality of input data groups; determining a multiplication operation result for each input data group based on the target partial product array; A multiplier operation method comprising:

2. determining a carry compensation term corresponding to the at least one lower-order bit input data group based on at least one lower-order bit input data group among the plurality of input data groups and the encoding scheme, determining a position of a carry compensation term corresponding to the at least one lower-order bit input data group based on the encoding scheme, a data bit width of the at least one lower-order bit input data group, and a position of the at least one lower-order bit input data group among the plurality of input data groups; determining a compensation value of a carry compensation term corresponding to the at least one lower-order bit input data group based on a numerical value of a sign bit of each data in the at least one lower-order bit input data group; 2. The multiplier operation method according to claim 1.

3. determining a position of a carry compensation term corresponding to the at least one lower-order bit input data group based on the encoding scheme, a data bit width of the at least one lower-order bit input data group, and a position of the at least one lower-order bit input data group among the plurality of input data groups, determining a position of a last row of a sub partial product array corresponding to the at least one lower-order bit input data group based on the encoding method, a data bit width of the at least one lower-order bit input data group, and a position of the at least one lower-order bit input data group among the plurality of input data groups; determining a compensation position of a carry compensation term corresponding to the at least one lower-order bit input data group based on a position of a last row of the sub partial product array corresponding to the at least one lower-order bit input data group; 3. The multiplier operation method according to claim 2.

4. determining a compensation value of a carry compensation term corresponding to the at least one lower-order bit input data group based on a numerical value of a sign bit of each data in the at least one lower-order bit input data group, performing an XNOR operation on the sign bit values ​​of the multiplier and multiplicand in each of the least significant bit input data groups to determine a post-XNOR value; determining a compensation value of a carry compensation term corresponding to the at least one lower-order bit input data group based on the value after the XNOR operation; 3. The multiplier operation method according to claim 2.

5. determining a compensation value of a carry compensation term corresponding to the at least one lower-order bit input data group based on a numerical value of a sign bit of each data in the at least one lower-order bit input data group, determining a sign value of a multiplication result of the multiplier and the multiplicand based on the value of the sign bit of the multiplier and the multiplicand in each lower-order bit input data group; inverting the sign value of the multiplication operation result to obtain a compensation value of a carry compensation term corresponding to each of the lower-order bit input data groups; 3. The multiplier operation method according to claim 2.

6. The step of obtaining a target partial product array based on the carry compensation term corresponding to the at least one lower-order bit input data group and the plurality of input data groups includes: Encoding each of the input data groups using an encoding method corresponding to a data bit width of each of the input data groups to obtain encoded data corresponding to each of the input data groups; generating an initial partial product array including sub partial product arrays corresponding to each of the input data groups based on coded data corresponding to each of the input data groups; adding the carry compensation term to the initial partial product array based on the position and the compensation value of the carry compensation term corresponding to the at least one lower-order bit input data group to obtain the target partial product array; 6. The multiplier operation method according to claim 2, wherein:

7. The step of determining at least one lower-order input data group from the plurality of input data groups includes: determining at least one lower-order bit input data group among the plurality of input data groups in response to a sum of data bit widths of the input data groups being equal to or less than a maximum data bit width that can be implemented by the multiplier; 6. The multiplier operation method according to claim 1, wherein:

8. determining a multiplication result for each input data group based on the target partial product array, compressing the target partial product array using a Wallace tree compressor to obtain compressed data; accumulating the compressed data to obtain a multiplication operation result for each of the input data groups; 6. The multiplier operation method according to claim 1, wherein:

9. a compensation determination module for determining a plurality of input data groups of a multiplier and an encoding scheme of the multiplier, determining at least one lower-order bit input data group among the plurality of input data groups, and determining a carry compensation term corresponding to the at least one lower-order bit input data group based on the at least one lower-order bit input data group and the encoding scheme; a partial product ordering module for determining a target partial product ordering based on the carry compensation term corresponding to the at least one lower-order bit input data group determined by the compensation determination module and the plurality of input data groups; a partial product processing module for determining a multiplication operation result for each input data group based on the target partial product sequence determined by the partial product sequence determination module; A computing device characterized by:

10. A cache memory built into a processor, The cache memory stores a computer program for executing the multiplier calculation method according to any one of claims 1 to 5, When the computer program is executed by the processor, the processor realizes the operation method of the multiplier. Cache memory characterized by:

11. a processor; a memory for storing instructions executable by the processor; The processor reads the executable instructions from the memory, and executes the executable instructions to realize the multiplier operation method according to any one of claims 1 to 5. An electronic device characterized by:

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