substrate

Abstract

To provide a substrate that can be reduced in cost and size. [Solution] The substrate 1 has a mounting portion A on which a plurality of power semiconductors 2 are mounted and a plurality of circuit portions P arranged in a row, and the circuit portion P has a drain connection portion 3 formed of a trapezoidal conductor c and connected to the drain terminal of the power semiconductor 2, and a source / emitter connection portion 4 formed of a trapezoidal conductor c and facing the drain / collector connection portion 3 with a gap between their hypotenuses and connected to the source terminal 2b of the power semiconductor 2, and the mounting portion A is arranged diagonally with respect to the substrate 1, including the hypotenuse portion of the drain / collector connection portion 3 and the hypotenuse portion of the source / emitter connection portion 4.

Description

[Technical Field]

[0001] The present invention relates to a substrate. [Background technology]

[0002] Conventional substrates on which power semiconductors such as FETs (Field-effect transistors) and IGBTs (Insulated Gate Bipolar Transistors) are mounted are used, for example, in inverters that drive motors, and include a plurality of circuits that form legs or arms in the inverter together with the mounted power semiconductors (see, for example, Patent Document 1). With such substrates, when it is necessary to supply a large current to the motor, multiple power semiconductors are used for one arm, and therefore multiple power semiconductors must be mounted on the substrate. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2013-225622 Summary of the Invention [Problem to be solved by the invention]

[0004] For example, when multiple FETs are mounted on a single circuit on a substrate, as shown in FIG. 4, in order to allow for a large current, it is conceivable to use thick, wide rectangular copper foils to prevent current concentration in the drain connection copper foil 101 and the source connection copper foil 102 connected to the drain terminal and source terminal 100a (not shown) on the underside of the FET 100, thereby suppressing heat generation.

[0005] Then, the drain connection copper foil 101 and the source connection copper foil 102 are arranged side by side with a gap between them, and multiple FETs 100 are mounted on the substrate 103 along the opposing portions of the drain connection copper foil 101 and the source connection copper foil 102.

[0006] In this way, when FET 100 is mounted by providing circuit 104 on substrate 103, if multiple circuits 104 are provided on substrate 103, each circuit 104 is large, which inevitably increases the size of substrate 103, making it difficult to mount on electrical equipment, and also increasing the amount of copper foil used, resulting in higher costs.

[0007] SUMMARY OF THE INVENTION An object of the present invention is to provide a substrate that can reduce costs and is small in size. [Means for solving the problem]

[0008] In order to achieve the above object, the substrate of the present invention is a substrate having a mounting portion on which a plurality of power semiconductors are mounted and a plurality of circuit portions arranged in a row, the circuit portion having a drain / collector connection portion formed of a triangular or trapezoidal conductor and connected to the drain terminal or collector terminal of the power semiconductor, and a source connection portion formed of a triangular or trapezoidal conductor and facing the drain / collector connection portion with a gap between their hypotenuses and connected to the source terminal of the power semiconductor, and the mounting portion is provided along the hypotenuse, including the hypotenuse portion of the drain / collector connection portion and the hypotenuse portion of the source / emitter connection portion.

[0009] In a substrate configured in this manner, the drain / collector connection portion and the source connection portion have a triangular or trapezoidal tapered shape, so that the number of power semiconductors through which current passes decreases from the wider base end to the narrower tip end, and the amount of conductor used in the substrate can be reduced while avoiding current concentration compared to using a rectangular conductor with a constant width, thereby reducing costs and suppressing heat generation in the substrate. Furthermore, while reducing the area of ​​the drain / collector connection portion and the source / emitter connection portion in a planar view, the triangular or trapezoidal drain / collector connection portion and the source / emitter connection portion are arranged with their hypotenuses facing each other, which allows the circuit portion to be made small and approximately rectangular. Therefore, when circuit portions are arranged on the substrate, the circuit portions can be arranged densely, thereby enabling the substrate to be made smaller.

[0010] Furthermore, the drain / collector connection and the source / emitter connection in the substrate may be formed by stacking multiple conductors. With a substrate configured in this manner, the cross-sectional area of ​​the current path can be secured by stacking multiple conductors that form the drain / collector connection and the source / emitter connection without increasing the thickness of the conductor. This allows the use of thin conductors that can tolerate large currents, making it possible to etch the conductors for mounting devices other than power semiconductors, such as microcomputers, whose terminals and pads are closely spaced. Therefore, the substrate allows the mounting of devices other than power semiconductors, such as microcomputers, whose terminals and pads are closely spaced. This eliminates the need to mount power semiconductors and microcomputers separately on multiple substrates, thereby reducing the cost of electronic devices including the substrate and contributing to the miniaturization of electronic devices.

[0011] Furthermore, the substrate may have a metal layer for heat dissipation at the bottom layer. With a substrate configured in this manner, heat generated by current flowing through the power semiconductors mounted on the substrate and the conductors in the substrate can be efficiently dissipated to the outside through the metal layer, thereby preventing the power semiconductors from burning out. [Effects of the Invention]

[0012] As described above, the substrate of the present invention can reduce costs and size. [Brief explanation of the drawings]

[0013] [Figure 1] FIG. 1 is a plan view of a substrate on which a FET is mounted in one embodiment. [Figure 2] FIG. 2 is an enlarged plan view of a portion of a substrate on which a FET is mounted in one embodiment. [Figure 3] Fig. 3(a) is a cross-sectional view showing an enlarged portion of the XX cross section of the substrate according to the embodiment, and Fig. 3(b) is a cross-sectional view showing an enlarged portion of the YY cross section of the substrate according to the embodiment. [Figure 4] FIG. 4 is an enlarged plan view of a portion of a conventional substrate. DETAILED DESCRIPTION OF THE INVENTION

[0014] The present invention will be described below based on the embodiments shown in the drawings. As shown in Figures 1 to 3, a substrate 1 according to one embodiment includes copper foils c as conductors laminated in multiple layers, and insulating layers i formed of insulators provided between the copper foils c, c, and includes six circuit sections P arranged in a row, each having a mounting section A on which seven FETs 2 as power semiconductors are mounted.

[0015] As shown in FIG. 2, in this embodiment, the FET 2 as a power semiconductor includes a rectangular resin case 2a that houses a semiconductor therein, a gate terminal 2c and a source terminal 2b that protrude from one end of the resin case 2a, and a drain terminal (not shown) at the bottom end of the resin case 2a.

[0016] On the other hand, the substrate 1 is configured to include a circuit portion P having a drain / collector connection portion 3 connected to the drain terminal of the FET 2, a source / emitter connection portion 4 connected to the source terminal 2b of the FET 2, and a gate connection portion 5 connected to the gate terminal 2c, as well as a metal layer 15 for heat dissipation in the lowest layer. In this embodiment, the substrate 1 is in the shape of a rectangular plate and includes six circuit portions P, each having a mounting portion A on which the FET 2 is mounted. Note that the circuit portions P in the substrate 1 have the same structure, and therefore, to avoid duplication of explanation, the configuration of only one circuit portion P will be described in detail.

[0017] The drain / collector connection part 3 is composed of copper foils c as three stacked trapezoidal conductors, and copper members 8 and 9 that are fully embedded in via holes 6 and 7 provided in an insulating layer i between the copper foils c and c to electrically connect the stacked copper foils c and c. A plurality of via holes 6 are provided near the hypotenuse of the trapezoidal copper foil c, and a plurality of via holes 7 are provided along the upper and lower bases of the trapezoidal copper foil c, which have a wider inner width.

[0018] Similarly to the drain / collector connection portion 3, the source / emitter connection portion 4 includes multiple stacked trapezoidal copper foils (c) as conductors, and copper members (12, 13) filled with via holes (10, 11) provided in the insulating layer (i) between the copper foils (c) to electrically connect the stacked copper foils (c). Multiple via holes (10) are provided near the hypotenuses of the trapezoidal copper foils (c), and multiple via holes (11) are provided along the upper and lower bases of the trapezoidal copper foils (c), which have a wider inner width. The first layer of copper foil (c) that constitutes the source / emitter connection portion 4, located on the top surface of the substrate 1, includes connection portions (4a) protruding from seven hypotenuses, the same number as the number of FETs (2) mounted on the mounting portion (A), to enable connection to the source terminals (2b) of the FETs (2). The drain / collector connection portion 3 or the source / emitter connection portion 4 may be triangular or trapezoidal, but it does not have to be a perfect triangle or trapezoid as long as it is roughly triangular or trapezoidal, and may have a notch or protrusion in part.

[0019] In the circuit portion P of the substrate 1 of this embodiment, the drain / collector connection portion 3 and the source / emitter connection portion 4 are both formed of three layers of copper foil c, but they may be formed of a single layer of copper foil c if the cross-sectional area of ​​the copper foil c through which the current passes can be secured, and the number of layers of copper foil c can be arbitrarily changed in design depending on the amount of current that is desired to be allowed. Note that although the conductor is copper foil c, it may be a metal other than copper foil.

[0020] As shown in Figures 1 and 2, the drain / collector connection portion 3 and the source / emitter connection portion 4 are disposed on the substrate 1 with their hypotenuses facing each other and spaced apart. The gate connection portion 5 is formed of copper foil c that is disposed along the hypotenuses of the drain / collector connection portion 3 and the source / emitter connection portion 4 in a layer above the copper foil c of the drain / collector connection portion 3 and the source / emitter connection portion 4 in a plan view. The gate connection portion 5 includes a main body portion 5a formed of elongated copper foil c and seven terminal connection portions 5b that protrude laterally from the main body portion 5a. Since the current flowing through the gate connection portion 5 is small, the main body portion 5a of the gate connection portion 5 is formed of elongated copper foil c.

[0021] The circuit portion P is configured to include a trapezoidal drain / collector connection portion 3 and a source / emitter connection portion 4 with their hypotenuses facing each other, and a gate connection portion 5 provided in a different layer from the drain / collector connection portion 3 and the source / emitter connection portion 4, and is formed in a substantially rectangular shape on the substrate 1. In the substrate 1 of this embodiment, a plurality of compact circuit portions P formed in a substantially rectangular shape are arranged in a row along the longitudinal direction of the substrate 1, so that the circuit portions P can be densely arranged in the substrate 1, and the substrate 1 can be made smaller.

[0022] As shown in Figures 1 and 2, the mounting portion A is an area that spans the drain / collector connection portion 3 and the source / emitter connection portion 4 in a plan view, including the hypotenuse portion of the drain / collector connection portion 3 in the circuit portion P, the hypotenuse portion of the source / emitter connection portion 4, and the portion that overlaps with the gate connection portion 5, and is provided along the hypotenuse of the drain / collector connection portion 3 and the hypotenuse of the source / emitter connection portion 4.

[0023] 3, the substrate 1 also includes a heat dissipation metal layer 15 formed of copper foil c on the underside of an insulating layer i provided below the copper foil c of the drain / collector connecting portion 3 and the source / emitter connecting portion 4. In this manner, the metal layer 15 is disposed below the lowermost insulating layer i, and is provided so as to cover the entire underside of the substrate 1, and is not connected at all to the copper foil c serving as a conductor in a different layer. The metal layer 15 is provided over the entire underside of the substrate 1 for efficient heat dissipation, but may also be provided on only a portion of the underside of the substrate 1.

[0024] As shown in Figure 3, after applying thermally conductive grease (not shown) to the metal layer 15 of the substrate 1, the metal layer 15 is abutted against the housing 50 that houses the substrate 1 or a heat sink, so that heat generated when current flows through the circuit section P can be conducted from the metal layer 15 to the housing 50 or the heat sink, and can be efficiently dissipated outside the substrate 1.

[0025] When the FET 2 is mounted on the mounting portion A of the circuit portion P, the source terminal 2b of the FET 2 is connected by soldering or the like to the copper foil c of the connection portion 4a of the source / emitter connection portion 4 arranged in the mounting portion A on the upper surface of the substrate 1, the gate terminal 2c is connected by soldering or the like to the copper foil c of the gate connection portion 5 arranged in the mounting portion A, and the drain terminal at the lower end of the resin case 2a is connected to the copper foil c of the drain / collector connection portion 3. As shown in FIG. 1 , the seven FETs 2 are mounted in a row along the longitudinal direction of the mounting portion A on the mounting portion A which is provided along the hypotenuse of the drain / collector connection portion 3 and the hypotenuse of the source / emitter connection portion 4 opposite to the hypotenuse of the drain / collector connection portion 3.

[0026] As shown in FIG. 3, the first layer of copper foil c of the drain / collector connection portion 3 is laid bare on the top surface of the substrate 1 and is connected to an external power supply (not shown) or a winding of a motor (not shown), while the first layer of copper foil c of the source / emitter connection portion 4 is laid bare on the top surface of the substrate 1 and is connected to a ground (not shown) or a winding of a motor (not shown), and the gate connection portion 5 is connected to a signal output terminal of a microcomputer (not shown) mounted on the substrate 1 via wiring separately provided within the substrate 1.

[0027] As described above, the substrate 1 is configured to include six circuit sections P in which FETs 2 are mounted in mounting section A, with the two circuit sections P on the left side each forming an arm and the two left side circuit sections P forming a pair to form one leg connected to the U-phase winding of a motor not shown, the two central circuit sections P each forming an arm and the two central circuit sections P forming a pair to form one leg connected to the V-phase winding of a motor not shown, and the two right side circuit sections P each forming an arm and the two right side circuit sections P forming a pair to form one leg connected to the W-phase winding of a motor not shown.

[0028] Adjacent circuit portions P in a pair are spaced apart from the substrate 1 and have the same configuration except that the shapes of the drain / collector connection portion 3 and the source / emitter connection portion 4 are inverted so that the left and right sides are swapped.

[0029] 1, the central set of circuit sections P is provided on the substrate 1 upside down in relation to the two circuit sections P on the right side and the two circuit sections P on the left side in FIG.

[0030] As shown in FIG. 1, in the left-hand circuit section P of the left-hand set, the source / emitter connection section 4 is connected to a ground not shown and the drain / collector connection section 3 is connected to one end of a U-phase winding of a motor not shown, and in the right-hand circuit section P of the left-hand set, the source / emitter connection section 4 is connected to a point on a U-phase winding of a motor not shown and the drain / collector connection section 3 is connected to an external power supply not shown.

[0031] Furthermore, the source / emitter connection part 4 of the left circuit part P of the central group is connected to one end of the V-phase winding of a motor not shown in the figure, and the drain / collector connection part 3 is connected to an external power supply not shown in the figure, and the source / emitter connection part 4 of the right circuit part P of the central group is connected to ground not shown in the figure, and the drain / collector connection part 3 is connected to one end of the V-phase winding of a motor not shown in the figure.

[0032] Furthermore, the source / emitter connection part 4 of the left circuit part P of the right set is connected to a ground not shown in the figure, and the drain / collector connection part 3 is connected to one end of a W-phase winding of a motor not shown in the figure, and the source / emitter connection part 4 of the right circuit part P of the right set is connected to one end of a W-phase winding of a motor not shown in the figure, and the drain / collector connection part 3 is connected to an external power supply not shown.

[0033] Therefore, when a voltage is applied to gate terminal 2c of FET2 via gate connection portion 5 from a microcomputer (not shown) mounted on substrate 1, FET2 turns on and current flows from the external power supply from drain / collector connection portion 3 toward source / emitter connection portion 4, and when the application of voltage to gate terminal 2c of FET2 from the microcomputer (not shown) stops, FET2 turns off and prevents current from flowing from drain / collector connection portion 3 toward source / emitter connection portion 4. In this way, substrate 1 forms an inverter circuit, and the on / off operation of FET2 can drive a motor (not shown).

[0034] In the substrate 1 of this embodiment, when the FETs 2 are mounted on the mounting portion A, the FETs 2 are mounted in a row along the hypotenuses of the trapezoidal drain / collector connection portion 3 and source / emitter connection portion 4 in a plan view. As a result, in FIG. 2, in the drain / collector connection portion 3, a current flows from the wider upper base side of the trapezoidal copper foil c to the narrower lower base side, and in the source / emitter connection portion 4, a current flows from the narrower upper base side of the trapezoidal copper foil c to the wider lower base side.

[0035] In the drain / collector connection portion 3, a current flows from the wider bottom side of the trapezoidal copper foil c to the narrower top side, and in the source / emitter connection portion 4, a current flows from the narrower top side of the trapezoidal copper foil c to the wider bottom side. Because the FETs 2 are mounted along the hypotenuses of the trapezoidal drain / collector connection portion 3 and source / emitter connection portion 4, the number of FETs 2 through which the current passes decreases as the current moves from the lower bottom to the upper bottom of the copper foil c in the drain / collector connection portion 3 and source / emitter connection portion 4. This allows the current density to be reduced without requiring the drain / collector connection portion 3 and source / emitter connection portion 4 to be rectangular in shape to match the width of the portion where the current density is most concentrated. Therefore, in the substrate 1 of this embodiment, the area of ​​the drain / collector connection portion 3 and source / emitter connection portion 4 in a plan view can be reduced while reducing the current density in the drain / collector connection portion 3 and source / emitter connection portion 4. That is, in the substrate 1 of this embodiment, the drain / collector connection portion 3 and the source / emitter connection portion 4 are trapezoidal, and therefore the number of FETs 2 through which a current tries to pass decreases from the widest base to the narrowest base, and compared to using rectangular copper foil with a constant width, the amount of copper foil c used in the substrate 1 can be reduced while avoiding current concentration, thereby reducing costs and suppressing heat generation in the substrate 1. Furthermore, while reducing the areas of the drain / collector connection portion 3 and the source / emitter connection portion 4 in a planar view, the trapezoidal drain / collector connection portion 3 and the source / emitter connection portion 4 are arranged with their hypotenuses facing each other, and therefore the circuit portion P can be made small and approximately rectangular, and therefore when the circuit portion P is arranged on the substrate 1, the circuit portion P can be arranged densely, and the substrate 1 can be made smaller.

[0036] Furthermore, in the substrate 1 configured as described above, the drain / collector connection portion 3 and the source / emitter connection portion 4, each connected to one FET 2, are formed of copper foil c laminated in multiple layers, and even when a large current flows through the FET 2, the cross-sectional area of ​​the copper foil c can be ensured without increasing the thickness of the copper foil c, which is the conductor through which the current passes in the drain / collector connection portion 3 and the source / emitter connection portion 4, thereby reducing electrical resistance and suppressing heat generation. In this way, by laminating multiple copper foils c that constitute the drain / collector connection portion 3 and the source / emitter connection portion 4 without increasing the thickness of the copper foil c, the cross-sectional area of ​​the current path can be ensured and the current density can be reduced. Therefore, the substrate 1 of this embodiment can use thin copper foil c that can tolerate a large current, and it becomes possible to etch the copper foil c for mounting devices other than the FET 2, such as a microcomputer with closely spaced terminals and pads.

[0037] As described above, the substrate 1 of this embodiment is a substrate 1 having a mounting portion A on which a plurality of FETs (power semiconductors) 2 are mounted and a plurality of circuit portions P arranged in a row, and the circuit portion P has a drain / collector connection portion 3 formed of a trapezoidal copper foil (conductor) c and connected to the drain terminal of the FET (power semiconductor) 2, and a source / emitter connection portion 4 formed of a trapezoidal copper foil (conductor) c and facing the drain / collector connection portion 3 with a gap between their hypotenuses and connected to the source terminal 2b of the FET (power semiconductor) 2, and the mounting portion A is provided along the hypotenuse, including the hypotenuse portion of the drain / collector connection portion 3 and the hypotenuse portion of the source / emitter connection portion 4.

[0038] In the substrate 1 configured in this manner, the drain / collector connection portion 3 and the source / emitter connection portion 4 are trapezoidal and tapered. This reduces the number of FETs (power semiconductors) 2 through which current passes from the wider base end to the narrower tip end. This allows for a reduction in the amount of copper foil (conductor) c used in the substrate 1 while avoiding current concentration, compared to using rectangular copper foil (conductor) with a constant width. This reduces costs and suppresses heat generation in the substrate 1. Furthermore, the planar areas of the drain / collector connection portion 3 and the source / emitter connection portion 4 are reduced, and the trapezoidal drain / collector connection portion 3 and the source / emitter connection portion 4 are arranged with their hypotenuses facing each other. This allows the circuit portion P to be made small and approximately rectangular. Therefore, when the circuit portion P is arranged on the substrate 1, the circuit portion P can be densely arranged, thereby enabling the substrate 1 to be miniaturized. As described above, the substrate 1 of this embodiment allows for cost reduction and miniaturization.

[0039] The shape of the copper foil (conductor) c in the drain / collector connecting portion 3 and the source / emitter connecting portion 4 may be triangular, and by arranging the drain / collector connecting portion 3 and the source / emitter connecting portion 4 with their hypotenuses facing each other, the amount of copper foil (conductor) c can be reduced, as in the case where the copper foil (conductor) c in the drain / collector connecting portion 3 and the source / emitter connecting portion 4 is trapezoidal, thereby reducing the cost of the substrate 1 and suppressing heat generation, and furthermore, since the circuit portion P can be made small and approximately rectangular, the substrate 1 can be made smaller. Note that one of the copper foil (conductor) c in the drain / collector connecting portion 3 and the copper foil (conductor) c in the source / emitter connecting portion 4 may be trapezoidal and the other may be triangular.

[0040] Furthermore, the drain / collector connection portion 3 and the source / emitter connection portion 4 in the substrate 1 of this embodiment are formed of copper foil (conductor) c laminated in multiple layers. With the substrate 1 configured in this manner, the cross-sectional area of ​​the current path can be secured by laminating multiple copper foils (conductors) c, c that constitute the drain / collector connection portion 3 and the source / emitter connection portion 4 without increasing the thickness of the copper foil (conductor) c. This allows the use of thin copper foil (conductor) c that can tolerate large currents, making it possible to etch the copper foil (conductor) c for mounting devices such as microcomputers with closely spaced terminals and pads in addition to the FET (power semiconductor) 2. Therefore, with the substrate 1 of this embodiment, it is possible to mount devices such as microcomputers with closely spaced terminals and pads in addition to the FET (power semiconductor) 2. This eliminates the need to separately mount the FET (power semiconductor) 2 and the microcomputer on multiple substrates, thereby reducing the cost of electronic devices including the substrate 1 and contributing to the miniaturization of electronic devices.

[0041] Furthermore, since the substrate 1 of this embodiment has a metal layer 15 for heat dissipation at the bottom layer, heat generated by current flowing through the FET (power semiconductor) 2 mounted on the substrate 1 and the copper foil (conductor) c in the substrate 1 can be efficiently dissipated to the outside from the metal layer 15, thereby preventing the FET (power semiconductor) 2 from burning out.

[0042] In the above description, the power semiconductor is described as an FET 2, but the power semiconductor may be an IGBT. In the case where the power semiconductor is an IGBT, the collector terminal of the IGBT is connected to the drain / collector connection part 3, the emitter terminal is connected to the source / emitter terminal 4, and the gate terminal is connected to the gate connection part 5, and the IGBT is mounted on the substrate 1.

[0043] Although the preferred embodiment of the present invention has been described in detail, modifications, variations and changes can be made thereto without departing from the scope of the appended claims. [Explanation of symbols]

[0044] 1···Substrate, 2···FET (power semiconductor), 3···Drain connection section, 4···Source / emitter connection section, 15···Metal layer, c···Copper foil (conductor), i···Insulating layer, A···Mounting section, P···Circuit section

Claims

1. A substrate having a mounting portion on which a plurality of power semiconductors are mounted and a plurality of circuit portions arranged in a row, The circuit unit includes: a drain / collector connection portion formed of a triangular or trapezoidal conductor and connected to a drain terminal or a collector terminal of the power semiconductor; a source / emitter connection portion formed of a triangular or trapezoidal conductor, facing the drain / collector connection portion with a gap between their hypotenuses, and connected to a source terminal or an emitter terminal of the power semiconductor; The mounting portion is provided along the oblique side, including the oblique side portion of the drain / collector connecting portion and the oblique side portion of the source / emitter connecting portion. A substrate characterized by:

2. The drain / collector connection and the source / emitter connection are formed by a conductor stacked in multiple layers. The substrate according to claim 1 .

3. The bottom layer is a metal layer for heat dissipation.

3. The substrate according to claim 1 or 2.

Images