Indication device

Abstract

To suppress deterioration of display quality.SOLUTION: A display device 11 comprises: a switching element 24; a first electrode 25 connected to the switching element 24; first wiring 27 connected to the switching element 24, located on a lower layer side from the first electrode 25, and transmitting an image signal supplied to the first electrode 25; a second electrode 38 located on an upper layer side from the first wiring 27, having a reflective layer 38B that reflects light and has an uneven surface 38S; a third electrode 37 located on the lower layer side from the first electrode 25 and the upper layer side from the first wiring 27, disposed so as to overlap at least each of the first electrode 25 and the first wiring 27, and set to a common potential; a first insulating film 35 interposed between the first electrode 25 and the third electrode 37; and a second insulating film 34 located on the upper layer side from the first wiring 27, disposed on the lower layer side to the third electrode 37, having a film thickness greater than that of the first insulating film 35.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The technology disclosed in this specification relates to a display device. [Background technology]

[0002] One example of a conventional display device is described in Patent Document 1 below. Patent Document 1 describes a reflective liquid crystal display element as the display device. The reflective liquid crystal display element described in Patent Document 1 includes a reflector, a counter substrate facing the reflector, and a liquid crystal layer sandwiched between the reflector and the counter substrate. The reflector is provided on a glass substrate and includes a photosensitive resin layer whose surface portion has a plurality of concave and convex surfaces inclined in a certain direction, and a reflective film provided on the photosensitive resin layer. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2000-105370 Summary of the Invention [Problem to be solved by the invention]

[0004] In the reflective LCD device described in Patent Document 1, a reflective film with an uneven surface functions as a pixel electrode, but the device does not include a structure for maintaining the potential of the reflective film charged by the TFTs when they are driven. To maintain the potential of the reflective film, for example, a common electrode may be provided overlapping the reflective film via an insulating film, forming a storage capacitor between the reflective film and the common electrode. However, in the reflective LCD device described in Patent Document 1, if a common electrode is provided overlapping the reflective film with an uneven surface via an insulating film, the common electrode will have an uneven shape that matches the reflective film. This makes it difficult to maintain a constant distance between the common electrode and the reflective film across the entire display. Variations in the distance between the common electrode and the reflective film can cause the storage capacitor to become unstable, potentially resulting in a degradation of display quality.

[0005] The technology described in this specification was developed based on the above circumstances, and aims to suppress the degradation of display quality. [Means for solving the problem]

[0006] (1) A display device according to the technology described in this specification includes a switching element, a first electrode connected to the switching element, a first wiring connected to the switching element and located below the first electrode, and transmitting an image signal supplied to the first electrode, a second electrode located above the first wiring and having a reflective layer that reflects light, the reflective layer having an uneven surface, a third electrode located below the first electrode and above the first wiring, overlapping at least with the first electrode and the first wiring and at a common potential, a first insulating film interposed between the first electrode and the third electrode, and a second insulating film located above the first wiring and located below the third electrode, having a thickness greater than that of the first insulating film.

[0007] (2) In addition to (1), the display device may further include a third insulating film that is disposed between the second electrode and the first electrode and has a thickness greater than that of the first insulating film, and the second electrode is disposed above the first electrode.

[0008] (3) In addition to (2), the display device may further include a fourth electrode arranged opposite the second electrode at a distance and at a common potential, and a liquid crystal layer interposed between the second electrode and the fourth electrode, wherein the second electrode is arranged to overlap the first electrode, and a first contact hole connecting the second electrode to the first electrode is opened in the third insulating film at a position where it overlaps both the second electrode and the first electrode.

[0009] (4) In addition to (1), the display device may further include a fourth insulating film in which the second electrode is disposed below the second insulating film, is positioned above the first wiring, is disposed below the second electrode, and is thicker than the first insulating film.

[0010] (5) In addition to the above (4), the display device may be configured such that the second electrode is at the common potential.

[0011] (6) In addition to (5), the display device may further include a plurality of the first electrodes arranged side by side with a gap therebetween, and the second electrode may be arranged in a range spanning the plurality of first electrodes.

[0012] (7) Furthermore, in addition to any one of (4) to (6), the display device may further include a fifth electrode arranged below the second insulating film and above the fourth insulating film, the second electrode having a transparent electrode film arranged below the reflective layer, the fifth electrode consisting of a part of the transparent electrode film and arranged to overlap a part of the switching element and to overlap a part of the first electrode, a second contact hole connecting the fifth electrode to the switching element being opened in the fourth insulating film at a position overlapping both the switching element and the fifth electrode, and a third contact hole connecting the first electrode to the fifth electrode being opened in the second insulating film at a position overlapping both the first electrode and the fifth electrode.

[0013] (8) In addition to (7), the display device may further include a sixth electrode arranged opposite the first electrode at a distance and at a common potential, and a liquid crystal layer interposed between the first electrode and the sixth electrode.

[0014] (9) Furthermore, in addition to any one of (1) to (8), the display device may further include a second wiring connected to the switching element, intersecting the first wiring, and transmitting a scanning signal; a fifth insulating film arranged above the first wiring and below the second wiring; and a third wiring arranged below the fifth insulating film and overlapping the second wiring, and a fourth contact hole connecting the second wiring to the third wiring may be opened at a position in the fifth insulating film where it overlaps both the second wiring and the third wiring. [Effects of the Invention]

[0015] According to the technology described in this specification, it is possible to suppress a decrease in display quality. [Brief explanation of the drawings]

[0016] [Figure 1]1 is a schematic cross-sectional view showing a liquid crystal panel, a driver, and a flexible substrate that constitute a liquid crystal display device according to Embodiment 1. [Figure 2] FIG. 1 is a plan view showing a pixel arrangement in a display area of ​​a liquid crystal panel according to a first embodiment; [Figure 3] FIG. 1 is an enlarged plan view showing a pixel arrangement in a display area of ​​a liquid crystal panel according to a first embodiment; [Figure 4] 4 is a cross-sectional view of the liquid crystal panel according to the first embodiment taken along line iv-iv in FIG. 3. [Figure 5] 4 is a cross-sectional view of the liquid crystal panel according to the first embodiment taken along line vv in FIG. 3. [Figure 6] FIG. 1 is an enlarged plan view showing a pixel arrangement in a display area of ​​a liquid crystal panel according to a first embodiment, in which a first metal film and a second metal film are shown in different hatched patterns; [Figure 7] FIG. 1 is an enlarged plan view showing a pixel array in a display region of a liquid crystal panel according to a first embodiment, in which a second transparent electrode film is shown in a shaded pattern. [Figure 8] 8 is a cross-sectional view of the liquid crystal panel according to the first embodiment taken along line VIII-VIII in FIG. 3. [Figure 9] FIG. 1 is an enlarged plan view showing a pixel array in a display region of a liquid crystal panel according to a first embodiment, in which a first transparent electrode film is shown in a shaded pattern. [Figure 10] FIG. 1 is an enlarged plan view showing a pixel array in a display area of ​​a liquid crystal panel according to Embodiment 1, in which a third transparent electrode film and a third metal film are shown in different hatched patterns. [Figure 11] 1 is a cross-sectional view of the liquid crystal panel according to the first embodiment taken along line xi-xi in FIG. 3 . [Figure 12] FIG. 10 is an enlarged plan view showing a pixel arrangement in a display area of ​​a liquid crystal panel according to a second embodiment. [Figure 13] 12. A cross-sectional view of the liquid crystal panel according to the second embodiment taken along line xiii-xiii in FIG. [Figure 14] 14 is a cross-sectional view of the liquid crystal panel according to the second embodiment taken along line xiv-xiv in FIG. 12. [Figure 15]FIG. 10 is an enlarged plan view showing a pixel array in a display area of ​​a liquid crystal panel according to a second embodiment, in which a first transparent electrode film and a third metal film are shown in different hatched patterns. [Figure 16] 13 is a cross-sectional view of the liquid crystal panel according to the second embodiment taken along line xvi-xvi in ​​FIG. 12 . [Figure 17] FIG. 10 is an enlarged plan view showing a pixel arrangement in a display region of a liquid crystal panel according to a second embodiment, in which a third transparent electrode film is shown in a shaded pattern. [Figure 18] FIG. 10 is an enlarged plan view showing a pixel array in a display area of ​​a liquid crystal panel according to a second embodiment, in which the second transparent electrode film is shown in a shaded pattern. [Figure 19] 12 in a cross section of the liquid crystal panel according to the second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0017] <Embodiment 1> Embodiment 1 will be described with reference to Figs. 1 to 11. In this embodiment, a semi-transmissive liquid crystal display device 10 will be illustrated. Note that X-axis, Y-axis, and Z-axis are shown in parts of each drawing, and each axis direction is drawn to correspond to the direction shown in each drawing. Also, the upper side of Figs. 1, 4, 5, 8, and 11 is the front side, and the lower side of each drawing is the back side.

[0018] As shown in FIG. 1, a transflective liquid crystal display device 10 includes a transflective liquid crystal panel (display device) 11 that displays an image and a backlight device (illumination device) that irradiates the liquid crystal panel 11 with light. The transflective liquid crystal panel 11 is capable of both reflective display, which reflects external light (ambient light, environmental light) for display, and transmissive display, which transmits light (backlight) emitted from the backlight device for display. The external light used in reflective display includes sunlight and indoor lighting. The central portion of the screen of the liquid crystal panel 11 is a display area where an image is displayed, and the frame-like outer peripheral portion of the screen surrounding the display area is a non-display area where no image is displayed. The backlight device is disposed on the rear side (lower side in FIG. 1) of the liquid crystal panel 11 and includes a light source (e.g., an LED) that emits white light and optical components that convert the light from the light source into planar light by applying an optical effect.

[0019] As shown in FIG. 1, the liquid crystal panel 11 is formed by bonding a pair of substrates 20 and 21 together. The front side (front surface) of the pair of substrates 20 and 21 is a counter substrate (second substrate, CF substrate) 20, and the back side (rear surface) is an array substrate (first substrate) 21. The counter substrate 20 and the array substrate 21 are formed by laminating various films on the inner surface of glass substrates (substrates) 20GS and 21GS, respectively, made of glass material. Examples of glass materials used for the glass substrates 20GS and 21GS include alkali-free glass. A predetermined gap is provided between the pair of substrates 20 and 21, and a liquid crystal layer 22 is provided therein. The liquid crystal layer 22 contains liquid crystal molecules, which are a substance whose optical properties change when an electric field is applied. A seal portion 23 that seals the liquid crystal layer 22 is interposed between the outer peripheral edges of the pair of substrates 20 and 21. The sealing portion 23 is made of a photocurable resin material, a thermosetting resin material, or the like, and is formed in a frame shape (endless ring) so as to surround the liquid crystal layer 22. Polarizing plates 14 are attached to the outer surfaces of both the substrates 20 and 21, respectively.

[0020] 1, the dimension of the counter substrate 20 in the Y-axis direction is shorter than the dimension of the array substrate 21 in the Y-axis direction. The counter substrate 20 is attached to the array substrate 21 so that one end portion in the Y-axis direction is aligned with the array substrate 21. Therefore, the other end portion of the array substrate 21 in the Y-axis direction is an exposed portion 21A that protrudes laterally from the counter substrate 20 and is exposed. A driver (signal supply unit) 12 and a flexible substrate 13 are mounted on this exposed portion 21A to supply various signals related to the display function, which will be described below.

[0021] The driver 12 is an LSI chip having an internal drive circuit. As shown in FIG. 1, the driver 12 is mounted on the exposed portion 21A of the array substrate 21 by COG (Chip On Glass). The driver 12 processes various signals transmitted by the flexible substrate 13. The flexible substrate 13 is configured by forming multiple wiring patterns on a base material made of an insulating and flexible synthetic resin material (e.g., polyimide resin). One end of the flexible substrate 13 is connected to the exposed portion 21A of the array substrate 21, and the other end is connected to an external circuit board (e.g., a control board). The driver 12 and the flexible substrate 13 supply various signals (e.g., scanning signals, image signals, etc.) to a backplane circuit (e.g., gate lines 26, source lines 27) provided in the liquid crystal panel 11.

[0022] An outline of the configuration of the display area of ​​the array substrate 21 will be described with reference to FIGS. 2 and 3. As shown in FIGS. 2 and 3, at least TFTs (transistors, switching elements) 24 and pixel electrodes (first electrodes) 25 are provided on the inner surface of the display area of ​​the array substrate 21. The TFTs 24 and pixel electrodes 25 are arranged in a matrix (row and column) with multiple TFTs 24 and multiple pixel electrodes 25 spaced apart along the X-axis and Y-axis directions. Gate wiring (second wiring, scanning wiring) 26 and source wiring (first wiring, image wiring, signal wiring) 27 are arranged around the TFTs 24 and pixel electrodes 25, intersecting each other at right angles (intersecting). The gate wiring 26 extends along the X-axis direction, with multiple gate wirings 26 arranged side by side with intervals along the Y-axis. The gate wiring 26 transmits scanning signals for driving the TFTs 24. The source wiring 27 extends along the Y-axis direction, with multiple source wirings 27 arranged side by side with intervals along the X-axis. The source wiring 27 transmits an image signal for charging the pixel electrode 25. The pixel electrode 25, together with a color filter 28 described below, constitutes a pixel, which is a display unit. The TFT 24, the gate wiring 26, and the source wiring 27 constitute a backplane circuit for driving the pixel.

[0023] The configuration of the display area of ​​the counter substrate 20 will be described with reference to FIG. 4. As shown in FIG. 4, three color filters 28, each representing a blue (B), green (G), and red (R), are provided on the inner surface of the display area AA of the counter substrate 20. The color filters 28, each representing a different color, are arranged adjacent to each other in the X-axis direction. The color filters 28, each representing a different color, extend along the Y-axis direction. As such, the color filters 28, each representing a different color, are arranged in a vertical stripe pattern overall. These color filters 28 are arranged to overlap with the pixel electrodes 25 on the array substrate 21 side in a plan view. The overlapping color filters 28 and pixel electrodes 25 form a pixel, which is a display unit. The color filters 28, each representing a different color, are arranged such that their boundaries (color boundaries) overlap with the source wiring 27. An overcoat film 29 is provided on the upper layer side (liquid crystal layer 22 side) of the color filters 28 for planarization. The overcoat film 29 is disposed in a solid state over almost the entire area of ​​the counter substrate 20 .

[0024] As shown in FIG. 4, a counter electrode (fourth electrode) 30 is provided on the upper side of the overcoat film 29. Like the overcoat film 29, the counter electrode 30 is solid and is provided across at least the entire display area. The counter electrode 30 is made of a transparent electrode material. A common potential is supplied to the counter electrode 30. Therefore, an electric field is generated between the counter electrode 30 and the pixel electrodes 25 charged by the TFTs 24, and this electric field can control the alignment state of the liquid crystal molecules contained in the liquid crystal layer 22. The liquid crystal panel 11 according to this embodiment operates in a VA (Vertical Alignment) mode. The VA mode is a display mode in which liquid crystal molecules are aligned vertically relative to the main surfaces of the glass substrates, and the alignment state of the liquid crystal molecules is switched by a vertical electric field. Furthermore, a spacer 31 protruding toward the array substrate 21 is provided on the upper side of the counter electrode 30 (see FIG. 2). The protruding tip surfaces of the spacers 31 are capable of contacting the inner surface of the array substrate 21, thereby maintaining the distance between the pair of substrates 20, 21, i.e., the cell gap (thickness of the liquid crystal layer 22). Note that, of both substrates 20, 21, an alignment film for aligning the liquid crystal molecules contained in the liquid crystal layer 22 is formed on the innermost surface (uppermost layer) that contacts the liquid crystal layer 22.

[0025] Next, various films laminated on the inner surface side of the array substrate 21 will be described with reference to Figures 4 and 5. On the array substrate 21, as shown in Figures 4 and 5, from the lower layer side (glass substrate 21GS side), a first metal film (first conductive film), a gate insulating film (fifth insulating film) 32, a semiconductor film, a second metal film (second conductive film), an interlayer insulating film 33, a first planarization film (second insulating film, first organic insulating film) 34, a first transparent electrode film (third conductive film), an interelectrode insulating film (first insulating film) 35, a second transparent electrode film (fourth conductive film), a second planarization film (third insulating film, second organic insulating film) 36, a third transparent electrode film (fifth conductive film), a third metal film (sixth conductive film), and an alignment film are laminated.

[0026] The first metal film, the second metal film, and the third metal film are each a single layer film made of one type of metal material selected from copper, titanium, aluminum, molybdenum, tungsten, etc., or a laminated film or alloy made of different types of metal materials, and are therefore conductive, light-reflective, and light-blocking. The first metal film constitutes the gate line 26, the gate electrode 24A of the TFT 24, etc. The second metal film constitutes the source line 27, the source electrode 24B, and the drain electrode 24C of the TFT 24, etc. The third metal film constitutes a part of the reflective electrode 38 described below, etc. The semiconductor film is made of a thin film using a semiconductor material such as an oxide semiconductor, and constitutes the semiconductor portion 24D of the TFT 24, etc. The first transparent electrode film, the second transparent electrode film, and the third transparent electrode film are made of transparent electrode materials (e.g., ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide)). The first transparent electrode film constitutes the common electrode 37 described below, etc. The second transparent electrode film constitutes the pixel electrode 25, etc. The third transparent electrode film constitutes a part of the reflective electrode 38 described later.

[0027] The gate insulating film 32, the interlayer insulating film 33, and the interelectrode insulating film 35 are each made of silicon nitride (SiN xThe first planarization film 34 and the second planarization film 36 are made of an inorganic insulating material such as silicon dioxide (SiO2). The first planarization film 34 and the second planarization film 36 are made of an organic insulating material such as PMMA (acrylic resin). The film thickness of the first planarization film 34 and the second planarization film 36 is larger than that of the gate insulating film 32, the interlayer insulating film 33, and the interelectrode insulating film 35, which are made of inorganic insulating materials, and is, for example, approximately 1 μm to 3 μm. The first planarization film 34 planarizes the structure (common electrode 37) made of the first transparent electrode film located above it. The second planarization film 36 ensures the degree of freedom regarding the cross-sectional shape of the structure (reflective electrode 38) made of the first transparent electrode film located above it. The gate insulating film 32 keeps the first metal film on the lower layer side insulated from the semiconductor film and second metal film on the upper layer side. The interlayer insulating film 33 and the first planarization film 34 keep the semiconductor film and second metal film on the lower layer side insulated from the first transparent electrode film on the upper layer side. The inter-electrode insulating film 35 keeps the lower first transparent electrode film and the upper second transparent electrode film in an insulated state, and the second planarizing film 36 keeps the lower second transparent electrode film and the upper third transparent electrode film insulated from each other.

[0028] The configuration of the TFT 24 will be described in detail using Figures 5 and 6. Figure 6 illustrates the same pixel array as Figure 3, and in Figure 6, the first metal film and the second metal film provided on the array substrate 21 are illustrated with different hatching. As shown in Figures 5 and 6, the TFT 24 has a gate electrode 24A made of the first metal film. The gate electrode 24A branches off from the gate line 26. More specifically, the gate electrode 24A is formed by extending a portion of the gate line 26 along the Y-axis direction toward the pixel electrode 25 to which it is connected, and has a vertically elongated, approximately rectangular shape in plan view. A scanning signal transmitted to the gate line 26 is supplied to the gate electrode 24A. The TFT 24 has a source electrode 24B made of the second metal film. The source electrode 24B branches off from the source line 27. More specifically, the source electrode 24B is formed by extending a portion of the source wiring 27 along the X-axis direction toward the pixel electrode 25 to be connected, then bending it toward the gate wiring 26 and extending it along the Y-axis direction, forming a substantially L-shape in plan view. The portion of the source electrode 24B on the tip side extending from the source wiring 27 (the right side portion in FIG. 6) is connected to a semiconductor portion 24D, which will be described below, and is disposed so as to overlap the gate electrode 24A.

[0029] As shown in FIGS. 5 and 6, the TFT 24 has a drain electrode 24C made of a second metal film. The drain electrode 24C has an island shape extending generally along the Y-axis direction. One end (lower side in FIG. 6) of the drain electrode 24C is connected to a semiconductor portion 24D (described below) at a position spaced apart from the source electrode 24B in the X-axis direction and is disposed overlapping the gate electrode 24A. The other end (upper side in FIG. 6) of the drain electrode 24C has a horizontally elongated rectangular shape and is connected to the pixel electrode 25. The drain electrode 24C is disposed overlapping the pixel electrode 25 over its entire area. A pixel contact hole CH1 is formed in the interlayer insulating film 33 and the first planarization film 34 at a position overlapping both the other end of the drain electrode 24C and a portion of the pixel electrode 25. The pixel electrode 25 is connected to the drain electrode 24C through the pixel contact hole CH1.

[0030] As shown in FIGS. 5 and 6, the TFT 24 has a semiconductor portion 24D made of a semiconductor film. The semiconductor portion 24D has a substantially rectangular shape in a plan view. One end of the semiconductor portion 24D in the X-axis direction (the left side in FIG. 6) is connected to the source electrode 24B, and the other end of the semiconductor portion 24D in the X-axis direction (the right side in FIG. 6) is connected to the drain electrode 24C. The semiconductor portion 24D is disposed so as to overlap the gate electrode 24A via the gate insulating film 32. When the TFT 24 is turned on based on a scanning signal supplied to the gate electrode 24A, an image signal supplied from the source line 27 to the source electrode 24B is supplied to the drain electrode 24C via the semiconductor portion 24D, and as a result, the pixel electrode 25 is charged to a potential based on the image signal.

[0031] The structure of the pixel electrode 25 will be described in detail with reference to FIGS. 4, 7, and 8. FIG. 7 illustrates the pixel array in the same range as FIG. 3, and in FIG. 7, the second transparent electrode film provided on the array substrate 21 is illustrated as a shaded area. As shown in FIG. 7, the pixel electrode 25 is disposed in an area surrounded by the gate lines 26 and the source lines 27, and has a vertically elongated, approximately rectangular shape in plan view. The pixel electrode 25 is disposed so as to overlap almost the entire area of ​​the TFT 24. The pixel electrode 25 is made of the second transparent electrode film, and as shown in FIGS. 4 and 8, is located above both the gate lines 26 and the source lines 27. As shown in FIGS. 7 and 8, the dimension of the pixel electrode 25 in the Y-axis direction is slightly larger than the arrangement interval of the gate lines 26. Therefore, the pixel electrode 25 partially overlaps the gate line 26, and the outer edge along the X-axis direction is located closer to the center in the line width direction (Y-axis direction) of the gate line 26 than the side edge of the gate line 26. As shown in Figures 4 and 7, the dimension of the pixel electrode 25 in the X-axis direction is approximately equal to the arrangement interval of the source lines 27. Therefore, the pixel electrode 25 is arranged so that the outer edge along the Y-axis direction overlaps the side edge of the source line 27.

[0032] As shown in FIGS. 4 and 8, the array substrate 21 is provided with a common electrode (third electrode, storage capacitor electrode) 37 for forming a storage capacitor between itself and the pixel electrodes 25. The configuration of the common electrode 37 will be described in detail below with reference to FIGS. 4, 5, 8, and 9. FIG. 9 illustrates the pixel array in the same range as FIG. 3, and in FIG. 9, the first transparent electrode film provided on the array substrate 21 is illustrated as a shaded pattern. As shown in FIGS. 4, 8, and 9, the common electrode 37 is disposed in a solid pattern across almost the entire display area. The common electrode 37 is made of a first transparent electrode film and is disposed below all pixel electrodes 25 disposed in the display area, with an inter-electrode insulating film 35 interposed between them. The common electrode 37, made of the first transparent electrode film, is located above both the gate lines 26 and the source lines 27. The common electrode 37 is also present in the regions (inter-pixel regions) between adjacent pixel electrodes 25 in the X-axis and Y-axis directions, and is therefore arranged to overlap the gate lines 26 and source lines 27. A common potential signal, which serves as a common potential (reference potential), is supplied to the common electrode 37 by the backplane circuit. The common electrode 37, which serves as the common potential, is arranged to overlap the pixel electrodes 25 charged by the TFTs 24 via the inter-electrode insulating film 35, so that a storage capacitance is formed between the pixel electrodes 25 and the common electrode 37. Utilizing this storage capacitance, the potential of the charged pixel electrodes 25 can be effectively maintained. Furthermore, as shown in FIG. 5 , a first opening 37A is provided in the common electrode 37 at a position overlapping the pixel contact hole CH1 to allow the pixel electrodes 25 to pass through. The first opening 37A prevents short-circuiting between the pixel electrodes 25 and the common electrode 37.

[0033] As shown in FIGS. 4 and 5 , in this embodiment, the common electrode 37, which has a common potential, is disposed above the source line 27 but below the pixel electrode 25. This suppresses parasitic capacitance that may occur between the source line 27 and the pixel electrode 25. Furthermore, the first planarization film 34, which is disposed above the source line 27 and below the common electrode 37, is thicker than the inter-electrode insulating film 35, ensuring sufficient flatness of the common electrode 37, which is disposed above the first planarization film 34. Ensuring the flatness of the common electrode 37 also ensures the flatness of the pixel electrode 25, which is disposed above the common electrode 37 via the inter-electrode insulating film 35. Therefore, compared to the conventional case in which a common electrode is provided overlapping a reflective layer having an uneven surface via an insulating film, the spacing between the pixel electrode 25 and the common electrode 37 is less likely to vary. This stabilizes the storage capacitance formed between the pixel electrode 25 and the common electrode 37, thereby reducing degradation of display quality.

[0034] As shown in FIGS. 4 and 8, the array substrate 21 is provided with a reflective electrode (second electrode) 38 for performing reflective display using external light. The configuration of the reflective electrode 38 will be described in detail below with reference to FIGS. 4, 5, 8, and 10. FIG. 10 illustrates the same pixel array as FIG. 3, and in FIG. 10, the third transparent electrode film and the third metal film provided on the array substrate 21 are illustrated with different hatching patterns. As shown in FIG. 5, the reflective electrode 38 has a layered structure including a transparent electrode layer 38A and a reflective layer 38B layered on the upper side of the transparent electrode layer 38A. The transparent electrode layer 38A is made of the third transparent electrode film and can efficiently transmit light. The reflective layer 38B is made of the third metal film and can efficiently reflect light. Thus, the reflective electrode 38 is disposed above the pixel electrode 25 made of the second transparent electrode film. The reflective electrode 38 has an uneven cross-sectional shape, and the reflective layer 38B disposed on its surface has an uneven surface 38S. The uneven surface 38S includes multiple convex portions 38S1 and multiple concave portions 38S2, and these convex portions 38S1 and concave portions 38S2 are alternately arranged within the uneven surface 38S. The cross-sectional shape of the reflective electrode 38 reflects the cross-sectional shape of the second planarization film 36 that underlies the reflective electrode 38. To form the cross-sectional shape of the second planarization film 36 into an uneven shape, for example, the second planarization film 36 may be made of a photosensitive organic insulating material, and the formed second planarization film 36 may be exposed and developed using a halftone mask or gray-tone mask having a pattern that reflects the uneven shape. In this way, the reflective layer 38B of the reflective electrode 38 has an uneven surface 38S, which allows it to diffuse and reflect external light, thereby achieving a display that is close to paper white. The alignment film disposed above the reflective electrode 38 has a cross-sectional shape that is uneven in accordance with the reflective electrode 38 .

[0035] As shown in Fig. 10, the reflective electrode 38 is disposed in a region surrounded by the gate lines 26 and the source lines 27, and has a vertically elongated, approximately rectangular shape in plan view. The dimension of the reflective electrode 38 in the Y-axis direction is slightly larger than the arrangement interval of the gate lines 26, and the dimension of the reflective electrode 38 in the X-axis direction is approximately equal to the arrangement interval of the source lines 27. In other words, the size of the reflective electrode 38 in plan view is approximately the same as that of the pixel electrodes 25, and the reflective electrode 38 is disposed so as to overlap the pixel electrodes 25 over substantially the entire area in plan view. The reflective electrode 38 is connected to the pixel electrodes 25, as shown in Fig. 5. An inter-electrode contact hole (first contact hole) CH2 is opened and formed in the second planarization film 36 interposed between the transparent electrode layer 38A constituting the reflective electrode 38 and the pixel electrode 25. The inter-electrode contact hole CH2 is disposed in a position on the second planarization film 36 that overlaps both the transparent electrode layer 38A and the pixel electrode 25 (specifically, on the right side of the pixel contact hole CH1 in FIG. 5 ). The transparent electrode layer 38A is connected to the pixel electrode 25 through the inter-electrode contact hole CH2, so that the reflective electrode 38 has the same potential as the pixel electrode 25. Therefore, when the pixel electrode 25 is charged as the TFT 24 is driven, the reflective electrode 38 is also charged to the same potential as the pixel electrode 25, and a storage capacitance is formed between the pixel electrode 25 and the common electrode 37, so that the potential of the reflective electrode 38 is also well maintained. The reflective electrode 38 is disposed closest to the liquid crystal layer 22 on the array substrate 21 after the alignment film, so that a sufficiently strong electric field is generated between the reflective electrode 38 and the counter electrode 30 that faces the reflective electrode 38 across the liquid crystal layer 22. This electric field controls the alignment state of the liquid crystal molecules contained in the liquid crystal layer 22, thereby controlling the amount of light emitted toward the front side of the liquid crystal panel 11 for each pixel, thereby making it possible to display a predetermined image in the display area. Note that the counter electrode 30 provided on the counter substrate 20 has an opening 30A at a position overlapping the inter-electrode contact hole CH2 as a structure for regulating the alignment of the liquid crystal molecules contained in the liquid crystal layer 22.

[0036] As shown in FIGS. 4, 8, and 10, the reflective electrode 38 has a transmissive opening 38C formed by partially cutting out the reflective layer 38B. The transmissive opening 38C is provided in the reflective layer 38B of the reflective electrode 38 but is not formed in the transparent electrode layer 38A. The transmissive opening 38C is located near the center of the reflective electrode 38 in the X-axis direction and is disposed in a position sandwiching the inter-electrode contact hole CH2 between the transmissive opening 38C and the inter-pixel contact hole CH1 in the Y-axis direction. The transmissive opening 38C has a substantially rectangular planar shape with four diagonally cut corners. Light irradiated from the backlight device toward the liquid crystal panel 11 can pass through the transparent electrode layer 38A and exit to the front side through the transmissive opening 38C in the reflective layer 38B. This enables transmissive display using light from the backlight device in addition to reflective display using external light.

[0037] 4, 5, and 8, in this embodiment, the reflective electrode 38 is disposed above the pixel electrode 25, so that light reflected by the reflective layer 38B of the reflective electrode 38 does not pass through the pixel electrode 25. Therefore, light can be reflected by the reflective layer 38B of the reflective electrode 38 with low loss and used to display an image. Because the thickness of the second planarization film 36 disposed below the reflective electrode 38 is greater than the thickness of the inter-electrode insulating film 35, the cross-sectional shape of the second planarization film 36 is more reliably formed as designed. Therefore, the reproducibility of the shape of the uneven surface 38S of the reflective layer 38B of the reflective electrode 38 is improved.

[0038] As shown in FIGS. 4 and 11, the array substrate 21 is provided with redundant wiring (third wiring) 39 connected to the source wiring 27. The configuration of the redundant wiring 39 will be described in detail below with reference to FIGS. 4, 6, and 11. As shown in FIGS. 4 and 11, the redundant wiring 39 is made of a first metal film and is arranged to overlap the source wiring 27 to be connected. As shown in FIG. 6, the redundant wiring 39 extends along the Y-axis direction parallel to the source wiring 27. The redundant wiring 39 has a line width greater than that of the source wiring 27, for example, approximately three times the line width. The redundant wiring 39 is arranged concentrically with the source wiring 27 in the line width direction (X-axis direction), and has a central portion overlapping the source wiring 27 and a pair of side portions sandwiching the central portion. Therefore, the pair of side portions sandwiching the central portion of the redundant wiring 39 do not overlap the source wiring 27 but overlap the pixel electrode 25 and the reflective electrode 38. The redundant wiring 39 has a length that extends from a position in the source wiring 27 that is above the portion where the source electrode 24B branches off as shown in FIG. 6 to a position that is below the portion where the source wiring 27 intersects with the gate wiring 26 as shown in FIG. 6.

[0039] As shown in FIG. 11 , an inter-wiring contact hole (fourth contact hole) CH3 is formed in the gate insulating film 32 interposed between the redundant wiring 39 made of the first metal film and the source wiring 27 made of the second metal film. The inter-wiring contact hole CH3 is arranged in the gate insulating film 32 at a position overlapping both the redundant wiring 39 and the source wiring 27. Two inter-wiring contact holes CH3 are provided in positions overlapping both ends of the redundant wiring 39 in the length direction (Y-axis direction). The source wiring 27 is connected to both ends of the redundant wiring 39 in the length direction through the two inter-wiring contact holes CH3. Therefore, for example, even if a break occurs in the source wiring 27 between the two inter-wiring contact holes CH3, an image signal transmitted from the signal supply source side (driver 12 side) of the source wiring 27 relative to the break can be transmitted to the signal supply destination side (opposite the driver 12 side) relative to the break via the redundant wiring 39. This ensures redundancy of the source wiring 27. Furthermore, since the redundant wiring 39 is wider than the source wiring 27, it can block light that would otherwise pass between adjacent pixels in the X-axis direction during transmissive display, thereby suppressing color mixing that can occur between pixels that exhibit different colors.

[0040] 4, in this embodiment, the storage capacitor is formed by the pixel electrode 25 and the common electrode 37, which are located in a layer separate from the redundant wiring 39. This makes it possible to freely set the formation area of ​​the pixel electrode 25 and the common electrode 37, regardless of the presence of the redundant wiring 39. Therefore, compared to a case in which a storage capacitor is formed by providing an electrode having the same potential as the pixel electrode 25 in the same layer (second metal film) as the source wiring 27, and then providing an electrode having a common potential in the same layer (first metal film) as the gate wiring 26 so as to overlap the electrode, the overlapping area of ​​the pixel electrode 25 and the common electrode 37 can be made larger. This makes it possible to increase the storage capacitor formed between the pixel electrode 25 and the common electrode 37, thereby more stably maintaining the potential of the pixel electrode 25.

[0041] As shown in FIG. 8, the array substrate 21 is also provided with gas vent holes 40 for releasing gas generated from the first planarization film 34. The configuration of the gas vent holes 40 will be described in detail below with reference to FIGS. 7 to 9. The gas vent holes 40 are provided in the common electrode 37, the inter-electrode insulating film 35, and the pixel electrode 25, which are interposed between the first planarization film 34 and the second planarization film 36. More specifically, the gas vent holes 40 are formed by interconnecting a second opening 37B provided in the common electrode 37, a third opening 35A provided in the inter-electrode insulating film 35, and a fourth opening 25A provided in the pixel electrode 25. The second opening 37B and the fourth opening 25A have approximately the same opening area, whereas the third opening 35A has a smaller opening area than the second opening 37B and the fourth opening 25A. As shown in FIGS. 7 and 9 , the gas vent hole 40 is positioned adjacent to the drain electrode 24C and the semiconductor portion 24D of the TFT 24 in a plan view. That is, the gas vent hole 40 is positioned so as not to overlap at least the source wiring 27, and the second opening 37B of the common electrode 37 is also positioned so as not to overlap at least the source wiring 27. This allows the common electrode 37 to sufficiently shield the electric field generated by the source wiring 27. If the organic insulating material of the first planarization film 34 and the second planarization film 36 is, for example, an acrylic resin material, gases such as ethylene gas and propane gas may be released from the first planarization film 34 and the second planarization film 36 over time after film formation. If gas is generated from the first planarization film 34, the gas can be released toward the second planarization film 36 through the second opening 37B, the third opening 35A, and the fourth opening 25A that constitute the gas vent hole 40. The gas generated from the first planarization film 34 and the second planarization film 36 can be released toward the liquid crystal layer 22 from the portion of the second planarization film 36 that is not covered by the reflective electrode 38. This allows the gas generated from the first planarization film 34 and the second planarization film 36 to be released.

[0042] As described above, the liquid crystal panel (display device) 11 of this embodiment includes a TFT (switching element) 24, a pixel electrode (first electrode) 25 connected to the TFT 24, a source wiring (first wiring) 27 connected to the TFT 24 and located below the pixel electrode 25, and transmitting an image signal supplied to the pixel electrode 25, a reflective electrode (second electrode) 38 located above the source wiring 27 and having a reflective layer 38B that reflects light, the reflective layer 38B having an uneven surface 38S, a common electrode (third electrode) 37 located below the pixel electrode 25 and above the source wiring 27, arranged to overlap at least the pixel electrode 25 and the source wiring 27, and having a common potential, an inter-electrode insulating film (first insulating film) 35 interposed between the pixel electrode 25 and the common electrode 37, and a first planarization film (second insulating film) 34 located above the source wiring 27 and located below the common electrode 37, and having a thickness greater than that of the inter-electrode insulating film 35.

[0043] When the TFT 24 is driven, the pixel electrode 25 is charged to a potential based on an image signal transmitted through the source line 27. The pixel electrode 25 is disposed overlapping a common electrode 37, which has a common potential, via an inter-electrode insulating film 35, forming a storage capacitance between the pixel electrode 25 and the common electrode 37. Utilizing this storage capacitance, the potential of the charged pixel electrode 25 can be maintained satisfactorily. Meanwhile, light is reflected by the reflective layer 38B of the reflective electrode 38, allowing images to be displayed using external light. The reflective layer 38B of the reflective electrode 38 has an uneven surface 38S, which allows external light to be diffusely reflected, thereby achieving a display that is close to paper white.

[0044] The common electrode 37, which has a common potential, is disposed above the source line 27 but below the pixel electrode 25, thereby suppressing parasitic capacitance that may occur between the source line 27 and the pixel electrode 25. The first planarization film 34, which is disposed above the source line 27 and below the common electrode 37, is thicker than the inter-electrode insulating film 35, ensuring sufficient flatness of the common electrode 37, which is disposed above the first planarization film 34. Ensuring the flatness of the common electrode 37 also ensures the flatness of the pixel electrode 25, which is disposed above the common electrode 37 via the inter-electrode insulating film 35. Therefore, compared to the conventional case where a common electrode is provided overlapping a reflective layer with an uneven surface via an insulating film, variations in the spacing between the pixel electrode 25 and the common electrode 37 are less likely to occur. This stabilizes the storage capacitance formed between the pixel electrode 25 and the common electrode 37, thereby reducing degradation of display quality.

[0045] The reflective electrode 38 is also disposed above the pixel electrode 25 and includes a second planarization film (third insulating film) 36 interposed between the reflective electrode 38 and the pixel electrode 25 and having a thickness greater than that of the inter-electrode insulating film 35. Because the reflective electrode 38 is disposed above the pixel electrode 25, light reflected by the reflective layer 38B of the reflective electrode 38 does not pass through the pixel electrode 25. Therefore, light can be reflected by the reflective layer 38B of the reflective electrode 38 with low loss and used to display images. Because the thickness of the second planarization film 36 disposed below the reflective electrode 38 is greater than the thickness of the inter-electrode insulating film 35, the reproducibility of the shape of the uneven surface 38S of the reflective layer 38B of the reflective electrode 38 is improved.

[0046] The liquid crystal display device also includes a counter electrode (fourth electrode) 30, which is disposed opposite the reflective electrode 38 at a distance and has a common potential, and a liquid crystal layer 22 interposed between the reflective electrode 38 and the counter electrode 30. The reflective electrode 38 is disposed so as to overlap the pixel electrode 25. An inter-electrode contact hole (first contact hole) CH2 connecting the reflective electrode 38 to the pixel electrode 25 is opened in the second planarization film 36 at a position where the second planarization film 36 overlaps both the reflective electrode 38 and the pixel electrode 25. The reflective electrode 38 is connected to the pixel electrode 25 through the inter-electrode contact hole CH2 in the second planarization film 36. Because the reflective electrode 38 has the same potential as the pixel electrode 25, a sufficiently strong electric field can be generated between the reflective electrode 38 and the counter electrode 30. This allows the orientation state of liquid crystal molecules contained in the liquid crystal layer 22 to be well controlled by utilizing the electric field generated between the reflective electrode 38 and the counter electrode 30.

[0047] The pixel also includes a gate line (second line) 26 connected to the TFT 24, intersecting the source line 27, and transmitting a scanning signal; a gate insulating film (fifth insulating film) 32 disposed above the source line 27 and below the gate line 26; and a redundant line (third line) 39 disposed below the gate insulating film 32 and overlapping the gate line 26. An inter-line contact hole (fourth contact hole) CH3 connecting the gate line 26 to the redundant line 39 is opened in the gate insulating film 32 at a position where the gate insulating film 32 overlaps both the gate line 26 and the redundant line 39. The TFT 24 is driven by a scanning signal transmitted to the gate line 26. The source line 27 is connected to the redundant line 39 through the inter-line contact hole CH3 in the gate insulating film 32. If a disconnection occurs in the source line 27, an image signal can be transmitted via the redundant line 39. This ensures redundancy of the source line 27. Furthermore, since the storage capacitor is formed by the pixel electrode 25 and the common electrode 37, which are located in a layer different from the redundant wiring 39, it is possible to freely set the formation area of ​​the pixel electrode 25 and the common electrode 37, regardless of the presence of the redundant wiring 39. Therefore, compared to a case in which a storage capacitor is formed by providing an electrode having the same potential as the pixel electrode 25 in the same layer as the source wiring 27, and then providing an electrode having a common potential in the same layer as the gate wiring 26 so as to overlap the electrode, the overlapping area of ​​the pixel electrode 25 and the common electrode 37 can be made larger. This allows the storage capacitor formed between the pixel electrode 25 and the common electrode 37 to be larger.

[0048] <Embodiment 2> 12 to 19. In this embodiment 2, the order of lamination of each film on the inner surface side of the array substrate 121 is changed, and the configurations of the pixel electrode 125, common electrode 137, reflective electrode 138, etc. are changed. Note that a redundant description of the structure, action, and effects similar to those of the above-mentioned embodiment 1 will be omitted.

[0049] The stacking order of various films stacked on the inner surface of an array substrate 121 constituting a liquid crystal panel 111 according to this embodiment will be described with reference to Figures 13 and 14. As shown in Figures 13 and 14, the array substrate 121 has stacked thereon, in order from the bottom, a first metal film, a gate insulating film (fifth insulating film) 132, a semiconductor film, a second metal film, an interlayer insulating film 133, a first planarization film (fourth insulating film) 134, a first transparent electrode film, a third metal film, a second planarization film (second insulating film) 136, a second transparent electrode film, an interelectrode insulating film (first insulating film) 135, a third transparent electrode film, and an alignment film.

[0050] As shown in FIGS. 12 and 13 , the reflective electrode 138 according to this embodiment is disposed below the pixel electrode 125 and the common electrode 137. Specifically, the reflective electrode 138 is disposed above the first planarization film 134 and below the second planarization film 136. As shown in FIGS. 13 , 15 , and 16 , the reflective electrode 138 is composed of a transparent electrode layer 138A formed from a first transparent electrode film and a reflective layer 138B formed from a third metal film. In this embodiment, a common potential signal, which is set as a common potential by the backplane circuit, is supplied to the reflective electrode 138. Accordingly, the reflective electrode 138 is disposed in a generally solid pattern across almost the entire display area. The reflective electrode 138 is disposed above both the gate wiring 126 and the source wiring 127. The reflective electrode 138 is also present in the regions (inter-pixel regions) between adjacent pixel electrodes 125 in the X-axis and Y-axis directions, and is therefore disposed so as to overlap the gate wiring 126 and the source wiring 127. The reflective electrode 138 has an uneven cross-sectional shape, and the reflective layer 138B disposed on its surface has an uneven surface 138S. The cross-sectional shape of the reflective electrode 138 reflects the cross-sectional shape of the first planarization film 134, which is the base of the reflective electrode 138. To form the uneven cross-sectional shape of the first planarization film 134, for example, the first planarization film 134 may be made of a photosensitive organic insulating material, and the formed first planarization film 134 may be exposed and developed using a half-tone mask or gray-tone mask having a pattern that reflects the uneven shape. Furthermore, as shown in FIG. 13 , the reflective electrode 138 has a transmissive opening 138C formed by partially cutting out the transparent electrode layer 138A in addition to the reflective layer 138B. The transmissive opening 138C is formed by a portion where the transparent electrode layer 138A and the reflective layer 138B that constitute the reflective electrode 138 are not formed.

[0051] 13, 14, and 17, the pixel electrode 125 according to this embodiment is made of a third transparent electrode film. As such, the pixel electrode 125 is disposed next to the alignment film on the array substrate 121 as close to the liquid crystal layer 122 as possible, and therefore an electric field of sufficient strength is generated between the pixel electrode 125 and the counter electrode 130 that faces the pixel electrode 125 across the liquid crystal layer 122. This electric field controls the alignment state of the liquid crystal molecules contained in the liquid crystal layer 122, thereby controlling the amount of light emitted toward the front side of the liquid crystal panel 111 during display for each pixel, thereby enabling a predetermined image to be displayed in the display area.

[0052] As shown in FIGS. 13 to 15, the pixel electrode 125 made of the third transparent electrode film is connected to the drain electrode 124C made of the second metal film via an intermediate electrode (fifth electrode) 41 located midway in the stacking direction (Z-axis direction). The intermediate electrode 41 is made of a part of the first transparent electrode film. That is, the intermediate electrode 41 is located in the same layer as the transparent electrode layer 138A that constitutes the reflective electrode 138. The intermediate electrode 41 made of a part of the first transparent electrode film does not include the third metal film that constitutes the reflective electrode 138. This allows light to pass through the intermediate electrode 41, and prevents a short circuit with the reflective electrode 138 due to remaining third metal film (reflective layer 138B). As shown in FIG. 15, the intermediate electrode 41 is located within the transmissive opening 138C in the reflective electrode 138 and forms an island shape surrounded by the edge of the transmissive opening 138C. The intermediate electrode 41 has a vertically elongated, approximately rectangular shape in a plan view, and is arranged so as to overlap both the drain electrode 124C and the pixel electrode 125 to be connected. In other words, the drain electrode 124C is provided so that a portion thereof extends into the transmissive opening 138C. In detail, one end portion of the intermediate electrode 41 in the Y-axis direction (the lower portion in FIG. 15) overlaps the drain electrode 124C and the pixel electrode 125, and the other end portion of the intermediate electrode 41 in the Y-axis direction (the upper portion in FIG. 15) overlaps the pixel electrode 125 but does not overlap the drain electrode 124C.

[0053] 13 and 14, a first pixel contact hole (second contact hole) CH4 is opened and formed in the interlayer insulating film 133 and first planarization film 134 interposed between the intermediate electrode 41 and the drain electrode 124C. The first pixel contact hole CH4 is arranged in a position in the interlayer insulating film 133 and the first planarization film 134 where it overlaps with both the intermediate electrode 41 and the drain electrode 124C. The intermediate electrode 41 is connected to the drain electrode 124C through the first pixel contact hole CH4. A second pixel contact hole (third contact hole) CH5 is opened and formed in the second planarization film 136 and the interelectrode insulating film 135 interposed between the pixel electrode 125 and the intermediate electrode 41. The second pixel contact hole CH5 is arranged in a position (specifically, on the right side of the first pixel contact hole CH4 in FIG. 14 ) of the second planarization film 136 and the inter-electrode insulating film 135 that does not overlap with the drain electrode 124C but overlaps with both the pixel electrode 125 and the intermediate electrode 41. The pixel electrode 125 is connected to the intermediate electrode 41 through the second pixel contact hole CH5. In this manner, the pixel electrode 125 is connected to the drain electrode 124C of the TFT 124 via the intermediate electrode 41. Note that in the second planarization film 136 and the inter-electrode insulating film 135, the cross-sectional shape of the second pixel contact hole CH5 is gentler than the cross-sectional shape of the first pixel contact hole CH4 in the interlayer insulating film 133 and the first planarization film 134. This makes it easier for the alignment film material to flow into the second pixel contact hole CH5 when it is applied to the innermost surface of the array substrate 121 during manufacturing, thereby increasing the reliability of uniform application of the alignment film. Also, the opening 130A of the counter electrode (sixth electrode) 130 provided on the counter substrate 120 is positioned so as to overlap the first pixel contact hole CH4.

[0054] The common electrode 137 according to this embodiment is made of a second transparent electrode film, as shown in FIGS. 13, 16, and 18. The common electrode 137 made of the second transparent electrode film is disposed below and overlaps a plurality of pixel electrodes 125 via an inter-electrode insulating film 135. This forms a storage capacitor between the common electrode 137, which has a common potential, and the pixel electrodes 125 charged by the TFTs 124, thereby enabling the potential of the charged pixel electrodes 125 to be well maintained. Furthermore, as shown in FIGS. 13 and 16, a first opening 137A is provided in the common electrode 137 at a position overlapping the second pixel contact hole CH5, allowing the pixel electrodes 125 to pass through.

[0055] As shown in FIGS. 13 and 16 , the pixel electrode 125 and the common electrode 137 are located above the second planarization film 136 and are planarized by the second planarization film 136, which is thicker than the inter-electrode insulating film 135. Therefore, the cross-sectional shapes of the pixel electrode 125 and the common electrode 137 are prevented from reflecting the uneven surface 138S of the reflective layer 138B constituting the reflective electrode 138. Because the flatness of the pixel electrode 125 and the common electrode 137 is sufficiently ensured, the gap between the pixel electrode 125 and the common electrode 137 is less likely to vary compared to the conventional case in which a common electrode is provided overlying a reflective layer having an uneven surface via an insulating film. This stabilizes the storage capacitance formed between the pixel electrode 125 and the common electrode 137, thereby reducing the degradation of display quality. In particular, in this embodiment, the pixel electrode 125 is arranged on the top layer of the array substrate 121, next to the alignment film, and the uneven surface 138S of the reflective layer 138B of the reflective electrode 138 is prevented from being exposed on the top layer next to the alignment film, which is advantageous in suppressing volume fluctuations of the liquid crystal layer 122.

[0056] 13 and 16, in this embodiment, in addition to the common electrode 137 having a common potential, a reflective electrode 138 having a common potential is disposed above the source line 127 and below the pixel electrode 125. Therefore, the electric field generated from the source line 127 can be doubly shielded by the common electrode 137 and the reflective electrode 138. This further reduces the parasitic capacitance that may occur between the source line 127 and the pixel electrode 125.

[0057] 19, the gas vent holes 140 according to this embodiment are provided in the common electrode 137 and the inter-electrode insulating film 135, which are located above the second planarization film 136. Specifically, the gas vent holes 140 are configured by a second opening 137B provided in the common electrode 137 and a third opening 135A provided in the inter-electrode insulating film 135, which are connected to each other. As shown in FIGS. 17 and 18, the gas vent holes 140 are arranged at positions overlapping the gate wiring 126 in a plan view, that is, between two pixel electrodes 125 adjacent to each other in the Y-axis direction. A plurality of the gas vent holes 140 are arranged side by side at intervals along the X-axis direction on the gate wiring 126, and the arrangement interval between the holes is approximately half the arrangement interval between the source wirings 127. Specifically, the gas vent hole 140 is disposed at a position overlapping the intersection of the gate wiring 126 and the source wiring 127 and at a midpoint between two adjacent source wirings 127 in the X-axis direction. Since the gas vent hole 140 according to this embodiment is disposed between two adjacent pixel electrodes 125 in the Y-axis direction, display defects caused by the gas vent hole 140 are less likely to be visually recognized. Here, as shown in FIGS. 13 and 14 , gas generated from the first planarization film 134 is released toward the second planarization film 136 through the transmissive opening 138C of the reflective electrode 138. As shown in FIG. 19 , gas generated from the first planarization film 134 and the second planarization film 136 passes through the second opening 137B and the third opening 135A of the second planarization film 136, which constitute the gas vent hole 140, and between the two adjacent pixel electrodes 125 in the Y-axis direction, and is released toward the liquid crystal layer 122. This allows gas generated from the first planarization film 134 and the second planarization film 136 to be released.

[0058] As described above, the liquid crystal panel 111 of this embodiment includes the TFT 124, the pixel electrode 125 connected to the TFT 124, the source wiring 127 connected to the TFT 124 and located below the pixel electrode 125, and transmitting an image signal supplied to the pixel electrode 125, the reflective electrode 138 located above the source wiring 127 and having a reflective layer 138B that reflects light, the reflective layer 138B having an uneven surface 138S, the common electrode 137 located below the pixel electrode 125 and above the source wiring 127, arranged to overlap at least the pixel electrode 125 and the source wiring 127, and having a common potential, the interelectrode insulating film 135 interposed between the pixel electrode 125 and the common electrode 137, and the second planarization film (second insulating film) 136 located above the source wiring 127 and located below the common electrode 137, and having a thickness greater than that of the interelectrode insulating film 135.

[0059] When the TFT 124 is driven, the pixel electrode 125 is charged to a potential based on an image signal transmitted through the source line 127. The pixel electrode 125 is arranged overlapping a common electrode 137, which has a common potential, via an inter-electrode insulating film 135, so a storage capacitor is formed between the pixel electrode 125 and the common electrode 137. Utilizing this storage capacitor, the potential of the charged pixel electrode 125 can be maintained well. Meanwhile, light is reflected by the reflective layer 138B of the reflective electrode 138, allowing images to be displayed using external light. The reflective layer 138B of the reflective electrode 138 has an uneven surface 138S, which allows external light to be diffused and reflected, thereby achieving a display that is close to paper white.

[0060] The common electrode 137, which has a common potential, is disposed above the source line 127 but below the pixel electrode 125, thereby suppressing parasitic capacitance that may occur between the source line 127 and the pixel electrode 125. The second planarization film 136, which is disposed above the source line 127 and below the common electrode 137, is thicker than the inter-electrode insulating film 135, ensuring sufficient flatness of the common electrode 137 located above the second planarization film 136. Ensuring the flatness of the common electrode 137 also ensures the flatness of the pixel electrode 125, which is disposed above the common electrode 137 via the inter-electrode insulating film 135. Therefore, compared to the conventional case where a common electrode is provided overlapping a reflective layer with an uneven surface via an insulating film, variations in the spacing between the pixel electrode 125 and the common electrode 137 are less likely to occur. This stabilizes the storage capacitance formed between the pixel electrode 125 and the common electrode 137, thereby reducing degradation of display quality.

[0061] The reflective electrode 138 is disposed below the second planarization film 136, is located above the source wiring 127, and includes a first planarization film (fourth insulating film) 134 that is disposed below the reflective electrode 138 and has a thickness greater than that of the inter-electrode insulating film 135. Because the reflective electrode 138 is disposed below the second planarization film 136, the uneven surface 138S of the reflective layer 138B of the reflective electrode 138 is planarized by the second planarization film 136. Compared to a case in which the reflective electrode is disposed above the pixel electrode 125, it is possible to prevent the uneven surface 138S of the reflective layer 138B from being exposed to the uppermost layer. Furthermore, because the thickness of the first planarization film 134 disposed below the reflective electrode 138 is greater than the thickness of the inter-electrode insulating film 135, reproducibility of the shape of the uneven surface 138S of the reflective layer 138B of the reflective electrode 138 is improved.

[0062] The reflective electrode 138 is set to a common potential. The reflective electrode 138 and the common electrode 137, both of which are set to a common potential, are disposed above the source line 127 and below the pixel electrode 125, so that the parasitic capacitance that may occur between the source line 127 and the pixel electrode 125 can be further suppressed.

[0063] Furthermore, the pixel electrodes 125 are arranged side by side with a gap therebetween, and the reflective electrode 138 is arranged in a range spanning the pixel electrodes 125. The reflective electrode 138 is arranged to overlap the pixel electrodes 125, and is also arranged in a region between two adjacent pixel electrodes 125. In this way, the amount of light reflected by the reflective layer 138B increases compared to when a plurality of reflective electrodes are provided so as to overlap the pixel electrodes 125 individually, which is preferable for improving the brightness of the displayed image.

[0064] The reflective electrode 138 also has an intermediate electrode (fifth electrode) 41 arranged below the second planarization film 136 and above the first planarization film 134, and the reflective electrode 138 has a transparent electrode layer 138A arranged below the reflective layer 138B, and the intermediate electrode 41 consists of a part of the transparent electrode layer 138A and is arranged to overlap a part of the TFT 124 and to overlap a part of the pixel electrode 125, and a first pixel contact hole (second contact hole) CH4 connecting the intermediate electrode 41 to the TFT 124 is opened and provided in a position of the first planarization film 134 that overlaps with both the TFT 124 and the intermediate electrode 41, and a second pixel contact hole (third contact hole) CH5 connecting the pixel electrode 125 to the intermediate electrode 41 is opened and provided in a position of the second planarization film 136 that overlaps with both the pixel electrode 125 and the intermediate electrode 41. The intermediate electrode 41 is connected to a part of the TFT 124 through a first pixel contact hole CH4 in the first planarization film 134, and a part of the pixel electrode 125 is connected to the intermediate electrode 41 through a second pixel contact hole CH5 in the second planarization film 136. The intermediate electrode 41, which is arranged to overlap the pixel electrode 125, is made of a part of the transparent electrode layer 138A and is therefore capable of transmitting light. In addition, since the intermediate electrode 41 does not have a reflective layer 138B, it is possible to avoid a short circuit with the reflective electrode 138 due to film residue of the reflective layer 138B.

[0065] The liquid crystal display device also includes a counter electrode (sixth electrode) 130, which is disposed opposite the pixel electrode 125 with a gap therebetween and is at a common potential, and a liquid crystal layer 122 interposed between the pixel electrode 125 and the counter electrode 130. An electric field of sufficient strength can be generated between the pixel electrode 125, which is connected to the TFT 124 via the intermediate electrode 41, and the counter electrode 130. This allows the orientation state of the liquid crystal molecules contained in the liquid crystal layer 122 to be well controlled by utilizing the electric field generated between the pixel electrode 125 and the counter electrode 130. The uneven surface 138S of the reflective layer 138B of the reflective electrode 138 is not exposed to the uppermost layer, which is advantageous in suppressing volume fluctuations in the liquid crystal layer 122.

[0066] <Other embodiments> The technology disclosed in this specification is not limited to the embodiments described above and illustrated in the drawings, and the following embodiments, for example, are also included in the technical scope.

[0067] (1) The specific planar shape, size in plan view, etc. of the pixel electrodes 25, 125 can be appropriately changed from those shown in the drawings.

[0068] (2) The specific arrangement, number, planar shape, size in plan view, etc. of the transmissive openings 38C, 138C in the reflective electrodes 38, 138 can be appropriately changed from those shown in the drawings.

[0069] (3) The arrangement and size in plan view of the electrodes 24A, 24B, 24C, and 124C and the semiconductor portion 24D that constitute the TFTs 24 and 124 can be appropriately changed from those shown in the drawings.

[0070] (4) The specific arrangement, number, planar shape, size in plan view, etc. of the gas vent holes 40, 140 may be appropriately changed from those shown in the drawings. For example, in the configuration described in embodiment 1, the gas vent holes 40 may be arranged in a position overlapping the gate wiring 26. For example, in the configuration described in embodiment 2, all of the gas vent holes 140 may be arranged in a position overlapping the gate wiring 126 but not overlapping the source wiring 127.

[0071] (5) The gas vent holes 40, 140 may be omitted.

[0072] (6) The specific line width, length, etc. of the redundant wiring 39 can be appropriately changed from those shown in the drawings. For example, the line width of the redundant wiring 39 may be approximately the same as that of the source wiring 27, 127.

[0073] (7) The redundant wiring 39 can be omitted.

[0074] (8) The liquid crystal panels 11 and 111 may be of a reflective type instead of a semi-transmissive type. If the liquid crystal panels 11 and 111 are of a reflective type, a backlight device can be omitted.

[0075] (9) As described in (8) above, when the liquid crystal panel 11, 111 is a reflective type, the transparent electrode layer 38A, 138A can be omitted from the reflective electrode 38, 138, and the reflective electrode 38, 138 can be configured with only the reflective layer 38B, 138B. In the configuration described in embodiment 2, when the first transparent electrode film that configures the transparent electrode layer 138A is omitted, the intermediate electrode 41 can be configured with a part of the third metal film.

[0076] (10) As in (8) above, when the liquid crystal panels 11, 111 are of a reflective type, the pixel electrodes 25, 125 and the common electrodes 37, 137 can be made of a metal film instead of a transparent electrode film.

[0077] (11) As described in (8) above, when the liquid crystal panel 11 is a reflective type, the transmissive opening 38C can be omitted from the reflective electrode 38 in the configuration described in the first embodiment.

[0078] (12) The material of the semiconductor film that constitutes the semiconductor portion 24D may be amorphous silicon, polysilicon (LTPS), or the like.

[0079] (13) The color filter 28 may be omitted from the counter substrate 20, 120 to form a semi-transmissive liquid crystal panel 11, 111 that displays monochrome. Alternatively, the color filter 28 may be omitted from the counter substrate 20, 120, and the specific types and number of colors of the color filter 28 may be changed.

[0080] (14) The color filter 28 may be provided on the array substrate 21 or 121 instead of the counter substrate 20 or 120.

[0081] (15) The operating mode of the liquid crystal panels 11, 111 may be an IPS (In-Plane Switching) mode or the like. [Explanation of symbols]

[0082] 11,111... liquid crystal panel (display device), 22,122... liquid crystal layer, 24,124... TFT (switching element), 25,125... pixel electrode (first electrode), 26,126... gate wiring (second wiring), 27,127... source wiring (first wiring), 30... opposing electrode (fourth electrode), 32,132... gate insulating film (fifth insulating film), 34... first planarization film (second insulating film), 35,135... inter-electrode insulating film (first insulating film), 36... second planarization film (third insulating film), 37,137... common electrode (third electrode), 38,138... reflective electrode (second electrode) ), 38B, 138B... reflective layer, 38S, 138S... uneven surface, 39... redundant wiring (third wiring), 41... intermediate electrode (fifth electrode), 130... opposing electrode (sixth electrode), 134... first planarization film (fourth insulating film), 136... second planarization film (second insulating film), 138A... transparent electrode layer, CH2... inter-electrode contact hole (first contact hole), CH3... inter-wiring contact hole (fourth contact hole), CH4... first pixel contact hole (second contact hole), CH5... second pixel contact hole (third contact hole)

Claims

1. A switching element; a first electrode connected to the switching element; a first wiring connected to the switching element, located below the first electrode, and transmitting an image signal supplied to the first electrode; a second electrode located above the first wiring and having a reflective layer that reflects light, the reflective layer having an uneven surface; a third electrode located below the first electrode and above the first wiring, overlapping at least the first electrode and the first wiring, and at a common potential; a first insulating film interposed between the first electrode and the third electrode; a second insulating film that is located above the first wiring and below the third electrode, and has a thickness greater than that of the first insulating film; the second electrode is disposed above the first electrode, The display device further comprises a third insulating film interposed between the second electrode and the first electrode, the third insulating film having a thickness greater than that of the first insulating film.

2. a fourth electrode disposed opposite the second electrode with a gap therebetween and set to a common potential; a liquid crystal layer interposed between the second electrode and the fourth electrode; the second electrode is disposed so as to overlap the first electrode, 2. The display device according to claim 1, wherein a first contact hole connecting the second electrode to the first electrode is opened in the third insulating film at a position where the third insulating film overlaps both the second electrode and the first electrode.

3. A switching element; a first electrode connected to the switching element; a first wiring connected to the switching element, located below the first electrode, and transmitting an image signal supplied to the first electrode; a second electrode located above the first wiring and having a reflective layer that reflects light, the reflective layer having an uneven surface; a third electrode located below the first electrode and above the first wiring, overlapping at least the first electrode and the first wiring, and at a common potential; a first insulating film interposed between the first electrode and the third electrode; a second insulating film that is located above the first wiring and below the third electrode, and has a thickness greater than that of the first insulating film; the second electrode is disposed below the second insulating film, a fourth insulating film located above the first wiring and below the second electrode, the fourth insulating film having a thickness greater than that of the first insulating film;

4. 4. The display device according to claim 3, wherein the second electrode is at the common potential.

5. a plurality of the first electrodes are arranged side by side at intervals, The display device according to claim 4 , wherein the second electrode is disposed in a range spanning a plurality of the first electrodes.

6. a fifth electrode disposed below the second insulating film and above the fourth insulating film; the second electrode has a transparent electrode film disposed below the reflective layer, the fifth electrode is made of a part of the transparent electrode film and is arranged to overlap a part of the switching element and a part of the first electrode, a second contact hole that connects the fifth electrode to the switching element is formed in the fourth insulating film at a position that overlaps both the switching element and the fifth electrode; 6. The display device according to claim 3, wherein a third contact hole is opened in the second insulating film at a position where the second insulating film overlaps both the first electrode and the fifth electrode, connecting the first electrode to the fifth electrode.

7. a sixth electrode that is disposed opposite the first electrode with a gap therebetween and has a common potential; The display device according to claim 6 , further comprising: a liquid crystal layer interposed between the first electrode and the sixth electrode.

8. A switching element; a first electrode connected to the switching element; a first wiring connected to the switching element, located below the first electrode, and transmitting an image signal supplied to the first electrode; a second electrode located above the first wiring and having a reflective layer that reflects light, the reflective layer having an uneven surface; a third electrode located below the first electrode and above the first wiring, overlapping at least the first electrode and the first wiring, and at a common potential; a first insulating film interposed between the first electrode and the third electrode; a second insulating film that is located above the first wiring and below the third electrode, and has a thickness greater than that of the first insulating film; a second wiring connected to the switching element, intersecting the first wiring, and transmitting a scanning signal; a fifth insulating film disposed above the first wiring and below the second wiring; a third wiring disposed below the fifth insulating film and overlapping the second wiring, A display device wherein a fourth contact hole that connects the second wiring to the third wiring is opened and provided in the fifth insulating film at a position where the fifth insulating film overlaps both the second wiring and the third wiring.

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