Display substrate and manufacturing method thereof

Abstract

To provide a display substrate which can be manufactured at lower price and can improve the efficiency of moving a micro LED.SOLUTION: The present disclosure relates to a display substrate and a method for manufacturing the display substrate. The display substrate includes a substrate, a first electrode located on the substrate, and a conductive bump located on the first electrode. The size of a cross section of the conductive bump in a plane parallel to the substrate has a negative correlation to the distance from the cross section to the first electrode.SELECTED DRAWING: Figure 1A

Description

[Technical Field]

[0001] The present disclosure relates to the field of display technology, and in particular to a display substrate and a method for manufacturing the same. [Background technology]

[0002] MicroLED is seen as the next-generation display technology with the greatest potential to replace OLED. The advantages of Micro LED include low power consumption, high brightness, ultra-high resolution and color saturation, fast response, ultra-low power consumption, long life, high efficiency, adaptability to various sizes, seamless connection, etc. Micro LED consumes 10% of the power consumption of LCD and 50% of the power consumption of OLED, making it suitable for wearable devices. Summary of the Invention [Means for solving the problem]

[0003] Embodiments of the present disclosure provide a display substrate and a manufacturing method thereof.

[0004] One aspect of the present disclosure provides a display substrate, the display substrate including a substrate, a first electrode located on the substrate, and a conductive bump located on the first electrode, wherein a cross-sectional size of the conductive bump in a plane parallel to the substrate is negatively correlated with a distance from the cross-sectional size to a surface of the first electrode.

[0005] In an exemplary embodiment of the present disclosure, the ratio of the smallest dimension of the surface of the conductive bump facing the substrate in a direction parallel to the substrate to the distance from the top of the conductive bump to the first electrode may be within a range of 1:1 to 1:3.

[0006] In an exemplary embodiment of the present disclosure, the shape of the conductive bump is selected from at least one of a pyramid, a truncated pyramid, and a prism.

[0007] In an exemplary embodiment of the present disclosure, the conductive bump includes a first portion and a second portion covering the first portion. The orthogonal projection of the first portion onto the substrate is located within the orthogonal projection of the first electrode onto the substrate. The second portion contacts the first electrode. A surface of the second portion away from the substrate and a surface of the first portion away from the substrate are conformal. The first portion is made of a dielectric material, and the second portion is made of a conductive material.

[0008] In an exemplary embodiment of the present disclosure, the dielectric material includes an organic material, and the conductive bump further includes an inorganic material layer located between the first portion and the second portion and covering the first portion.

[0009] In an exemplary embodiment of the present disclosure, the second portion further covers a surface of the first electrode adjacent to the first portion.

[0010] In an exemplary embodiment of the present disclosure, the conductive bumps are made of a conductive material.

[0011] In an exemplary embodiment of the present disclosure, the first electrode is integrally formed with the conductive bump, and the ratio of the thickness of the first electrode to the distance from the top of the conductive bump to the bottom of the first electrode is in the range of 1:4 to 1:2.

[0012] In an exemplary embodiment of the present disclosure, a plurality of the conductive bumps arranged in an array are disposed on each of the first electrodes.

[0013] In an exemplary embodiment of the present disclosure, the conductive bump comprises a triangular prism. The triangular prism has a first surface parallel to the surface of the substrate. The first surface has a first side and a second side intersecting the first side. The dimension of the first side is 2 to 10 μm, the dimension of the second side is 1 to 5 μm, the height of the triangular prism in a direction perpendicular to the substrate is 1 to 5 μm, the distance between two adjacent conductive bumps along the first side is 2 to 10 μm, and the distance between two adjacent conductive bumps along the second side is 2 to 5 μm.

[0014] In an exemplary embodiment of the present disclosure, the display substrate further includes an electronic device disposed on the conductive bumps and an adhesive disposed between the conductive bumps, wherein pins of the electronic device contact the conductive bumps and the adhesive bonds the pins to the first electrodes.

[0015] In an exemplary embodiment of the present disclosure, the display substrate further includes a thin film transistor disposed on the substrate and a first dielectric layer disposed on the thin film transistor, and the first electrode is disposed on the first dielectric layer and electrically connected to the thin film transistor.

[0016] In an exemplary embodiment of the present disclosure, the first dielectric layer includes a first sub-dielectric layer and a second sub-dielectric layer stacked in sequence. The display substrate further includes a second electrode and a third electrode disposed between the first sub-dielectric layer and the second sub-dielectric layer. The second electrode is connected to the source / drain region of the thin film transistor through a first hole in the first sub-dielectric layer. The first electrode includes a first sub-electrode and a second sub-electrode. The first sub-electrode is connected to the second electrode through a second hole in the second sub-dielectric layer. The second sub-electrode is connected to the third electrode through a third hole in the second sub-dielectric layer.

[0017] One aspect of the present disclosure provides a method for manufacturing a display substrate, the method including the steps of providing a substrate, forming a first electrode on the substrate, and forming a conductive bump on the first electrode, wherein a cross-sectional size of the conductive bump in a plane parallel to the substrate is negatively correlated with a distance from the cross-sectional size to a surface of the first electrode.

[0018] In an exemplary embodiment of the present disclosure, forming the conductive bump includes forming a dielectric material layer on the first electrode, patterning the dielectric material layer to form a first portion of the conductive bump, forming a first conductive material layer on the substrate, the first electrode, and the first portion, and patterning the first conductive material layer to form a second portion of the conductive bump, wherein an orthogonal projection of the first portion onto the first electrode lies within an orthogonal projection of the second portion onto the first electrode, and the second portion teeth The second portion is in contact with the first electrode, and the surface of the first portion facing away from the substrate is conformal.

[0019] In an exemplary embodiment of the present disclosure, before forming the first conductive material layer on the first portion, the method further comprises roughening a surface of the first portion.

[0020] In an exemplary embodiment of the present disclosure, the second portion is formed to further cover a surface of the first electrode adjacent to the first portion.

[0021] In an exemplary embodiment of the present disclosure, the dielectric material layer includes a photosensitive material. The step of patterning the dielectric material layer includes exposing and developing the dielectric material layer using a first mask. The exposure dose of light, the dimensions of the light-shielding portions of the first mask in a direction perpendicular to the direction in which the light-shielding portions extend, and the distance from the first mask to the dielectric material layer are arranged so that diffracted light occurs at the edges of the light-shielding portions during the exposure, and at least a portion of the diffracted light reaches a surface of the dielectric material layer located below a center of the light-shielding portions.

[0022] In an exemplary embodiment of the present disclosure, forming the conductive bump further includes forming an inorganic material layer on the first portion after forming the first portion and before forming the first conductive material layer, wherein a surface of the inorganic material layer facing away from the substrate and a surface of the first portion facing away from the substrate are conformal.

[0023] In an exemplary embodiment of the present disclosure, the step of forming the first electrode on the substrate and the step of forming the conductive bump on the first electrode include the step of forming a second conductive material layer on the substrate and the step of patterning the second conductive material layer to form the first electrode and the conductive bump located on the first electrode.

[0024] In an embodiment of the present disclosure, the method further includes forming an adhesive layer to cover the conductive bump and a portion located between the conductive bump of the first electrode, placing an electronic device on the adhesive layer, applying a force to the electronic device to penetrate the conductive bump through the adhesive layer and contact the electronic device, thereby joining the electronic device and the first electrode through the adhesive layer, and curing the adhesive layer.

[0025] Adapted and further aspects and scopes will become apparent from the description provided herein. The various aspects of the present disclosure may be implemented alone or in combination with one or more other aspects. Further, the description and specific examples herein are for illustrative purposes only and are not intended to limit the scope of the present invention.

Brief Description of the Drawings

[0026] The drawings described herein are used only for illustrative purposes of selected embodiments and are not intended to limit the scope of the present disclosure, not all possible embodiments. [Figure 1A] It is a schematic cross-sectional view of a display substrate according to an embodiment of the present disclosure. [Figure 1B] It is a schematic diagram showing the shape of a conductive bump according to an embodiment of the present disclosure. [Figure 1C] It is a schematic diagram showing the shape of a conductive bump according to an embodiment of the present disclosure. [Figure 1D] It is a schematic diagram showing the shape of a conductive bump according to an embodiment of the present disclosure. [Figure 1E]1A and 1B are schematic diagrams illustrating the shape of a conductive bump according to an embodiment of the present disclosure. [Figure 1F] 1A and 1B are schematic diagrams illustrating the shape of a conductive bump according to an embodiment of the present disclosure. [Figure 2] FIG. 10 is a schematic cross-sectional view of a display substrate according to another embodiment of the present disclosure. [Figure 3] FIG. 10 is a schematic cross-sectional view of a display substrate according to yet another embodiment of the present disclosure. [Figure 4] FIG. 10 is a schematic cross-sectional view of a display substrate according to yet another embodiment of the present disclosure. [Figure 5] FIG. 10 is a schematic cross-sectional view of a display substrate according to yet another embodiment of the present disclosure. [Figure 6] FIG. 2 is a perspective view of a display substrate according to an embodiment of the present disclosure. [Figure 7A] FIG. 10 is a schematic cross-sectional view of a display substrate according to yet another embodiment of the present disclosure. [Figure 7B] FIG. 10 is a schematic cross-sectional view of a display substrate according to yet another embodiment of the present disclosure. [Figure 7C] FIG. 10 is a schematic cross-sectional view of a display substrate according to yet another embodiment of the present disclosure. [Figure 8] FIG. 10 is a schematic cross-sectional view of a display substrate according to yet another embodiment of the present disclosure. [Figure 9] 1 is a flowchart illustrating a method for manufacturing a display substrate according to an embodiment of the present disclosure. [Figure 10] 1A to 1C are schematic diagrams illustrating a method for manufacturing a conductive bump according to an embodiment of the present disclosure. [Figure 11] 1A to 1C are schematic diagrams illustrating a method for manufacturing a conductive bump according to an embodiment of the present disclosure. [Figure 12] 1A to 1C are schematic diagrams illustrating a method for manufacturing a conductive bump according to an embodiment of the present disclosure. [Figure 13] 1A to 1C are schematic diagrams illustrating a method for manufacturing a conductive bump according to an embodiment of the present disclosure. [Figure 14] 1A to 1C are schematic diagrams illustrating a method for manufacturing a conductive bump according to an embodiment of the present disclosure. [Figure 15] 1A to 1C are schematic diagrams illustrating a method for manufacturing a conductive bump according to an embodiment of the present disclosure. [Figure 16]1A to 1C are schematic diagrams illustrating a method for manufacturing a conductive bump according to an embodiment of the present disclosure. [Figure 17] 1A to 1C are schematic diagrams illustrating a method for manufacturing a conductive bump according to an embodiment of the present disclosure. [Figure 18] 5A to 5C are schematic diagrams illustrating a method for manufacturing a conductive bump according to another embodiment of the present disclosure. [Figure 19] 5A to 5C are schematic diagrams illustrating a method for manufacturing a conductive bump according to another embodiment of the present disclosure. [Figure 20] 5A to 5C are schematic diagrams illustrating a method for manufacturing a conductive bump according to another embodiment of the present disclosure. [Figure 21] 5A to 5C are schematic diagrams illustrating a method for manufacturing a conductive bump according to another embodiment of the present disclosure. [Figure 22] 1A and 1B are schematic diagrams illustrating a method for manufacturing a conductive bump according to another embodiment of the present disclosure.In the various schematic views of these drawings, corresponding reference numerals indicate corresponding parts or features. DETAILED DESCRIPTION OF THE INVENTION

[0027] First, unless the context clearly indicates otherwise, the singular forms of terms used in this specification and the appended claims include the plural, and vice versa. Thus, when referring to the singular, the plural of the corresponding term is generally included. Similarly, the words "comprises" and "includes" should be interpreted as inclusive, not exclusive. Similarly, the terms "comprises" and "or" should be interpreted as inclusive, unless the context dictates otherwise. When the term "exemplary" is used herein, particularly when following a series of terms, said "exemplary" is merely exemplary and descriptive and should not be considered exclusive or broad.

[0028] Additionally, when introducing elements of the present disclosure and embodiments thereof, the articles "a," "an," "the," and "said" are intended to mean that there are one or more elements. Unless otherwise specified, "plurality" means two or more than two. The terms "including," "including," "comprising," and "having" are intended to be inclusive and mean that there may be additional elements other than the listed elements. The terms "first," "second," "third," etc. are for descriptive purposes only and should not be understood to denote or imply relative importance or order of formation.

[0029] Also, in the drawings, the thickness and area of ​​each layer are exaggerated for clarity. When a layer, region, or component is referred to as being "on" another part, it should be understood that it may be directly on top of the other part, or there may be other components interposed therebetween. Conversely, when a component is referred to as being "directly" on another component, it means that there are no other components interposed therebetween.

[0030] The flowcharts described in this disclosure are merely examples. There may be many variations of the flowcharts or the steps described therein without departing from the spirit of the disclosure. For example, steps may be performed in a different order, or may be added, deleted, or modified. All of these variations are considered to be part of the aspects described in the claims.

[0031] Exemplary embodiments will now be described in more detail with reference to the drawings.

[0032] Currently, micro LED technology faces considerable technical challenges. Micro LED transfer and bonding is one of the key technologies in micro LED technology.

[0033] Conventionally, there are four methods for bonding micro LEDs. The first method uses solder paste, but the solder paste must be heated during bonding, which degrades the performance of the micro LED. The second method uses anisotropic conductive paste, but the cost of anisotropic conductive paste is high. The third method is die-bonding, but if pressure is applied to the display substrate during die-bonding, it can adversely affect the characteristics of electronic devices such as thin-film transistors on the display substrate. The fourth method involves transferring metal to metal, but the adhesive between the metals is difficult to remove, reducing the contact area between the metals.

[0034] An embodiment of the present disclosure provides a display substrate including conductive bumps, which are arranged to facilitate connection with micro LEDs, thereby reducing manufacturing costs and improving the transfer efficiency of micro LEDs.

[0035] 1A is a schematic cross-sectional view of a display substrate 100 according to an embodiment of the present disclosure. As shown in FIG. 1A, the display substrate 100 includes a substrate 1, a first electrode 2 disposed on the substrate 1, and a conductive bump 3 disposed on the first electrode 2.

[0036] 1A, in an exemplary embodiment of the present disclosure, the size of a cross section S1 of a conductive bump 3 in a plane parallel to a substrate 1 has a negative correlation with a distance D1 from the cross section S1 to the surface of the first electrode 2. Here, the negative correlation means that the larger the distance D1, the smaller the size of the cross section S1. Note that the size of the cross section S1 here refers to, for example, the area of ​​the cross section S1, and the surface of the first electrode 2 refers to the surface of the first electrode 2 that contacts the conductive bump 3. Furthermore, in an exemplary embodiment of the present disclosure, the number of conductive bumps may be one or more, and the present disclosure is not particularly limited thereto.

[0037] In FIG. 1A and other drawings described below, the proportional relationship between the dimensions of each part should not be considered as limiting the present disclosure. To clearly illustrate the structure of a part, the dimensions of the part may be drawn larger than the dimensions of other parts. The drawings of the present disclosure are merely illustrative and should not be considered as limiting the present disclosure.

[0038] In an exemplary embodiment of the present disclosure, the ratio of the area occupied by the orthogonal projection of the conductive bump 3 on the surface of the first electrode 2 to the surface area of ​​the first electrode 2 may be, for example, greater than 20%.

[0039] In an exemplary embodiment of the present disclosure, as shown in FIG. 1A, the ratio of the minimum dimension L1 of the surface of the conductive bump 3 facing the substrate 1 in a direction parallel to the substrate 1 to the distance D2 from the top of the conductive bump 3 to the first electrode 2 can be within a range of 1:1 to 1:3.

[0040] In an exemplary embodiment of the present disclosure, the shape of the conductive bump 3 is selected from at least one of a pyramid, a truncated pyramid, and a prism. and as shown in Figure 6 The shape of the conductive bump may include a prism.

[0041] 1B to 1F are schematic diagrams of the shapes of conductive bumps according to embodiments of the present disclosure. The shape of the conductive bump 3 in FIGS. 1B to 1F may be irregular. For example, in FIG. 1B, the shape of the conductive bump 3 may be a cone with one side edge arcuate. For example, in FIGS. 1C to 1F, the conductive bump 3 may have multiple pointed portions.

[0042] The structure of the conductive bump 3 according to the embodiment of the present disclosure will be specifically described below.

[0043] On the other hand, in the embodiment of the present disclosure, the conductive bump 3 includes a first portion and a second portion covering the first portion.

[0044] 2 is a schematic cross-sectional view of a display substrate according to an embodiment of the present disclosure. In an exemplary embodiment of the present disclosure, as shown in FIG. 2, the conductive bump 3 may include a first portion 31 and a second portion 32 covering the first portion 31. For example, the orthogonal projection of the first portion 31 onto the substrate 1 may be located within the orthogonal projection of the first electrode 2 onto the substrate 1. The second portion 32 may be in contact with the first electrode 2. A surface 311 of the first portion 31 away from the substrate 1 and a surface 321 of the second portion 32 away from the substrate 1 may be conformal, i.e., the shape of the surface of the first portion 31 away from the substrate 1 and the shape of the surface of the second portion 32 away from the substrate 1 are similar in shape.

[0045] In an exemplary embodiment of the present disclosure, the first portion 31 of the conductive bump 3 may be made of a dielectric material. In an exemplary embodiment of the present disclosure, the second portion 32 of the conductive bump 3 may be made of a conductive material.

[0046] For example, the dielectric material may include an organic material. Further, for example, the organic material may include an organic resin material. Examples of the organic resin material include polyimide resin and acrylic resin.

[0047] By way of example, the conductive material may include aluminum, copper, molybdenum, titanium, tungsten, and the like.

[0048] In the exemplary embodiment of the present disclosure, the material of the second portion 32 of the conductive bump 3 may be the same as or different from the material of the first electrode 2. Those skilled in the art can select the material according to their needs or in consideration of the manufacturing process, etc., and the present disclosure is not particularly limited thereto.

[0049] 3 is a schematic cross-sectional view of a display substrate according to an embodiment of the present disclosure. Also, as another embodiment of the present invention, as shown in FIG. 3, the conductive bump 3 may further include an inorganic material layer 33 located between the first portion 31 and the second portion 32 and covering the first portion 31. The inorganic material layer 33 can protect the underlying dielectric material (i.e., the first portion 31) when manufacturing the second portion 32 of the conductive bump 3. For example, when the second portion 32 is formed by sputtering, sputtered ions (e.g., metal ions) continuously collide with the surface of the first portion 31, generating a large amount of heat, which can cause the first portion 31 to melt. 1 portion 31 This can cause deformation, such as collapse, in dielectric materials such as organic materials.

[0050] In the exemplary embodiment of the present disclosure, the material of the inorganic material layer 33 may include, for example, silicon nitride (SiNx) or silicon oxide (SiOx).

[0051] 4 is a schematic cross-sectional view of a display substrate according to an embodiment of the present disclosure. Furthermore, in another embodiment of the present disclosure, the second portion 32 of the conductive bump 3 can cover the surface of the first electrode 2 exposed between two adjacent first portions 31, as shown in the dotted circle in FIG. 4, thereby making the electrical connection between the conductive bump 3 and the first electrode 2 more effective and further reducing the contact resistance.

[0052] On the other hand, in the embodiments of the present disclosure, the conductive bump 3 may consist of only conductive material.

[0053] In the embodiments of the present disclosure, the first electrode 2 and the conductive bump 3 may be integrally formed. That is, the first electrode 2 and the conductive bump 3 may be made of the same material and may be formed in the same process.

[0054] 5 is a schematic cross-sectional view of a display substrate according to an embodiment of the present disclosure. As shown in FIG. 5, the ratio of the thickness T1 of the first electrode 2 to the distance D3 from the top of the conductive bump 3 to the bottom of the first electrode 2 can be in the range of 1:4 to 1:2. As an example, the thickness T1 can be 0.5 μm. As an example, the distance D3 can be 1 to 2 μm.

[0055] As in the previous embodiment, in this embodiment, the conductive material may include, for example, aluminum, copper, molybdenum, titanium, or tungsten.

[0056] 6 is a perspective view of a display substrate 100 according to an embodiment of the present disclosure. In an exemplary embodiment of the present disclosure, as shown in FIG. 6, a plurality of conductive bumps 3 arranged in an array are disposed on each of the first electrodes 2. Note that the number of conductive bumps 3 shown in FIG. 6 is merely an example and should not be considered as a limitation of the present disclosure.

[0057] As shown in FIG. 6, in another embodiment, the conductive bump 3 may be a triangular prism. In this embodiment, the triangular prism 3 may include a first surface S2 parallel to the surface of the substrate 1. The first surface S2 may include a first side L2 and a second side L3 intersecting the first side L2. As an example, the distance D4 between two adjacent conductive bumps 3 (i.e., triangular prisms 3) in the extension direction of the first side L2 (i.e., the X direction) may be within a range of 2 to 10 μm. As an example, the distance D5 between two adjacent conductive bumps 3 (i.e., the triangular prisms 3) in the extension direction of the second side L3 (i.e., the Y direction) may be within a range of 2 to 5 μm. As an example, the dimension of the first side L2 may be 2 to 10 μm, the dimension of the second side L3 may be 1 to 5 μm, and the height H1 of the triangular prism 3 in the direction perpendicular to the substrate 1 may be within a range of 1 to 5 μm.

[0058] As another example, the triangular prism 3 may include a regular triangular prism as shown in FIG.

[0059] 7A is a schematic cross-sectional view of a display substrate according to an embodiment of the present disclosure. Also, as shown in FIG. 7A, the display substrate 100 may further include an electronic device 4 disposed on the conductive bumps 3 and an adhesive 5 disposed between the conductive bumps 3.

[0060] In an exemplary embodiment of the present disclosure, pins 41, 42 of an electronic device 4 may be in contact with conductive bumps 3. An adhesive 5 bonds the pins 41, 42 to the first electrode 2. Note that the distances D4, D5 between the conductive bumps 3 in FIG. 6 are arranged so that when the pins 41, 42 and the first electrode 2 are bonded with the adhesive 5, the adhesive 5 can be more effectively discharged from the bonded portion, thereby realizing good electrical contact between the pins 41, 42 and the first electrode 2.

[0061] The contact state between the conductive bump 3 and the pins 41 and 42 shown in FIG. 7A is merely an example (hereinafter, FIG. 8 of The structure is also illustrative, but the present disclosure is not particularly limited thereto. In actual use, as shown in FIG. 7B, the tops of the conductive bumps 3 can be allowed to deform so as to fit the shapes of the pins 41 and 42.

[0062] Furthermore, if the hardness of the material of the conductive bump 3 is greater than that of the material of the pins 41 and 42, the top of the conductive bump 3 can be pierced by the pins 41 and 42, as shown in FIG. 7C, thereby achieving more effective electrical and mechanical connections.

[0063] In an exemplary embodiment of the present disclosure, the electronic device 4 may include a micro LED.

[0064] Materials for the adhesive 5 may include, for example, a silicone-based adhesive, a resin-based adhesive, a photo-curable adhesive, etc. As an example, the photo-curable adhesive may include an acrylate-based prepolymer (also referred to as an oligomer), a reactive monomer, an ultraviolet photoinitiator, etc. FIG. 8 is a schematic cross-sectional view of a display substrate according to an embodiment of the present disclosure. As shown in FIG. 8, the display substrate 100 may further include a thin film transistor 6 located on the substrate 1 and a first dielectric layer 7 located on the thin film transistor 6. In this embodiment, the first electrode 2 is located on the first dielectric layer 7 and is electrically connected to the thin film transistor 6. In an exemplary embodiment of the present disclosure, as shown in FIG. 8, the thin film transistor 6 The thin film transistor shown in FIG. 8 may include a buffer layer 61 located on the substrate 1, an active layer 62 located on the buffer layer 61, an insulating layer 63 covering the buffer layer 61 and the active layer 62, and a gate electrode layer 64 located on the insulating layer 63. 6 is a top-gate thin-film transistor, 6 The thin film transistor shown in FIG. 8 may be a bottom-gate thin film transistor. Those skilled in the art can select the type of thin film transistor as needed. 6 is merely an example and is not intended to limit the present disclosure.

[0065] 8, the first dielectric layer 7 may include a first sub-dielectric layer 71 and a second sub-dielectric layer 72 stacked in sequence. The first sub-dielectric layer 71 may cover the insulating layer 63 and the gate electrode layer 64. For example, the first sub-dielectric layer 71 may be an interlayer insulating layer. For example, the second sub-dielectric layer 72 may be a passivation layer or a planarization layer.

[0066] 8 , the display substrate 100 may further include a second electrode 81 and a third electrode 82 disposed between the first dielectric sub-layer 71 and the second dielectric sub-layer 72. In an exemplary embodiment of the present disclosure, the second electrode 81 may be connected to the source / drain region of the thin film transistor 6 through a first hole 711 in the first dielectric sub-layer 71.

[0067] In an exemplary embodiment of the present disclosure, the second electrode 81 may be disposed in the same layer as the third electrode 82. That is, the second electrode 81 and the third electrode 82 may be made of the same material and may be formed in the same process. As an example, the second electrode 81 may be a thin film transistor (TFT). 6 For example, the third electrode 82 may be a wiring within the display substrate 100.

[0068] 8 , the first electrode 2 may include a first sub-electrode 21 and a second sub-electrode 22. The first sub-electrode 21 may be connected to the second electrode 81 through a second hole 721 in the second sub-dielectric layer 72. The second sub-electrode 22 may be connected to the third electrode 82 through a third hole 722 in the second sub-dielectric layer 72. As an example, the first electrode 2 may be a bonding pad for bonding the electronic device 4.

[0069] In an embodiment of the present invention, for example, after bonding the electronic device 4 to the first electrode 2, a thin film transistor 6 For example, if the electronic device 4 includes a micro LED, a thin film transistor (TFT) may be used to control the electronic device 4. 6 The light emission of the micro LED can be controlled by the first electrode 2 and the conductive bump 3.

[0070] The embodiments of the present disclosure further provide a method for manufacturing a display substrate, and the display substrate manufactured by the embodiments of the present disclosure has conductive bumps arranged to easily connect with micro LEDs, thereby reducing manufacturing costs and improving the bonding yield of micro LEDs.

[0071] 9 is a flowchart showing a method for manufacturing a display substrate according to an embodiment of the present disclosure. As shown in FIG. 9, the method for manufacturing a display substrate may include steps S901 to S903. As shown in FIGS. 1A and 9, in step S901, a substrate 1 is provided. In step S902, a first electrode 2 is formed on the substrate 1. In step S903, a conductive bump 3 is formed on the first electrode 2.

[0072] 1A , in an exemplary embodiment of the present disclosure, as shown in FIG. 1A , the size of the cross section S1 of the conductive bump 3 in a plane parallel to the substrate 1 has a negative correlation with the distance D1 from the cross section S1 to the surface of the first electrode 2. Here, the negative correlation means that the larger the distance D1, the smaller the size of the cross section S1. Note that the size of the cross section S1 here refers to, for example, the area of ​​the cross section S1, and the surface of the first electrode 2 refers to the surface of the first electrode 2 that contacts the conductive bump 3. Furthermore, in one embodiment of the present disclosure, the number of conductive bumps may be one or more, and the present disclosure is not particularly limited thereto.

[0073] For some explanations regarding the conductive bumps 3, please refer to the explanations regarding FIGS. 1A to 1F, and the explanations will be omitted here.

[0074] A method for forming the conductive bumps 3 will now be described in detail.

[0075] 10 to 17, a process for forming the conductive bump 3 according to the embodiment of the present disclosure will be described. The formed conductive bump 3 has a structure as shown in FIG.

[0076] 10 is a flowchart illustrating a method for forming a conductive bump according to an embodiment of the present disclosure. As shown in FIG. 10 and FIG. 11, in step S9031, a dielectric material layer 3′ is formed on the substrate 1 and the first electrode 2.

[0077] Returning to Figure 10, in step S9032, the layer of dielectric material is patterned to form a first portion of a conductive bump.

[0078] In an exemplary embodiment of the present disclosure, the material of the dielectric material layer may include a photosensitive material, for example, an organic photosensitive material.

[0079] For examples of materials for the dielectric material layer, reference can be made to the above description regarding FIG. 2, and the description thereof will be omitted here.

[0080] Specifically, when the material of the dielectric material layer includes a photosensitive material, as shown in FIG. 12, the process of patterning the dielectric material layer 3′ may include a step of exposing and developing the dielectric material layer 3′ using a first mask M1 to form a first portion 31 of the conductive bump 3 (shown in the dashed line portion in FIG. 12).

[0081] In an exemplary embodiment of the present disclosure, the dose of light L exposing the dielectric material layer 3', the dimension D6 of the light-shielding portion M1-1 in a direction perpendicular to the direction in which the light-shielding portion M1-1 of the first mask M1 extends, and the distance D7 from the first mask M1 to the dielectric material layer 3' are arranged so that diffracted light LD is generated at the edge of the light-shielding portion M1-1 during exposure.

[0082] In the exemplary embodiment of the present disclosure, at least a portion of the diffracted light LD can reach the surface of the dielectric material layer 3′ located below the central portion C of the light-shielding portion M1-1. The intensity of the diffracted light LD incident on the corresponding portion of the dielectric material located directly below the central portion C decreases as the distance to the corresponding portion decreases, so that an unexposed portion having a convex shape of the corresponding portion of the dielectric material shown by the dashed line in FIG. 12 is formed, and the unexposed portion forms the first portion 31 of the conductive bump 3.

[0083] Returning to FIG. 12, in the exemplary embodiment of the present disclosure, the dimension D6 of the light-shielding portion M1-1 of the first mask M1 and the dimension D7 of the non-light-shielding portion M1- 2 The ratio of the dimension D to the dimension D8 can be in the range of 1:1 to 3:2.

[0084] In addition, in a conventional exposure process, the distance between the mask and the structure to be exposed is generally constant. In an exemplary embodiment of the present disclosure, when the distance D7 from the first mask M1 to the dielectric material layer 3' is large, the dose of the light L can be increased. On the other hand, when the distance D7 from the first mask M1 to the dielectric material layer 3' is small (even more in contact), the dose of the light L can be decreased. Those skilled in the art can select this according to the actual manufacturing process, and the present disclosure is not particularly limited thereto.

[0085] In another embodiment of the present disclosure, patterning the dielectric material layer 3′ may include imprinting the dielectric material layer 3′ to obtain the first portions 31 of the conductive bumps 3. In this embodiment, the surface of the imprint head that performs the imprinting may have recessed structures corresponding to the protruding portions.

[0086] The structure finally obtained by the above method is shown in Fig. 13. Then, returning to Fig. 10, in step S9033, First conductive material layer 3'' Form.

[0087] Specifically, in the exemplary embodiment of the present disclosure, as shown in FIG. 14, a first conductive material layer 3'' is formed on the surfaces of the substrate 1, the first electrode 2, and the first portion 31 of the conductive bump.

[0088] In the embodiment of the present disclosure, the method for forming the first conductive material layer 3'' may include, for example, a sputtering method.

[0089] Returning to FIG. 10, in step S9034, a second portion of the conductive bump is formed.

[0090] Specifically, in an embodiment of the present disclosure, the first conductive material layer 3'' is patterned to form the second portion 32 of the conductive bump 3, as shown in Figures 14 and 15. The resulting structure is shown in Figure 15.

[0091] As an example, the patterning can be performed using a photolithography method conventionally used in the art, and the present disclosure is not particularly limited thereto.

[0092] For examples of materials for the first conductive material layer, the description of FIG. 2 above can be referred to, and the description thereof will be omitted here.

[0093] In an exemplary embodiment of the present disclosure, the conductive bump 3 may include a first portion 31 and a second portion 32 covering the first portion 31, as shown in FIG. 15 . The orthogonal projection of the first portion 31 onto the substrate 1 may be located within the orthogonal projection of the first electrode 2 onto the substrate 1. The second portion 32 may be in contact with the first electrode 2. A surface 311 of the first portion 31 facing away from the substrate 1 and a surface 321 of the second portion 32 facing away from the substrate 1 may be conformal. In another embodiment of the present disclosure, as shown within the dotted circle in FIG. 16 , the second portion 32 of the conductive bump 3 may be located on a surface of the first electrode 2 that is not covered by the first portion 31, thereby enabling a more effective electrical connection between the conductive bump 3 and the first electrode 2.

[0094] In another embodiment of the present disclosure, step S9035 may be included between step S9032 and step S9033 as shown in FIG. 10 . That is, before forming the first conductive material layer 3″, the surface of the first portion 31 of the conductive bump 3 may be roughened as shown in FIG. 13 . For example, the roughening may include microetching. This can improve the adhesion between the first conductive material layers 3″ in the first portion 31 of the conductive bump 3 during the formation of the first conductive material layer 3″.

[0095] In another embodiment of the present disclosure, the process of forming the first conductive material layer 3'' by sputtering may cause the collapse of the top of the first portion 31 of the conductive bump, and to solve this problem, at least one of the following two methods can be adopted.

[0096] The first method is to reduce the deposition power of the first conductive material layer, i.e., deposit it multiple times, but deposit a smaller amount of conductive material each time, which can improve the collapse problem.

[0097] The second method includes forming a first portion of the conductive bump and then forming a first conductive material layer on the conductive bump. The first part of 10, a step S9036 for forming the inorganic material layer may be included between step S9032 and step S9033.

[0098] That is, in an exemplary embodiment of the present disclosure, as shown in FIG. 17 , after forming the first portion 31, an inorganic material layer 33 may be formed on the surface of the first portion 31 before forming the first conductive material layer 3″. Alternatively, after roughening the surface of the first portion 31, the inorganic material layer 33 may be formed on the surface of the first portion 31 before forming the first conductive material layer 3″. This is advantageous for effective adhesion of the inorganic material layer 33 and the first conductive material layer 3″ to the first portion 31.

[0099] In an exemplary embodiment of the present disclosure, the inorganic material layer 33 and the surface of the first portion 31 facing away from the substrate 1 are conformal.

[0100] In the exemplary embodiment of the present disclosure, the material of the inorganic material layer 33 may include, for example, silicon nitride (SiNx) or silicon oxide (SiOx).

[0101] The inorganic material layer 33 can be manufactured by a conventional process such as a CVD method, as long as it does not cause undesirable deformation such as collapse of the first portion 31.

[0102] 18 to 22, a process for forming the conductive bump 3 according to the embodiment of the present disclosure will be described. The formed conductive bump 3 has a structure as shown in FIG.

[0103] 18 is a flowchart of a method for manufacturing a conductive bump according to an embodiment of the present disclosure. As shown in FIG. 18, the method for manufacturing a conductive bump includes steps S9031' and S9032'.

[0104] 18 and 19, in step S9031', a second conductive material layer 3''' is formed on the substrate 1. The second conductive material layer 3''' can be formed by, for example, sputtering.

[0105] As shown in FIG. 18 and FIG. 5, in step S9032′, the second conductive material layer 3′″ is patterned to form the first electrode 2 and the conductive bump 3 located on the first electrode 2.

[0106] As an example, the patterning can be performed using conventional photolithography methods, although the present disclosure is not particularly limited thereto.

[0107] In an exemplary embodiment of the present disclosure, the ratio of the thickness T1 of the first electrode 2 to the distance D3 from the top of the conductive bump 3 to the bottom of the first electrode 2 may be in the range of 1:4 to 1:2. As an example, the thickness T1 may be 0.5 μm. As an example, the distance D3 may be 1 to 2 μm.

[0108] As in the previous embodiment, in this embodiment, the conductive material may include, for example, aluminum, copper, molybdenum, titanium, or tungsten.

[0109] For other detailed descriptions of the conductive bumps, please refer to the descriptions of the structural embodiments above, and the description thereof will be omitted here.

[0110] In addition, in the exemplary embodiment of the present disclosure, the method for manufacturing a display substrate may further include steps S904 to S906, as shown in the steps enclosed by the dotted line in the flowchart of FIG.

[0111] 20 and 21, in step S904, an adhesive layer is applied. Specifically, the adhesive layer 5 is applied above and between the conductive bumps 3 so as to cover the tops of the conductive bumps. In an exemplary embodiment of the present disclosure, the top surface of the adhesive layer 5 is approximately 1 μm higher than the tops of the conductive bumps 3. In step S905, as shown in FIG. 21, the electronic device 4 is bonded to the adhesive layer 5, resulting in the structure shown in FIG. 7A. Specifically, the electronic device 4 is placed on the adhesive layer 5, and a force F is applied to the electronic device 4, causing the conductive bumps 3 to penetrate the adhesive layer 5 and contact the electronic device 4, thereby bonding the electronic device 4 and the first electrode 2 via the adhesive layer 5.

[0112] More specifically, in an exemplary embodiment of the present disclosure, when the pins 41, 42 of the electronic device 4 are bonded to the first electrode 2 via the adhesive layer 5, a mass transfer technique is used to simultaneously transfer a plurality of electronic devices 4 onto the adhesive layer 5 (e.g., a resin material). The pins 41, 42 of the electronic device 4 contact the conductive bumps 3. At this time, the pins 41, 42 of the electronic device 4 penetrate into the resin material.

[0113] The mass transfer technique is a technique for simultaneously transferring a large number of electronic devices to the structure shown in FIG. 1A and FIGS. 2 to 5 (hereinafter referred to as the intermediate structure) using vacuum, electrostatic, adhesive, or the like. During the above process, the surface of the intermediate structure having the conductive bumps 3 faces upward to facilitate bonding with the electronic devices 4. In an exemplary embodiment of the present disclosure, after an adhesive layer 5 (e.g., a resin material) is applied to the intermediate structure, when the electronic devices 4 are transferred and bonded to the intermediate structure, the resin material may overflow. Specifically, for example, when transferring the electronic devices 4 onto the intermediate structure, the electronic devices 4 must be pressed into the resin material with a certain pressure so that the pins 41 and 42 of the electronic devices 4 contact the tops of the conductive bumps. The entry of the electronic devices 4 causes the resin material to overflow.

[0114] 7A is merely an example of the contact state between the conductive bump 3 and the pins 41 and 42, and the present disclosure is not particularly limited thereto. In actual use, as shown in FIG. 7B, the top of the conductive bump 3 can be allowed to deform so as to fit the shape of the pins 41 and 42.

[0115] Furthermore, if the hardness of the material of the conductive bump 3 is greater than that of the material of the pins 41 and 42, the top of the conductive bump 3 can be pierced by the pins 41 and 42, as shown in FIG. 7C, thereby achieving more effective electrical and mechanical connections.

[0116] In step S906, the adhesive layer 5 is cured. As an example, the material of the adhesive layer 5 may contain a resin. The resin may contain, for example, a solvent. In exemplary embodiments of the present disclosure, curing can be achieved using a conventional thermal curing process. For example, the resin material is heated to cure the resin material. Since the resin material contains solvents, the solvents evaporate upon heating, thereby curing the resin material. For example, the heating temperature can be approximately 140°C.

[0117] As the resin material hardens, the surface tension of the resin material presses down on the electronic device 4. The pressing force from the electronic device 4 causes the tops of the conductive bumps 3 to break through the resin material that surrounds them, thereby establishing electrical connection between the electronic device 4 and the first electrodes 2. For example, if the hardness of the material of the pins 41 and 42 of the electronic device 4 is lower than the hardness of the material of the conductive bumps 3, the tension causes the tops of the conductive bumps 3 to eventually penetrate the pins 41 and 42, further ensuring electrical connection between the electronic device 4 and the first electrodes 2. The robustness of the electrical connection is also ensured even after the resin material hardens.

[0118] Furthermore, as another embodiment of the present disclosure, as shown in the flowchart of FIG. 22, after forming the substrate and before forming the first electrode, the method for manufacturing a display substrate may further include steps S2301 to S2307.

[0119] 22 and 8, in step S2301, a thin film transistor 6 is formed on the first substrate 1.

[0120] More specifically, the steps of forming the thin film transistor 6 may include the steps of forming a buffer layer 61 on the substrate 1, forming an active layer material layer on the buffer layer 61, patterning the active layer material layer to form an active layer 62, forming an insulating layer 63 on the buffer layer 61 and the active layer 62, forming a gate electrode material layer on the insulating layer 63, and patterning the gate electrode material layer to form a gate electrode layer 64.

[0121] Next, in step S2302, a first sub-dielectric layer is formed. Specifically, a first sub-dielectric layer 71 is formed on the insulating layer 63 and the gate electrode layer 64. As an example, the first sub-dielectric layer 71 may be an interlayer insulating layer.

[0122] In step S2303, a first hole is formed in the first sub-dielectric layer 71. Specifically, through processes such as exposure, development, and etching, a first hole 711 is formed in the first sub-dielectric layer 71, exposing the source / drain region of the thin film transistor 6 (i.e., exposing the active layer 62).

[0123] In step S2304, a third conductive material layer is formed. Specifically, the third conductive material layer is formed on the first sub-dielectric layer 71.

[0124] In step S2305, the second electrode and the third electrode are formed. Specifically, the second electrode 81 and the third electrode 82 are formed by patterning the third conductive material layer.

[0125] In the exemplary embodiment of the present disclosure, the second electrode 81 is, for example, a thin film transistor 6 The second electrode 81 may be connected to the active layer 62 of the thin film transistor 6 through the first hole 711. As an example, the third electrode 82 may be a wiring within the display substrate 100.

[0126] Next, in step S2306, a second dielectric sub-layer is formed. Specifically, the second dielectric sub-layer 72 is formed on the first dielectric sub-layer 71, the second electrode 81, and the third electrode 82. For example, the second dielectric sub-layer 72 may be a passivation layer or a planarization layer.

[0127] In step S2307, a second hole and a third hole are formed in the second dielectric sublayer 72. Specifically, the second dielectric sublayer 72 is patterned to form a second hole 721 and a third hole 722 in the second dielectric sublayer 72. In this embodiment, the second hole 721 exposes the second electrode 81, and the third hole 722 exposes the second electrode 81. 722 exposes the third electrode 82.

[0128] In addition, in an exemplary embodiment of the present disclosure, As shown in Figure 8, The first electrode 2 may include a first sub-electrode 21 and a second sub-electrode 22. The first sub-electrode 21 is connected to the second electrode 81 through a second hole 721 in the second sub-dielectric layer 72. The second sub-electrode 22 is connected to the third electrode 82 through a third hole 722 in the second sub-dielectric layer 72. As an example, the first electrode 2 may be a bonding pad for bonding the electronic device 4.

[0129] In the embodiment of the present disclosure, for example, the electronic device 4 may be bonded to the first electrode 2 and then formed into a thin film transistor (TFT). 6 By way of example, if the electronic device 4 includes a micro LED, a thin film transistor (TFT) 6 can control the light emission of the micro LED through the first electrode 2 and the conductive bump 3.

[0130] Those skilled in the art will be able to use conventional processes such as exposure, development, and etching for the specific steps used in patterning, and therefore, the description thereof will be omitted here.

[0131] The foregoing description of the embodiments has been provided for purposes of illustration and description. It is not intended to be exhaustive or to limit the present disclosure. Various elements or features of particular embodiments are generally not limited to particular embodiments, but where appropriate, these elements and features may be interchangeable and used in selected embodiments even if not specifically shown or described. Likewise, the embodiments may be modified in many ways. Such modifications are not considered a departure from the present application, and all such modifications are within the scope of the present application.

Claims

1. A substrate; a first electrode located on the substrate; a conductive bump located on the first electrode; a micro LED disposed on the conductive bump, wherein a pin of the micro LED contacts the conductive bump; an adhesive disposed between the conductive bumps, the adhesive bonding the pin and the first electrode; a thin film transistor located on the substrate; a first dielectric layer located over the thin film transistor; the first electrode is located on the first dielectric layer and electrically connected to the thin film transistor; a size of a cross section of the conductive bump in a plane parallel to the substrate has a negative correlation with a distance from the cross section to a surface of the first electrode; the conductive bump includes a first portion and a second portion covering the first portion, the second portion contacting the first electrode, and a surface of the second portion facing away from the substrate and a surface of the first portion facing away from the substrate are conformal; the first portion is made of a dielectric material and the second portion is made of a conductive material; the number of the conductive bumps electrically connected to one of the first electrodes is plural, the conductive bumps further include a connection portion provided in the same layer as the second portion, the connection portion covers a portion of the surface of the first electrode located between the first portions corresponding to two adjacent conductive bumps, and the connection portion is provided in contact with the second portions corresponding to the two adjacent conductive bumps and the first electrode; Display board.

2. A substrate, a first electrode located on the substrate; a conductive bump located on the first electrode; a micro LED disposed on the conductive bump, wherein a pin of the micro LED contacts the conductive bump; an adhesive disposed between the conductive bumps, the adhesive including an adhesive that bonds the pin and the first electrode; a size of a cross section of the conductive bump in a plane parallel to the substrate has a negative correlation with a distance from the cross section to a surface of the first electrode; the conductive bump includes a first portion and a second portion covering the first portion, the second portion contacting the first electrode, and a surface of the second portion facing away from the substrate and a surface of the first portion facing away from the substrate are conformal; the first portion is made of a dielectric material and the second portion is made of a conductive material; the number of the conductive bumps electrically connected to one of the first electrodes is plural, the conductive bumps further include a connection portion provided in the same layer as the second portion, the connection portion covers a portion of the surface of the first electrode located between the first portions corresponding to two adjacent conductive bumps, and the connection portion is provided in contact with the second portions corresponding to the two adjacent conductive bumps and the first electrode; the conductive bump includes a triangular prism; The triangular prism includes two triangular bases and three side surfaces adjacent to the bases, One of the three sides is parallel to the surface of the substrate. The side surface includes a second side common to the adjacent bottom surface and a first side intersecting the second side, The dimension of the second side is 1 to 5 μm, The height of the triangular prism in a direction perpendicular to the substrate is 1 to 5 μm. Display board.

3. 2. The display substrate of claim 1, wherein the ratio of the minimum dimension of the surface of the conductive bump facing one side of the substrate in a direction parallel to the substrate to the distance from the top of the conductive bump to the first electrode is in the range of 1:1 to 1:

3.

4. The display substrate of claim 1 , wherein the conductive bumps have a shape selected from at least one of a pyramid, a truncated pyramid, and a prism.

5. The display substrate of claim 1 , wherein an orthogonal projection of the first portion onto the substrate is located within an orthogonal projection of the first electrode onto the substrate.

6. The display substrate of claim 1 , wherein the dielectric material comprises an organic material.

7. 7. The display substrate according to claim 6, wherein the dielectric material includes at least one of a polyimide resin and an acrylic resin.

8. The display substrate of claim 1 , wherein the conductive bump further includes an inorganic material layer located between the first portion and the second portion and covering the first portion.

9. The display substrate of claim 1 , wherein the second portion further covers a surface of the first electrode adjacent to the first portion.

10. The display substrate according to claim 1 , wherein a plurality of the conductive bumps arranged in an array are disposed on each of the first electrodes.

11. The display substrate of claim 1 , wherein the surface of the first portion away from the first electrode is roughened.

12. the dimension of the first side is 2 to 10 μm; the distance between two adjacent conductive bumps in the extending direction of the first side is 2 to 10 μm; the distance between two adjacent conductive bumps in the extension direction of the second side is 2 to 5 μm; The display substrate according to claim 2 .

13. The micro LED includes a first pin and a second pin, and the first pin and the second pin respectively contact the conductive bumps corresponding to different electrodes. The display substrate according to claim 1 .

14. the first dielectric layer includes a first sub-dielectric layer and a second sub-dielectric layer that are sequentially stacked; The display substrate further includes a second electrode and a third electrode disposed between the first sub-dielectric layer and the second sub-dielectric layer, and the second electrode is connected to the source / drain region of the thin film transistor through a first hole in the first sub-dielectric layer; the first electrode includes a first sub-electrode and a second sub-electrode, the first sub-electrode is connected to the second electrode through a second hole in the second sub-dielectric layer, and the second sub-electrode is connected to the third electrode through a third hole in the second sub-dielectric layer; The display substrate according to claim 1 .

15. providing a substrate; forming a thin film transistor on the substrate; forming a first dielectric layer over the thin film transistor; forming a first electrode on the first dielectric layer and electrically connecting the first electrode to the thin film transistor; forming a conductive bump on the first electrode; a size of a cross section of the conductive bump in a plane parallel to the substrate has a negative correlation with a distance from the cross section to a surface of the first electrode; the conductive bump includes a first portion and a second portion covering the first portion, the second portion contacting the first electrode, and a surface of the second portion facing away from the substrate and a surface of the first portion facing away from the substrate are conformal; the first portion is made of a dielectric material and the second portion is made of a conductive material; the number of the conductive bumps electrically connected to one of the first electrodes is plural, the conductive bumps further include a connection portion provided in the same layer as the second portion, the connection portion covers a portion of the surface of the first electrode located between the first portions corresponding to two adjacent conductive bumps, and the connection portion is provided in contact with the second portions corresponding to the two adjacent conductive bumps and the first electrode; further forming an adhesive layer to cover the conductive bumps and portions of the first electrode located between the conductive bumps; placing a micro LED on the adhesive layer and applying a force to the micro LED to cause the conductive bumps to penetrate the adhesive layer and contact the micro LED; and curing the adhesive layer. A method for manufacturing a display substrate.

16. The step of forming the conductive bumps includes: forming a layer of dielectric material over the first electrode; patterning the layer of dielectric material to form the first portion of the conductive bump; forming a first conductive material layer over the substrate, the first electrode, and the first portion; patterning the first conductive material layer to form the second portion of the conductive bump and the connection portion; an orthogonal projection of the first portion onto the first electrode is located within an orthogonal projection of the second portion onto the first electrode; 16. The method of claim 15.

17. 17. The method of claim 16, further comprising roughening a surface of the first portion prior to forming the first layer of conductive material over the first portion.

18. the dielectric material layer includes a photosensitive material; patterning the dielectric material layer includes exposing and developing the dielectric material layer using a first mask; 17. The method of claim 16, wherein the exposure dose of light used, the dimensions of the light-shielding portion of the first mask in a direction perpendicular to the direction in which the light-shielding portion of the first mask extends, and the distance from the first mask to the dielectric material layer are arranged such that, during the exposure, diffracted light is generated at the edge of the light-shielding portion, and at least a portion of the diffracted light reaches the surface of the dielectric material layer located below the center of the light-shielding portion.

19. 17. The method of claim 16, wherein forming the conductive bump further comprises forming an inorganic material layer over the first portion after forming the first portion and before forming the first conductive material layer, wherein the inorganic material layer and the surface of the first portion remote from the substrate are conformal.

20. The method of claim 15 , wherein the connecting portion and the second portion are made of the same material and are manufactured by the same process.

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