Large-size silicon carbide single crystal materials with reduced crystallographic stress

Abstract

Silicon carbide (SiC) materials, including SiC wafers and SiC boules, and related methods are disclosed that provide large sized SiC wafers with reduced crystallographic stress. Growth conditions for the SiC materials include maintaining a generally convex growth surface of the SiC crystal, controlling the difference in thermal profile from the front to the back of the growing SiC crystal, providing sufficient source flux to enable commercially viable growth rates for the SiC crystal, and reducing the inclusion of contaminants or non-SiC particles in the SiC source material and the corresponding SiC crystal. By forming larger sized SiC crystals that exhibit lower crystallographic stress, the overall dislocation density associated with missing or additional planes of atoms may be reduced, thereby improving crystal quality and usable SiC crystal growth height.

Description

[Technical Field]

[0001] The present disclosure relates to crystalline materials, and more particularly to large size silicon carbide single crystal materials with reduced crystallographic stress. [Background technology]

[0002] Silicon carbide (SiC) exhibits many attractive electrical and thermophysical properties. SiC is particularly useful due to its physical strength and high resistance to chemical attack, as well as various electronic properties such as radiation resistance, high breakdown field, relatively wide band gap, high saturated electron drift velocity, high temperature operation, and absorption and emission of high-energy photons in the blue, violet, and ultraviolet ranges of the spectrum. Compared to conventional wafer or substrate materials, including silicon and sapphire, these properties make SiC more suitable for fabricating wafers or substrates for high-power density solid-state devices, such as power electronics, radio frequency, and optoelectronic devices. SiC occurs in many different crystalline structures, called polytypes, with certain common polytypes (e.g., 4H-SiC and 6H-SiC) having a hexagonal crystalline structure.

[0003] Although SiC exhibits excellent material properties, the crystal growth techniques required to grow SiC are very different from conventional growth processes for other crystalline materials and are significantly more challenging. Conventional crystalline materials used in semiconductor manufacturing, such as silicon and sapphire, have significantly lower melting points, enabling direct crystal growth techniques from molten source materials and the fabrication of large-diameter crystalline materials. In contrast, bulk crystalline SiC is often produced by a seeded sublimation growth process at high temperatures, which presents various challenges, including impurity incorporation, structural defects related to thermal and crystallographic stresses, and the formation of unintended polytypes, among others. In a typical SiC growth technique, the substrate and source material are both placed inside a reaction crucible. The thermal gradient created when the crucible is heated promotes vapor-phase transfer of material from the source material to the substrate, where it then condenses, resulting in bulk crystal growth. It is known that impurities can be introduced into SiC as dopants, and that these dopants can regulate certain properties. In sublimation growth of SiC, dopants may be introduced into the chamber in various ways so that they are present in the SiC crystal produced from the process. The process is controlled to provide the appropriate concentration of dopant for a particular application. After bulk crystal growth, individual wafers of SiC may be obtained by slicing the bulk crystal ingot or boule of SiC, and the individual wafers may subsequently be subjected to additional processes such as lapping or polishing.

[0004] The unique properties of SiC wafers enable the design and fabrication of arrays of high-power and / or high-frequency semiconductor devices. Continuous development has led to a level of maturity in the fabrication of SiC wafers that allows the production of such semiconductor devices for an ever-expanding range of commercial applications. As the semiconductor device industry continues to mature, SiC wafers with larger usable diameters are desired. The usable diameter of SiC wafers can be limited by certain structural defects in the material composition of SiC and certain wafer topography characteristics. Structural defects in the material composition can include dislocations (e.g., micropipes, threading edges, threading screws, and / or basal plane dislocations), hexagonal voids, and stacking faults, among others. Wafer topography characteristics associated with SiC can include bowing, bending, and thickness variations, which can be related to wafer flatness. These various structural defects and wafer topography characteristics can contribute to crystallographic stresses that can be detrimental to the fabrication and proper operation of semiconductor devices subsequently formed on conventional SiC wafers. Such crystallographic stress is generally proportional to the square of the wafer radius, making it economically difficult to produce high quality, larger diameter SiC semiconductor wafers.

[0005] The art continues to seek improved SiC wafers of larger dimensions and related solid-state devices that overcome the challenges associated with conventional SiC wafers. Summary of the Invention [Problem to be solved by the invention]

[0006] Silicon carbide (SiC) materials, including SiC wafers and SiC boules, and related methods are disclosed that provide large-sized SiC wafers with reduced crystallographic stress. Growth conditions for the SiC materials include maintaining a generally convex growth surface of the SiC crystal, adjusting the difference in thermal profile from the front to the back of the growing SiC crystal, providing sufficient source flux to enable commercially viable growth rates for the SiC crystal, and reducing the inclusion of contaminants or non-SiC particles in the SiC source material and the corresponding SiC crystal. By forming larger-sized SiC crystals that exhibit lower crystallographic stress, the overall dislocation density associated with missing or additional planes of atoms can be reduced, thereby improving crystal quality and usable SiC crystal growth height. [Means for solving the problem]

[0007] In one embodiment, the SiC wafer has a density of 1000 centimeters per cubic centimeter (cm / cm) about a first area bounded by a dimension of at least 195 millimeters (mm) and a radius from the center of the SiC wafer that is at least 50% of the wafer radius of the SiC wafer. 3 ) of the crystal plane

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[0008] In another aspect, the SiC boule includes a width in the range of 195 mm to 305 mm and a boule height in the range of 50 mm to 300 mm. In certain embodiments, the width is in the range of 195 mm to 205 mm or in the range of 100 mm to 300 mm. In certain embodiments, at least 50% of the boule height is configured to provide a plurality of SiC wafers, each SiC wafer of the plurality of SiC wafers having a radius of 1000 cm / cm about a first region bounded by a radius from the center of the SiC wafer that is at least 50% of the wafer radius of the SiC wafer. 3 of the crystal plane

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[0009] In another aspect, a method for providing SiC source material for crystal growth includes: forming a plurality of milling media from a SiC crystalline material; and increasing the density of the SiC source powder by milling the SiC source powder with the plurality of milling media. In certain embodiments, the method further includes removing surface contamination from the plurality of milling media and then reducing the particle size of the SiC source powder. In certain embodiments, removing the surface contamination includes using a milling process before reducing the particle size of the SiC source powder. In certain embodiments, removing the surface contamination further includes applying a chemical etch to the plurality of milling media. In certain embodiments, the SiC crystalline material includes a SiC crystal boule. In certain embodiments, forming the plurality of milling media includes wire sawing the SiC crystal boule. In certain embodiments, the density of the SiC source powder is 1.5 grams per cubic centimeter (g / cm) after milling with the plurality of milling media. 3 ) to 3.2 g / cm 3 or 1.5g / cm 3 to 2.5 g / cm 3 is in the range.

[0010] In another aspect, a method for forming a SiC single crystal material includes: growing a SiC boule having a width in the range of 195 mm to 305 mm and a boule height in the range of 50 mm to 300 mm. In certain embodiments, the method further includes separating a plurality of SiC wafers from the SiC boule, each of the plurality of SiC wafers having a width in the range of 195 mm to 305 mm. In certain embodiments, the SiC boule is grown along a (0001) crystallographic plane. In certain embodiments, the SiC boule is grown along an M-plane of the SiC boule. In certain embodiments, the method further includes separating the plurality of SiC wafers from the SiC boule along a (0001) crystallographic plane of the SiC boule or within 4 degrees of the (0001) crystallographic plane ...

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[0011] In other aspects, any of the foregoing aspects individually or together, and / or various separate aspects and features described herein may be combined for additional advantage. Various features and elements disclosed herein may be combined with one or more other disclosed features and elements, unless otherwise indicated herein.

[0012] Those skilled in the art will appreciate the scope of the present disclosure and realize additional aspects thereof after reading the following detailed description of the preferred embodiments in connection with the accompanying drawing figures.

[0013] The accompanying drawing figures, which are incorporated in and form a part of this specification, illustrate several aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure. [Brief explanation of the drawings]

[0014] [Figure 1A] X-ray topography image of a 1 cm x 1 cm section of a 4H silicon carbide (SiC) wafer, showing the crystallographic planes

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[0015] The examples set forth below represent the information necessary to enable one skilled in the art to practice the examples and to illustrate the best mode of practicing the examples. By reading the following description in light of the accompanying drawing figures, one skilled in the art will understand the concepts of the present disclosure and will recognize applications of these concepts not specifically addressed herein. It is to be understood that these concepts and applications are encompassed within the scope of this disclosure and the appended claims.

[0016] Terms such as first, second, etc. may be used herein to describe various elements, but it should be understood that these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element can be referred to as a second element, and similarly, a second element can be referred to as a first element, without departing from the scope of the present disclosure. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0017] When an element such as a layer, region, or substrate is said to be "on" or extend "onto" another element, it will be understood that it can be directly on or extend directly onto the other element, or that intervening elements may be present. In contrast, when an element is said to be "directly on" or extend "directly onto" another element, there are no intervening elements present. Similarly, when an element such as a layer, region, or substrate is said to be "over" or extend "over" another element, it will be understood that it can be directly on or extend directly onto the other element, or that intervening elements may be present. In contrast, when an element is said to be "directly on" or extend "directly onto" another element, there are no intervening elements present. It will be understood that when an element is said to be "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there may be intervening elements. In contrast, when an element is said to be "directly connected" or "directly coupled" to another element, there are no intervening elements present.

[0018] Relative terms such as "below" or "upper" or "above" or "lower" or "horizontal" or "vertical" may be used herein to describe the relationship of one element, layer, or region to another element, layer, or region as illustrated in the figures. It will be understood that these terms, and those discussed above, encompass various orientations of the device in addition to the orientation shown in the figures.

[0019] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It will be further understood that the terms "comprise," "comprising," "include," and / or "including," as used herein, specify the presence of referenced features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0020] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be understood that terms used herein should be interpreted to have a meaning consistent with their meaning in the context of the present specification and related art, and should not be interpreted in an idealized or overly formal sense unless expressly defined as such herein.

[0021] Examples are described herein with reference to schematic illustrations of embodiments of the present disclosure. Accordingly, actual dimensions of layers and elements may vary, and variations from the illustrated shapes are expected, e.g., as a result of manufacturing techniques and / or tolerances. For example, regions illustrated or described as square or rectangular may have rounded or curved features, and regions shown as straight lines may have some irregularities. Accordingly, regions illustrated in the figures are schematic, and their shapes do not represent the precise shape of a region of a device and are not intended to limit the scope of the present disclosure. Elements common between figures may be designated herein by the common element number and will not be described again later.

[0022] Silicon carbide (SiC) materials, including SiC wafers and SiC boules, and related methods are disclosed that provide large-sized SiC wafers with reduced crystallographic stress. Growth conditions for the SiC materials include maintaining a generally convex growth surface of the SiC crystal, adjusting the difference in thermal profile from the front to the back of the growing SiC crystal, providing sufficient source flux to enable commercially viable growth rates for the SiC crystal, and reducing the inclusion of contaminants or non-SiC particles in the SiC source material and the corresponding SiC crystal. By forming larger-sized SiC crystals that exhibit lower crystallographic stress, the overall dislocation density associated with missing or additional planes of atoms may be reduced, thereby improving crystal quality and usable SiC crystal growth height or length. As used herein, missing and additional planes of atoms may be used interchangeably to describe stress states in a crystal in either compression or tension.

[0023] SiC can be a very difficult crystalline material to grow because it does not have a liquid state at ambient pressure, but instead converts directly from solid to gas and back to solid. This makes it different from most materials because liquid-phase growth is not available. Another major challenge for SiC crystal growth is the very low stacking fault energy observed in SiC, which makes it very easy to introduce additional planes of atoms and their associated defect structures into the crystal lattice. This low stacking fault energy, combined with the very high temperatures used in conventional physical vapor transport growth of SiC, makes it difficult to maintain growth in a regime where the energy available from the local stress field is lower than the energy required to create stacking faults. Crystallographic stress in SiC can be controlled by many factors. Crystal height and diameter can play important roles, as stress can increase proportionally with crystal height and as a square power of the crystal diameter. Conventional SiC growth techniques have achieved SiC crystals with diameters of 100 and 150 millimeters (mm). The dimensions of such SiC crystals are typically limited so that the induced crystal stress does not exceed the critical resolved shear stress of the SiC crystal at which a high density of dislocations forms. For larger diameter SiC crystals (e.g., greater than 150 mm) disclosed herein, the amount of increase in diameter can disproportionately increase crystal stress, thereby producing a shorter usable crystal height during growth. In particular, stress levels in a crystal generally increase as the square of the crystal's diameter increases. For example, the approximate stress level in a 200 mm SiC crystal, if grown according to the same conditions as a 150 mm SiC crystal, can be expected to have about 1.78 times the stress of a 150 mm SiC crystal. Furthermore, stress is known to generally increase with the height or length of the grown crystal, thereby limiting larger diameter crystals to shorter growth heights or lengths to prevent the critical resolved shear stress from being exceeded.

[0024] Furthermore, the induced growth stress and critical resolved shear stress may have different magnitudes in different crystallographic directions. In this regard, the optimal low-stress condition corresponds to the direction in which both the induced growth stress and the critical resolved shear stress are minimized. For SiC, this corresponds to having the basal plane or (0001) plane aligned perpendicular to the growth direction. For growth directions in which the basal plane is non-perpendicular to the growth direction, higher relative stresses can be resolved on the basal plane. Thus, for reduced stress conditions, SiC crystals are grown with the basal plane aligned perpendicular to the growth direction and then cut at an off-axis angle for device applications in which off-axis SiC wafers are preferred. By not cutting the wafer in a direction substantially perpendicular to the growth direction, the top or bottom portions of the grown crystal cannot geometrically form a SiC wafer, and these unusable crystal portions correspond to the diameter. As an example, cutting a 4-degree off-axis wafer from a 150 mm diameter crystal can result in an unusable crystal with a height or length of approximately 10.5 mm. Scaling this up to 200 mm diameter crystals can result in approximately 14 mm of unusable crystal. Furthermore, larger diameter wafers can require increased thickness to retain adequate rigidity for subsequent device fabrication processes, which further reduces the number of wafers that can be obtained from a given crystal growth height.

[0025] In this regard, conventional crystal growth techniques used for 150 mm and smaller SiC crystals are not necessarily scalable to practically obtain larger diameter SiC crystals. In accordance with the principles of the present disclosure, techniques are provided that exhibit lower crystallographic stresses, thereby enabling larger diameter SiC crystals (e.g., 200 mm and larger) with increased usable crystal height. As used herein, the height or length of a crystalline material are terms that may be used interchangeably to refer to the dimension of the SiC crystal measured in a direction perpendicular to the seed on which the SiC crystal grows. As described in further detail below, such techniques include maintaining a generally convex growth surface for the SiC crystal, providing sufficient source flux to enable commercially viable growth rates for the SiC crystal, and reducing the inclusion of contaminants or non-SiC particles in the SiC source material and the corresponding SiC crystal.

[0026] The general aspects of seeded sublimation growth processes for SiC are well established. Accordingly, those skilled in the art of crystal growth, particularly in the art of SiC growth and related systems, will understand that the specific details of a given technique or process can vary depending on the many relevant circumstances, processing conditions, and equipment configurations. Accordingly, the description provided herein is appropriately given largely in a general and schematic sense, with the understanding that those skilled in the art will be able to implement and use the various embodiments disclosed herein based on the disclosure provided without undue experimentation. Furthermore, those skilled in the art will understand that SiC sublimation systems of the type described herein are commercially available in a variety of standard configurations. Alternatively, sublimation systems may be designed and implemented in custom configurations as needed or appropriate. Accordingly, the embodiments described herein are not limited to a particular subset of sublimation systems or any particular system configuration. Rather, many different types and configurations of sublimation systems may be used to grow crystalline SiC material according to the embodiments disclosed herein.

[0027] As used herein, "substrate" refers to a crystalline material, such as a single-crystal semiconductor material, that may be formed from a bulk crystalline material. Bulk crystalline material may refer to bulk crystals and crystalline boules. As used herein, the term "bulk crystal" may be used synonymously with the term "boule." In certain embodiments, a substrate may have a sufficient thickness to (i) be surface-processed (e.g., lapped and polished) to support epitaxial deposition of one or more layers of semiconductor material, and optionally (ii) be free-standing when and if separated from a rigid carrier. In certain embodiments, the terms "substrate" and "wafer" may be used synonymously, as wafers are typically used as substrates for semiconductor devices that may be formed on them. Thus, a substrate or wafer may refer to a free-standing crystalline material that has been separated from a larger or bulk crystalline material or substrate. In certain embodiments, the SiC wafer may have a generally cylindrical or circular shape and / or may have at least about one or more of the following thicknesses: 100 microns (μm), 200 μm, 300 μm, 350 μm, 500 μm, 750 μm, 1 mm, 2 mm, 3 mm, 5 mm, 1 centimeter (cm), 2 cm, 5 cm, 10 cm, 20 cm, 30 cm, or more. In certain embodiments, the thickness may include any number of ranges, including various combinations of the above-listed values. For example, thicknesses may be provided in ranges including 200 μm to 300 μm, or 200 μm to 350 μm, or 200 μm to 500 μm, or 200 μm to 750 μm, or 200 μm to 1 mm, and so forth. In this regard, various thickness ranges may be provided, starting from each of the above-listed values ​​and ending at all possible higher values ​​listed above. In further embodiments, the SiC wafer may have a non-circular shape, such as a square or rectangle, having any of the dimensions described above. The principles of the present disclosure may be provided in the context of a circular wafer shape. However, any of the wafer diameter values ​​provided may be referred to as dimensions or the longest dimension of the wafer, regardless of the wafer shape.

[0028] In certain embodiments, the wafer may include a thicker wafer that can be split into two thinner wafers. In certain embodiments, the wafer may be part of a thicker wafer having one or more epitaxial layers (optionally with one or more metal contacts) arranged on a surface thereof as part of a device wafer with a plurality of electrically operable devices. The device wafer may be split to provide a thinner device wafer and a second, thinner wafer on which one or more epitaxial layers (optionally with one or more metal contacts) can subsequently be formed.

[0029] In certain embodiments, wafers may have a diameter of approximately 200 mm or greater, approximately 300 mm or greater, approximately 450 mm or greater, or in the range of approximately 200 mm to approximately 450 mm, inclusive, or in the range of approximately 200 mm to approximately 300 mm, inclusive. With respect to relative dimensions, the term "approximately" or "about" is defined to mean a nominal dimension within a certain tolerance, such as plus or minus 5 mm from the diameter dimension. To account for such tolerances, a wafer described herein having a "200 mm" diameter may encompass a diameter range of 195 mm to 205 mm, inclusive; a wafer having a "300 mm" diameter may encompass a diameter range of 295 mm to 305 mm, inclusive; and a wafer having a "450 mm" diameter may encompass a diameter range of 445 mm to 455 mm, inclusive. In other embodiments, such tolerances may be smaller, such as plus or minus 1 mm or plus or minus 0.25 mm. For non-circular wafers, any of the diameter values ​​mentioned above may refer to the longest dimension of the wafer having a non-circular shape.

[0030] The methods disclosed herein may be applied to substrates or wafers of a wide variety of crystalline materials, both single-crystalline and polycrystalline. In certain embodiments, the methods disclosed herein may utilize cubic, hexagonal, and other crystalline structures and may target crystalline materials with on-axis and off-axis crystallographic orientations. In certain embodiments, the methods disclosed herein may be applied to semiconductor materials and / or wide bandgap materials. Exemplary materials include, but are not limited to, silicon carbide (SiC), silicon (Si), gallium arsenide (GaAs), sapphire, and diamond. In certain embodiments, such methods may utilize single-crystalline semiconductor materials having a hexagonal crystal structure, such as 4H-SiC, 6H-SiC, or Group III nitride materials (e.g., gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), indium gallium nitride (InGaN), aluminum gallium nitride (AlGaNI), or aluminum indium gallium nitride (AlInGaN)). In certain embodiments, a substrate or wafer may comprise 4H—SiC having a diameter of approximately 200 mm, or 300 mm, or greater, and a thickness ranging from 100 μm to 1000 μm, or from 100 μm to 800 μm, or from 100 μm to 600 μm, or from 150 μm to 500 μm, or from 150 μm to 400 μm, or from 200 μm to 500 μm, or any other thickness range, or having endpoints determined at any of the values ​​specified above. In this regard, various thickness ranges may be provided starting from each of the values ​​recited above and ending at all possible higher values ​​recited above.

[0031] While various illustrative embodiments described below refer generally to SiC or specifically to 4H—SiC, it should be understood that other suitable crystalline materials may be used. Among the various SiC polytypes, the 4H—SiC polytype is particularly attractive for power electronics devices due to its high thermal conductivity, wide bandgap, and isotropic electron mobility. The embodiments disclosed herein may be applied to on-axis SiC (i.e., no intended angular deviation from its c-plane) or off-axis SiC (i.e., typically off-axis from a growth axis such as the c-axis by a non-zero angle, typically in the range of 0.5° to 10°, or a subrange thereof such as 2° to 6°, or another subrange). Certain embodiments disclosed herein may utilize on-axis 4H—SiC or vicinal (off-axis) 4H—SiC with an offcut in the range including 1° to 10°, or 2° to 6°, or about 2°, 4°, 6°, or 8°. The embodiments disclosed herein may be applied to SiC wafers having multiple polytypes (eg, 4H and 6H polytypes within a common SiC wafer).

[0032] The embodiments disclosed herein may be applied to both doped crystalline semiconductor materials (e.g., N-type doped conductivity SiC and / or P-type doped SiC), co-doped and / or undoped crystalline semiconductor materials (e.g., semi-insulating SiC or high resistivity SiC). In certain embodiments, SiC crystalline materials, including SiC boules and SiC wafers, are used in applications where the SiC crystalline materials are in the range of 1×10 17 cm -3 From 1×10 21 cm -3 range including, or 1 x 10 17 cm -3 From 3 x 10 18 cm -3 range including, or 1 x 10 18 cm -3 From 1×10 19 cm -3 range, or 1×10 18 cm -3 From 3 x 10 18 cm -3It may contain N-type doping (including intended and unintended dopants such as nitrogen (N)) at concentrations in the range of 0.1 to 1.0.

[0033] In certain embodiments, N-type doped SiC crystal materials may have a resistivity in the range of 0.001 ohm-cm to 0.05 ohm-cm, inclusive, or in the range of 0.001 ohm-cm to 0.03 ohm-cm, inclusive, or in the range of 0.005 ohm-cm to 0.05 ohm-cm, or in the range of 0.005 ohm-cm to 0.03 ohm-cm. In other embodiments, higher resistivity SiC crystal materials, including semi-insulating SiC boules and semi-insulating SiC wafers, may have a resistivity of at least 1500 ohm-cm, or at least 5000 ohm-cm, or at least 50,000 ohm-cm, or at least 1×10 5 ohm·cm, or at least 1×10 6 ohm·cm, or at least 1×10 9 ohm·cm, or at least 1×10 11 ohm·cm, or 1500 ohm·cm to 1×10 11 range including ohm-cm, or 1 x 10 5 ohm·cm to 1×10 9 range including ohm-cm, or 1 x 10 5 ohm·cm to 1×10 11 They may include unintentionally doped or undoped SiC with resistivities ranging from ohm·cm to ohm·cm. Semi-insulating SiC wafers may be doped with boron (B), vanadium (V), aluminum (Al), or combinations thereof. Co-doped SiC wafers may include combinations of two or more dopants, such as N, Al, B, and V, among others, depending on the embodiment.

[0034] Crystalline SiC can contain a variety of crystal defects, including dislocations (e.g., threading edge, threading screw, basal plane, and / or superscrew dislocations, or micropipes, among others), hexagonal voids, and stacking faults. Mixed dislocations can include one or more combinations of various dislocations (e.g., threading edge, threading screw, basal plane, and / or superscrew dislocations, or micropipes) that intersect or terminate with each other. For example, mixed dislocations may include threading screw dislocations and basal plane dislocations that intersect or terminate with each other. The various crystal defects described above may form during crystal growth and / or during heating or cooling after growth, resulting in the formation of one or more dislocations in the material lattice structure of the crystalline SiC. Such crystal defects can be detrimental to the fabrication, proper operation, device yield, and reliability of semiconductor devices subsequently formed on the SiC wafer. In particular, defects associated with missing prismatic planes of atoms can cause significant crystallographic stresses that can limit practical wafer diameters and crystal growth lengths. These missing prismatic planes of atoms may be connected by various dislocations, for example, bond basal plane dislocations may move within the plane of the corresponding wafer, and bond threading edges may move perpendicular to the plane of the wafer. Although missing prismatic planes of atoms may be difficult to quantify, basal plane dislocations associated with such missing prismatic planes of atoms may be readily detectable by wafer imaging, including x-ray topography. For example, in SiC wafers with a hexagonal crystal structure, basal plane dislocations associated with missing atomic planes may be located in the crystallographic planes.

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[0035] FIG. 1A is an x-ray topography image 10 of a 1 cm×1 cm section of a 4H—SiC wafer 12, showing the crystallographic planes

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[0036] FIG. 1B is an x-ray topography image 16 of a 1 cm×1 cm section of the same 4H—SiC wafer as image 10 of FIG. 1A, showing the crystallographic planes.

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[0037] FIG. 1C shows the wafer center 12 C From wafer periphery 12 P 1A is an x-ray topography image 20 of a larger portion of the same 4H—SiC wafer 12 as image 10 of FIG. 1A, spanning the wafer center 12. As noted above, the SiC wafer 12 has a diameter of approximately 200 mm, and therefore image 20 is taken from the wafer center 12. C From wafer periphery 12 P The superimposed vertical dashed lines represent the crystal planes.

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[0038] FIG. 2 is an x-ray topography image 24 similar to image 20 of FIG. 1C, but of a different 4H—SiC wafer 26, showing a larger area with reduced basal plane dislocations associated with missing atomic planes. The SiC wafer 26 has a diameter of approximately 200 mm, and therefore image 24 is taken from the wafer center 26. C From wafer periphery 26 PThe thickness of the SiC wafer 26 is the same as that of the SiC wafer 12 in FIG. 1C. The superimposed vertical dashed lines represent the crystal planes.

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[0039] As described in more detail below, growth conditions and techniques are disclosed that provide large area SiC wafers with reduced crystallographic stress, such as exemplary SiC wafer 12 of FIGS. 1A-1C and exemplary SiC wafer 26 of FIG. 2. By characterizing the SiC wafer with the x-ray topography described above, the overall crystallographic stress and missing atomic planes for the SiC wafer can be quantified in terms of the corresponding linear density of basal plane dislocations per unit volume. FIG. 3 shows the distribution of the crystallographic stress and missing atomic planes for the SiC wafer at the wafer center 28. C 28' radius from R a first region 28' bounded by a first region 28' and a wafer periphery 28'; P 1 is a front view of an exemplary SiC wafer 28 showing a second region 28″ defined between the first and second crystal planes.

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[0040] FIG. 4 is a cross-sectional view of a SiC growth system 30 including a crucible 32, a source material 34, and a crucible lid 36 that can be used to form a SiC crystal 38. In this regard, the SiC growth system 30 can be used to provide crystal growth conditions with reduced crystallographic stress to produce large-width or large-diameter boules and corresponding wafers. Although not shown, it is understood that a seed, e.g., a crystalline SiC material, can be disposed near the crucible lid 36 to form the SiC crystal 38 during growth. The source material 34 and the seed are generally contained in the crucible 32, and the source material 34 can be positioned above, below, or adjacent to the seed. The crucible 32 may include a material that is relatively stable to Si- and C-containing gases. In certain embodiments, the crucible 32 may comprise one or more of graphite, graphite coated with tantalum carbide (TaC) and / or niobium carbide (NbC), and solid TaC and NbC, among others. In certain embodiments, the crucible 32 may be sealed to prevent gas escape or may be partially open to allow some gas to flow out of the crucible 32. In certain embodiments, the crucible 32 may be electrically conductive so that heating is inductive, while other embodiments may use radiant heating, and still other embodiments may use a combination of inductive and radiant heating. In certain embodiments, the temperature profile of the crucible 32 may be controlled so that heat input to the system is taken into account and insulating baffles are used to control heat flow. In certain embodiments, the source material 34 may be kept at a higher temperature than the crucible lid 36 so that a temperature gradient is created within the crucible 32. This temperature gradient helps to effect the transport of a vapor flux 40 containing Si- and C-containing gaseous species from the source material 34 to the SiC crystals 38. As the source material 34 sublimes and condenses to form the SiC crystals 38, the vapor flux 40 may be propelled by a gas flow from the source material 34 to the SiC crystals 38. In certain embodiments, the gas source may be propelled through a high temperature region to enable cracking of the gas into constituent parts, or various gaseous species may interact directly with the SiC crystals 38. In certain embodiments, one or more radio frequency electric fields are used to assist the gas cracking process.

[0041] Growth conditions for SiC crystal 38 may typically be implemented by providing a vapor flux 40 for the deposition of Si and C. There are many ways to accomplish this, and the embodiments described herein are provided to alter certain aspects of SiC crystal growth to reduce crystalline defects, including missing atomic planes, in the corresponding SiC crystal and resulting SiC wafer. Vapor flux 40 may be provided by generating one or more of SiC, SiC2, Si2C, and Si vapors through heating of source material 34, which may include one or more of: polycrystalline SiC; single crystal SiC; polymers of Si and C; a mixture of Si and C powders where the Si:C ratio is 1:1 or within a 20% tolerance of the 1:1 ratio; a mixture of SiC, Si, and C powders where the Si:C ratio is 1:1 or within a 20% tolerance of the 1:1 ratio; a puck or chunk of amorphous or crystalline SiC (e.g., polycrystalline or single crystal); and a porous mesh of SiC. Depending on the application, the source material may include additional materials beyond Si and C, such as dopant source materials. In certain embodiments, a gaseous source may be used to provide the vapor flux 40, either separately or in addition to the source materials 34 described above. Such a gaseous source may include one or more species such as SiH, SiH, SiClH, SiClH, SiCl, CH, CH, and Si(CH). In embodiments involving a combination of gaseous and solid sources, the ratio of Si to C in the solid source may vary from 1:1, as a portion of the Si or C supply may be provided by the gas.

[0042] In certain embodiments, these sources may contain primarily pure SiC, although impurities may often be added to achieve intentional doping of the crystal, modify surface energy, intentionally introduce point defects, and modify lattice size. These impurities can include almost any element in the periodic table, often Group III elements such as boron (B) to induce p-type doping, or N to induce n-type doping, and atoms with even larger atomic radii, including Ge and Sn, V, and some lanthanides, may be included to modify surface energy and change the resulting crystal lattice parameter size, or to introduce deep level electrical defects.

[0043] In certain embodiments, improved polytype control and growth rate may be obtained by controlling growth conditions to maintain a generally convex growth surface of the growing SiC crystal 38. This may be achieved by managing the radial thermal profile so that the central region of the SiC crystal 38 is cooler than the peripheral portion to provide a higher growth rate in the central region. If such a thermal profile is too large, crystallographic stress may increase. The distance 42 between the source material 34 and the SiC crystal 38 partially contributes to the thermal gradient between the source material 34 and the SiC crystal 38. A higher thermal gradient is associated with increased crystal stress during growth, while a lower thermal gradient may be associated with a lower growth rate. In this regard, simply reducing the thermal gradient to avoid crystal stress may result in an even lower growth rate that is impractical for providing production-scale quantities of SiC crystal 38. Furthermore, if the distance 42 is too short, the achievable boule height or length of the growing SiC crystal 38 may be limited.

[0044] While providing a convex growth surface can be important for polytype control and reducing the formation of certain crystallographic defects, controlling the radial heat profile without introducing missing atomic planes can be challenging, especially for larger diameter SiC crystals. In particular, any deviation in the radial heat profile from the front or growth surface of the SiC crystal 38 to the back surface of the SiC crystal 38, closer to the seed and crucible lid 36, can induce intra-crystalline shear stresses and missing atomic planes. According to aspects of the present disclosure, various crystal growth techniques are described that promote a convex growth surface while also reducing the front-to-back deviation in the radial heat profile of the growing SiC crystal 38. In certain embodiments, a shadow mask may be used on the front surface of the growing SiC crystal 38 to promote a convex growth surface without the need to provide a more highly gradient thermal profile on the back surface. To allow for a larger boule height for the SiC crystal 38 when a shadow mask is present, the SiC crystal 38 may be slowly moved away from the source material 34 to allow more physical space for growth of the SiC crystal 38 while maintaining the condition for a convex growth surface. Furthermore, slowly moving the SiC crystal 38 away from the source material 34 may provide a consistent distance from the surface of the growing SiC crystal 38 to the source material 34. The above effect may be achieved by slowly moving the source material 34 away from the growing crystal 38.

[0045] FIG. 5 is a cross-sectional view of a SiC growth system 44 that can provide crystal growth conditions with reduced crystallographic stress for the production of large-width or large-diameter boules and corresponding wafers. In certain embodiments, the SiC growth system 44 includes an arrangement that promotes additional heat dissipation at the center of the crucible lid 36. An insulating layer 46 is illustrated surrounding the crucible 32 and crucible lid 36. The insulating layer 46 forms an opening 48 aligned with the center of the crucible lid 36 and the SiC crystal 38. In this manner, heat 50 can be more easily dissipated at the opening 48, thereby providing a radial thermal profile with a cooler center of the SiC crystal 38 to form a convex growth surface. In certain embodiments, the size and location of the opening 48 can be configured to match the thermal profile from front to back to promote a convex growth surface and reduce the formation of missing atomic planes. Although the opening 48 is illustrated as being formed entirely through the entire thickness of the insulating layer 46, the opening 48 may embody a sub-opening such that the insulating layer 46 reduces in thickness at the opening 48. In other embodiments, the backside thermal profile of the SiC crystal 38 may be dynamically adjusted during growth so that higher gradients in the thermal profile that may be beneficial at the beginning of growth can be reduced during later growth stages. For example, the positions of the insulating layer 46 and the opening 48 (or sub-opening) relative to the crucible 32 may move during growth. Alternatively, the position of the SiC crystal 38 relative to the insulating layer 46 may shift during growth. In still other instances, the opening 48 may be closed, open, and / or resized during growth to compensate for any changes in the front-to-backside thermal profile as the SiC crystal 38 grows longer. The active heating element may be located around the periphery of the crucible 32 and / or registered at the center of the crucible 32, which may be dynamically adjusted during growth.

[0046] In certain embodiments, silicon carbide growth system 44 may include a crucible 32 design that provides an increased vapor flux 40 to the center of SiC crystal 38 to promote a convex growth surface. For example, one or more interior sidewalls 32′ of crucible 32 may be formed with one or more sidewall features that provide orifices or passages for vapor flux 40 within crucible 32 that are smaller than the diameter of SiC crystal 38. Various sidewall features on interior sidewall 32′ may be integrated with crucible 32 or another component attached to crucible 32. The sidewall features may include one or more protrusions that extend away from interior sidewall 32′ toward the center of crucible 32 to define orifices or passages. Depending on the embodiment, the resulting orifices or passages may be formed in any number of shapes, including circular, rectangular, and hexagonal. The hexagonal orifice or passage is

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[0047] In certain embodiments, the SiC growth system 44 may include a design that accounts for the formation of a boundary layer that may be present during growth. At growth temperatures for SiC, the vapor flux 40 provided by the source material 34 may provide more Si species than C species, although the growing SiC crystal 38 generally receives equal amounts of each. In this regard, excess species in the vapor flux 40 may be rejected to form a boundary layer within the crucible 32 along the surface of the growing SiC crystal 38. The boundary layer may include both C and Si species. After the boundary layer forms, subsequent vapor fluxes 40 must then pass through the boundary layer to reach the surface of the SiC crystal 38. The boundary layer may therefore limit the growth rate of the SiC crystal 38. To account for the boundary layer and allow the vapor flux 40 to reach the SiC crystal 38 in a more controlled manner, a tube configured to provide a disruptive gas flow to the boundary layer may be provided within the crucible 32. For example, an inert gas may be provided through a tube and toward the center of the boundary layer, thereby interrupting or reducing the thickness of the boundary layer along the center of the SiC crystal 38. In this manner, the growth rate of the SiC crystal 38 may be increased at the center without requiring a larger radial heat profile that would otherwise promote crystallographic stress. In certain embodiments, the tube may include graphite, TaC, NbC, graphite coated with one or more of TaC and NbC, and combinations thereof. The inert gas may include argon (Ar) and may be provided to the boundary layer in a pulsed or steady flow in an amount that promotes improved delivery of the vapor flux 40. The tube may be provided from the bottom of the crucible 32 or elsewhere along the interior sidewall 32' of the crucible 32 to provide controlled disruption of the boundary layer. Other approaches to disrupting the boundary layer include one or more combinations of periodically reducing and re-establishing gas pressure within the crucible 32, applying ultrasonic or low frequency pulses to the growing SiC crystal 38 and / or boundary layer, rotating the SiC crystal 38 during growth at a constant or variable speed, and configuring specific exhaust passages to direct the gas flow pattern.In further embodiments, any of the above principles describing the boundary layer may be used alone or in combination with any of the insulating layer 46 and opening 48, and / or in combination with sidewall features of the crucible 32, or in combination with any of the other principles of the present disclosure disclosed herein.

[0048] For growing larger or larger-diameter SiC boules, e.g., 200 mm and larger, maintaining the proper stoichiometric ratio of Si- and C-containing species from the vapor flux 40 across the entire surface of the SiC crystal 38 becomes increasingly more challenging. For example, the Si / C ratio may be higher at the center of the growth surface than at the edge of the growing SiC crystal 38. This may cause step bunching and terrace formation to be more extensive in the crystal 38, thereby inducing defects in the resulting crystal. Several mechanisms are provided to adjust or tailor the relative Si / C ratio in the radial direction in the growing SiC crystal 38 or to modify the surface and step free energies to reduce the creation of extensive surface terraces. It should be noted that the SiC crystal 38 may exhibit various defects if the relative Si / C ratio is too high or too low, and therefore adjustment of the Si / C ratio may be required for a particular set of growth conditions. The range of suitable Si / C ratios can be effectively reduced if there is too much variation in the Si / C ratio from the center to the edge along the radius of the growing SiC crystal 38, thus making maintaining a suitable Si / C ratio for larger diameter growth conditions significantly more challenging. As mentioned above, various approaches for achieving a Si / C ratio in the vapor flux 40 throughout the growing SiC crystal 38 may include providing one or more of the openings 48 in the insulating material 46, providing various sidewall features in the interior sidewall 32′ of the crucible 32, and various techniques for disrupting the boundary layer.

[0049] In certain embodiments, the varying parameters accordingly include varying the crystal surface temperature of the growing SiC crystal 38 and varying the composition of the incoming gas or vapor flux 40. In certain embodiments, the growth technique may include adjusting the size of Si- and C-containing species in the vapor flux 40. Additionally, the vapor flux 40 may include other atomic species in the gas phase, such as N, Ar, He, B, and / or other metallic species. The presence of the other atomic species may be provided throughout the growth of the SiC crystal 38, or during certain portions of the growth in the crucible 32 and / or at the growth surface of the SiC crystal 38. For example, the other atomic species may be provided as one or more bursts in the vapor flux 40 at the beginning, middle, and / or end of growth. In other embodiments, the other atomic species may be provided in different and variable amounts during various portions of the growth of the SiC crystal 38. In yet other embodiments, one or more of the other atomic species may be provided in one or more bursts, while others of the one or more atomic species are provided in a continuous manner during one or more portions of growth.

[0050] In certain embodiments, the electric field between the SiC crystal 38 and the source material 34 and / or the energy spectrum of the incoming radiation may be used to control growth conditions. In certain embodiments, the presence and / or distribution of through-edge and through-thread dislocations within the seed used for growth may be tailored for large diameter growth. One or more interruptions of the vapor flux 40 may be made during growth to allow for restructuring of the crystal surface of the SiC crystal 38. In certain embodiments, strain present in the SiC crystal 38 due to thermal gradients or incorporated dislocation networks may cause changes in the in-plane lattice constant, thereby altering the surface energy parameters. In certain embodiments, the doping level of the growing SiC crystal 38 may be adjusted to result in differential radiation absorption and different axial thermal gradients near the surface of the SiC crystal 38.

[0051] The principles of the present disclosure may be utilized to grow SiC crystals 38 with corresponding growth plane crystallographic orientations ranging from 0 degrees to several degrees off-axis, depending on the embodiment and for either polarity of the growth surface (e.g., C-face or Si-face). In still other embodiments, the selection of the primary crystal growth plane for SiC crystals 38 may be based on other basal planes, such as the M-plane family of hexagonal crystallographic structures.

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[0052] Other growth techniques for increasing the achievable boule height for SiC crystals with adequately low crystallographic stress, particularly for large diameter crystals, involve source material improvements. In SiC crystal growth, boule height, yield, and cost can depend on the weight of the source material that can be placed in the crucible. Thus, increasing the density of the source material allows for an increase in the weight of the source material in the crucible, thereby providing higher boule heights and yields at reduced cost. The source material may include one or more of polycrystalline SiC, single crystal SiC, polymers of Si and C, powders of Si, C, and / or SiC, pucks or chunks of amorphous or crystalline SiC, solid blocks or other solid forms of SiC, and porous meshes of SiC, among other forms of SiC. In certain embodiments, the source material for SiC growth has a density of about 0.9 to 1.3 grams per cubic centimeter (g / cm). 3 ) as used herein. Tap density (or tapped density) refers to the mass of the powder divided by the final volume of the powder after a tapping process has been used for an appropriate length of time and / or an appropriate number of taps (e.g., 1200 taps). According to embodiments of the present disclosure, the particle size distribution of the SiC powder is at least 1.5 g / cm 3 , or at least 1.8 g / cm 3 , or at least 2.0 g / cm 3 , or at least 2.5 g / cm 3 , or 1.5 g / cm 3 to 2.5 g / cm 3 or 1.8g / cm 3 to 2.5 g / cm 3 or 2.0 g / cm 3 to 2.5 g / cm3 or 1.8g / cm 3 to 3.2 g / cm 3 or 2.0 g / cm 3 to 2.5 g / cm 3 In certain embodiments, SiC powders having any of the above tap densities may be pressed to provide a tap density in the range of 0.9 g / cm with reduced contamination. 3 to 3.2 g / cm 3 range, or 1.3 g / cm 3 to 3.2 g / cm 3 or 1.5g / cm 3 to 3.2 g / cm 3 or 1.8g / cm 3 to 3.2 g / cm 3 or 1.8g / cm 3 to 2.5 g / cm 3 or 2.0 g / cm 3 to 2.5 g / cm 3 Solid SiC source materials may be formed with source densities in the range of 1000 to 15000. Such improvements to the SiC powder source material may double, triple, or even multiply the achievable boule height compared to conventional source materials.

[0053] The particle size distribution and corresponding density of conventional SiC powders used as source materials are limited due to contamination introduced during powder production. For example, conventional milling media may be used to form SiC powders, typically 10 -1 From 10 0 Contamination levels on the order of parts per million (ppm) can be observed. Such contamination levels restrict the particle size distribution in the powder to larger values, thereby resulting in lower densities (e.g., 1.3 g / cm). 3 ) is provided. According to aspects of the present disclosure, improved milling media may be provided by SiC crystals having higher purity levels compared to conventional milling media. In this regard, SiC boules may be split and processed to form milling media with significantly reduced contaminant levels.

[0054] FIG. 6 illustrates a generalized process 52 for forming SiC crystals 54 into milling media 54′ for subsequent use in milling SiC powder with increased density levels and reduced contamination. The SiC crystals 54 may embody any solid SiC crystalline material, such as a SiC boule grown according to either conventional crystal growth techniques or the crystal growth techniques of the present disclosure. In certain embodiments, the SiC crystals 54 may not necessarily achieve production targets, including doping level and crystallographic defects, among others. Rather than being scrapped, the SiC crystals 54 may be used to form milling media 54′. In other embodiments, the SiC crystals 54 are not considered production scrap material. To form the milling media 54′, the SiC crystals 54 may be separated by wire sawing into smaller cubic sections, with dimensions ranging from 5 mm by 5 mm to 15 mm by 15 mm, although other dimensions may also be provided. After separating the SiC crystals 54 into smaller milling media 54', any residual surface contamination may be removed by subjecting the milling media 54' to one or more initial powder milling operations to effectively polish the milling media 54'. Additionally, residual surface contamination may be removed by subjecting the milling media 54' to chemical etching. In certain embodiments, removal of surface contamination may be achieved by an initial powder milling operation or chemical etching, individually, or by a combination of an initial powder milling operation and chemical etching. In addition to the surface contamination removal steps described above, other cleaning techniques may be contemplated without departing from the principles of the present disclosure.

[0055] After appropriate removal of surface contamination, milling media 54' may be used to mill the reduced particle size and appropriate particle size distribution SiC powder to form a dense SiC powder source material with reduced contamination. While milling media 54' is shown in cubic form, milling media 54' may be provided in other shapes, such as round or oval balls. Additionally, milling media 54' may be used to mill other materials beyond the SiC source powder. In yet other examples, SiC powder milled with milling media 54' may be subjected to ceramic forming techniques to form the SiC powder into additional milling media of various sizes and shapes.

[0056] According to embodiments disclosed herein, one or more of the above-described improved crystal growth techniques described with respect to Figures 4-5 and the source material improvements described with respect to Figure 6, alone or in various combinations with one another, can provide large diameter SiC crystals with reduced crystallographic stress and larger boule heights. In certain embodiments, SiC crystals having a diameter of approximately 200 mm may be formed with boule heights greater than 50 mm, or greater than 100 mm, or greater than 200 mm, or in the range of 50 mm to 300 mm, or in the range of 100 mm to 300 mm, or any number in a range including various combinations of the values ​​listed above. For such boule heights, at least 50%, or at least 60%, or at least 75%, or at least 90%, or in the range of 50% to 90%, or in the range of 60% to 90%, or in the range of 50% to 75%, or in the range of 60% to 75%, or any other range bounded by any of the above values, may be configured to provide a plurality of SiC wafers, each SiC wafer of the plurality of SiC wafers comprising reduced crystallographic stress and missing atomic planes. That is, at least the above percentages of the boule height are within a range of 1000 cm / cm for an area bounded by a radius that is at least 50%, or at least 90%, or at least 95% of the total wafer radius. 3 Less than or 200cm / cm 3 Less than or 100cm / cm 3 Less than or 0cm / cm 3Or 20cm / cm 3 Any range of crystal planes starting from

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[0057] It is contemplated that any of the foregoing aspects, and / or various individual aspects and features described herein, may be combined for additional advantage. Any of the various embodiments disclosed herein may be combined with one or more other disclosed embodiments, unless indicated to the contrary herein.

[0058] Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure, and all such improvements and modifications are considered to be within the scope of the concepts disclosed herein and the following claims.

Claims

1. a dimension of at least 195 millimeters (mm) and a total linear density of basal plane dislocations associated with missing atomic planes based on X-ray topography; [Equation 1] The total linear density of basal plane dislocations aligned within 5 degrees of a group is less than 1000 centimeters per cubic centimeter (cm / cm) for a first region bounded by a radius that is at least 50% of the wafer radius of the SiC wafer from the center of the SiC wafer. ３ ) or less.

2. 10. The SiC wafer of claim 1, wherein the dimension is in the range of 195 mm to 205 mm.

3. 10. The SiC wafer of claim 1, wherein the dimension is in the range of 195 mm to 455 mm.

4. 0 cm / cm ３ to 1000 cm / cm ３ of the crystal planes in the range of [Equation 2] 2. The SiC wafer of claim 1, wherein the total linear density of basal plane dislocations aligned within 5 degrees of a group.

5. the crystal plane of the first region [Equation 3] The total linear density of basal plane dislocations aligned within 5 degrees from the group is 200 cm / cm ３ The SiC wafer of claim 1 , wherein the SiC wafer is less than 1000 nm.

6. the crystal plane of the first region [Equation 4] The total linear density of basal plane dislocations aligned within 5 degrees from the group is 100 cm / cm ３ The SiC wafer of claim 1 , wherein the SiC wafer is less than 1000 nm.

7. 10. The SiC wafer of claim 1, wherein the radius bounding the first region comprises at least 90% of the wafer radius of the SiC wafer.

8. The method further includes: forming a second region defined between the first region and a periphery of the SiC wafer; the second region being higher than the first region in terms of a crystal plane; [Equation 5] 10. The SiC wafer of claim 1, comprising a total linear density of basal plane dislocations aligned within 5 degrees of a group.

9. The crystal plane in the second region [Equation 6] The total linear density of basal plane dislocations aligned within 5 degrees from the group is 1000 cm / cm ３ The SiC wafer of claim 8 , wherein the SiC wafer is less than 1000 nm.

10. 10. The SiC wafer of claim 1, wherein the SiC wafer comprises at least one of a 4H—SiC wafer, a semi-insulating SiC wafer, and an n-type SiC wafer.

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