Systems and methods for handling asynchronous reset events while maintaining persistent memory state - Patents.com

Abstract

Described herein are techniques for handling asynchronous power transition events while maintaining persistent memory state. In some embodiments, a system may proxy asynchronous reset events through system logic, which generates an interrupt to invoke a special persistent flush interrupt handler that performs a persistent cache flush before invoking a hardware power transition. Additionally or alternatively, the system may include a hardware backup mechanism to ensure that all requested resets and power transitions in hardware are completed within a bounded window of time, regardless of the success / failure of the persistent cache flush handler.

Description

[Technical Field]

[0001] FIELD OF THE DISCLOSURE The present disclosure relates to cache management techniques, and more particularly to techniques for flushing volatile cache state upon a power loss event. [Background technology]

[0002] background Modern server designs often incorporate persistent memory (PMEM), such as Data Center Persistent Memory Modules (DCPMMs) or Non-Volatile Dual In-Line Memory Modules (NVDIMMs), into their memory architecture. Persistent memory offers several advantages over block-based persistent media, including low-latency random access times and the ability to perform remote direct memory access (RDMA) operations directly into the persistent memory.

[0003] Because storing data directly in persistent memory devices is expensive, servers with persistent memory typically support the ability to treat some volatile on-chip state as persistent to limit the number of times software needs to perform explicit store operations. A program can treat any data stored in a volatile buffer as persistent if the system can guarantee that the state of the volatile buffer is flushed to persistent memory on every reset or power transition that could cause the contents stored in the volatile buffer to be lost. One such technique for flushing volatile buffers is called asynchronous dynamic random access memory refresh (ADR), which includes the memory controller's volatile buffer in the persistent domain. With this technique, the system reserves a small amount of energy required to power the system long enough after a power loss to flush the volatile memory controller's buffer to the persistent memory device.

[0004] Another technology, referred to as enhanced ADR (eADR) or persistent cache flush (PCF), extends the volatile state that can be treated as persistent to include all processor caches and on-chip buffers. Typically, processor caches are orders of magnitude larger than the memory controller's volatile memory buffers. Therefore, the system requires significantly more energy to complete the flush process. Servers that support persistent cache flushing must include some form of auxiliary energy storage to power the system during persistent cache flush operations. Some servers include a battery backup unit (BBU) to provide enough energy to complete the flush of data from the processor cache to persistent memory after a power loss. While BBUs can store significant amounts of energy, they present many challenges, including a large footprint, limited ability to supply the high current required by server systems, thermal constraints, and additional cost.

[0005] Asynchronous hardware reset events further complicate the implementation of persistent cache flush operations. Asynchronous hardware resets are typically implemented by directly asserting a reset request pin and may be invisible to the processor or chipset's power sequencing logic. If the system allows an externally initiated reset event to trigger a hardware reset without invoking a persistent flush handler prior to the reset, persistent memory state may not be properly flushed. If applications rely on persistent cache flushes when platform hardware does not fully support them, application data may be lost or corrupted during a power disruption event.

[0006] The approaches described in this section are approaches that could be pursued, but not necessarily approaches that have been previously conceived or pursued. Thus, unless otherwise indicated, it should not be assumed that any of the approaches described in this section qualify as prior art by virtue of their inclusion in this section.

[0007] Embodiments are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings. It should be noted that references to "an" embodiment or "one" embodiment in this disclosure do not necessarily refer to the same embodiment, but rather mean "at least one" embodiment. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 illustrates a system for performing a persistent cache flush operation, according to some embodiments. [Figure 2] FIG. 10 illustrates an example set of operations for performing a persistent cache flush operation to maintain persistent memory state, according to some embodiments. [Figure 3] FIG. 1 illustrates an example set of operations for managing persistent cache flush operations in a system with multiple power sources, according to some embodiments. [Figure 4] FIG. 1 illustrates an example system for managing multiple power sources, according to some embodiments. [Figure 5] FIG. 10 is an example timing diagram illustrating staggered warning signals from separate power supply units, according to some embodiments. [Figure 6] FIG. 1 illustrates an example set of operations for handling an externally initiated asynchronous reset event, according to some embodiments. [Figure 7] FIG. 1 illustrates an example system for intercepting and processing an externally initiated asynchronous reset event, according to some embodiments. [Figure 8]FIG. 10 illustrates an example set of operations for adjusting a persistent memory operating mode, according to some embodiments. [Figure 9] FIG. 1 is a block diagram illustrating a computer system according to some embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0009] Detailed Description In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding. One or more embodiments may be practiced without these specific details. Features described in one embodiment may be combined with features described in another embodiment. In some instances, well-known structures and devices are described in block diagram form in order to avoid unnecessarily obscuring the present invention.

[0010] 1. General Overview Described herein are techniques that utilize a system power supply unit (PSU) to provide supplemental energy for flushing volatile system memory to persistent memory after a loss of alternating current (AC) power. In some embodiments, these techniques include implementing a long enough extended hold-up window after a power outage event to fully flush processor caches and memory controller buffers using available energy in the PSU's bulk capacitors. These techniques may enable flushing volatile system cache without requiring a BBU, even though the amount of available energy in the PSU is relatively small compared to most BBUs.

[0011] Many PSUs include large capacitors that allow the system to handle a temporary 10 millisecond (ms) loss of AC power. An example PSU implementation assumes a worst-case output load and provides a 10 ms timer that turns off the supply output when the timer expires. This implementation limits the longest holdup window that can be enforced by the PSU to 10 ms regardless of system power consumption, which may not be enough time to flush all system caches.

[0012] In some embodiments, the PSU is implemented to extend the hold-up window for an indefinite time window determined by the system's power consumption, rather than a fixed time window. The voltage of one or more PSU's internal bulk capacitors may be monitored, and a notification may be triggered when a programmable low-power warning threshold voltage is detected on the bulk capacitor. The system may configure a voltage threshold in the PSU to indicate that a certain minimum amount of energy required to successfully complete a cache flush operation is available. The PSU may further implement a second voltage threshold related to the minimum amount of energy required to safely sequentially voltage-down the system's power rails. Because both notifications are based on the amount of energy available in the PSU's bulk capacitors, the system may implement a configurable hold-up window, where the window duration is determined by the system's power consumption, rather than a fixed duration. As a result, the system may define an operating point to minimize energy consumption without being constrained by a fixed-duration timer.

[0013] In some embodiments, the system logic may implement an energy counter that estimates the total amount of energy available across all installed PSUs and generate an interrupt signal that invokes a persistent flush handler when the estimated total system energy reaches a threshold related to the minimum energy required to successfully complete a cache flush operation. The system logic may implement an energy counter for each PSU installed in the system. After a PSU generates a low power warning signal to the system logic, the system logic may begin decrementing the energy counter associated with that PSU at a rate proportional to the number of active power sources in the system and in the system's operating mode. The system logic may estimate the total available energy by summing the PSU counters. When the total estimated energy falls below a critical threshold, the system logic may invoke a persistent cache flush handler and generate an interrupt signal.

[0014] In some embodiments, the system is configured to reduce power consumption during the flash process to minimize the amount of energy required to complete the flash. The processor, persistent memory device, and support circuits may remain powered. Other system components not involved in the flash process, such as fans, input / output (I / O) devices, and hard disk drives, may have power disabled. The system's power control loop may further contain hooks to reduce central processing unit (CPU) power consumption, such as by reducing processor frequency.

[0015] To ensure that volatile system resources containing state considered persistent are properly flushed to persistent media prior to a system reset or power transition, in some embodiments, a persistent flush handler is executed that writes all volatile state to persistent media prior to every reset or power transition. The system may trap accesses to registers used to initiate a reset or power state transition to initiate a persistent cache flush before allowing the trapped write to complete. By trapping accesses to registers, the system can run a cache flush handler before performing the requested reset or power transition action. A similar mechanism may be implemented to handle resets and power transitions requested by platform entities external to the host subsystem.

[0016] In addition to power outages, system resets and power transitions can also occur in response to events initiated by external agents. For example, certain system errors can trigger a hardware (HW)-initiated system reset. As another example, a user can initiate a warm reset or forced brownout by pressing a button or flipping a switch. If the system allows an externally initiated reset or power transition event to trigger a hardware reset without invoking a flush handler before the reset, data in volatile processor caches or memory buffers can be lost. To ensure that externally initiated system resets or power transitions properly invoke persistent flush handlers, the system can proxy these asynchronous events through system logic to generate an interrupt to invoke a special persistent flush interrupt handler that performs a persistent cache flush before invoking the requested HW operation. Additionally or alternatively, the system can include a HW backup mechanism to ensure that all HW-requested resets and power transitions are completed within a bounded window of time, regardless of the success or failure of the persistent cache flush handler.

[0017] The techniques described herein further provide a handshake mechanism and protocol for informing the operating system of system hardware support for persistent cache flushing. The system may determine whether the hardware can support a full flush of processor caches and volatile memory buffers in the event of a power outage or asynchronous reset. If hardware support is possible, persistent cache flushing may be selectively enabled and the operating system may be notified. Once persistent cache flushing is enabled, the operating system may treat data stored in volatile processor caches as persistent data. If persistent cache flushing is disabled or not supported by the system hardware, such data may be lost due to a power loss or reset event, and the platform need not inform the operating system of its support for persistent cache flushing.

[0018] This general summary section may not include one or more embodiments described and / or recited in the claims herein.

[0019] 2. System Architecture In some embodiments, the techniques described herein are implemented in one or more computing devices that include persistent memory in their memory layout, such as server facilities or other network hosts. While example computing architectures are provided herein, these techniques are applicable to a wide variety of computing architectures depending on the particular implementation. These techniques may be used to (a) determine whether a particular combination of system components can support persistent cache flushing, (b) if supported, configure the system components to enable persistent cache flushing, and / or (c) if persistent cache flushing is enabled, execute a persistent cache flush handler prior to a power transition or reset.

[0020] 1 illustrates a system for performing a persistent cache flush operation, according to some embodiments. As shown, FIG. 1 includes PSU 102a, PSU 102b, power management subsystem 104, persistent cache flush handler 106, memory subsystem 108, CPU 116, system management module 118, system firmware 120, peripheral components 124, and operating system 122. In other embodiments, system 100 may include more or fewer components than those illustrated in FIG. 1. In some cases, the components illustrated in FIG. 1 may be local or remote from one another.

[0021] PSUs 102a and 102b convert power into a form that enables proper operation of the components of system 100. In some embodiments, PSUs 102a and 102b convert AC power into direct current (DC) energy used to power the components of system 100. Additionally or alternatively, PSUs 102a and 102b may include DC-to-DC power conversion, such as a converter that steps up or down the input voltage. PSUs 102a and 102b may be electrically coupled to other components of system 100 by one or more power rails, such as +3 volts (V), +5V, and / or +12V rails. Although two PSUs are shown, the system may have only one PSU or additional PSUs depending on the particular implementation.

[0022] Power management subsystem 104 controls the delivery of power to components of system 100 by the system PSUs. In some embodiments, power management subsystem 104 selectively powers down components during a reset or power-down event to gracefully shut down system 100. Additionally or alternatively, power management subsystem 104 may monitor voltage levels on the bulk capacitors of PSUs 102a and 102b. If the voltage levels drop below a programmable threshold, power management subsystem 104 may assert or deassert a signal to notify other components of system 100.

[0023] The memory subsystem 108 includes volatile and non-volatile storage areas. In some embodiments, the volatile storage areas include a processor cache 110 and a memory buffer 112. The processor cache 110 may include caches internal to the CPU 116, such as a level 3 (L3) cache and a level 4 (L4) cache, that may be used by the CPU 116 to reduce data access times to main memory. The memory buffer 112 may include registers and / or a memory controller of the CPU 116 that provide intermediate storage for data being transferred between separate areas. For example, a memory controller buffer may provide temporary storage for data being transferred between the processor cache 110 and main memory.

[0024] The persistent memory 114 includes one or more non-volatile memory devices, such as data center persistent memory modules (DCPMMs) and non-volatile dual in-line memory modules (NVDIMMs). In some embodiments, the persistent memory 114 is byte-addressable and resides on a memory bus, providing speeds and latencies similar to volatile DRAM, which is typically much faster than peripheral non-volatile storage devices, such as hard disks and flash drives, that are not on the memory bus. Furthermore, the persistent memory 114, like volatile DRAM, can be paged and mapped by the operating system 122, which is not common with other forms of persistent storage. The persistent memory 114 may serve as a main memory internal to the system 100. In other cases, the main memory may include one or more volatile memory modules, such as DRAM.

[0025] When a persistent cache flush handler is installed and a platform signaling mechanism is enabled, data stored within volatile memory areas, including processor cache 110 and memory buffer 112, can be treated as part of the persistent memory state, even in the event of a power outage or other power transition event. To maintain the persistent state, cache flush handler 106 performs and manages cache flush operations in response to detecting a trigger event. Without a persistent cache flush handler, a full cache flush may not be performed during a power transition event, potentially resulting in the loss of some or all of the data within the volatile memory areas. Without a persistent cache flush handler, data may be flushed from memory buffer 112 but not from processor cache 110, potentially reducing the time required to perform the flush operation.

[0026] System management module 118 comprises software and / or hardware for managing system-level operations. In some embodiments, system management module 118 includes a service processor (SP) and a CPU chipset. System management module 118 may interface with one or more sensors to monitor hardware components. Additionally or alternatively, system management module 118 may perform other functions, including trap writing to system registers, generating system management interrupts (SMIs), and monitoring the system's boot state.

[0027] System firmware 120 includes software that provides low-level control of system hardware. In some embodiments, system firmware 120 includes software such as basic input / output system (BIOS) firmware that manages startup processes, such as when the system is powered on or reset. System firmware 120 may also provide runtime services for operating system 122, such as persistent cache flush operations and management of peripheral components 124.

[0028] Operating system 122 includes software that supports operations including scheduling instructions on CPU 116, providing services to software applications, and controlling access to peripheral components 124. In some embodiments, system firmware 120, if supported by system 100, may advertise the ability to include cached contents in a persistent domain. Operating system 122 may then selectively enable or disable persistent cache flushing. When persistent cache flushing is enabled, operating system 122 may treat data stored in volatile memory, including processor cache 110 and memory buffer 112, as persistent.

[0029] Peripheral components 124 include auxiliary hardware devices such as hard disks, input devices, display devices, and / or other output devices that may be electrically coupled to other components of system 100. The power consumption of system 100 may vary in part depending on which peripheral components 124 are connected and active. A worst-case scenario for maximum power load may be calculated by assuming all hardware components, including peripheral components 124, are operating at full capacity.

[0030] 3. Persistent Cache Flush 3.1 Managing Cache Flushing Behavior During Power Disruption Events When AC power is disrupted, it may not be desirable to immediately initiate a cache flush operation because power may be restored quickly. However, if too much time passes without power being restored, there is a risk that the hold-up energy within PSU 102a and PSU 102b may be insufficient to perform a full cache flush. Thus, if persistent cache flushing is enabled, the persistent memory state may become corrupted. To maintain the persistent memory state, power management subsystem 104 may generate a warning signal when the residual energy within the bulk capacitors of PSU 102a and PSU 102b falls below a threshold level.

[0031] 2 is a diagram illustrating an example set of operations for performing a cache flush operation to maintain persistent memory state, according to some embodiments. One or more of the operations illustrated in FIG. 2 may be modified, rearranged, or omitted. Thus, the particular order of the operations illustrated in FIG. 2 should not be construed as a limitation on the scope of one or more embodiments.

[0032] 2, process 200 includes estimating the overall amount of ride-through time and hold-up time based on the system load (operation 202). The ride-through time corresponds to the estimated time that system 100 can operate without AC power while still having enough energy remaining to perform a cache flush and sequentially brown out the power rails. The hold-up time corresponds to the time to perform a full cache flush and sequentially brown out the power rails, given the system load. The estimates may be calculated based on the total system load or a reduced system load with an upper limit as described further herein.

[0033] In some embodiments, process 200 programs one or more energy thresholds based on the estimated ride-through and hold-up times (operation 204). For example, process 200 may estimate a voltage level on a PSU's bulk capacitor that will guarantee system 100, under a bounded system load, an estimated amount of hold-up time to complete cache flush and sequential power rail shutdown operations. This voltage level may then be programmed as the threshold. In other implementations, the time may be set based on the estimated ride-through time rather than a voltage / energy-based threshold.

[0034] In some embodiments, operations 202 and 204 are performed as separate processes from the remaining operations described herein. For example, operations 202 and 204 may be performed during a startup sequence of system 100 to calculate the amount of energy required and the associated voltage thresholds for each operating point. The calculations may be performed based in part on the system components sensed by the startup sequence and the estimated power requirements for operating the components during normal operation and / or during reduced-power operating modes. The startup sequence may then set programmable voltage thresholds for system 100. In other embodiments, the programmable thresholds may be set or changed by user input. For example, a system administrator may set programmable voltage thresholds for each operating point, allowing the system administrator to incorporate domain knowledge regarding the system's power requirements.

[0035] 2, process 200 includes monitoring for loss of AC power (act 206). In some embodiments, system 100 may include sensors and / or circuitry built into PSU 102a and / or PSU 102b that detect when input AC power is disrupted. In other embodiments, external circuitry and / or sensors may signal system 100 when AC power is lost.

[0036] Process 200 may detect a loss of AC power based on the monitoring circuitry (operation 208). In response, process 200 initiates a notification (operation 210). In some embodiments, the notification is initiated by deasserting the acok signal. Deasserting the acok signal provides warning that power is no longer stable and that the energy reserves within the PSU's bulk capacitors have fallen to a critical point where a system shutdown must be initiated to maintain data persistence, and writes the start of an estimated hold-up time. In other words, the notification alerts power management subsystem 104 to store enough energy in the system PSU to hold up the power rails long enough to perform a full cache flush of processor caches 110 and memory buffers 112.

[0037] In some implementations, an early warning mechanism is associated with a period of time prior to shutdown, which allows power management subsystem 104 to assume system 100 is operating at maximum load, ensuring the shortest time possible to complete a cache flush and sequentially brown out the power rails under maximum load. However, this approach can revert to traditional implementations where system shutdown is initiated prematurely, particularly during persistent cache flushes, where the maximum PSU load is significantly greater than the actual system load. In comparison, a programmable early warning threshold allows the system to trade off energy consumption before assertion of the warning signal for ride-through and energy consumption after assertion of the warning signal for hold-up.

[0038] After the notification is initiated, process 200 continues to power the system components in the first operating mode (operation 212). The system components may be powered using energy from the PSU ultracapacitors while operating in the first operating mode. In some embodiments, power may be provided as if AC power was not interrupted. In other embodiments, power saving adjustments may be made internal to system 100. For example, processor frequency or display brightness may be reduced, and / or other power saving actions may be employed. Additionally or alternatively, data may be continuously written and updated to processor cache 110 and memory buffer 112.

[0039] Process 200 further monitors the energy level within one or more system PSUs based on a programmed threshold (operation 214). In some embodiments, system 100 includes a sensor for monitoring the voltage of the PSU's bulk capacitor. Because the bulk capacitor has a fixed capacitance value, the bulk capacitor voltage can be used as a proxy for the PSU energy level when AC power is disrupted. In other embodiments, the energy level can be calculated as a function of the bulk capacitor's capacitance value and the measured voltage.

[0040] Process 200 further determines whether the energy level of one or more PSUs meets a threshold (operation 216). For example, process 200 may determine whether the threshold is met if the measured voltage of one or more bulk capacitors drops below the voltage threshold programmed in operation 204. If the threshold is not met, process 200 may continue to monitor the PSU energy level until power is restored or until the voltage of the PSU bulk capacitor drops below the programmable threshold. Once the threshold is met, a warning signal may be asserted to initiate a cache flush and voltage reduction sequence.

[0041] In some embodiments, process 200 enters a second operating mode by reducing system load to minimize power consumption (operation 218). During this phase, power management subsystem 104 may reduce the voltage of components not involved in the cache flush operation. For example, peripheral components 124 that power management subsystem 104 may reduce the voltage of may include hard disk drives, fans, displays, Peripheral Component Interconnect Express (PCIe) devices, and / or other peripheral hardware. Additionally or alternatively, power management subsystem 104 may reduce the clock speed or frequency of CPU 116 to minimize power consumption.

[0042] Process 200 further performs a cache flush (operation 220). During the cache flush operation, CPU 116 may write data stored in processor cache 110 and memory buffer 112 to persistent memory 114 to maintain the persistent state of the data. In some embodiments, process 200 may continue to monitor the PSU energy level during this operation. If the PSU energy level drops below a second voltage threshold, process 200 may initiate a voltage-down sequence even if the cache flush is not complete to prevent all power rails from failing simultaneously. The second voltage threshold may be programmed to a level much lower than the first threshold that leaves enough energy to sequentially voltage-down the power rails.

[0043] Once the cache flush is complete, process 200 powers down the remaining system components (operation 224). Process 200 may power down the power rails in sequence to gracefully shut down system 100. The power rail power down sequence may vary from system to system.

[0044] 2 can maintain persistent memory state without having to install or rely on energy from a BBU. Instead, the energy within one or more PSU's bulk capacitors can be managed by the power management subsystem 104 to ensure persistence. Additionally, by having the power management subsystem 104 understand the runtime power load, variable ride-through and hold-up times allow for more efficient and effective use of stored energy.

[0045] 3.2 Managing Multiple Power Supply Units When a system has multiple PSUs and one or more of the PSUs lose AC power, the amount of energy from a single PSU may be insufficient to complete a cache flush operation. However, the combined energy of the multiple PSUs may be sufficient to complete a cache flush to maintain a persistent state of the data. When there are multiple PSUs, the power management subsystem 104 may monitor the total energy available across all power sources. When the combined voltage level crosses a threshold to trigger a cache flush operation, the power management system 104 may signal an insufficient power warning.

[0046] In some embodiments, the power management subsystem 104 detects the following events for each PSU it manages:

[0047] Loss of AC power, which can be detected by deassertion of the acok signal. Upon receiving this signal from one or more PSUs, the power management subsystem 104 enters a first operating mode and reduces power during the ride-through window if AC power is restored.

[0048] An indication that the energy or voltage level of a PSU has crossed a first threshold, which may be detected by the assertion of the vwarn signal. The power management subsystem 104 combines the voltage warning information from all PSUs to determine when to enter the second operating mode, thereby causing the persistent cache flush handler 106 to initiate a cache flush operation. During the second operating mode, the power management system 104 may further reduce power as previously described.

[0049] An indication that the PSU energy or voltage level has crossed a second threshold, which may be detected by the assertion of the pwrok signal. The power management subsystem 104 may combine the information in the pwrok signal to determine whether to immediately reduce the system voltage. If the PSU energy level drops further and there is not enough energy remaining to safely sequentially reduce the power rail voltage, a shutdown may be initiated.

[0050] In some embodiments, in the event of AC power loss, the power management subsystem 104 maintains a set of per-PSU counters in each PSU to track estimated energy levels. The initial value of the per-PSU counters may be hard-coded or programmable to correspond to the amount of energy available at the PSU when it asserts vwarn. When the power management subsystem 104 detects that a PSU has asserted vwarn, it may begin decrementing the associated PSU's energy counter at a rate proportional to the number of active power supplies in the system and the maximum load per power supply. For example, if there is one active PSU and the maximum load is 1200 watts (W), the counter may be decremented at 1.2 joules (J) / ms. If there are two active power supplies and the load per power supply is 600 W, the energy counter may be decremented at 600 mJ / ms. If there are four active power supplies, the energy counter may be decremented at 300 mJ / ms. As another example, if the worst-case system load drops to 1000 W, the counter decrement rate can be changed to 1 J / ms for one power supply, 500 mJ / ms for two power supplies, and 250 mJ / ms for four power supplies. The counter can be adjusted to provide maximum ride-through time while maintaining enough energy to maintain persistent cache flushes for extended power outage periods.

[0051] 3 illustrates an example set of operations for managing persistent cache flush operations in a system with multiple power sources, according to some embodiments. One or more of the operations illustrated in FIG. 3 may be modified, rearranged, or omitted. Thus, the particular order of the operations illustrated in FIG. 3 should not be construed as a limitation on the scope of one or more embodiments.

[0052] 3, process 300 detects assertion of one or more vwarn signals from one or more PSUs (operation 302). As mentioned above, each PSU may be configured to assert a vwarn signal when AC power is lost and the energy in the PSU bulk capacitor falls below a threshold, which may be programmable.

[0053] In response to detecting the vwarn signal, process 300 starts one or more associated countdown timers (operation 304). In some embodiments, a countdown timer tracks the estimated energy level for each PSU that asserts the vwarn signal. Process 300 may decrement a counter at a rate proportional to the number of PSUs in the system and the maximum load per power supply. In other embodiments, other mechanisms may be used to track the internal energy levels of the PSUs. For example, rather than decrementing a counter, process 300 may increment the counter until a threshold is reached or may use other tracking logic.

[0054] Additionally or alternatively, process 300 may cause system 100 to enter a reduced power mode in response to detecting one or more vwarn signals. The reduced power operating mode may be initiated by one signal or a threshold number of signals, depending on the particular implementation. In other embodiments, process 300 may gradually reduce power with each new detected signal. For example, process 300 may gradually reduce the CPU frequency for each new vwarn signal and / or initiate or intensify other power saving actions as previously described.

[0055] The process 300 further monitors (a) the total energy level of the combined PSUs based on a countdown timer (or other tracking logic), (b) the assertion of additional vwarn signals from other PSUs, and (c) the assertion of pwrok signals from the PSUs (operation 306). If additional vwarn signals are detected, the process 300 starts a countdown timer associated with the PSU that asserted the signal (operation 304).

[0056] If the total energy level meets a first threshold, process 300 performs a cache flush operation (operation 308). For example, process 300 may determine whether the total energy level of all PSUs has dropped below a minimum threshold. During the cache flush operation, CPU 116 may write data stored in processor cache 110 and memory buffer 112 to persistent memory 114 to maintain the persistent state of the data. In some embodiments, process 300 may continue to monitor the PSU energy level during this operation.

[0057] Once the cache flush operation is complete or the PSU drops below a second voltage threshold number that activates one or more pwrok signals, process 300 sequentially reduces the voltage of the power rails (operation 310). When a pwrok signal is detected, process 300 may initiate a voltage reduction sequence to prevent the power rails from all simultaneously failing, even if the cache flush is not complete. The second voltage threshold may be programmed to a level much lower than the first threshold that leaves enough energy to sequentially voltage down the power rails.

[0058] FIG. 4 illustrates an exemplary system 400 for managing multiple power sources, according to some embodiments. System 400 includes PSUs 402 and 404. However, the number of PSUs may vary depending on the particular implementation. One or more large-capacity capacitors, such as capacitor 406, may be included in each PSU to store electrostatic energy obtained from the connected AC power network. Capacitor-based storage allows the PSUs to be implemented in a smaller footprint than BBUs and provides faster charge and discharge rates. PSUs 402 and 404 may be connected to the same AC power network or separate AC power networks, depending on the particular implementation. When connected to separate AC power networks, if one PSU loses AC power, the other PSU continues to be powered by the separate AC network. In this scenario, each PSU may provide a separate acok signal (not shown) to power management subsystem 408. These signals may be deasserted separately by the individual PSUs when AC power is lost to notify the PSU that lost power. In other cases, the deassertion of the acok signal may signal that a group or all of the PSUs have lost AC power.

[0059] In some embodiments, each PSU asserts a vwarn signal when the energy in its bulk capacitor (e.g., bulk capacitor 406) reaches a threshold. The vwarn signal thus notifies power management subsystem 408 that the available energy of the associated PSU has reached a first threshold level. Power management subsystem 408 maintains a separate energy counter for each PSU that is activated when the associated PSU asserts the vwarn signal. For example, if PSU 402 asserts the vwarn signal, power management subsystem 408 may then decrement energy counter 410 at a rate proportional to the number of PSUs in the system and the maximum load per power supply. Energy counter 412 is managed independently of energy counter 410 (a vwarn signal from a PSU does not activate counters for other, unrelated PSUs) and is decremented in response to PSU 404 asserting the vwarn signal. An adder 414 included in the power management subsystem 408 sums together the estimated energy counts of each PSU to calculate a total energy counter 416 .

[0060] In some embodiments, the system threshold may be programmable and vary depending on the particular implementation, and the power management subsystem monitors a total energy counter 416 to determine whether the total energy of all PSUs drops below the system threshold. When the threshold is reached, the power management subsystem 408 asserts an SMI signal, halting the current task being performed by the CPU / chipset 422 in preparation for a persistent cache flush and reset. A persistent cache flush handler 424 may initiate the aforementioned persistent cache flush operation in response to the SMI.

[0061] 5 illustrates an example timing diagram 500 showing staggered warning signals from various power supply units, according to some embodiments. The top half of diagram 500 represents the timing of a power shortage, and the bottom half represents potential power reductions that system 100 may implement in response to an impending power shortage. Diagram 500 assumes worst-case behavior, where the system operates at full load until a power shortage cache flush is triggered. Once a power shortage cache flush is triggered, the system's power consumption is reduced to minimize the load as it completes the flush operation.

[0062] The variables in diagram 500 may be defined as follows: ·t psu0_v1warn - When the first PSU asserts v1warn ·t psu1_v1warn - When the second PSU asserts v1warn ·t flush_start - the point at which the power management subsystem 104 initiates a power-down flush operation ·t psu1_pwrok - The second PSU deasserts pwrok and the system 100 begins a brownout sequence. T v1warn_delay -t psu0_v1warn and t psu1_v1warn The time delay between T v1warn_debounce -t psu1_v1warn From t flush_start Time delay until T v1warn - E of power supply under maximum load v1warn Time to use all your energy P max - Maximum system load P throttle - System load after the first PSU asserts v1warn P debounce - System load after all PSUs assert v1warn P flush - System load after underpower flash operation is initiated E v1warn- Usable energy available in the PSU after v1warn assertion and before pwrok deassertion E pwrok - Usable energy available in the PSU after pwrok deassertion before the primary power rail is lost E psu0_reserve - The second PSU is psu1_v1warn After asserting v1warn at E reserve - The total available energy remaining in all PSUs after all PSUs assert v1warn until the last PSU deasserts pwrok E v1warn_delay - System 100 is t v1warn_delay Energy consumed during E flush - Low power The energy required to successfully complete the flash operation N - Number of active PSUs powering the system Referring to FIG. 5, the first PSU psu0_v1warn When v1warn is asserted in the v1warn +E pwrok ) energy is available. There are N active PSUs, and the system load is distributed among all active PSUs in the system. A second PSU is installed at a time lag of t psu1_v1warn Assert v1warn at t psu0_v1warn and t psu1_v1warn The amount of energy consumed during v1warn_delay It is expressed as:

[0063] The system 100 draws energy from all N active PSUs from the time the first power supply asserts v1warn until the second power supply asserts v1warn. After the first PSU asserts v1warn, it v1warn +E pwrok) is consumed. When the second CPU asserts v1warn, the remaining energy in the first PSU is E psu0reserve It is expressed as:

[0064] T v1warn_delay If v1warn is small, the second PSU will deassert pwrok before the system consumes all of the energy from the first power supply. In the worst case, when both power supplies simultaneously assert v1warn, both power supplies will simultaneously deassert pwrok. Under these circumstances, when all power supplies deassert pwrok, the system will shut down, and the first power supply's E pwrok To allow for this possibility, the system 100 may be configured to reduce the E pwrok It may be constructed with the assumption that energy is not available.

[0065] To fully utilize the energy of both power sources, the system 100 may be configured to not immediately initiate a brownout flush when the second PSU asserts v1warn. Instead, the system 100 may delay initiating the flush until the amount of energy stored in all active PSUs equals the amount required to complete the flush. The system 100 may use E to store enough energy to complete the cache flush operation. reserve ≧E flush It may be further configured to ensure:

[0066] If both PSUs assert v1warn simultaneously, T v1warn_delay = 0, and T v1warn_debounce =T v1warn If both PSUs assert v1warn far apart in time, T v1warn_debounce = 0 and an underpower flash can be initiated as soon as the second PSU asserts v1warn. The power management subsystem 104 can program the energy / voltage thresholds accordingly.

[0067] 4. Managing externally initiated asynchronous reset events Power disruption events are not the only cause of a system shutdown or reset. In some cases, a system error or user action can initiate a system shutdown or reset. For these externally initiated asynchronous events, A / C power may be relatively constant, so monitoring for power loss may be insufficient to maintain persistent memory state. Asynchronous hardware resets are typically performed by directly asserting a reset request pin, which initiates a reset in the HW and may not provide the ability to invoke a software cache flush handler prior to the reset. In some embodiments, to prevent data loss, the board logic is configured to generate an SMI signal that initiates a cache flush when an externally initiated reset request is detected.

[0068] 6 illustrates an example set of operations for handling an externally initiated asynchronous reset event, according to some embodiments. One or more of the operations illustrated in FIG. 6 may be entirely modified, rearranged, or omitted. Thus, the particular order of the operations illustrated in FIG. 6 should not be construed as a limitation on the scope of one or more embodiments.

[0069] 6, process 600 intercepts the assertion of a HW reset request signal (operation 602). In some embodiments, platform-initiated reset requests, including reset requests initiated by system management module 118, are proxied through power management subsystem 104. This allows system 100 to actuate persistent cache flush handler 106 before performing the requested reset or power transition action.

[0070] In some embodiments, process 600 determines whether persistent cache flushing is enabled (operation 604). As described further below, system firmware (or other system logic) can selectively enable or disable persistent cache flushing to configure whether data in processor cache 110 is included in the persistent memory state.

[0071] If persistent cache flushing is not enabled, then process 600 routes the request to the reset pin (operation 606). In some embodiments, power management subsystem 104 routes the request to the system chipset, which may initiate a HW reset sequence.

[0072] If persistent cache flushing is enabled, process 600 routes the request to system management module 118 (operation 608). In this case, the reset pin is not immediately asserted in response to a platform or user initiated reset to allow time for the software-based cache flush handler to be invoked.

[0073] In some embodiments, process 600 generates an SMI signal to transition system 100 into system management mode (operation 610). The SMI signal may be asserted by system management module 118 using a special signal line coupled directly to CPU 116. The SMI signal may cause system firmware 120 (e.g., BIOS) to stop tasks currently being performed by CPU 116 in preparation for a cache flush and reset.

[0074] In some embodiments, when persistent cache flush is enabled, system firmware 120 (e.g., BIOS) then configures an internal general-purpose input / output (GPIO) pin of system management module 118 as a trigger for an SMI. The GPIO pin may be used to notify system firmware 120 when a cache flush followed by a warm reset is performed. This GPIO may be different from the GPIO used to notify the chipset of an impending power outage, to signal the persistent cache flush handler to exit with a requested warm reset rather than a power off.

[0075] Process 600 then performs a cache flush operation (operation 612). In response to the SMI signal, system firmware 120 may invoke cache flush handler 106 to manage the cache flush operation, as previously described. Accordingly, data is transferred from volatile memory, such as processor cache 110 and memory buffer 112, to persistent memory 114, thereby maintaining persistent state.

[0076] The process 600 further determines whether the flush is complete (act 614). The persistent cache flush handler 106 may assert or notify a signal when data in the processor cache 110 and memory buffer 112 has been written to the persistent memory 114.

[0077] Once the cache flush is complete, process 600 generates a reset request (operation 622). For example, persistent cache flush handler 106 may initiate a system reset by writing a particular value to a register of a particular IO port / PCH (e.g., writing 0x06 to port CF9) or by requesting system logic to assert a HW reset request signal to the chipset.

[0078] If the flush is not complete, process 600 may determine whether a timeout has been reached (operation 616). For example, process 600 may allow one second or another threshold period, configurable by system 100, for the flush operation to complete. In some cases, system conditions associated with a reset event may prevent the flush from completing. Enforcing a timeout may prevent system 100 from entering a state in which a warm reset cannot be performed.

[0079] If the timeout is reached, process 600 generates a reset request signal directly to the chipset (operation 618). The reset request in operation 622 may be a direct reset request to the chipset or a software-based request. Thus, the mechanism for resetting the system may differ based on whether the flash completed successfully.

[0080] In response to the reset signal, the system 100 is then reset (operation 420). A reset in this situation may cause the system 100 to shut down or restart.

[0081] 7 shows an example system 700 for intercepting and processing externally initiated asynchronous reset events, according to some embodiments. System 700 includes a system management module 702, which may be implemented by programmable hardware, such as a field programmable gate array (FPGA), or other hardware components (or a combination of hardware and software), as described further below. System management module 702 acts as a proxy, intercepting the assertion of a hardware request signal, which may be initiated by a user pressing a reset button or a reset request asserted by a board management controller (BMC) or debug header.

[0082] The system management module 702 includes a logic gate 704 that routes the asserted reset request signal to a demultiplexer 706. A select wire coupled to the demultiplexer 706 may be set based on whether persistent cache flushing is enabled or disabled. A "0" or low voltage state represents a memory operating mode with persistent cache flushing disabled, in which data in the processor cache 110 and memory buffer 112 is not managed as part of the persistent domain. A "1" or high voltage state represents a persistent cache operating mode with persistent cache flushing enabled, in which data in the processor cache 110 and memory buffer 112 is part of the persistent domain. However, the values ​​on the select wires may be swapped depending on the particular implementation.

[0083] When persistent cache flushing is disabled, the system management module 702 then asserts a request reset interrupt signal on a pin electrically coupled to the CPU / chipset 712. In response, the reset control logic 714 of the CPU / chipset 712 stops the current task being executed and initiates a hardware reset, which may include sending a signal to reset the finite state machine (FSM) 710. The reset of the FSM 710 may voltage down the power rails in a particular order to avoid damage to the hardware components. As mentioned above, the order in which the power rails are voltage down may vary depending on the system architecture.

[0084] When persistent cache flushing is enabled, system management module 702 asserts an SMI using a special signal line that is directly coupled to another pin on CPU / chipset 712. This signal line is different from the previously described line used to perform a HW reset when persistent cache flushing is disabled. In response to detecting an SMI, CPU / chipset 712 sends a software-based request to power-down flush handler 716 to initiate a persistent cache flush.

[0085] A persistent cache flush handler 716 responds to the request by initiating a persistent cache flush operation and transferring data from the processor cache and memory buffers to the persistent storage medium. Upon successful completion of the cache flush, the power-down flush handler 716 sends a software reset request to the reset control logic 714, which may initiate a power-down sequence as previously described.

[0086] When persistent cache flushing is enabled, the system management module 702 also initializes a timer 708. The timer 708 may decrement or increment until it is canceled or reaches a timeout value. The count may be canceled in response to detecting the assertion of a signal on an input pin that resets the FSM 710. This signal indicates that the power-down flush handler 716 has successfully flushed the processor cache and memory buffers to persistent storage, and a reset sequence is initiated. If the timer reaches the timeout value before being canceled, then the system management module 702 directly asserts the rst_req_in pin of the CPU / chipset 712 to initiate a HW reset.

[0087] 5. Coordination of persistent cache flushing states among system components System boot firmware may expose persistent cache flush support through a user-configurable option. However, boot firmware may be deployed across a wide variety of hardware platforms, and the presentation of this option may not imply that the particular platform hardware can support persistent cache flush. Whether a platform can support persistent cache flush may depend on the hardware configuration, the presence and / or health of an energy storage module, and the capabilities of the underlying hardware components. In some embodiments, components of system 100 (a) determine whether the hardware has sufficient capabilities to support persistent cache flush, (b) selectively enable / disable persistent cache flush, (c) configure system components to support persistent cache flush when persistent cache flush is enabled, and (d) perform a handshake to communicate to the operating system whether persistent cache flush was successfully enabled.

[0088] 8 illustrates an example set of operations for adjusting a persistent memory operating mode, according to some embodiments. One or more of the operations illustrated in FIG. 8 may be modified, rearranged, or omitted. Thus, the particular order of the operations illustrated in FIG. 8 should not be construed as a limitation on the scope of one or more embodiments.

[0089] 8, process 800 begins a boot sequence (operation 802). In some embodiments, the boot sequence loads system firmware 120, which may include BIOS firmware. System firmware 120 may be configured to expose a user-configurable option regarding persistent cache flushing. For example, system firmware 120 may present a prompt to the user asking whether to enable persistent cache flushing, or the user may navigate a user interface, such as a BIOS setup utility screen.

[0090] In some embodiments, the user interface exposes multiple settings for a "Persistence Domain" setup option to configure whether the platform operates in ADR mode or persistent cache flush mode. For example, the user interface may expose an option to select a "Memory Controller" setting or a "CPU Cache Tier" setting. The "Memory Controller" setting enables ADR but disables persistent cache flushing. When this setting is selected, memory buffers 112 are flushed during a power-down event, but the flush operation does not apply to processor cache 110. In some embodiments, the system hardware may be configured with this setting by default.

[0091] The "CPU Cache Hierarchy" setting enables persistent cache flushing. Thus, when this option is selected, data in memory buffer 112 and processor cache 110 is flushed during a power loss event if the platform hardware supports persistent cache flush operations.

[0092] Additionally or alternatively, other settings may be supported. For example, a "standard domain" setting may be selected in which cache data is not flushed during a power loss event. As previously described, the user may select a preferred setting via a user interface. If the user does not select a setting, system firmware 120 may select a default setting that varies depending on the particular implementation.

[0093] In some embodiments, system firmware 120 checks to determine whether persistent cache mode was selected by a user or is the default (operation 804). Even if an option is selected, in some cases, the platform hardware may not support persistent cache flush operations. Furthermore, system hardware may change over time as components are added, removed, age, and / or fail.

[0094] If persistent cache mode is not selected, system firmware 120 continues the boot sequence without signaling support for persistent cache mode (operation 822). The boot sequence may include steps of initializing hardware components, loading the operating system, and / or processing outstanding system boot files. The boot sequence may continue without performing hardware capability checks, which are described further below.

[0095] If persistent cache mode is selected, system firmware 120 sends a request to system management module 118 to determine whether system 100 can support persistent cache flush operations (operation 806).

[0096] In response to the request, system management module 118 evaluates the hardware capabilities of system 100 (operation 808). In some embodiments, system management module 118 handshakes with one or more hardware components to determine settings, configurations, and / or other information that indicate whether persistent cache flushing is supported. For example, firmware that may be included in hardware components that are connected during a boot sequence provides system firmware with a list of features that the component supports. System management module 118 scans the provided feature list and / or other information to determine whether features that support persistent cache flushing are present.

[0097] In some embodiments, evaluating the hardware capabilities of system 100 includes determining whether PSU 102a and / or PSU 102b support generating a pre-warning signal and configuring a programmable vwarn threshold. For example, system management module 118 may determine whether PSU 402 includes a pin for asserting a vwarn signal. If the PSU does not have these capabilities, system management module 118 may determine that the platform hardware does not support persistent cache flush operations.

[0098] Additionally or alternatively, system management module 118 may determine whether power management subsystem 104 includes logic for detecting a vwarn signal, monitoring the combined energy level of multiple PSUs, and / or initiating an interrupt when the overall system energy level is below a threshold. If power management subsystem 104 does not have these capabilities, system management module 118 may determine that the platform hardware does not support persistent cache flush operations.

[0099] Additionally or alternatively, system management module 118 may evaluate other hardware capabilities. For example, system management module 118 may evaluate system 100 to determine whether system 100 supports the ability to configure GPIO pins to intercept reset signals and handle asynchronous reset events. As another example, system management module 118 may evaluate CPU 116 to determine whether CPU 116 includes a special signal line for invoking a persistent cache flush handler.

[0100] Additionally or alternatively, system management module 118 may determine whether any BBUs that support persistent cache flush operations are installed. If a BBU is installed, system management module 118 may determine that persistent cache flush is supported even if the PSU architecture does not. On the other hand, system management module 118 may determine that persistent cache flush is not supported if a BBU is not installed and the PSU and / or power management subsystem does not support persistent cache flush operations.

[0101] Additionally or alternatively, system management module 118 may evaluate other hardware capabilities. For example, system management module 118 may evaluate the capacity of auxiliary energy storage devices, such as BBUs, installed on the platform to determine whether these devices provide sufficient energy to power active system components during the flush process. Additionally or alternatively, system management module 118 may evaluate battery health, such as by measuring battery impedance, to determine whether the platform hardware supports persistent cache flushing.

[0102] Based on the evaluation, system management module 118 returns a response to system firmware 120 indicating whether the platform can support persistent cache flushing (operation 810). This response may authorize system firmware 120 to enable persistent cache flushing (if supported). Otherwise, system management module 118 does not authorize system firmware 120 to enable persistent cache flushing.

[0103] When system firmware 120 receives the response, it determines whether system 100 supports persistent cache flushing (act 812).

[0104] If the platform hardware does not support persistent cache flushing, system firmware 120 continues the boot sequence without informing operating system 122 of support for persistent cache flushing (operation 822). When persistent cache flushing is not informed or enabled, operating system 122 may prevent applications from attempting to treat processor cache as persistent in system 100.

[0105] If persistent cache flushing is supported, system firmware 120 and / or system management module 118 configures system components to support persistent cache flushing operations (operation 814). For example, system firmware 120 may establish GPIO pins, initialize per-PSU timers, configure the PSUs, and otherwise configure system hardware / software to perform cache flushing operations, as previously described.

[0106] System firmware 120 and / or system management module 118 then inform operating system 122 of support for persistent cache flush (operation 816). In some embodiments, system firmware 120 may provide operating system 122 with a list of supported features and / or configuration settings. The list may include an entry indicating that persistent cache flush is supported and enabled. However, the manner in which support is announced may vary depending on the particular implementation.

[0107] Based on the indication, operating system 122 detects that persistent cache mode is supported (act 818). For example, during the boot sequence, operating system 122 scans a list of supported features to determine whether system firmware or system management module 118 has indicated support for persistent cache flushing.

[0108] If persistent cache mode is enabled and supported by the platform hardware, operating system 122 informs one or more applications of the persistent cache mode (operation 820). In some embodiments, an application queries operating system 122 to determine whether persistent cache mode is available and supported. Operating system 122 may provide a response indicating whether the application may rely on persistent cache. Depending on whether persistent cache is enabled and supported, an application may implement different logic. For example, if enabled, a database application may treat reads and writes as committed without performing complex software-based checks, simplifying application code and allowing reads and writes to be executed more efficiently.

[0109] When system components change, process 800 can be repeated to determine whether support for persistent cache mode has changed. A change in hardware, such as installing a BBU or upgrading a PSU, may cause system 100 to advertise support for persistent cache flushing if it was not previously supported. In other cases, the advertisement can be removed if a component, such as a BBU, is removed or fails.

[0110] 6. Hardware Implementation According to one embodiment, the techniques described herein are implemented by one or more special-purpose computing devices. The special-purpose computing devices may be hard-wired to execute the techniques, or may include digital electronic devices such as one or more application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or network processing units (NPUs) permanently programmed to execute the techniques, or may include one or more general-purpose hardware processors programmed to execute the techniques according to program instructions in firmware, memory, other storage, or a combination. Such special-purpose computing devices may also combine custom hard-wired logic, ASICs, FPGAs, or NPUs with custom programs to accomplish the techniques. The special-purpose computing devices may be desktop computer systems, portable computer systems, handheld devices, networking devices, or other devices incorporating hard-wired and / or program logic to implement the techniques.

[0111] 9 is a block diagram illustrating a computer system 900 in which one embodiment of the present invention may be implemented. Computer system 900 includes a bus 902 or other communication mechanism for communicating information, and a hardware processor 904 coupled with bus 902 for processing information. Hardware processor 904 may be, for example, a general-purpose microprocessor.

[0112] Computer system 900 also includes a main memory 906, such as a random access memory (RAM) or other dynamic storage device, coupled to bus 902 for storing information and instructions executed by processor 904. Main memory 906 may also be used for storing temporary variables or other intermediate information during execution of instructions by processor 904. When such instructions are stored in a non-transitory storage medium accessible to processor 904, computer system 900 becomes a special-purpose machine custom-tailored to perform the operations specified in those instructions.

[0113] Computer system 900 further includes a read-only memory (ROM) 908 or other static storage device coupled to bus 902 for storing static information and instructions for processor 904. A storage device 910, such as a magnetic or optical disk, is provided and coupled to bus 902 for storing information and instructions.

[0114] Computer system 900 may be coupled via bus 902 to a display 912, such as a cathode ray tube (CRT) or light emitting diode (LED) monitor, for displaying information to a computer user. Input device 914, which may include alphanumeric and other keys, is coupled to bus 902 for communicating information and command selections to processor 904. Another type of user input device is a cursor control 916, such as a mouse, trackball, touch screen, or cursor direction keys, for communicating directional information and command selections to processor 904 and for controlling cursor movement on display 912. Input device 914 typically has two degrees of freedom in two axes, a first axis (e.g., x) and a second axis (e.g., y), to specify a position in a plane.

[0115] Computer system 900 may be combined with custom hardwired logic, one or more ASICs or FPGAs, firmware and / or program logic to form or be programmed into a special purpose machine to implement the techniques described herein. According to one embodiment, the techniques herein are performed by computer system 900 in response to processor 904 executing one or more sequences of one or more instructions contained in main memory 906. Such instructions may be read into main memory 906 from another storage medium, such as storage device 910. Processor 904 executes the sequences of instructions contained in main memory 906 to perform the process steps described herein. In alternative embodiments, hardwired circuitry may be used in place of or in combination with software instructions.

[0116] The term "storage medium," as used herein, refers to any non-transitory medium that stores data and / or instructions that cause a machine to operate in a specific fashion. Such storage media may comprise non-volatile media and / or volatile media. Non-volatile media include, for example, optical or magnetic disks, such as storage device 910. Volatile media include dynamic memory, such as main memory 906. Common forms of storage media include, for example, floppy disks, flexible disks, hard disks, solid-state drives, magnetic tape or other magnetic data storage media, CD-ROMs, other optical data storage media, any physical media with a pattern of holes, RAM, PROMs, and EPROMs, FLASH-EPROMs, NVRAMs, other memory chips or cartridges, content-addressable memories (CAMs), and ternary content-addressable memories (TCAMs).

[0117] Storage media are distinct from, but may be used in the context of, transmission media. Transmission media participates in transferring information between storage media. For example, transmission media include coaxial cables, copper wire, and fiber optics, including the wires that comprise bus 902. Transmission media can also take the form of acoustic or light waves, such as those generated during radio wave or infrared data communications.

[0118] Various forms of media may be involved in carrying one or more sequences of one or more instructions to processor 904 for execution. For example, the instructions may initially be carried on a magnetic disk or solid-state drive of a remote computer. The remote computer may load the instructions into its dynamic memory and send the instructions over a network line, such as a telephone line, fiber optic cable, or coaxial cable using a modem. A modem local to computer system 900 may receive the data on the network line and use an infrared transmitter to convert the data to an infrared signal. An infrared detector can receive the data carried in the infrared signal and appropriate circuitry can place the data on bus 902. Bus 902 carries the data to main memory 906, from which processor 904 retrieves and executes the instructions. The instructions received by main memory 906 may optionally be stored on storage device 910 either before or after execution by processor 904.

[0119] Computer system 900 also includes a communication interface 918 coupled to bus 902. The communication interface 918 provides a two-way data communication coupling to a network link 920 that is connected to a local network 922. For example, communication interface 918 may be an Integrated Services Digital Network (ISDN) card, a cable modem, a satellite modem, or a modem that provides a data communication connection to a corresponding type of telephone line. As another example, communication interface 918 may be a local area network (LAN) card to provide a data communication connection to a compatible LAN. A wireless link may also be implemented. In any such implementation, communication interface 918 sends and receives electrical, electromagnetic or optical signals that carry digital data streams representing various types of information.

[0120] Network link 920 typically provides data communication through one or more networks to other data devices. For example, network link 920 may provide a connection through local network 922 to data equipment operated by a host computer 924 or by an Internet Service Provider (ISP) 926. ISP 926, in turn, provides data communication services through the global packet data communication network 928 now commonly referred to as the "Internet." Local network 922 and Internet 928 both use electrical, electromagnetic or optical signals that carry digital data streams. The signals through the various networks and the signals on network link 920 and through communication interface 918 are exemplary forms of transmission media, carrying the digital data to and from computer system 900.

[0121] Computer system 900 can send messages and receive data, including program code, through the network(s), network link 920 and communication interface 918. In the Internet example, a server 930 might transmit a requested code for an application program through Internet 928, ISP 926, local network 922 and communication interface 918.

[0122] The code may be executed by processor 904 as it is received, and / or stored in storage device 910, or other non-volatile storage for later execution.

[0123] 7. Other expansion parts Embodiments are directed to systems having one or more devices including a hardware processor, the devices configured to perform any of the operations described herein and / or recited in any of the claims below.

[0124] In one embodiment, the non-transitory computer-readable storage medium contains instructions that, when executed by one or more hardware processors, perform any of the operations described herein and / or recited in any of the claims.

[0125] Any combination of the features and functionality described herein may be used by one or more embodiments. In the foregoing specification, embodiments are described with reference to numerous specific details that may vary from implementation to implementation. Accordingly, the specification and drawings should be regarded as illustrative rather than restrictive. The sole and exclusive indication of the scope of the invention, and what the applicant intends to be the scope of the invention, is the literal scope equivalent of the set of claims in the specific form of the claims issued by this application, including any subsequent amendments.

Claims

1. identifying a request to initiate a reset or power transition in a computer system; determining whether a first mode is enabled in the computer system to perform a persistent cache flush in response to identifying the request; generating an interrupt in response to determining that the first mode is enabled to initiate a persistent cache flush operation; delaying the reset or the power transition until the persistent cache flush operation is completed or a timeout expires; and (b) when operating in a second mode, proxying the source of the power transition event through system logic configured to: (a) generate the interrupt that initiates the persistent cache flush operation and delay a power transition event when in the first mode; and (b) route a request to perform a power transition directly to a chipset of the computer system when operating in a second mode.

2. The method of claim 1, further comprising: identifying a request to initiate a reset or power transition in a computer system; determining whether a first mode is enabled in the computer system to perform a persistent cache flush in response to identifying the request; generating an interrupt in response to determining that the first mode is enabled to initiate a persistent cache flush operation; delaying the reset or the power transition until the persistent cache flush operation is completed or a timeout expires; When the first mode is disabled, a reset request is routed to a reset pin of the computer system without flushing a processor cache.

3. 10. The method of claim 1, wherein the request to initiate the reset or the power transition is detected based on an error in the computer system.

4. 10. The method of claim 1, wherein the request to initiate the reset or the power transition is detected based on a user interaction with hardware of the computer system.

5. 10. The method of claim 1, wherein the request to initiate the reset or the power transition is detected based on a user interaction with a board management controller of the computer system.

6. 6. The method of claim 1, further comprising, in response to determining that the first mode is enabled, configuring a general purpose input / output pin of a hardware component internal to the computer system, wherein when an interrupt is asserted on the general purpose input / output pin, the hardware component initiates the persistent cache flush operation.

7. The method of any one of claims 1 to 6, wherein the persistent cache flush operation transfers data in a volatile processor cache to persistent memory.

8. 8. The method of claim 1, wherein resetting the computer system after the persistent cache flush operation is completed comprises writing a value to a register that initiates a warm reset of the computer system.

9. 9. The method of claim 1, wherein initiating a power transition of the computer system after the persistent cache flush operation is completed comprises writing a value to a register that triggers a power transition of the computer system.

10. 10. The method of claim 1, wherein resetting the computer system after the persistent cache flush operation is completed or after the timeout expires comprises asserting a reset request signal to a chipset of the computer system.

11. 11. The method of claim 1, wherein initiating a power transition of the computer system after the persistent cache flush operation is completed or the timeout expires comprises asserting a power state transition request signal to a chipset of the computer system.

12. 12. The method of claim 1, wherein a reset or power transition request is routed to an interrupt signal that is used to invoke an interrupt handler that flushes processor caches when the first mode is enabled.

13. a hardware processor; and a chipset coupled to the hardware processor, the chipset including: (a) a first pin for receiving an interrupt signal that initiates a persistent cache flush operation; and (b) a second pin for receiving a reset request signal; the chipset responsive to detecting an interrupt signal on the first pin stops execution of tasks on the hardware processor and invokes a persistent cache flush handler; The system, wherein the chipset, in response to detecting a reset request signal on the second pin, stops execution of tasks on the hardware processor and initiates a reset without invoking the persistent cache flush handler.

14. further comprising system logic that is a proxy for the source of the reset or power transition event; 14. The system of claim 13, wherein the system logic is electrically coupled to the first pin and the second pin, and (a) when in a first mode, generates the interrupt signal to invoke the persistent cache flush handler and delays a reset or power transition event, and (b) when operating in a second mode, routes a request to perform a reset or power transition directly to the second pin of the chipset.

15. 15. The system of claim 14, wherein the system logic includes a timer that is started when the interrupt signal is generated, and is configured to send a reset request signal to the first pin in response to detecting expiration of the timer, and to cancel the timer if the persistent cache flush operation is completed before the timer expires.

16. 16. The system of claim 14 or 15, wherein the system logic intercepts requests to initiate reset or power transition events from board management controllers, debug headers, and user-interacting hardware components.

17. the first pin is a general-purpose input / output pin; 17. The system of claim 13, wherein the chipset is configured to detect an interrupt signal and, in response to detecting that persistent cache flushing is enabled in the system, invoke a persistent cache flush handler.

18. the hardware processor includes a set of volatile processor caches; The system of any one of claims 13 to 17, wherein the persistent cache flush handler, when invoked, transfers data in a volatile processor cache to persistent memory.

19. A system comprising means for performing the operations of any one of claims 1 to 12.

20. A computer readable program comprising instructions that, when executed by a hardware processor, cause the operations of any one of claims 1 to 12 to be performed.

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