Method for patterning photonic devices

Abstract

A method and apparatus for etching a wafer includes positioning a wafer adjacent to a cathode in a vacuum chamber. The wafer includes a first stack of layers, the first stack of layers including a crystalline composition of a first element and a second element different from the first element. The crystalline composition can be BaTiO3 (BTO). A gas including a first partial gas and a second partial gas is received. The first partial gas and the second partial gas can be HBr and Cl2, respectively. The wafer is chemically etched by ionizing the gas and injecting the ionized gas into the stack of layers. Chemically etching includes reacting the first partial gas with the first element and reacting the second partial gas with the second element.

Description

[Technical Field]

[0001] FIELD Embodiments herein relate generally to etching components of electro-optical devices such as phase shifters and switches. [Background technology]

[0002] Electro-optic (EO) modulators and switches are used in the optical field. Some EO modulators utilize free-carrier electrorefraction, free-carrier electroabsorption, the Pockels effect, or the DC Kerr effect to modify optical properties during operation, for example, to change the phase of light propagating through the EO modulator or switch. As an example, optical phase modulators can be used in integrated optics, waveguide structures, and integrated optoelectronics.

[0003] Despite advances made in the field of EO modulators and switches, there is a need in the art for improved methods and systems for patterning and etching wafer stacks used in EO modulators and switches. Summary of the Invention

[0004] Some embodiments described herein relate to apparatus and methods for etching wafers to build electro-optical components.

[0005] In some embodiments, a wafer is positioned adjacent to a cathode in a vacuum chamber. The wafer can include a first stack of layers, the first stack of layers including a crystalline composition of a first element and a second element different from the first element. The crystalline composition can be BaTiO3 (BTO).

[0006] A gas including a first partial gas and a second partial gas can be received. The first partial gas and the second partial gas can be HBr and Cl2, respectively. The gas is ionized and the ionized gas is injected into the stack to chemically etch the wafer. The chemical etching can include reacting the first partial gas with a first element and reacting the second partial gas with a second element.

[0007] This summary is intended to provide an overview of some of the subject matter described herein. Accordingly, it will be understood that the features described above are merely examples and should not be construed as narrowing the scope or spirit of the subject matter described herein in any way. Other features, aspects, and advantages of the subject matter described herein will become apparent from the following detailed description, drawings, and claims.

[0008] For a better understanding of the various described embodiments, the following detailed description should be read in conjunction with the following drawings, in which like reference characters refer to corresponding parts throughout. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a simplified schematic diagram illustrating an optical switch according to some embodiments. [Figure 2] FIG. 2 is a schematic diagram of a pre-fabricated wafer including stacks according to some embodiments. [Figure 3A] FIG. 3A is a simplified schematic diagram showing a cross section of a waveguide structure showing the direction of an induced electric field, according to some embodiments. [Figure 3B] FIG. 3B is a simplified schematic diagram showing a cross section of a waveguide structure according to an alternative embodiment. [Figure 4] FIG. 4 is a simplified schematic diagram illustrating a top view of a waveguide structure according to some embodiments. [Figure 5] FIG. 5 is a schematic diagram of a wafer etching apparatus according to some embodiments. [Figure 6]FIG. 6 is a schematic diagram of an ion milling etching procedure according to the prior art. [Figure 7] FIG. 7 is a schematic illustration of etching an electro-optic layer using an ionized partial gas mixture, according to some embodiments. [Figure 8] FIG. 8 is a schematic illustration of etching a wafer using a thin SiO 2 hard mask, according to some embodiments. [Figure 9] FIG. 9 is a schematic diagram of etching a wafer using a thin Si 3 N 4 hard mask, according to some embodiments. [Figure 10] FIG. 10 is a schematic diagram of etching a wafer using a thick SiO 2 hard mask, according to some embodiments. [Figure 11] FIG. 11 is a schematic diagram of etching a wafer using a thick Si 3 N 4 hard mask, according to some embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0010] While the features described herein may be susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and are herein described in detail. It should be understood, however, that the drawings and detailed description are not intended to limit the invention to the particular forms disclosed, but on the contrary, are intended to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the subject matter as defined by the appended claims.

[0011] Reference will now be made in detail to the embodiments, examples of which are illustrated in the accompanying drawings. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of various described embodiments. However, it will be apparent to those skilled in the art that various described embodiments may be practiced without these specific details. In other instances, well-known methods, procedures, components, circuits, and networks have not been described in detail as not to unnecessarily obscure aspects of the embodiments.

[0012] Also, in some instances, terms such as "first," "second," etc. are used herein to describe various elements, but it is understood that these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, a first electrode layer may be named a second electrode layer, and similarly, a second electrode layer may be named a first electrode layer, without departing from the scope of the various described embodiments. The first electrode layer and the second electrode layer are both electrode layers, but are not the same electrode layer.

[0013] The foregoing description has been set forth with reference to specific embodiments for purposes of explanation. However, the exemplary discussion above is not intended to be exhaustive or to limit the scope of the claims to the precise form disclosed. Many modifications and variations are possible in light of the above teachings. The embodiments have been selected to best explain the principles underlying the claims and their practical application, thereby enabling those skilled in the art to utilize the embodiments to the fullest extent possible, along with various modifications tailored to the particular use envisioned.

[0014] electro-optical devices Embodiments of the present invention relate to etching and patterning methods for constructing components of optical systems. By way of example only, embodiments of the present invention are provided in the context of integrated optical systems that include active optical devices, although the present invention is not limited to this example and has broad applicability to a variety of optical and optoelectronic systems.

[0015] According to some embodiments, the active photonic devices described herein utilize electro-optic effects, such as free-carrier-induced refractive index variations in semiconductors, the Pockels effect, and / or the DC Kerr effect, to modulate and / or switch optical signals. Therefore, embodiments of the present invention are applicable to both modulators that modulate transmitted light on or off or that modulate light by partially changing the transmission ratio, and optical switches that output transmitted light on a first output (e.g., a waveguide) or a second output (e.g., a waveguide), or optical switches with three or more outputs, as well as optical switches with two or more inputs. Therefore, embodiments of the present invention are applicable to a variety of designs, including M (inputs) × N (outputs) systems that utilize the methods, devices, and techniques described herein. Some embodiments also relate to electro-optic phase shifter devices, also referred to herein as phase adjustment sections, that can be used within switches or modulators.

[0016] FIG. 1 is a simplified schematic diagram illustrating an optical switch according to one embodiment of the present invention. Referring to FIG. 1, switch 100 includes two inputs, input 1 and input 2, and two outputs, output 1 and output 2. By way of example, the inputs and outputs of switch 100 may be implemented as optical waveguides operable to support single-mode or multimode optical beams. By way of example, switch 100 may be implemented as a Mach-Zehnder interferometer including a set of 50 / 50 beam splitters 105 and 107, respectively. As shown in FIG. 1, input 1 and input 2 are optically coupled to first 50 / 50 beam splitter 105. First 50 / 50 beam splitter 105, also known as a directional coupler, receives light from input 1 or input 2 and, through evanescent coupling within the 50 / 50 beam splitter, directs 50% of the input light from input 1 to waveguide 110 and directs 50% of the input light from input 1 to waveguide 112. At the same time, the first 50 / 50 beam splitter 105 directs 50% of the input light from input 2 into waveguide 110 and 50% of the input light from input 2 into waveguide 112. Considering only the input light from input 1, the input light is split evenly between waveguide 110 and waveguide 112.

[0017] Mach-Zehnder interferometer 120 includes phase adjustment section 122. A voltage V can be applied across the waveguides in phase adjustment section 122, allowing for a controllably altered refractive index in phase adjustment section 122. Because the light in waveguides 110 and 112 still has a well-defined phase relationship after propagating through first 50 / 50 beam splitter 105 (e.g., the waveguides can be in phase, 180° out of phase, etc.), phase adjustment in phase adjustment section 122 can introduce a predetermined phase difference between the light propagating in waveguide 130 and the light propagating in waveguide 132. As will be apparent to those skilled in the art, the phase relationship between the light propagating in waveguide 130 and the light propagating in waveguide 132 can cause the output light to be present at output 1 (e.g., the light beams are in phase) or at output 2 (e.g., the light beams are out of phase), thereby providing a switching function as a function of the voltage V applied to phase adjustment section 122 when the light is directed to output 1 or output 2. Although a single active arm is shown in Figure 1, it will be understood that both arms of the Mach-Zehnder interferometer may include a phase adjustment section.

[0018] As shown in Figure 1, electro-optical switching technology, in comparison to all-optical switching technology, utilizes the application of an electrical bias (e.g., V in Figure 1) across the active area of ​​the switch to produce optical fluctuations. The electric field and / or current resulting from the application of this voltage bias changes one or more optical properties of the active area, such as the refractive index or absorbance.

[0019] 1 shows a Mach-Zehnder interferometer implementation, embodiments of the present invention are not limited to this particular switch architecture and other phase adjustment devices are within the scope of the present invention, including ring resonator designs, Mach-Zehnder modulators, generalized Mach-Zehnder modulators, etc. Those skilled in the art will recognize many variations, modifications, and alternatives.

[0020] The optical switch shown in FIG. 1 can include a waveguide structure patterned from a wafer. FIG. 2 illustrates an exemplary wafer that can be received from a wafer manufacturer and etched in accordance with embodiments described herein to produce a waveguide structure. FIG. 2 illustrates a cross-section of a first wafer including a stack of layers that can be received as part of the fabrication process for various devices described herein, according to various embodiments. As shown, a first insulating substrate layer 202 can be (optionally) disposed below a seed layer 204. The seed layer 204 is disposed below an electro-optic layer 206. The electro-optic layer 206 is (optionally) disposed below an electrode layer 208. The electrode layer 208 is (optionally) disposed below a second insulating substrate layer 210. Alternatively, the electrode layer 208 can be located between the electro-optic layer 206 and the first insulating substrate layer 202. While FIG. 2 illustrates the presence of five layers 202-210, respectively, any one or more of these layers can be eliminated in various embodiments. In other words, the first wafer can be of various types depending on the particular fabrication method used, and the seed layer, electrode layer, and second substrate layer can optionally be present or absent as desired. One or more of the layers shown in Figure 2 can be chemically etched to produce electro-optical components according to embodiments described herein.

[0021] Each of the layers of the wafer can be any of a variety of types of material. For example, the electrode layer 208 may be composed of a conductive material such as a metal, or alternatively, may be composed of a semiconductor material. In various embodiments, the electrode layer is composed of one of gallium arsenide (GaAs), aluminum gallium arsenide (AlGaAs) / GaAs heterostructures, indium gallium arsenide (InGaAs) / GaAs heterostructures, zinc oxide (ZnO), zinc sulfide (ZnS), indium oxide (InO), doped silicon, strontium titanate (STO), doped STO, barium titanate (BTO), barium strontium titanate (BST), hafnium oxide, lithium niobate, zirconium oxide, titanium oxide, graphene oxide, tantalum oxide, lead zirconate titanate (PZT), lead lanthanum zirconate titanate (PLZT), strontium barium niobate (SBN), aluminum oxide, doped variants or solid solutions thereof, or a two-dimensional electron gas. In embodiments in which the electrode layer is composed of doped STO, the STO may be either niobium doped or lanthanum doped, or may contain vacancies, according to various embodiments.

[0022] In various embodiments, the electro-optic layer 206 is composed of one of strontium titanate (STO), barium titanate (BTO), barium strontium titanate (BST), hafnium oxide, lithium niobate, zirconium oxide, titanium oxide, graphene oxide, tantalum oxide, lead zirconate titanate (PZT), lead lanthanum zirconate titanate (PLZT), strontium barium niobate (SBN), aluminum oxide, or doped variants or solid solutions thereof. The electro-optic layer, in some embodiments, can be composed of a transparent material having a refractive index greater than the refractive index of the first and second insulating substrate layers.

[0023] Figure 3A: Induced electric field in a photonic phase shifter FIG. 3A is a simplified schematic diagram showing a cross section of an exemplary completed waveguide structure according to some embodiments, with the direction of the induced electric field indicated by the arrow. The waveguide structure shown in FIG. 3A can be fabricated from the wafer shown in FIG. 2 by performing the etching techniques of embodiments described herein. FIG. 3A presents two electrical contacts, each including a conductive wire 330 and 332 connected to an electrode 340 and 342. It is noted that, as used herein, the term "electrode" refers to a device component that directly couples to the waveguide structure (e.g., to vary the voltage drop across the waveguide structure and activate a photonic switch). Furthermore, the term "conductive wire" refers to a back-end structure that couples the electrode to other components of the device (e.g., the conductive wire can couple the electrode to a controllable voltage source), but the conductive wire is separate from the waveguide structure and does not directly couple to the waveguide structure. In some embodiments, the conductive wire may be composed of a metal (e.g., copper, gold, etc.) or, alternatively, may be composed of a semiconductor material.

[0024] As shown, Figure 3A presents a photonic device including a first cladding layer 310 and a second cladding layer 312 on either side of a waveguide. It is noted that the terms "first" and "second" are only intended to distinguish between the two cladding layers; for example, the term "first cladding layer" may refer to the cladding layer on one side of a waveguide.

[0025] 3A further shows a slab layer 320 comprising a first material. The slab layer is coupled to a first electrode of the first electrical contact and a second electrode of the second electrical contact. In some embodiments, the waveguide structure further includes a ridge portion 351 made of the first material (or a different material) coupled to the slab layer, the ridge portion being disposed between the first and second electrical contacts.

[0026] As shown in Figure 3A, the small arrows indicate the direction of the induced electric field, which is generally along the positive x-direction through the electrodes of the device. The electric field curves convexly both above and below the electrodes, as shown. Additionally, the large arrow 350 pointing in the positive x-direction indicates the polarization direction of the optical mode that may pass through the slab layer and the waveguide.

[0027] 3B illustrates an architecture in which a ridge portion 351 of the waveguide structure is disposed on the upper surface of the slab layer and extends into the first cladding layer 312, with the first and second electrodes coupled to the slab layer at a lower surface opposite the upper surface of the slab layer. As shown, the combination of the ridge portion and slab layer has a first thickness 362 that is greater than a second thickness 360 of the slab layer 320 alone, with the excess of the first thickness relative to the second thickness extending into the first cladding layer 312 on the upper surface of the slab layer 320. As shown in FIG. 3B, the first and second electrodes 340 and 342 are coupled to the slab layer 320 at a lower surface opposite the upper surface of the slab layer. Additionally, first electrical contact 330 is coupled to first electrode 340 by penetrating slab layer 320 from the top surface of the slab layer to the bottom surface of the slab layer, and second electrical contact 332 is coupled to second electrode 342 by penetrating slab layer 320 from the top surface of the slab layer to the bottom surface of the slab layer.

[0028] Figure 4. Top-down view of the photonic phase shifter 4 is a top-down view of the architecture of the photonic phase shifter of FIGS. 3A and 3B, which may be patterned according to embodiments described herein. As shown, the phase shifter may include first and second conductors 430 and 432, first and second electrodes 440 and 442, a slab layer (e.g., a waveguide layer) 420, and a ridge portion 451 of the waveguide structure.

[0029] Figure 5. Wafer etching equipment FIG. 5 is a schematic diagram illustrating a wafer etching apparatus 600 according to some embodiments. The illustrated wafer etching apparatus is one example of a wafer etching apparatus, but it is understood that various modified types of apparatus for performing the etching methods described herein are within the scope of this disclosure. As shown, process gas (e.g., a combination of HBr and Cl, among other possibilities) can be inserted through the top of an etching process chamber 602 and distributed across the upper region of the chamber using a showerhead 604. As shown, an inductor coil 606 wrapped around the chamber 602 is connected to a high-frequency (HF) radio-frequency (RF) generator (e.g., a 60 MHz RF generator) 608 configured to introduce a rapidly oscillating magnetic field within the chamber 602. The induced oscillating field can interact with the process gas and ionize it. At the bottom of the chamber 602, a low-frequency (LF) RF generator (e.g., a typically 13.5 MHz generator, or another frequency) 610 can capacitively couple to a pedestal 612 to introduce an oscillating capacitive charge on the top surface of the pedestal. This LF oscillating charge accelerates ionized gas particles downward to impinge on and chemically etch a wafer (e.g., a substrate containing one or more layers to be etched) 614 positioned on pedestal 612. Finally, gaseous chemical by-products from the chemical etching reaction can be exhausted through a low suction pump 616 located at the bottom of chamber 602.

[0030] BTO patterning Building the electro-optical components described above can involve etching processes that modify wafers into electro-optical components such as waveguide structures. While prior art wafer etching methods exhibit limitations, embodiments herein present improved wafer etching methods.

[0031] FIG. 6 illustrates a prior art ion milling method for etching BaTiO (BTO). BTO is a challenging material to pattern using reactive ion etching (RIE) because it does not form volatile by-products with fluorine or chlorine, the halides commonly used in plasma etching. The chemical by-products from conventional fluorine and chlorine etching of BTO are nonvolatile below approximately 1500°C. Therefore, these by-products cannot desorb from the wafer at the temperatures and pressures available in an RIE chamber. As a result, as shown in FIG. 6, some prior implementations for patterning a BTO layer 20 have focused on ion beam etching using argon, a process that is slow and non-selective to a mask (e.g., a silicon oxide hard mask) 22. During ion milling, argon ions accelerate toward the BTO surface, physically splitting barium and titanium atoms. These atoms are then expelled through an exhaust. However, the etched atoms often redeposit elsewhere on the wafer's surface, potentially creating undesirable defects. Additionally, due to the lack of selectivity of ion milling, effective use of the hard mask requires the hard mask 22 to be thicker than the desired patterning depth, which may increase material costs and etching time.

[0032] To address these and other concerns, embodiments herein propose a method for etching a BTO layer 20 using a mixture of hydrogen bromide (HBr) and chlorine (Cl), forming volatile byproducts BaBr and TiCl, respectively. As shown in FIG. 7, a partial gas mixture of HBr and Cl is ionized, and this ionized gas is used to etch the BTO. BaBr becomes volatile at 120° C. at 1 atm pressure, well within the range of conventional RIE chambers. In various embodiments, several integration schemes with a SiO hard mask 22 or a SiN hard mask 24 can be used to pattern the wafer, as both materials are compatible with HBr / Cl-containing moieties.

[0033] In some embodiments, the formation of BaBr2 can be assisted by the presence of oxygen, hydrogen, and / or argon ions in the plasma. The oxygen, hydrogen, and / or argon ions can be accelerated toward the surface with lower energies than those used in ion milling. The Br and Cl radicals are electrically neutral and can diffuse to the wafer surface.

[0034] Both by-products easily detach from the wafer surface and can be pumped out of the chamber without redepositing on the wafer.

[0035] An additional advantage is that the HBr / Cl2 mixture is selective to either SiO2 or Si3N4 hardmasks, and compared to physical ion milling processes, the use of chemically assisted etching increases the BTO etch rate and reduces the risk of creating scratches that result in line edge roughness (LER).

[0036] Figures 8 to 11 Use of hard mask 8-11 illustrate various methods of utilizing a hard mask when patterning an electro-optic layer, according to various embodiments.

[0037] FIG. 8 illustrates patterning the BTO layer 20 using a SiO hard mask 22. In one embodiment, the BTO layer 20 can be used as the slab / ridge electro-optic layer 320 in the device of FIG. 3B. The SiO hard mask 22 is chosen because of its high selectivity to SiO in an HBr-based plasma. The hard mask 22 can be patterned in a previous step. Optionally, an STO layer 40 can be located below the BTO layer 20. The STO layer 40 can be used to form the dielectric electrodes 340, 342 of FIG. 3B. The STO layer 40 can be patterned by any suitable method, such as ion milling, before forming the BTO layer 20. The optional STO layer 40 and the BTO layer 20 can be formed on an insulating substrate layer 202, such as a silicon dioxide or silicon nitride layer described above with respect to FIG. 2. The insulating substrate layer 202 can be a temporary layer that is subsequently removed, or it can be retained in the final electro-optic device as a cladding layer. Additionally, a seed layer 204 can optionally be formed under the BTO layer 40 as described above. The seed layer 204 may be subsequently removed or retained in the final electro-optical device. As shown, an HBr / Cl chemistry is used to etch the BTO layer 20. In addition to the two main etch gases, O is added for selectivity to the SiO hard mask 22 and for profile control, and argon is added in the form of ion bombardment to provide energy.

[0038] 9 illustrates the patterning of a BTO layer 20 using a silicon nitride (Si3N4) hard mask 24. Silicon nitride is similar to silicon dioxide in that it is difficult to etch using HBr, which provides high selectivity, as in the case of the SiO2 hard mask 22, and an HBr / Cl2 chemistry is used to etch the BTO layer 20. Just as in the case of the SiO2 hard mask, in addition to the two main etch gases, O2 is added for profile control and argon is added in the form of ion bombardment to provide energy.

[0039] FIG. 10 shows a SiO hard mask 22 similar to that shown in FIG. 8. In some embodiments, this hard mask 22 can be used to pattern the BTO layer 20. The hard mask 22 is thicker than in FIG. 8 due to the increased etch depth. The BTO layer 20 and the STO layer 40 are etched together using either an HBr / Cl chemistry or an HBr / Cl chemistry to etch the BTO layer 20, followed by optionally etching the STO layer 40 using ion milling. In addition to the two main etching gases, O is added for selectivity to the SiO hard mask 22 and profile control, and argon is added in the form of ion bombardment to provide energy. In this embodiment, the entire BTO stack is etched, and the process stops at the underlying SiO insulating substrate layer 202.

[0040] FIG. 11 shows a SiN hard mask 24 similar to that shown in FIG. 9. This hard mask 24 can be used to pattern the BTO layer 40. The hard mask 24 is thicker than that shown in FIG. 9 to accommodate the increased etch depth. The BTO layer 20 and the STO layer 40 are etched together using either an HBr / Cl chemistry or an HBr / Cl chemistry to etch the BTO layer 20, followed by optional ion milling to etch the STO layer 40. In addition to the two main etch gases, O is added for selectivity to the silicon nitride hard mask 22 and profile control, and argon is added in the form of ion bombardment to provide energy. In this embodiment, the entire BTO stack is etched, and the process stops at the underlying SiO insulating substrate layer 202.

[0041] Embodiments described herein for etching BTO layer 40 offer advantages over prior art methods, such as ion milling using fluorine mixed with argon ions. Because by-products produced by embodiments herein readily desorb from the surface, the resulting wafer (i.e., insulating substrate layer 202 supporting etched BTO layer 40) can exit process chamber 602, shown in FIG. 5, with fewer defects than wafers produced using ion milling processes. Additionally, chemically assisted etching increases etch rates and reduces processing time. Furthermore, etching methods described according to some embodiments have more adjustable parameters, such as pressure, power, and gas composition, allowing for improved process control. Embodiments herein improve selectivity to hard masks and simplify process integration. Chemical etching methods described herein are less physical than ion milling, reducing the risk of striations and edge grooves that result in line edge roughness (LER).

[0042] In some embodiments, HBr may react with moisture from the air and redeposit on the wafer. This redeposition, called time-dependent haze, can be eliminated during wafer cleaning. In some embodiments, unprocessed wafers can be physically separated from processed wafers. This prevents haze from building up on the surface of the unprocessed wafer and creating micromasks.

[0043] The terminology used in describing the various described embodiments herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used in describing the various described embodiments and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. Additionally, the term "and / or," as used herein, is understood to refer to and encompass any and all combinations of one or more of the associated listed items. Furthermore, the terms "includes," "including," "comprises," and / or "comprising," as used herein, specify the presence of stated features, integers, steps, operations, elements, and / or components, but are understood not to exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0044] As used herein, the term "when" is to be interpreted to mean "when" or "when" or "in response to a determination that" or "in response to detecting" or "in accordance with a determination that," depending on the context, as appropriate.

[0045] The foregoing description has been set forth with reference to specific embodiments for purposes of explanation. However, the exemplary discussion above is not intended to be exhaustive or to limit the scope of the claims to the precise form disclosed. Many modifications and variations are possible in light of the above teachings. The embodiments have been selected to best explain the principles underlying the claims and their practical application, thereby enabling those skilled in the art to utilize the embodiments to the fullest extent, along with various modifications tailored to the particular use envisioned.

[0046] It is also understood that the examples and embodiments described herein are for illustrative purposes only, and that various modifications or changes in light thereof will be suggested to those skilled in the art and are within the spirit and scope of the present application and the appended claims.

Claims

1. 1. A method of forming an electro-optical device, comprising: providing a wafer including a barium titanate (BTO) layer; On the BTO layer, silicon dioxide (SiO ２ ) or silicon nitride (Si ３ N ４ providing a hard mask layer comprising: patterning the hard mask layer; positioning the wafer within a plasma etch chamber; introducing gases into the plasma etching chamber, the gases being hydrogen bromide (HBr) and chlorine (Cl ２ ) and The HBr and the Cl ２ to generate an ionized gas; etching the wafer by spraying the ionized gas onto the BTO layer and the patterned hard mask layer to pattern the BTO layer, the hard mask layer protecting portions of the BTO layer from being sprayed by the ionized gas; providing a cladding layer on the patterned BTO layer, the cladding layer having a refractive index less than that of the BTO layer; The method comprising:

2. The method of claim 1 , further comprising: pumping out desorbed by-products of the chemical reaction between the ionized gas and the BTO layer.

3. The desorbed by-product is barium bromide (BaBr ２ ) and titanium tetrachloride (TiCl ４ 3. The method of claim 2, wherein the barium titanate layer consists essentially of barium, titanium, and oxygen.

4. the BTO layer overlies a strontium titanate (STO) layer; the hard mask layer is provided on the BTO layer opposite the STO layer; the wafer further includes a substrate layer disposed on an opposite side of the BTO layer from the hard mask layer; 10. The method of claim 1, wherein chemically etching the wafer comprises completely etching a portion of the BTO layer and a portion of the STO layer until the substrate layer is exposed.

5. The substrate layer is Silicon dioxide (SiO ２ ), or Silicon nitride (Si ３ N ４ ), The method of claim 4 , comprising one of:

6. The gas is oxygen gas (O ２ 10. The method of claim 1, further comprising:

7. The method of claim 1 , wherein the gas further comprises argon (Ar).

8. 1. A method of forming an electro-optical device, comprising: A method for forming a semiconductor wafer comprising: positioning a wafer within a plasma etching chamber, the wafer including a first stack of layers, the first stack of layers including a substrate layer, an electrode layer on the substrate layer, an electro-optic layer on the electrode layer, and a hard mask layer disposed on the first stack of layers, the hard mask layer being made of silicon dioxide (SiO ２ ) or silicon nitride (Si ３ N ４ wherein the substrate layer, the electrode layer, and the electro-optic layer comprise different materials, and the electro-optic layer comprises a crystalline composition comprising a first element and a second element different from the first element; receiving a gas comprising a first partial gas and a second partial gas; ionizing the gas; etching the wafer by spraying the ionized gas onto the stack and the hard mask layer, the etching including reacting an ionized component of the first partial gas with the first element and an ionized component of the second partial gas with the second element to pattern the electro-optic layer, the hard mask layer protecting a portion of the first stack from being sprayed with the ionized gas; providing a cladding layer over the patterned electro-optic layer, the cladding layer having a refractive index less than that of the electro-optic layer; Including, the electro-optic layer comprises a barium titanate (BTO) layer consisting essentially of barium, titanium, and oxygen; the first partial gas includes hydrogen bromide (HBr); The second partial gas is chlorine (Cl ２ ) The method.

9. further comprising: pumping out desorbed by-products of the reaction of the ionized components of the first partial gas with the first element and the reaction of the ionized components of the second partial gas with the second element; The desorbed by-product is barium bromide (BaBr ２ ) and titanium tetrachloride (TiCl ４ 9. The method of claim 8, comprising:

10. the substrate layer is disposed on the first stack opposite the hard mask layer; 9. The method of claim 8, wherein chemically etching the wafer comprises completely etching a portion of the first stack layer until the substrate layer is exposed.

11. The substrate layer is Silicon dioxide (SiO ２ ), or Silicon nitride (Si ３ N ４ ), The method of claim 10, comprising one of:

12. The gas further includes a third partial gas, and the third partial gas is oxygen gas (O ２ 9. The method of claim 8, wherein

13. The ionized gas is ionized argon (Ar ＋ 9. The method of claim 8, further comprising:

14. The method of claim 1 , wherein the BTO layer comprises a waveguide layer of the electro-optic device.

15. The method of claim 14 , wherein the BTO layer comprises a slab / ridge waveguide layer and the electro-optic device comprises a Mach-Zehnder interferometer.

16. The method of claim 8 , wherein the stack further comprises at least one of a seed layer and an electrode layer.

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