Semiconductor Devices

Abstract

The present disclosure pertains to a semiconductor device capable of reducing the burden involved in designing. Provided is a semiconductor device comprising: a first substrate; and a second substrate joined to the first substrate via a joint part to which a bump is joined. The bump is configured as a unit paired with a prescribed function. The present disclosure can be applied to, for example, an optical detector such as a solid-state imaging device.

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device, and more particularly to a semiconductor device that can reduce the design load. [Background technology]

[0002] In structures such as a CoC (Chip on Chip) structure and a CoW (Chip on Wafer) structure, bump bonding is used (see, for example, Patent Document 1).

[0003] Bump bonding in CoC and CoW structures requires the addition of circuits that take into account reliability factors such as electrostatic discharge (ESD) during bonding. In addition, the design must take into account delay information and power consumption for the exchange of signals between boards. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2017-175047 Summary of the Invention [Problem to be solved by the invention]

[0005] However, when using bump bonding, it was a burden in terms of both design quality and efficiency when using large-scale connection paths, and it was not possible to flexibly respond to design changes, so technology to reduce the design burden was needed.

[0006] The present disclosure has been made in light of these circumstances, and aims to reduce the design burden. [Means for solving the problem]

[0007] A semiconductor device according to one aspect of the present disclosure comprises a first substrate and a second substrate joined to the first substrate via a joint where a bump is joined, and the bump is configured as a unit paired with a predetermined function.

[0008] In one aspect of the present disclosure, a semiconductor device is composed of a first substrate and a second substrate joined to the first substrate via a joint where a bump is joined, and the bump is configured as a unit paired with a predetermined function.

[0009] The semiconductor device according to one aspect of the present disclosure may be an independent device or an internal block constituting a single device. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a diagram illustrating a configuration example of a semiconductor device to which the present disclosure is applied. [Figure 2] 1 is a diagram illustrating a configuration example of a semiconductor device to which the present disclosure is applied. [Figure 3] 1 is a diagram showing the configuration of a bump-bonded substrate in a current semiconductor device; [Figure 4] 1A and 1B are diagrams illustrating an example of the configuration of a bump-bonded substrate in a semiconductor device to which the present disclosure is applied. [Figure 5] FIG. 2 is a diagram illustrating a first example of a unit configuration. [Figure 6] FIG. 2 is a diagram illustrating a first example of a unit configuration. [Figure 7] FIG. 10 is a diagram illustrating a second example of the unit configuration. [Figure 8] FIG. 10 is a diagram illustrating a third example of a unit configuration. [Figure 9] FIG. 10 is a diagram illustrating a fourth example of a unit configuration. [Figure 10] FIG. 10 is a diagram illustrating a fifth example of a unit configuration. [Figure 11] FIG. 10 is a diagram illustrating a sixth example of a unit configuration. [Figure 12] FIG. 10 is a diagram illustrating a seventh example of a unit configuration. [Figure 13] FIG. 13 is a diagram illustrating an eighth example of a unit configuration. [Figure 14] FIG. 13 is a diagram illustrating a ninth example of a unit configuration. [Figure 15] FIG. 19 is a diagram showing a tenth example of a unit configuration. [Figure 16] FIG. 11 is a diagram showing an eleventh example of a unit configuration. [Figure 17] FIG. 12 is a diagram showing a twelfth example of a unit configuration. [Figure 18] FIG. 13 is a diagram showing a thirteenth example of a unit configuration. [Figure 19] FIG. 14 is a diagram showing a fourteenth example of a unit configuration. [Figure 20] FIG. 15 is a diagram showing a fifteenth example of a unit configuration. [Figure 21] FIG. 16 is a diagram showing a 16th example of a unit configuration. [Figure 22] FIG. 10 is a diagram showing a first example of a planar layout of units arranged in an array. [Figure 23] FIG. 10 is a diagram showing a second example of a planar layout of units arranged in an array. [Figure 24] FIG. 10 is a diagram showing a third example of a planar layout of units arranged in an array. [Figure 25] 1A and 1B are diagrams showing examples of a circuit diagram and a plan view of a unit on a substrate. [Figure 26] 1A and 1B are diagrams showing examples of a circuit diagram and a plan view of a unit on a substrate. [Figure 27] 1A and 1B are diagrams showing examples of cross sections of bump bonding portions of a substrate; [Figure 28] FIG. 10 is a diagram illustrating an example of the arrangement of units. DETAILED DESCRIPTION OF THE INVENTION

[0011] 1. Embodiments of the Present Disclosure

[0012] (Configuration of semiconductor device) 1 and 2 are diagrams showing configuration examples of a semiconductor device to which the present disclosure is applied.

[0013] Fig. 1 shows a front view of a semiconductor device 10. In Fig. 1, the semiconductor device 10 is composed of a substrate 11 and a substrate 12. Bumps are formed on the substrates 11 and 12, respectively, and a bonding portion is formed by arranging the bumps so that they face each other and performing pressure bonding, heating, or the like.

[0014] 2 shows an example of the arrangement of bumps formed on the opposing surfaces of substrate 11 and substrate 12. On the surface of substrate 11 that faces substrate 12, a plurality of bumps such as bumps 111, 112, and 113 are formed at predetermined positions. On the surface of substrate 12 that faces substrate 11, a plurality of bumps such as bumps 211, 212, and 213 are formed at predetermined positions. The plurality of bumps formed on substrate 11 and the plurality of bumps formed on substrate 12 are aligned and arranged.

[0015] (Internal structure) Next, the configuration of bump-bonded substrates 11 and 12 in semiconductor device 10 will be described. For comparison with substrates 11 and 12 to which the present disclosure is applied, the configuration of bump-bonded substrates in current semiconductor devices is shown in FIG. 3. The configuration of substrates 11 and 12 to which the present disclosure is applied is shown in FIG. 4.

[0016] In FIG. 3, the substrate 11 and the substrate 12 are bonded via a plurality of bumps such as bumps 111, 112, and 113 and bumps 211, 212, and 213.

[0017] Substrate 11 has blocks 101-1 to 101-3. Each block 101 has bumps 111 and 112, circuits 121 and 122 including protective elements, and a main circuit 131 that performs various processes. Substrate 12 has blocks 201-1 and 201-2. Each block 201 has bumps 211, 212, and 213, circuits 221 and 222 including protective elements, and a main circuit 231 that performs various processes.

[0018] On substrates 11 and 12, blocks 101-1 and 201-1 are electrically connected via bumps, allowing various signals to be exchanged between main circuits 131-1 and 231-1. Similarly, blocks 101-2 and 101-3 are electrically connected via bumps to block 201-2, allowing various signals to be exchanged between main circuits 131-2 and 131-3 and main circuit 231-2.

[0019] As shown in Figure 3, bonding between substrates using bumps in a CoC structure or other structure requires the addition of circuits (e.g., circuits 121 and 122, or circuits 221 and 222) that take into account reliability factors such as ESD during bonding. In addition, a design that takes into account delay information and power consumption for the exchange of signals between substrates is required.

[0020] However, when the bump connection paths become large-scale (for example, several hundred), performing the entire process within the scope of analog design poses a burden in terms of both quality and efficiency.In addition, there is a possibility that design changes will be required for previous design assets such as functional block circuits and macros including bumps, as well as third-party intellectual property cores (IP cores).

[0021] As described above, current substrate configurations impose a burden on both design quality and efficiency when large-scale connection paths are used, and they are unable to flexibly accommodate design changes, so a technology to reduce the design burden is needed. Therefore, in a semiconductor device to which the present disclosure is applied, bumps and functions are configured as a pair of units, thereby reducing the design burden. Hereinafter, a detailed configuration of a semiconductor device to which the present disclosure is applied will be described with reference to FIGS. 4 to 28.

[0022] (Configuration of bump-bonded substrate) Fig. 4 is a diagram showing an example of the configuration of a bump-bonded substrate in a semiconductor device to which the present disclosure is applied. In Fig. 4, parts corresponding to those in Fig. 3 are given the same reference numerals, and their description will be omitted as appropriate.

[0023] In FIG. 4, the substrate 11 and the substrate 12 are bonded via a plurality of bumps such as bumps 111, 112, and 113 and bumps 211, 212, and 213.

[0024] In the substrate 11, the block 101-1 has a main circuit 131-1. The main circuit 131-1 is connected to the units 301-1-1 and 301-1-2. The unit 301-1-1 has a bump 111 and a circuit 121 including a protective element and the like. The unit 301-1-2 has a bump 112 and a circuit 122 including a protective element and the like.

[0025] Furthermore, on the substrate 11, the main circuit 131-2 included in the block 101-2 is connected to the units 301-1-3 and 301-1-4, and the main circuit 131-3 included in the block 101-3 is connected to the units 301-1-5 and 301-1-6. Each of the units 301-1-3 to 301-1-6 is composed of a circuit including bumps and protective elements, etc., similar to the units 301-1-1 and 301-1-2.

[0026] In the substrate 12, the block 201-1 has a main circuit 231-1. The main circuit 231-1 is connected to the units 301-2-1 and 301-2-2. The unit 301-2-1 has a bump 211 and a circuit 221 including a protective element and the like. The unit 301-2-2 has a bump 212 and a circuit 222 including a protective element and the like.

[0027] Furthermore, on the substrate 12, the main circuit 231-2 included in the block 201-2 is connected to the units 301-2-3 and 301-2-4 and the units 301-2-5 and 301-2-6. Each of the units 301-2-3 to 301-2-6 is configured with a circuit including bumps and protective elements, etc., similar to the units 301-2-1 and 301-2-2.

[0028] On the substrates 11 and 12, the units 301-1-1 and 301-2-1, and the units 301-1-2 and 301-2-2 are electrically connected via bumps, allowing the main circuits 131-1 and 231-1 to exchange various signals.

[0029] Similarly, units 301-1-3 and 301-2-3, units 301-1-4 and 301-2-4, units 301-1-5 and 301-2-5, and units 301-1-6 and 301-2-6 are electrically connected via bumps, allowing main circuits 131-2, 131-3 and main circuit 231-2 to exchange various signals.

[0030] On boards 11 and 12, unit 301 is configured as a pair of units that includes a bump and minimum functions and has information on the operation model, delay, power consumption, etc. Examples of combinations of bumps and functions are explained using the equivalent circuits shown in Figures 5 to 21.

[0031] However, in the following explanation, when there is no need to distinguish between unit 301-1-i (i is an integer greater than or equal to 1) on the substrate 11 side and unit 301-2-j (j is an integer greater than or equal to 1) on the substrate 12 side, they will be described as unit 301. Also, for convenience of explanation, bumps 111 and 112 on the substrate 11 side and bumps 211 and 212 on the substrate 12 side will be described as bump 311 without distinction.

[0032] (First example) FIG. 5 is a diagram showing a first example of the configuration of the unit 301. As shown in FIG.

[0033] 5, the unit 301A has a bump 311A ​​and a protective element 321A. In the unit 301A, in addition to the bump 311A, the protective element 321A provides a protective function as a minimum function.

[0034] Note that unit 301A in Fig. 5 shows the configuration for input, but the configuration for output is as shown in Fig. 6. In Fig. 6, unit 301B is configured to include bump 311B and protective element 321B.

[0035] (Second example) FIG. 7 is a diagram showing a second example of the configuration of the unit 301. In FIG.

[0036] 7, unit 301C has bump 311C, protective element 321C, and output circuit 322C. In addition to bump 311C, unit 301C has, as minimum functions, a protective function provided by protective element 321C and an output function provided by output circuit 322C.

[0037] (Third example) FIG. 8 is a diagram showing a third example of the configuration of the unit 301. In FIG.

[0038] 8, unit 301D has bump 311D, protective element 321D, and power supply circuit 322D. In addition to bump 311D, unit 301D has, as minimum functions, a protective function provided by protective element 321D and a power supply function provided by power supply circuit 322D.

[0039] (Example 4) FIG. 9 is a diagram showing a fourth example of the configuration of the unit 301. In FIG.

[0040] 9, the unit 301E has a bump 311E, a protective element 321E, and a GND supply circuit 322E. In addition to the bump 311E, the unit 301E has, as minimum functions, a protection function provided by the protective element 321E and a ground supply function provided by the GND supply circuit 322E.

[0041] (Fifth Example) FIG. 10 is a diagram showing a fifth example of the configuration of the unit 301. In FIG.

[0042] 10, the unit 301F has a bump 311F, a protection element 321F, a control circuit 322F, and an input circuit 323F. In addition to the bump 311F, the unit 301F has, as minimum functions, a protection function provided by the protection element 321F, a control function provided by the control circuit 322F, and an input function provided by the input circuit 323F.

[0043] The control circuit 322F may have a function to prevent unstable operation when the bump 311F is not in contact (open). Other control circuits, which will be described later, may also have the same function as the control circuit 322F.

[0044] (Example 6) FIG. 11 is a diagram showing a sixth example of the configuration of the unit 301. In FIG.

[0045] 11, unit 301G has bump 311G, protection element 321G, pull-up circuit 322G, and input circuit 323G. In addition to bump 311G, unit 301G has, as minimum functions, a protection function provided by protection element 321G, a pull-up function provided by pull-up circuit 322G, and an input function provided by input circuit 323G.

[0046] (Example 7) FIG. 12 is a diagram showing a seventh example of the configuration of the unit 301. In FIG.

[0047] 12, the unit 301H has a bump 311H, a protection element 321H, a pull-down circuit 322H, and an input circuit 323H. In addition to the bump 311H, the unit 301H has, as minimum functions, a protection function provided by the protection element 321H, a pull-down function provided by the pull-down circuit 322H, and an input function provided by the input circuit 323H.

[0048] (Example 8) FIG. 13 is a diagram showing an eighth example of the configuration of the unit 301. In FIG.

[0049] 13, the unit 301I has a bump 311I, a protection element 321I, a control circuit 322I, and a Schmitt input circuit 323I. In addition to the bump 311I, the unit 301I has, as minimum functions, a protection function provided by the protection element 321I, a control function provided by the control circuit 322I, and an input function provided by the Schmitt input circuit 323I.

[0050] (Example 9) FIG. 14 is a diagram showing a ninth example of the configuration of the unit 301. In FIG.

[0051] 14, unit 301J has bump 311J, protection element 321J, pull-up circuit 322J, and Schmitt input circuit 323J. In addition to bump 311J, unit 301J has, as minimum functions, a protection function provided by protection element 321J, a pull-up function provided by pull-up circuit 322J, and an input function provided by Schmitt input circuit 323J.

[0052] (Example 10) FIG. 15 is a diagram showing a tenth example of the configuration of the unit 301. In FIG.

[0053] 15, the unit 301K has a bump 311K, a protection element 321K, a pull-down circuit 322K, and a Schmitt input circuit 323K. In addition to the bump 311K, the unit 301K has, as minimum functions, a protection function provided by the protection element 321K, a pull-down function provided by the pull-down circuit 322K, and an input function provided by the Schmitt input circuit 323K.

[0054] (Example 11) FIG. 16 is a diagram showing an eleventh example of the configuration of the unit 301. In FIG.

[0055] 16, the unit 301L has a bump 311L, a protection element 321L, an input circuit 322L, and an output circuit 323L. In addition to the bump 311L, the unit 301L has, as minimum functions, a protection function provided by the protection element 321L, an input function provided by the input circuit 322L, and an output function provided by the output circuit 323L.

[0056] (Example 12) FIG. 17 is a diagram showing a twelfth example of the configuration of the unit 301. In FIG.

[0057] 17, unit 301M has bump 311M, protection element 321M, pull-up circuit 322M, input circuit 323M, and output circuit 324M. In addition to bump 311M, unit 301M has, as minimum functions, a protection function provided by protection element 321M, a pull-up function provided by pull-up circuit 322M, an input function provided by input circuit 323M, and an output function provided by output circuit 324M.

[0058] (Example 13) FIG. 18 is a diagram showing a thirteenth example of the configuration of the unit 301. In FIG.

[0059] 18, a unit 301N has a bump 311N, a protection element 321N, a pull-down circuit 322N, an input circuit 323N, and an output circuit 324N. In addition to the bump 311N, the unit 301N has, as minimum functions, a protection function provided by the protection element 321N, a pull-down function provided by the pull-down circuit 322N, an input function provided by the input circuit 323N, and an output function provided by the output circuit 324N.

[0060] (Example 14) FIG. 19 is a diagram showing a fourteenth example of the configuration of the unit 301. In FIG.

[0061] 19, the unit 301O has a bump 311O, a protection element 321O, a Schmitt input circuit 322O, and an output circuit 323O. In addition to the bump 311O, the unit 301O has, as minimum functions, a protection function provided by the protection element 321O, an input function provided by the Schmitt input circuit 322O, and an output function provided by the output circuit 323O.

[0062] (Example 15) FIG. 20 is a diagram showing a fifteenth example of the configuration of the unit 301. In FIG.

[0063] 20, unit 301P has bump 311P, protection element 321P, pull-up circuit 322P, Schmitt input circuit 323P, and output circuit 324P. In addition to bump 311P, unit 301P has, as minimum functions, a protection function provided by protection element 321P, a pull-up function provided by pull-up circuit 322P, an input function provided by Schmitt input circuit 323P, and an output function provided by output circuit 324P.

[0064] (Example 16) FIG. 21 is a diagram showing a sixteenth example of the configuration of the unit 301. In FIG.

[0065] 21, unit 301Q has bump 311Q, protection element 321Q, pull-down circuit 322Q, Schmitt input circuit 323Q, and output circuit 324Q. In addition to bump 311Q, unit 301Q has, as minimum functions, a protection function provided by protection element 321Q, a pull-down function provided by pull-down circuit 322Q, an input function provided by Schmitt input circuit 323Q, and an output function provided by output circuit 324Q.

[0066] In this way, in unit 301, bump 311 and the minimum functions are configured as a pair of units having information on an operation model, delay, power consumption, etc. For example, the minimum functions can include at least one of a protection function, an input function, an output function, a power supply function, a ground supply function, a control function, a pull-up function, and a pull-down function.

[0067] Unit 301 is configured as a pair of units that includes not only the physical configuration of bump 311 but also information on the operation model, delay, power consumption, etc., including the minimum functions, so it is possible to create a library that contains information on the operation model, delay, and power consumption. This allows compliance with standard full-digital design.

[0068] 5 to 21 are merely examples, and other combinations may be adopted. For example, in the example of unit 301 shown in FIG. 16 or 19, a control function by a control circuit may be provided.

[0069] (Example of a flat layout) 22 to 24, an array arrangement in which a plurality of units 301 are combined will be described.

[0070] In FIG. 22, four units 301, units 301-1 to 301-4, are arranged in a 1×4 array in the horizontal direction (east-west direction) and vertical direction (north-south direction).

[0071] 22, in unit 301-1, a power supply VDD wiring 331 and a ground VSS wiring 332 are formed in a rail-like manner in the horizontal and vertical directions at predetermined positions relative to bump 311-1. In the other units 301, the VDD wiring 331 and VSS wiring 332 are formed in a similar manner, and in the four units 301 arranged in a 1×4 array, the VDD wiring 331 and VSS wiring 332 are arranged in a rail-like manner in the horizontal and vertical directions.

[0072] In FIG. 23, 12 units 301 consisting of units 301-11 to 301-31, units 301-12 to 301-32, units 301-13 to 301-33, and units 301-14 to 301-34 are arranged in a 4×3 array in the horizontal and vertical directions.

[0073] 23, in unit 301-11, VDD wiring 331 and VSS wiring 332 are formed in a rail-like manner in the horizontal and vertical directions relative to bump 311-11. VDD wiring 331 and VSS wiring 332 are similarly formed in other units 301, and in the 12 units 301 arranged in a 4×3 array, VDD wiring 331 and VSS wiring 332 are arranged in a rail-like manner in the horizontal and vertical directions.

[0074] 22 and 23, by combining a plurality of units 301 and arranging them in a rectangular shape (macro shape), it becomes possible to arrange the units 301 adjacent to each other. By arranging a plurality of units 301 in an array in a rectangular shape, it is possible to connect the VDD wiring 331 and the VSS wiring 332 in adjacent units 301, thereby realizing the smallest possible configuration.

[0075] In Figures 22 and 23, when multiple units 301 are arranged in a rectangular shape, they are arranged in a 1 x 4 or 4 x 3 array, but the number of units 301 in the horizontal and vertical directions is arbitrary, and other array arrangements may be adopted.

[0076] 24, eleven units 301, namely, units 301-11 to 301-31, units 301-22 to 301-42, units 301-23 to 301-43, and units 301-34 to 301-44, are arranged in a shape with concaves and convexes in the horizontal and vertical directions. Specifically, unit 301-11 forms a convex portion, and the area below unit 301-31 and the area above unit 301-34 form a concave portion.

[0077] 24, in unit 301-11, VDD wiring 331 and VSS wiring 332 are formed in a rail-like shape in the horizontal and vertical directions relative to bump 311-11. In other units 301, VDD wiring 331 and VSS wiring 332 are formed in a similar manner, and in the 11 units 301 arranged in an uneven shape, VDD wiring 331 and VSS wiring 332 are arranged in a rail-like shape in the horizontal and vertical directions.

[0078] 24, by combining multiple units 301 and arranging them in a shape with protrusions and recesses (macro shape), it is possible to effectively utilize extremely small areas and dead space within the substrate, and since the layout efficiency within the substrate leads to a reduction in chip size, the number of chips that can be secured on one wafer increases, and cost benefits can also be expected. Furthermore, since efficient layout within the substrate is possible, it is possible to save the chip area, which can realize, for example, cost reduction.

[0079] (Specific application examples) Specific application examples of the unit 301 will be described with reference to FIGS.

[0080] Fig. 25 shows an example of a circuit diagram and a plan view of a unit 301 formed on a substrate 11. In Fig. 25A, a unit 301F has a bump 311F, a protection element 321F, a control circuit 322F, and an input circuit 323F, similar to the configuration shown in Fig. 10. In the unit 301F, a VDD wiring 331 and a VSS wiring 332 are arranged in a rail shape in the horizontal and vertical directions relative to the bump 311F (Fig. 25B).

[0081] Fig. 26 shows an example of a circuit diagram and a plan view of a unit 301 formed on a substrate 12. In Fig. 26A, a unit 301B has a bump 311B and a protective element 321B, similar to the configuration shown in Fig. 6. In the unit 301B, a VDD wiring 331 and a VSS wiring 332 are arranged in a rail-like manner in the horizontal and vertical directions relative to the bump 311B (Fig. 26B).

[0082] Fig. 27 is a diagram showing an example of a cross section of a bump bonding portion between substrates 11 and 12. In Fig. 27, the upper cross section in the figure shows a cross section of unit 301F (Fig. 25) formed on substrate 11, and the lower cross section in the figure shows a cross section of unit 301B (Fig. 26) formed on substrate 12. Bump 311F of unit 301F is bonded to bump 311B of unit 301B, thereby bonding substrates 11 and 12 via the bumps.

[0083] In the examples of Figures 25 to 27, a case is illustrated in which unit 301F is formed on substrate 11 and unit 301B is formed on substrate 12, but the combination of units 301 formed on each substrate is not limited to this, and may be, for example, any combination of units 301 shown in Figures 5 to 21 above.

[0084] 25 to 27 show an example in which a pair of bumps are bonded as the bump bonding portion between substrate 11 and substrate 12, but as described above, multiple units 301 can be combined and arranged in a predetermined shape (macro shape) such as a rectangular shape. For example, as shown in Fig. 28, multiple units 301 can be combined and arranged in a 4 x 8 array in the horizontal and vertical directions, allowing units 301 to be arranged adjacent to each other.

[0085] As described above, in semiconductor device 10 to which the present disclosure is applied, bumps and functions are configured as a pair of units on substrates 11 and 12, so that, for example, even when changes are made during the design stage, the components can be flexibly rearranged, thereby reducing the design load and enabling the design load to be reduced.

[0086] Furthermore, in the semiconductor device 10 to which the present disclosure is applied, the substrates 11 and 12 are configured as a pair of units that include not only the physical configuration of the bumps but also the minimum functions and have information on the operation model, delay, power consumption, etc., thereby realizing a library that has information on the operation model, delay, power consumption, etc. This allows compliance with standard full-digital design.

[0087] In other words, by applying the present disclosure, in a design style using bumps in a structure such as a CoC structure, when only the physical part of the bump is configured as a block circuit or macro incorporated as an input / output terminal of a large-scale circuit configuration, it is possible to comply with a fully digital design style by creating a cell library lineup of units with the minimum configuration (optimal configuration) necessary and sufficient for designers to use in designing power / ground, signals, etc.

[0088] Furthermore, for the above-mentioned unit groups (equivalent circuits shown in Figures 5 to 21), by managing and operating front-end data consisting of various models such as behavior models, delay models, and power consumption models, and cell libraries that require back-end data of physical data, it is possible to adopt a design method that conforms to a standard (general) semiconductor design flow that utilizes existing design tools.

[0089] <2. Modifications>

[0090] In the above description, the semiconductor device 10 to which the present disclosure is applied has been described as a semiconductor device in general, but the present disclosure can also be applied to a photodetector such as a solid-state imaging device having a photoelectric conversion element. This photodetector can be mounted in electronic devices such as smartphones, tablet terminals, mobile phones, PCs (Personal Computers), digital still cameras, and digital video cameras.

[0091] Furthermore, although the above description has exemplified bump bonding in a CoC structure, the present disclosure can also be applied to bump bonding in other structures, such as a CoW structure, etc. In this specification, the term "substrate" includes the meaning of a chip, so "substrate" may be read as "chip."

[0092] It should be noted that the embodiments of the present disclosure are not limited to the above-described embodiments, and various modifications are possible within the scope of the gist of the present disclosure. Furthermore, the effects described in this specification are merely examples and are not intended to be limiting, and other effects may also be obtained.

[0093] The present disclosure can also be configured as follows.

[0094] (1) a first substrate; a second substrate bonded to the first substrate via a bonding portion where the bumps are bonded; Equipped with The bumps are configured as a unit paired with a predetermined function. Semiconductor device. (2) the first substrate has a first unit including a first bump and a first function paired with the first bump; the second substrate has a second unit including a second bump and a second function paired with the second bump; The first bump and the second bump are bonded together. The semiconductor device according to (1) above. (3) the first substrate has a plurality of first bumps formed on a first surface, each of the first bumps constituting a first unit; The second substrate has a plurality of second bumps formed on a second surface opposite to the first surface, and each of the second bumps constitutes a second unit. The semiconductor device according to (2) above. (4) In the unit, power supply and ground wiring is formed at predetermined positions relative to the bumps. The semiconductor device according to any one of (1) to (3). (5) The wiring is formed in a rail shape in a first direction and a second direction perpendicular to the first direction relative to the bump. The semiconductor device according to (4) above. (6) The predetermined function includes at least one of a protection function, an input function, an output function, a power supply function, a ground supply function, a control function, a pull-up function, and a pull-down function. The semiconductor device according to any one of (1) to (5). (7) The first function and the second function include different functions. The semiconductor device according to (2) or (3) above. (8) the plurality of first units are arranged in an array, The plurality of second units are arranged in an array corresponding to the plurality of first units. The semiconductor device according to (3) above. (9) The plurality of first units and the plurality of second units are arranged in a rectangular shape or a shape having projections and recesses. The semiconductor device according to (8) above. (10) Configured as a photodetector The semiconductor device according to any one of (1) to (9). [Explanation of symbols]

[0095] 10 semiconductor device, 11 substrate, 12 substrate, 111, 112, 113 bump, 211, 212, 213 bump, 301, 301A to 301Q unit, 311, 311A ​​to 311Q bump, 321A to 321Q protection element, 322C, 323L, 323O, 324M, 324N, 324P, 324Q output circuit, 322D power supply circuit, 322E GND supply circuit, 322F, 322I control circuit, 322G, 322J, 322M, 322P pull-up circuit, 322H, 322K, 322N, 322Q pull-down circuit, 322L, 323F, 323G, 323H, 323M, 323N Input circuit, 322O, 323I, 323J, 323K, 323P, 323Q Schmitt input circuit, 331 VDD wiring, 332 VSS wiring

Claims

1. a first substrate; a second substrate bonded to the first substrate via a bonding portion where the bumps are bonded; Equipped with the first substrate has a first unit including a first bump and a first function paired with the first bump and including at least one of a protection function, an input function, an output function, a power supply function, a ground supply function, a control function, a pull-up function, and a pull-down function; the second substrate has a second unit including a second bump and a second function paired with the second bump and including at least one of a protection function, an input function, an output function, a power supply function, a ground supply function, a control function, a pull-up function, and a pull-down function; The first bump and the second bump are bonded together. Semiconductor device.

2. the first substrate has a plurality of first bumps formed on a first surface, each of the first bumps constituting a first unit; The second substrate has a plurality of second bumps formed on a second surface opposite to the first surface, and each of the second bumps constitutes a second unit. The semiconductor device according to claim 1 .

3. In the first unit, first wiring for power supply and ground is formed at a predetermined position relative to the first bump, In the second unit, second wiring for power supply and ground is formed at a predetermined position relative to the second bump. The semiconductor device according to claim 1 .

4. the first wiring is formed in a rail shape in a first direction and a second direction perpendicular to the first direction with respect to the first bump; The second wiring is formed in a rail shape in the first direction and the second direction relative to the second bump. The semiconductor device according to claim 3 .

5. The first function and the second function include different functions. The semiconductor device according to claim 1 .

6. the plurality of first units are arranged in an array, The second units are arranged in an array corresponding to the first units. The semiconductor device according to claim 2 .

7. The plurality of first units and the plurality of second units are arranged in a rectangular shape or a shape having projections and recesses. The semiconductor device according to claim 6.

8. Configured as a photodetector The semiconductor device according to claim 1 .

9. The first substrate further has a first main circuit connected to the first unit; The second substrate further includes a second main circuit connected to the second unit. The semiconductor device according to claim 1 .

Images