Method for manufacturing a semiconductor device

Abstract

To provide a semiconductor device with excellent electric characteristics.SOLUTION: A semiconductor device is manufactured by a first step of forming a semiconductor layer containing metal oxide, a second step of forming a first insulating layer, a third step of forming a first conductive film on the first insulating layer, a fourth step of forming a first conductive layer by etching a part of the first conductive film and forming a first region overlapping with the first conductive layer on the semiconductor layer and a second region not overlapping with the first conductive layer on the semiconductor layer, and a fifth step of performing a first process on the conductive layer. The first process is a plasma process under an atmosphere including a mixed gas of a first gas containing an oxygen element and not containing a hydrogen element, and a second gas containing the hydrogen element and not containing the oxygen element.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] One embodiment of the present invention relates to a semiconductor device and a manufacturing method of the semiconductor device. The present invention relates to a transistor and a method for manufacturing the transistor.

[0002] Note that one embodiment of the present invention is not limited to the above technical fields. The technical field of one embodiment of the present invention is a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, and the like. , electronic device, lighting device, input device, input / output device, driving method thereof, or manufacturing method thereof Semiconductor devices function by utilizing the semiconductor properties. This refers to all devices that can do this. [Background technology]

[0003] Oxide semiconductors using metal oxides are attracting attention as semiconductor materials that can be used in transistors. For example, in Patent Document 1, a plurality of oxide semiconductor layers are stacked, and the plurality of oxide semiconductor layers are Among the oxide semiconductor layers, an oxide semiconductor layer serving as a channel contains indium and gallium, and By increasing the ratio of indium to that of gallium, the field effect mobility (simply called mobility) can be improved. A semiconductor device with enhanced mobility, or μFE, is disclosed.

[0004] Metal oxides that can be used for the semiconductor layer can be formed using a sputtering method or the like. Therefore, it can be used for the semiconductor layer of a transistor that constitutes a large display device. By improving some of the production facilities for transistors using polycrystalline silicon and amorphous silicon, This allows for the use of metal oxide transistors, which reduces capital investment. The capacitor has a higher field effect mobility than amorphous silicon, so it can be used in the drive circuit. A high-performance display device can be realized.

[0005] Furthermore, Patent Document 2 discloses a semiconductor device using a low-resistance conductive material. Patent Document 2 discloses a method for forming copper, which is one of the low-resistance conductive materials. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Laid-Open No. 2014-7399 [Patent Document 2] Japanese Patent Application Laid-Open No. 2001-210630 Summary of the Invention [Problem to be solved by the invention]

[0007] One embodiment of the present invention is to provide a semiconductor device with favorable electrical characteristics and a manufacturing method thereof. Another object of the present invention is to provide a semiconductor device having stable electrical characteristics and a manufacturing method thereof. Another object of one embodiment of the present invention is to provide a highly reliable display device. This is one of the challenges.

[0008] The description of these problems does not preclude the existence of other problems. It is not necessary for one embodiment to solve all of these problems. The subject matter can be extracted from the description, drawings, claims, etc. [Means for solving the problem]

[0009] One embodiment of the present invention includes a first step of forming a semiconductor layer containing a metal oxide, and a second step of covering the semiconductor layer. The second step is to form a first insulating layer, and the second step is to form a first conductive film on the first insulating layer. a third step of etching a part of the first conductive film to form a first conductive layer; a first region where the first conductive layer overlaps the conductor layer, and a second region where the first conductive layer does not overlap the semiconductor layer; a fourth step of forming a second region; and a fifth step of performing a first process on the first conductive layer. and a sixth step of forming a second insulating layer containing an oxide in contact with the first conductive layer. The first conductive layer comprises copper, silver, gold, or aluminum. The first treatment comprises oxygen a first gas containing hydrogen and no oxygen; and a second gas containing hydrogen and no oxygen. The second insulating layer is formed by plasma treatment in an atmosphere containing a mixed gas of the first insulating layer and the second insulating layer. plasma generation using a film formation gas containing the first gas and a third gas containing silicon element; The sixth step is formed by chemical vapor deposition without exposure to the atmosphere after the fifth step. It is done consecutively.

[0010] Another embodiment of the present invention is a method for manufacturing a semiconductor device including a first step of forming a semiconductor layer containing a metal oxide, a second step of forming a first insulating layer over the layer; and a second step of forming a first metal a third step of forming an oxide film and a first conductive film; and a third step of forming the first conductive film and the first metal oxide film. A first conductive layer and a first metal oxide layer are formed by etching a portion of the film, and a semiconductor a first region where the first conductive layer overlaps the semiconductor layer, and a second region where the first conductive layer does not overlap the semiconductor layer. a fourth step of forming the region; and a fifth step of performing a first treatment on the first conductive layer. and a sixth step of forming a second insulating layer containing an oxide in contact with the first conductive layer. The first conductive layer includes copper, silver, gold, or aluminum. The first treatment is a treatment using oxygen atoms. a first gas containing hydrogen and not containing oxygen; and a second gas containing hydrogen and not containing oxygen. The second insulating layer is formed by plasma treatment in an atmosphere containing a mixed gas of the above-mentioned gas. A plasma chemical vapor deposition method using a deposition gas containing a first gas and a third gas containing silicon element. The sixth step is formed by a phase deposition method without exposure to the atmosphere after the fifth step. This is carried out.

[0011] In the above, the first treatment in the fifth step is a first gas supplied to the treatment chamber. When the flow rate of the first gas is 100%, the flow rate of the second gas is 0 It is preferable to control the temperature so that it is between 0.5% and 100%.

[0012] In the above, the first gas contains N2O or O2, and the second gas contains NH3 Or preferably contains H2.

[0013] In the above, in the first step, the semiconductor layer is formed by a second metal oxide film and a third metal oxide film. After forming the second metal oxide layer and the third metal oxide film in this order, The third metal oxide layer is formed by etching the first metal oxide layer. It is preferable to form the insulating layer so that it has higher crystallinity than the oxide layer.

[0014] In the above, a seventh step of forming a first conductive layer and a second step of forming a second conductive layer are performed before the first step. an eighth step of forming a third insulating layer over the first conductive layer between the seventh step and the first step; In the first step, the semiconductor layer is formed so as to overlap with the first conductive layer. It is preferable. [Effects of the Invention]

[0015] According to one embodiment of the present invention, a semiconductor device with favorable electrical characteristics and a manufacturing method thereof can be provided. Furthermore, a semiconductor device having stable electrical characteristics and a manufacturing method thereof can be provided. One embodiment of the present invention can provide a highly reliable display device.

[0016] The description of these effects does not preclude the existence of other effects. An embodiment does not necessarily have to have all of these effects. can be extracted from descriptions in the specification, drawings, claims, etc. [Brief explanation of the drawings]

[0017] [Figure 1] (A), (B), and (C) are examples of transistor configurations. [Figure 2] (A), (B), and (C) are examples of transistor configurations. [Figure 3] (A), (B), and (C) are examples of transistor configurations. [Figure 4] (A), (B), and (C) are examples of transistor configurations. [Figure 5] 1A, 1B, 1C, 1D, and 1E are diagrams illustrating a method for manufacturing a transistor. [Figure 6] 1A, 1B, 1C, and 1D are diagrams illustrating a method for manufacturing a transistor. [Figure 7] (A) and (B) are top views of the display device. [Figure 8] FIG. [Figure 9] FIG. [Figure 10] FIG. [Figure 11] (A) is a block diagram of the display device, and (B) and (C) are circuit diagrams. [Figure 12] (A), (C), and (D) are circuit diagrams of the display device, and (B) is a timing chart. [Figure 13](A) and (B) are examples of display module configurations. [Figure 14] (A), (B), (C), (D) and (E) are examples of electronic device configurations. [Figure 15] (A), (B), (C), (D), (E), (F) and (G) are examples of electronic device configurations. [Figure 16] (A), (B), (C) and (D) are examples of electronic device configurations. DETAILED DESCRIPTION OF THE INVENTION

[0018] Hereinafter, embodiments will be described with reference to the drawings. It is understood that the present invention may be embodied in various different forms without departing from its spirit and scope. It will be readily apparent to those skilled in the art that various modifications may be made to the mode and details of the present invention. The invention should not be construed as being limited to the following description of the embodiments.

[0019] In addition, in each figure described in this specification, the size, layer thickness, or area of ​​each component is May be exaggerated for clarity.

[0020] In addition, the ordinal numbers "first," "second," and "third" used in this specification refer to the number of components. This is added to avoid confusion and is not intended to limit the number.

[0021] In addition, in this specification, the terms "above" and "below" that indicate placement refer to the relationship between components. The positional relationship between the components is used for convenience in explaining the drawings. The positional relationship between the elements changes depending on the direction in which each element is depicted. The terms are not limited to those explained in the detailed description, but may be rephrased appropriately depending on the situation.

[0022] In this specification and the like, the functions of the source and the drain of a transistor are different. When using polarity transistors or when the direction of current changes during circuit operation, etc. For this reason, the terms source and drain are sometimes used interchangeably. It is possible to do so.

[0023] In this specification, the channel length direction of a transistor is the direction in which the source region and the drain region are connected. This refers to one of the directions parallel to the line connecting the gate regions at the shortest distance. The direction corresponds to one of the directions of current flow through the semiconductor layer when the transistor is in the on state. The channel width direction refers to the direction perpendicular to the channel length direction. Depending on the structure and shape of the transistor, the channel length direction and the channel width direction are determined as one. This may not be possible.

[0024] In addition, in this specification, "electrically connected" means "something that has some kind of electrical effect." This includes cases where the device is connected via a "of" is not subject to any particular restrictions as long as it allows the transmission and reception of electrical signals between connected objects. For example, "things that have some kind of electrical action" include electrodes, wiring, and transistors. It has various functions such as switching elements, resistors, inductors, capacitors, etc. This includes elements such as:

[0025] In addition, in this specification and the like, the terms "film" and "layer" are interchangeable. For example, the terms "conductive layer" and "insulating layer" can be interchanged with "conductive film" and "insulating layer." The term "insulating film" may be used interchangeably in some cases.

[0026] Unless otherwise specified, in this specification and the like, the off-state current refers to the current that flows when a transistor is off. This refers to the drain current when the device is in a non-conducting state (also known as a cut-off state). Unless otherwise specified, for an n-channel transistor, the voltage V between the gate and source gs is the threshold voltage V th (For p-channel transistors, V th Higher than (i) This refers to a state.

[0027] In this specification, a display panel, which is one aspect of a display device, displays (outputs) an image or the like on a display surface. Therefore, a display panel is one aspect of an output device.

[0028] In this specification, the substrate of the display panel is provided with, for example, an FPC (Flexible Printed Circuit). Integrated Circuit) or TCP (Tape Carrier Packet ge) or a connector such as COG (Chip On Ground) is attached to the board. The IC mounted on the display panel module is called a display module. It may also be called a display panel or simply a display panel.

[0029] In this specification and the like, a touch panel, which is one aspect of a display device, is a device for displaying images and the like on a display surface. The function of displaying the information and detecting when a detectable object such as a finger or stylus touches, presses, or approaches the display surface. It also functions as a touch sensor to detect when something is touching the screen. A rule is one form of input / output device.

[0030] The touch panel is, for example, a display panel (or display device) with a touch sensor, A touch panel can also be called a display panel (or display device) with a touch function. Alternatively, the display panel may have a touch sensor panel. It may also be configured to have a touch sensor function inside or on the surface.

[0031] In addition, in this specification, a touch panel substrate on which a connector or IC is mounted is referred to as a touch panel. , touch panel module, display module, or simply touch panel. be.

[0032] (Embodiment 1) In this embodiment, a semiconductor device, a display device, and a manufacturing method thereof according to one embodiment of the present invention will be described. and explain.

[0033] One embodiment of the present invention is a method for manufacturing a semiconductor device including: a semiconductor layer in which a channel is formed on a formation surface; A gate insulating layer (also called the first insulating layer) and a conductive layer that functions as a gate electrode are formed on the gate insulating layer. The semiconductor layer is a semiconductor layer, and the second conductive layer is a conductive layer. It is preferable that the semiconductor layer is made up of a metal oxide (hereinafter also referred to as an oxide semiconductor) exhibiting a high conductivity. The gate insulating layer is preferably an insulating layer containing oxide.

[0034] One way to improve the electrical characteristics of a transistor is to use a low-resistance material for the conductive layer. For example, the gate electrode, source or drain of a transistor, or By using low-resistance materials for wiring between capacitors, parasitic resistance is reduced and electrical characteristics are improved. A good transistor and semiconductor device can be obtained.

[0035] The low resistance material is, for example, a material mainly composed of copper, silver, gold, or aluminum. Copper or aluminum is particularly preferred because of its excellent mass productivity. However, copper is more susceptible to oxidation than silver and gold. When copper oxidizes, The resistance is increased, and the electrical characteristics of a semiconductor device having a transistor or a plurality of transistors are improved. or reliability may be adversely affected.

[0036] In the first embodiment, an example will be described in which a conductive layer containing copper as a main component is used for the gate electrode. As a method for suppressing oxidation of the gate electrode, a mixture of oxygen-containing gas and reducing gas is used. Plasma treatment is performed using a mixed gas, which makes it possible to suppress oxidation of the gate electrode. It becomes Noh.

[0037] More specifically, a first gas containing oxygen and not containing hydrogen, and a second gas containing hydrogen and a second gas mixture not containing oxygen, The first gas is, for example, N2O (nitrous oxide or nitrous oxide). Nitrogen oxides such as nitrous oxide, NO2 (nitrogen dioxide), NO (nitric oxide), or O It is preferable to use a gas containing O2 (oxygen), O3 (ozone), etc. It is preferable to use a gas containing, for example, NH3 (ammonia) or H2 (hydrogen). In particular, the mixed gas used in plasma processing is N2 (nitrogen) in addition to N2O and NH3. ), or a mixed gas containing a rare gas such as Ar.

[0038] The ratio of the first gas to the second gas in the mixed gas is determined by the ratio of the gases supplied to the plasma processing chamber. This can be controlled by controlling the flow rate of each gas. The ratio of the two gases can be expressed, for example, as a volume ratio, partial pressure ratio, or weight ratio. Here, the flow rate ratio of the two types of gases supplied to the processing chamber is determined by the volume ratio of the two types of gases and The voltage division ratio roughly corresponds to the voltage division ratio.

[0039] If the ratio of the second gas is too low (the flow rate is too small), the oxidation reaction will occur more frequently than the reduction reaction. On the other hand, the ratio of the second gas is If the temperature is too high, excess hydrogen atoms in the second gas will be channeled into the semiconductor layer through the gate insulating layer. This may cause the carrier density in the semiconductor layer to increase. It is preferable that the flow rate of the second gas is at least equal to or less than the flow rate of the first gas. This reduces the amount of hydrogen atoms supplied to the semiconductor layer. Even if there is an excess of unreacted hydrogen element contained in the first gas, the oxygen element contained in the second gas It is presumed that this is because hydrogen reacts with the hydrogen atom and is discharged from the treatment chamber in the form of hydroxide.

[0040] The flow rate ratio of the first gas to the second gas is as follows: The flow rate of the gas is set to 0.5% or more and 100% or less, preferably 1% or more and 90% or less, more preferably Preferably, the ratio is 3% or more and 80% or less, more preferably 3% or more and 60% or less, and even more preferably 3% or more. It can be set to more than 50% or less.

[0041] Furthermore, after the plasma treatment, the oxide was continuously removed without being exposed to the atmosphere. It is preferable to deposit an insulating layer containing the insulating layer. The insulating layer is deposited by plasma enhanced chemical vapor deposition ( It is preferable to use a plasma CVD method. It is preferable to perform the film formation in succession in the same film formation chamber in the same device. It is preferable that the deposition of the insulating layer and the deposition of the insulating layer are carried out at the same temperature.

[0042] In addition, a deposition gas containing silicon or the like is used as the deposition gas for forming an insulating layer containing oxide. It is preferable to use a mixed gas containing the above gas and the first gas used in the plasma treatment. By using the same gas containing oxygen element for the plasma treatment and the formation of the insulating layer, This makes it possible to improve the interface between the gate insulating layer and the insulating layer. N2O gas was used as the gas, and a mixed gas containing N2O gas and SiH4 (silane) gas was used as the film formation gas. A silicon oxynitride layer can be formed using the silicon dioxide as a source.

[0043] In addition, when copper is used as a low-resistance material, copper atoms diffuse into the insulating layer containing oxide. It is preferable to provide a barrier layer that prevents the transistor from malfunctioning by blocking the barrier layer. This means that the copper-based conductive layer can be isolated from the insulating layer by wrapping it in a barrier layer. For example, titanium nitride, tantalum nitride, or tungsten nitride can be used as a barrier layer. When a barrier layer is formed on a conductive layer containing copper as a main component, A step of removing oxidized portions of the copper-based conductive layer may be necessary.

[0044] The plasma treatment described above can penetrate into the insulating layer without providing a barrier layer on the copper-based conductive layer. In addition, the silicon oxynitride layer can be formed on the conductive layer to suppress the diffusion of copper atoms. In other words, the plasma treatment can prevent oxidation of the conductive layer. The step of removing the conductive layer and the step of forming a barrier layer are not required. By simply performing the above plasma treatment before forming the silicon oxide layer, a copper-based conductive film can be easily formed. Therefore, oxidation of the conductive layer can be suppressed.

[0045] Between the gate insulating layer and the gate electrode, copper atoms diffuse into the gate insulating layer, forming a barrier. It functions as an oxygen layer and prevents oxygen contained in the gate insulating layer from being absorbed by the gate electrode. It is preferable to provide a metal oxide layer that functions as a barrier layer. The layer acts as a barrier layer to prevent hydrogen and water contained in the gate electrode from diffusing into the gate insulating layer. The metal oxide layer may have a higher oxygen and hydrogen content than the gate insulating layer, for example. The metal oxide layer can be made of a material that is difficult to penetrate. are preferably processed so as to roughly coincide with each other.

[0046] In this specification, the phrase "the upper surface shapes are roughly the same" means that there is at least a small difference between the layers. For example, the upper and lower layers may have the same mask pattern. This includes cases where the entire surface is processed using the same mask pattern, or where part of the surface is processed using the same mask pattern. The shells do not overlap, and the upper layer is sometimes located inside the lower layer, and sometimes the upper layer is sometimes located outside the lower layer. In this case too, it is said that "the top surface shapes roughly match."

[0047] Next, the semiconductor layer will be described. The gate insulating layer is formed on the upper surface of the semiconductor layer processed into an island shape. It is particularly preferable that the semiconductor layer is provided in contact with the side surface of the semiconductor layer. In this case, the gate insulating layer preferably comprises an oxide.

[0048] The semiconductor layer includes a channel forming region where a channel can be formed, a source region, and a drain region. The channel forming region has a pair of low resistance regions which function as a gate insulating film in the semiconductor layer. The pair of low resistance regions are set on either side of the channel forming region. This region has a lower resistance than the channel formation region.

[0049] The pair of low resistance regions preferably contain an impurity element. The impurity element may be hydrogen, Boron, carbon, nitrogen, fluorine, phosphorus, sulfur, arsenic, aluminum, magnesium, silicon Examples of rare gas elements include helium and rare gas elements. , neon, argon, krypton, and xenon. In particular, those containing boron or phosphorus It is preferable to do so.

[0050] In particular, the pair of low resistance regions preferably contain an impurity element that easily bonds with oxygen. For example, boron, phosphorus, aluminum, magnesium, silicon, etc. may be mentioned.

[0051] In addition, the gate insulating layer has a portion that contacts the pair of low resistance regions, i.e., the gate electrode and The non-overlapping portion also preferably contains the impurity element. The portion of the gate electrode that is in contact with the channel forming region, i.e., the portion that overlaps with the gate electrode, is Preferably, no impurities are added.

[0052] At this time, the impurity element is supplied by a plasma ion doping method or an ion implantation method. These methods are preferred because they make it easier to adjust the depth of ion doping. This makes it easier to target the region including the gate insulating layer and the semiconductor layer with ions.

[0053] For example, the low resistance region of the semiconductor layer has an impurity concentration of 1×10 19atoms / cm 3 Below Top, 1×10 23 atoms / cm 3 Less than 1 × 10 20 atoms / cm 3 That's it, 1 x 10 22 atoms / cm 3 It is preferable that the semi- The low-resistance region of the conductor layer has a higher impurity concentration than the region in contact with the low-resistance region of the gate insulating layer. It is preferable to have a region with a low resistance. This makes it possible to form a low resistance region with an extremely low resistance. Cut.

[0054] In addition, the region of the gate insulating layer that does not overlap with the gate electrode has a higher impurity concentration than the low-resistance region. It is preferable that the region is low and higher than the portion overlapping the gate electrode.

[0055] In addition, when an element that easily bonds with oxygen is used as an impurity element, the impurity element In other words, the impurity element removes oxygen from the semiconductor layer. This causes oxygen vacancies in the semiconductor layer, and the oxygen vacancies bond with hydrogen in the film, resulting in carrier Furthermore, since the impurity elements in the semiconductor layer are stable in an oxidized state, A stable low resistance region can be realized without desorption due to heat or other factors applied during the process. For example, if temperatures exceeding 400°C, 600°C, or 800°C are applied during the process, Even if the resistance is high, a stable low resistance region can be maintained.

[0056] The impurity element is an element that bonds with oxygen in the semiconductor layer and the gate insulating layer to stabilize it. For example, it is preferable to use an element whose oxide can exist in a solid state under standard conditions. Particularly preferred elements are rare gases, typical nonmetallic elements other than hydrogen, typical metals, and the like. The elements can be selected from the group elements and transition metal elements, in particular boron, phosphorus, aluminum, It is preferable to use aluminum, magnesium, silicon, etc.

[0057] A more specific example will be described below with reference to the drawings.

[0058] [Configuration example 1] 1A is a top view of a transistor 100, and FIG. 1B is a top view of the transistor 100 shown in FIG. FIG. 1(C) corresponds to a cross-sectional view of the cut surface taken along the dashed line A1-A2 shown in FIG. 1(A). It corresponds to a cross-sectional view of the cut surface taken along the dashed line B1-B2. Some of the components of the transistor 100 (such as the gate insulating layer) are omitted in the illustration. The dashed line A1-A2 direction is the channel length direction, and the dashed line B1-B2 direction is the channel width direction. In addition, the top view of the transistor is the same as that of FIG. Similarly, some of the components are omitted in the drawings.

[0059] The transistor 100 is provided on a substrate 102, an insulating layer 103, a semiconductor layer 108, an insulating layer 109, a semiconductor layer 109a, and a semiconductor layer 109b. The semiconductor device includes an edge layer 110, a metal oxide layer 114, a conductive layer 112, an insulating layer 116, etc. The dielectric layer 108 is provided on the insulating layer 103. The insulating layer 110 is provided on the upper surface of the insulating layer 103, The metal oxide layer 114 and the conductive layer 112 are provided in contact with the top and side surfaces of the conductive layer 108. are stacked in this order on the insulating layer 110 and have portions overlapping with the semiconductor layer 108. The insulating layer 116 is formed on the top surface of the insulating layer 110, the side surface of the metal oxide layer 114, and the conductive layer 11. It is provided to cover the top surface of 2.

[0060] A portion of the conductive layer 112 functions as a gate electrode. A portion of the insulating layer 110 functions as a gate insulator. The transistor 100 has a gate electrode provided on the semiconductor layer 108. This is a so-called top-gate transistor.

[0061] As shown in FIGS. 1A and 1B, the transistor 100 is formed on an insulating layer 116. The conductive layer 120a and the conductive layer 120b may be formed on the substrate 110. The conductive layer 120a and the conductive layer 120b function as a source electrode and a drain electrode. are the openings 141a and 141b provided in the insulating layer 116 and the insulating layer 110, respectively. It is electrically connected to the region 108n, which will be described later, via 141b.

[0062] The semiconductor layer 108 preferably comprises a metal oxide.

[0063] For example, the semiconductor layer 108 may be made of indium and M (M is gallium, aluminum, silicon, etc.). Ni, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel , germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium one or more selected from the group consisting of aluminum, tantalum, tungsten, and magnesium; and zinc. In particular, M is aluminum, gallium, yttrium, or It is preferable to use one or more selected from tin.

[0064] In particular, the semiconductor layer 108 is made of an oxide containing indium, gallium, and zinc. It is preferable.

[0065] The semiconductor layer 108 may be a layer having a different composition, a layer having a different crystallinity, or a layer having a different impurity concentration. Alternatively, a laminated structure may be used in which different layers are laminated.

[0066] The conductive layer 112 and the metal oxide layer 114 are processed so that their top surface shapes roughly match each other. It has been done.

[0067] The metal oxide layer 114 located between the insulating layer 110 and the conductive layer 112 is It functions as a barrier film that prevents oxygen contained therein from diffusing toward the conductive layer 112. The metal oxide layer 114 is formed by diffusing hydrogen and water contained in the conductive layer 112 to the insulating layer 110 side. The metal oxide layer 114 also functions as a barrier film to prevent, for example, at least the insulating layer 11 A material that is less permeable to oxygen and hydrogen than 0 can be used.

[0068] The metal oxide layer 114 allows the conductive layer 112 to easily absorb oxygen, such as aluminum or copper. Even if a thin metal material is used, oxygen does not diffuse from the insulating layer 110 to the conductive layer 112. Even when the conductive layer 112 contains hydrogen, the conductive layer 112 Therefore, it is possible to prevent hydrogen from diffusing into the semiconductor layer 108 via the insulating layer 110. As a result, the carrier density in the channel formation region of the semiconductor layer 108 is made extremely low. It is possible.

[0069] The metal oxide layer 114 can be made of an insulating material or a conductive material. If the metal oxide layer 114 has insulating properties, it functions as a part of the gate insulating layer. If the metal oxide layer 114 is conductive, it functions as a part of the gate electrode.

[0070] The metal oxide layer 114 is made of an insulating material having a higher dielectric constant than silicon oxide. In particular, an aluminum oxide film, a hafnium oxide film, or a hafnium aluminate film is preferable. It is preferable to use a film such as a PET film, since the driving voltage can be reduced.

[0071] The metal oxide layer 114 may be, for example, indium oxide or indium tin oxide (ITO). or silicon-containing indium tin oxide (ITSO), In particular, conductive oxides containing indium are preferred because of their high conductivity. .

[0072] The metal oxide layer 114 may be an oxide material containing one or more of the same elements as the semiconductor layer 108. In particular, it is preferable to use an oxide semiconductor material that can be used for the semiconductor layer 108. In this case, it is preferable to use the same type of metal oxide layer 114 as the semiconductor layer 108. By applying metal oxide films formed using sputtering targets, equipment can be standardized. This is preferable because it allows

[0073] Alternatively, both the semiconductor layer 108 and the metal oxide layer 114 may contain indium and gallium. When a metal oxide material containing gallium is used, the composition (content ratio) of gallium is higher than that of the semiconductor layer 108. It is preferable to use a material having a high oxygen blocking property. At this time, the semiconductor layer 108 contains a material having a higher indium content than the metal oxide layer 114. By using such a material, the field-effect mobility of the transistor 100 can be increased.

[0074] The metal oxide layer 114 is preferably formed using a sputtering apparatus. For example, when forming an oxide film using a sputtering device, the film is formed in an atmosphere containing oxygen gas. By forming the insulating layer 110 and the semiconductor layer 108, oxygen can be suitably added to the insulating layer 110 and the semiconductor layer 108.

[0075] The semiconductor layer 108 has a region overlapping with the conductive layer 112 and a pair of low-resistance regions sandwiching the region. The region of the semiconductor layer 108 that overlaps with the conductive layer 112 is a transistor On the other hand, the region 108n functions as a channel forming region of the transistor 100. The source or drain region of the semiconductor substrate is formed by the gate electrode.

[0076] The region 108n is a region with a lower resistance and a higher carrier concentration than the channel formation region. These regions are also called regions with high oxygen vacancy density, regions with high impurity concentration, or regions that are n-type. can be done.

[0077] The region 108n of the semiconductor layer 108 is a region containing an impurity element. Examples of suitable elements include hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, arsenic, aluminum, and Typical examples of rare gas elements include helium, neon, and These include argon, krypton, and xenon. In particular, they contain boron or phosphorus. It is preferable that the composition contains two or more of these elements.

[0078] The insulating layer 110 is formed in a region in contact with the channel forming region of the semiconductor layer 108, i.e., the conductive layer 1 The insulating layer 110 has a region overlapping with the low resistance region 12 of the semiconductor layer 108. 08n and has a region that does not overlap with the conductive layer 112.

[0079] The insulating layer 103 and the insulating layer 110 in contact with the channel formation region of the semiconductor layer 108 are It is preferable to use an oxide film. For example, a silicon oxide film, a silicon oxynitride film, an oxide An oxide film such as an aluminum film can be used. The oxygen released from the insulating layer 103 and the insulating layer 110 during the heat treatment in the manufacturing process is transferred to the semiconductor. The oxygen vacancies in the semiconductor layer 108 can be reduced by supplying the oxygen to the channel forming region of the semiconductor layer 108. can.

[0080] The side and top surfaces of the conductive layer 112 have regions 112d that contact the insulating layer 116. When depositing the layer 116, it is preferable that the region 112d is not oxidized. In the figure, d indicates the surface of the conductive layer 112 as a region where oxidation of the conductive layer 112 is suppressed. As will be explained in detail with reference to FIG. 6, when the insulating layer 116 is formed, the insulating layer 116 is formed in the region 112d. In the plasma treatment, a mixed gas of an oxygen-containing gas and a reducing gas is used. The plasma treatment prevents the region 112d from being oxidized, and the electrical characteristics of the transistor are improved. This can suppress deterioration of reliability.

[0081] For example, the conductive layer 112 may be made of copper, silver, gold, aluminum, or the like. A low-resistance conductive material is preferable. For example, a copper-based conductive material has low electrical conductivity. Since it is a material with a high modulus and high ductility, it is particularly suitable for semiconductor devices that require flexibility (e.g. It is a suitable wiring material for devices such as display devices.

[0082] The insulating layer 116 functions as a protective layer to protect the transistor 100. 16 has the function of preventing oxygen that may be released from the insulating layer 110 from diffusing to the outside. For example, inorganic insulating materials such as oxides or nitrides can be used. More specific examples include silicon nitride, silicon nitride oxide, silicon oxynitride, and silicon oxide. Aluminum, aluminum oxide nitride, aluminum nitride, hafnium oxide, hafnium aluminium An inorganic insulating material such as laminate can be used.

[0083] The insulating layer 110 has a region 110d containing the above-mentioned impurity element. The region 110d is located at least near the interface with the region 108n. In a region where the conductive layer 112 is not provided and a region where the conductive layer 112 is not overlapped, at least It is also located near the interface with the insulating layer 103. As shown in FIGS. The region 110d is provided in a portion that contacts the channel forming region of the semiconductor layer 108. It is preferable that there is no

[0084] The insulating layer 103 contains the above-described impurity element near the interface where the insulating layer 103 contacts the insulating layer 110. The region 103d is also provided near the interface in contact with the region 108n. In this case, the impurity concentration of the portion overlapping with the region 108n is set to be equal to or lower than that of the insulating layer 110. The concentration is lower than that of the area in contact with the

[0085] Here, the impurity concentration in the region 108n becomes higher as it approaches the insulating layer 110. It is preferable that the upper part of the region 108n has a concentration gradient such as this. Therefore, the contact resistance with the conductive layer 120a (or the conductive layer 120b) can be reduced more effectively. In addition, compared to the case where the density is uniform across the entire region 108n, Since the total amount of impurity elements in 108n can be reduced, the cha The amount of impurities that can diffuse into the channel forming region can be kept low.

[0086] The impurity concentration in the region 110d increases as it approaches the semiconductor layer 108. It is preferable to have such a concentration gradient. In the insulating layer 110, the region 110d to which the impurity element is added is different from the other regions. Therefore, the region 108n of the insulating layer 110 can be prevented from releasing oxygen. The region 110d located near the interface functions as a blocking layer against oxygen, and the region 1 This effectively reduces the amount of oxygen supplied to the 08n.

[0087] As will be described later, the process of adding impurity elements to the regions 108n and 110d is a conductive process. This can be done using the layer 112 as a mask, so that the formation of the region 108n can be performed simultaneously. Region 110d can be formed in a self-aligned manner.

[0088] 1B, 1C, etc., the high impurity concentration portion of the insulating layer 110 is the semiconductor layer Region 110d is shown as insulating layer 110 to exaggerate its location near the interface with 108. Although the hatched pattern is only shown near the semiconductor layer 108 in the figure, in reality The insulating layer 110 contains the above impurity element throughout its thickness.

[0089] The region 108n and the region 110d each have an impurity concentration of 1×10 19 atoms / cm 3 That's it, 1 x 10 23 atoms / cm 3 Less than or equal to 5 x 10 19 atoms / cm 3 That's it, 5 x 10 22 atoms / cm 3 Less than 1×10, more preferably 20 at oms / cm3 That's it, 1 x 10 22 atoms / cm 3 It is preferred to include areas that are: Furthermore, the region 108n has a higher impurity concentration than the region 110d of the insulating layer 110. It is preferable that the region 108n has a component, because the electrical resistance of the region 108n can be more effectively reduced.

[0090] The concentrations of impurities contained in the regions 108n and 110d are measured by, for example, secondary ion mass spectrometry. Secondary Ion Mass Spectrometry (SIMS) and , X-ray Photoelectron Spectroscopy (XPS) When XPS analysis is used, By combining ion sputtering from the front or back side with XPS analysis, The concentration distribution in the thickness direction can be seen.

[0091] Here, the semiconductor layer 108 and oxygen vacancies that may be formed in the semiconductor layer 108 will be described. do.

[0092] The oxygen vacancies formed in the semiconductor layer 108 are problematic because they affect the transistor characteristics. For example, when oxygen vacancies are formed in the semiconductor layer 108, hydrogen bonds to the oxygen vacancies. When a carrier source is generated in the semiconductor layer 108, This causes a change in the electrical characteristics of the transistor 100, typically a shift in the threshold voltage. Therefore, it is preferable that the semiconductor layer 108 have as few oxygen vacancies as possible.

[0093] Therefore, in one aspect of the present invention, the insulating film near the semiconductor layer 108, specifically, the semiconductor The insulating layer 110 located above the dielectric layer 108 and the insulating layer 103 located below are made of oxide. The insulating layer 103 and the insulating layer 110 are formed into a semiconductor film by heat or the like during the manufacturing process. By transferring oxygen to the semiconductor layer 108, oxygen vacancies in the semiconductor layer 108 can be reduced. It becomes Noh.

[0094] Furthermore, the semiconductor layer 108 preferably has a region in which the atomic ratio of In is greater than the atomic ratio of M. The higher the atomic ratio of In, the more the field-effect mobility of the transistor can be improved. Cut.

[0095] In the case of metal oxides containing In, Ga, and Zn, the bonding strength between In and oxygen is greater than that between Ga and oxide. Therefore, when the atomic ratio of In is large, oxygen deficiency occurs in the metal oxide film. In addition, even if the metal element shown above as M is used instead of Ga, the same problem occurs. When there are many oxygen vacancies in the metal oxide film, the electrical characteristics of the transistor tend to deteriorate. This can lead to degradation and reduced reliability.

[0096] However, in one embodiment of the present invention, the semiconductor layer 108 containing a metal oxide contains a very large amount of Since oxygen can be supplied, it is possible to use metal oxide materials with a large atomic ratio of In. This allows for extremely high field-effect mobility, stable electrical characteristics, and high reliability. It is possible to realize a transistor having such a structure.

[0097] For example, the atomic ratio of In is 1.5 times or more, or 2 times or more, or Preferably, a metal oxide having a molten metal content of 3 times or more, 3.5 times or more, or 4 times or more is used. It is possible.

[0098] In particular, the atomic ratio of In, M, and Zn in the semiconductor layer 108 is In:M:Zn=5:1. : 6 or its vicinity (when In is 5, M is 0.5 or more and 1.5 or less, and Zn is 5 It is preferable that the ratio of the number of In, M, and Zn atoms is 7 or more (including 7 or less). It is preferable that the composition of the semiconductor layer 108 is In:M:Zn=4:2:3 or a value close to that. As the composition, the ratio of the number of atoms of In, M, and Zn in the semiconductor layer 108 may be approximately equal. That is, the ratio of the number of In, M, and Zn atoms is In:M:Zn=1:1:1 or It may also include nearby materials.

[0099] For example, the above-mentioned high field effect mobility transistor is used as a gate driver for generating a gate signal. By using this as a driver, it is possible to provide a display device with a narrow frame width (also called a narrow frame). In addition, the above-mentioned transistors with high field effect mobility are used in the source driver (especially the source It can be used for a demultiplexer connected to the output terminal of the shift register of the driver. As a result, it is possible to provide a display device with a small number of wires connected to the display device.

[0100] Even if the semiconductor layer 108 has a region in which the atomic ratio of In is greater than the atomic ratio of M, However, if the crystallinity of the semiconductor layer 108 is high, the field-effect mobility may be reduced. The crystallinity of 108 can be determined by, for example, X-ray diffraction (XRD). or by transmission electron microscopy (TEM). This can be analyzed using a TEM (Electron Microscope).

[0101] Here, impurities such as hydrogen or moisture mixed into the semiconductor layer 108 may cause transistor characteristics Therefore, in the semiconductor layer 108, hydrogen or water The fewer impurities such as silicon dioxide, the better. By using a thin film, a transistor having excellent electrical characteristics can be fabricated. By reducing the impurity concentration and the defect level density (reducing oxygen vacancies), The carrier density can be reduced. The transistor has electrical characteristics in which the threshold voltage is negative (also called normally on). In addition, a transistor using such a metal oxide film has a significant off-state current. Therefore, very small characteristics can be obtained.

[0102] The semiconductor layer 108 may have a stacked structure of two or more layers.

[0103] For example, the semiconductor layer 108 may be formed by stacking two or more metal oxide films having different compositions. For example, when an In-M-Zn oxide is used, the number of atoms of In, M, and Zn is The ratio is In:M:Zn=5:1:6, In:M:Zn=4:2:3, In:M:Zn=1 :1:1, In:M:Zn=2:2:1, In:M:Zn=1:3:4, In:M:Zn =1:3:2 or a film formed using a sputtering target with a ratio of approximately It is preferable to use two or more laminated layers.

[0104] In addition, the semiconductor layer 108 may be formed by stacking two or more metal oxide films having different crystallinity. In this case, by using the same oxide target and changing the film formation conditions, It is preferable that they are formed continuously without touching each other.

[0105] For example, the oxygen flow rate during the deposition of the first metal oxide film is set to be equal to the oxygen flow rate during the deposition of the second metal oxide film. The oxygen flow rate ratio is set to be smaller than that during the formation of the first metal oxide film. During film formation, oxygen is not allowed to flow. This prevents oxygen from flowing during film formation of the second metal oxide film. In addition, the first metal oxide film is more resistant to the oxidation than the second metal oxide film. On the other hand, the second layer provided on the upper side has a lower crystallinity and a higher electrical conductivity. The second metal oxide film is made to have higher crystallinity than the first metal oxide film, thereby Damage during processing of the insulating layer 08 and during deposition of the insulating layer 110 can be suppressed.

[0106] More specifically, the oxygen flow rate ratio during the formation of the first metal oxide film is set to 0% or more and less than 50%. Preferably, it is 0% or more and 30% or less, more preferably 0% or more and 20% or less, and typically 10%. The oxygen flow rate ratio during the formation of the second metal oxide film is set to 50% or more and 100% or less, preferably Preferably, it is 60% or more and 100% or less, more preferably, 80% or more and 100% or less, and even more preferably The first metal oxide film is preferably 90% or more and 100% or less, and typically 100%. The conditions for forming the first metal oxide film and the second metal oxide film, such as pressure, temperature, and power, may be different. By keeping the conditions other than the oxygen flow rate the same, the time required for the film formation process can be shortened. This is preferable.

[0107] By adopting such a configuration, the transistor 100 has excellent electrical characteristics and high reliability. This can be achieved.

[0108] The above is the explanation of the first configuration example.

[0109] [Configuration example 2] Below, a configuration example of a transistor with a part of its configuration different from that of the above-mentioned Configuration Example 1 will be described. .

[0110] In the following, explanations of parts that overlap with the above-mentioned configuration example 1 may be omitted. In the drawings shown below, parts having the same functions as those in the above-mentioned configuration example 1 are indicated by hatching. In some cases, the turns are the same and no symbols are assigned.

[0111] 2A is a top view of the transistor 100, and FIG. 2B is a top view of the transistor 100. 2(C) is a cross-sectional view of the transistor 100 in the channel length direction, and FIG. 2(D) is a cross-sectional view of the transistor 100 in the channel width direction. Cross-sectional view.

[0112] 2 differs from FIG. 1 in that an insulating layer 118 is provided to cover the upper surface of the insulating layer 116. is different.

[0113] The insulating layer 118 functions as a protective layer to protect the transistor 100. 18 has the function of preventing oxygen that may be released from the insulating layer 110 from diffusing to the outside. For example, inorganic insulating materials such as oxides or nitrides can be used. More specific examples include silicon nitride, silicon nitride oxide, silicon oxynitride, and silicon oxide. Aluminum, aluminum oxide nitride, aluminum nitride, hafnium oxide, hafnium aluminium An inorganic insulating material such as laminate can be used.

[0114] In this example, the protective layer has a laminated structure of an insulating layer 116 and an insulating layer 118. However, either the insulating layer 116 or the insulating layer 118 may be made up of multiple layers. For example, the insulating layer 116 may be made up of two or more layers of oxides with different compositions. The insulating layer 116a in contact with the edge layer 110 contains more oxygen than the insulating layer 116b. The insulating layer 16b preferably contains more nitrogen than the insulating layer 116a. By this, the insulating layer 116a can supply a large amount of oxygen to the insulating layer 110, and the insulating layer 116b can supply a large amount of oxygen to the outside. This can suppress the diffusion of impurities such as hydrogen from the substrate.

[0115] [Configuration example 3] Below, a configuration example of a transistor with a part of its configuration different from that of the above-mentioned configuration example 2 will be described. In the following, explanations of parts that overlap with the above-mentioned configuration example 2 may be omitted. In the drawings shown below, parts having the same functions as those in the above-mentioned configuration example 2 are indicated by hatching. In some cases, the turns are the same and no symbols are assigned.

[0116] 3A is a top view of the transistor 100A, and FIG. 3B is a top view of the transistor 100B. 3(C) is a cross-sectional view of the channel length direction of the transistor 100A, and FIG. 3(D) is a cross-sectional view of the channel width direction of the transistor 100A. 1 is a cross-sectional view in the direction of the arrow.

[0117] The transistor 100A has a conductive layer 106 between a substrate 102 and an insulating layer 103. The main difference from Configuration Example 2 is that the conductive layer 106 overlaps the semiconductor layer 108 and the conductive layer 112. It has a convoluted area.

[0118] In the transistor 100A, the conductive layer 106 is a first gate electrode (bottom gate electrode). The conductive layer 112 functions as a second gate electrode (also referred to as a top gate electrode). A part of the insulating layer 103 functions as a first gate insulating layer. A portion of the insulating layer 110 functions as a second gate insulating layer.

[0119] The portion of the semiconductor layer 108 that overlaps with at least one of the conductive layer 112 and the conductive layer 106 , which functions as a channel forming region. The portion of the conductive layer 112 of the conductive film 8 is sometimes called a channel forming region. The area (including the area 108n) that does not overlap with the layer 112 but overlaps with the conductive layer 106 is also A channel can be formed.

[0120] As shown in FIG. 3C, the conductive layer 106 includes a metal oxide layer 114 and an insulating layer 110. and electrically connected to the conductive layer 112 through an opening 142 provided in the insulating layer 103. This allows the conductive layer 106 and the conductive layer 112 to be given the same potential. can be done.

[0121] The conductive layer 106 is made of the same material as the conductive layer 112, the conductive layer 120a, or the conductive layer 120b. In particular, when a material containing copper is used for the conductive layer 106, the wiring resistance can be reduced. The conductive layer 106 has a region 106d. When the insulating layer 103 is formed in this manner, the region 106d is supplied with a gas containing oxygen and a gas having reducing properties. By this plasma treatment, the region 112 This can prevent oxidation of d and suppress deterioration of the electrical characteristics and reliability of the transistor. The plasma treatment performed on the region 106d can be performed on the region 112d of the conductive layer 112. Since this is a similar process to the plasma treatment used in the present invention, a detailed description thereof will be omitted.

[0122] As shown in FIGS. 3A and 3C, the conductive layer 112 and the It is preferable that the conductive layer 106 protrudes outward beyond the edge of the semiconductor layer 108. 3C, the entire semiconductor layer 108 in the channel width direction is covered with the insulating layer 11. 0 and insulating layer 103, and is covered with conductive layer 112 and conductive layer 106.

[0123] With this configuration, the semiconductor layer 108 is subjected to an electric field generated by the pair of gate electrodes. In this case, the conductive layer 106 and the conductive layer 112 can be electrically surrounded by the same material. It is preferable to apply the same potential to the semiconductor layer 108. Since an electric field for the purpose can be effectively applied, the on-current of the transistor 100A can be increased. This also makes it possible to miniaturize the transistor 100A.

[0124] The conductive layer 112 and the conductive layer 106 may not be connected to each other. A constant potential is applied to one of the gate electrodes of the transistor 100A, and a signal for driving the transistor 100A is applied to the other gate electrode. At this time, the transistor 100A may be turned on by applying a potential to one electrode. It is also possible to control the threshold voltage when driving with one electrode.

[0125] This concludes the description of configuration example 3.

[0126] [Application example] In the following description, a semiconductor film containing impurities is used as one electrode of a capacitor element, and a transistor is An example in which the capacitor element is formed on the same surface will be described.

[0127] In the cross-sectional view shown in FIG. 4A, a capacitor is arranged next to the transistor 100 illustrated in Configuration Example 2. An element 130A is provided.

[0128] In the cross-sectional view shown in FIG. 4B, the transistor 100A illustrated in Configuration Example 3 is A capacitance element 130A is provided.

[0129] The capacitive element 130A is formed between the semiconductor layer 108c and the conductive layer 120b, and functions as a dielectric. The insulating layer 110, the insulating layer 116, and the insulating layer 118 are provided.

[0130] The semiconductor layer 108c is provided on the same plane as the semiconductor layer 108. For example, the semiconductor layer 1 The region 108c is formed by processing the same metal oxide film as the semiconductor layer 108, and then forming the same impurity layer as the region 108n. It can be formed by adding a pure element.

[0131] By adopting such a configuration, the capacitor element 130A can be manufactured without increasing the number of steps. can be done.

[0132] The capacitor 130B shown in FIG. 4C has a conductive layer 106c and a semiconductor layer 108c. The semiconductor device has a configuration in which an insulating layer 103 is provided, which functions as a dielectric.

[0133] The conductive layer 106c is provided on the same surface as the conductive layer 106. The conductive layer 106 can be formed by processing the same conductive film.

[0134] The capacitance element 130B can have a thinner dielectric than the capacitance element 130A, so A large-capacitance capacitive element can be formed.

[0135] The above is a description of the application example.

[0136] [Components of semiconductor device] Next, the components included in the semiconductor device of this embodiment will be described in detail.

[0137] 〔substrate〕 There is no particular restriction on the material of the substrate 102, but it should be strong enough to withstand the subsequent heat treatment. For example, single crystals made of silicon or silicon carbide are Semiconductor substrates, polycrystalline semiconductor substrates, compound semiconductor substrates such as silicon germanium, SOI substrates The substrate 102 may be a plate, a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, or the like. In addition, a substrate having a semiconductor element formed thereon may be referred to as the substrate 102. It may be used.

[0138] In addition, a flexible substrate is used as the substrate 102, and the transistor 10 is directly formed on the flexible substrate. Alternatively, a peeling layer may be provided between the substrate 102 and the transistor 100. The release layer may be removed from the substrate 102 after a semiconductor device is partially or completely completed thereon. The transistor 100 can be separated and transferred to another substrate. The above can be transferred to a substrate having poor heat resistance or a flexible substrate.

[0139] [Insulating layer 103] The insulating layer 103 can be formed by sputtering, CVD, evaporation, pulsed laser deposition ( The insulating layer 103 can be formed by using a suitable method such as pulsed laser deposition (PLD). The insulating film can be formed as a single layer or a stack of an oxide insulating film or a nitride insulating film. In order to improve the interface characteristics with the semiconductor layer 108, at least the semiconductor The region in contact with the insulating layer 103 is preferably formed using an oxide insulating film. It is preferable to use a film that releases oxygen when heated.

[0140] The insulating layer 103 may be made of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, or nitride. silicon oxide, aluminum oxide, hafnium oxide, gallium oxide or Ga-Zn oxide The above may be used, and the layer may be formed as a single layer or a laminate.

[0141] In addition, the insulating layer 103 may have a film other than an oxide film such as a silicon nitride film on the side in contact with the semiconductor layer 108. When the film is used, the surface in contact with the semiconductor layer 108 is pretreated with oxygen plasma or the like. and oxidizing the surface or the vicinity of the surface.

[0142] [Conductive film] The conductive layer 112 and the conductive layer 106 function as a gate electrode and a source electrode, respectively. The conductive layer 120a and the conductive layer 120b functioning as a drain electrode may be made of chromium, copper, or aluminum. Aluminum, gold, silver, zinc, molybdenum, tantalum, titanium, tungsten, manganese, A metal element selected from nickel, iron, and cobalt, or a composite containing the above metal elements. They can be formed using gold or an alloy combining the above-mentioned metal elements.

[0143] In addition, the conductive layer 112, the conductive layer 106, the conductive layer 120a, and the conductive layer 120b contain In. -Sn oxide, In-W oxide, In-W-Zn oxide, In-Ti oxide, In-Ti -Sn oxide, In-Zn oxide, In-Sn-Si oxide, In-Ga-Zn oxide, etc. An oxide conductor or a metal oxide film can also be applied.

[0144] Here, we will explain about oxide conductors (OC). For example, oxygen vacancies are formed in a metal oxide having semiconductor properties, and hydrogen is added to the oxygen vacancies. As a result, a donor level is formed near the conduction band. As a result, the metal oxide has high conductivity. The metal oxide that has become a conductor can be called an oxide conductor.

[0145] In addition, as the conductive layer 112, a conductive film containing the oxide conductor (metal oxide) and a metal Alternatively, a laminated structure of a conductive film containing a metal or an alloy may be used. In this case, the insulating layer that functions as a gate insulating film is It is preferable to apply a conductive film containing an oxide conductor to the side in contact with the edge layer.

[0146] The conductive layers 112, 106, 120a, and 120b are made of the above-mentioned gold. Among the group elements, titanium, tungsten, tantalum, and molybdenum are particularly preferred. It is particularly preferable to use a tantalum nitride film. The tantalum nitride film has electrical conductivity and has the following properties with respect to copper, oxygen, or hydrogen: Since the barrier layer 104 has a high barrier property and releases little hydrogen from itself, it is preferable that the barrier layer 104 is in contact with the semiconductor layer 108. It can be suitably used as a conductive film or a conductive film in the vicinity of the semiconductor layer 108 .

[0147] [Insulating layer 110] The insulating layer 110, which functions as a gate insulating film for the transistor 100, etc., is formed by PECVD. The insulating layer 110 can be formed by a sputtering method or the like. silicon nitride film, silicon oxide nitride film, silicon nitride film, aluminum oxide film, hafnium oxide film um film, yttrium oxide film, zirconium oxide film, gallium oxide film, tantalum oxide film, One or more of magnesium oxide film, lanthanum oxide film, cerium oxide film, and neodymium oxide film The insulating layer 110 may have a two-layer laminate structure or a three-layer or more laminate structure. The above laminated structure may also be used.

[0148] The insulating layer 110 in contact with the semiconductor layer 108 is preferably an oxide insulating film. It is more preferable to have a region containing oxygen in excess of the stoichiometric composition. The insulating layer 110 is an insulating film capable of releasing oxygen. For example, The insulating layer 110 is formed by the above method, and the insulating layer 110 after the film formation is subjected to a heat treatment in an oxygen atmosphere. Alternatively, an oxide film may be formed on the insulating layer 110 in an oxygen atmosphere. Oxygen can also be supplied into the insulating layer 110 by, for example, forming a film.

[0149] In addition, the insulating layer 110 is made of a material having a higher dielectric constant than silicon oxide or silicon oxynitride. Materials such as hafnium oxide can also be used. This allows the thickness of the insulating layer 110 to be increased. The leakage current due to the tunnel current can be suppressed. In particular, hafnium oxide, which has crystallinity, It is preferable because it has a higher relative dielectric constant than crystalline hafnium oxide.

[0150] [Semiconductor layer] When the semiconductor layer 108 is an In-M-Zn oxide, in order to form an In-M-Zn oxide film, The sputtering target used in this method must have an In atomic ratio equal to or greater than the M atomic ratio. The atomic ratio of the metal elements in such a sputtering target is preferably In:M :Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=2:1:3, In:M:Zn=3:1:2, In:M:Zn=4:2:4.1, In:M:Zn=5: 1:6, In:M:Zn=5:1:7, In:M:Zn=5:1:8, In:M:Zn= Examples include In:M:Zn=6:1:6 and In:M:Zn=5:2:5.

[0151] In addition, a target containing a polycrystalline oxide is used as the sputtering target. This is preferable because the semiconductor layer 108 can be easily formed with crystallinity. The atomic ratio of the semiconductor layer 108 is determined by the atomic ratio of the metal elements contained in the sputtering target. The ratio of the number of atoms may vary by ±40%. When the composition of the ring target is In:Ga:Zn=4:2:4.1 [atomic ratio], film formation The composition of the semiconductor layer 108 is approximately In:Ga:Zn=4:2:3 [atomic ratio]. This may be the case.

[0152] When the atomic ratio is described as In:Ga:Zn=4:2:3 or in the vicinity, it means In When the atomic ratio of Ga is 4, the atomic ratio of Ga is 1 or more and 3 or less, and the atomic ratio of Zn is 2 The atomic ratio of In:Ga:Zn is 5:1:6 or more. When describing it as being in the vicinity of , when the atomic ratio of In is 5, the atomic ratio of Ga is 0. The atomic ratio of Zn is greater than 1 and less than 2, and includes the case where the atomic ratio of Zn is greater than 5 and less than 7. When describing that the atomic ratio is In:Ga:Zn=1:1:1 or close to it, When the atomic ratio of Ga is 1, the atomic ratio of Zn is 0.1 or more and 2 or less. This includes cases where the numerical ratio is greater than 0.1 and less than 2.

[0153] The semiconductor layer 108 has an energy gap of 2 eV or more, preferably 2.5 eV or more. In this way, by using metal oxides with a wider energy gap than silicon, As a result, the off-state current of the transistor can be reduced.

[0154] The semiconductor layer 108 preferably has a non-single-crystal structure. This includes the CAAC structure, polycrystalline structure, microcrystalline structure, and amorphous structure, which will be described later. In the structure, the amorphous structure has the highest defect level density, and the CAAC structure has the lowest defect level density. low.

[0155] Below, we explain about CAAC (c-axis aligned crystal). CAAC represents an example of a crystal structure.

[0156] The CAAC structure has multiple nanocrystals (crystalline regions with a maximum diameter of less than 10 nm). It is one of the crystalline structures of thin films, etc., and each nanocrystal has a c-axis oriented in a specific direction and a-axis and The b-axis and b-axis do not have any orientation, and the nanocrystals are continuously connected without forming grain boundaries. In particular, thin films with a CAAC structure have the following characteristics: The c-axis of the thin film is oriented in the thickness direction, the normal direction to the surface on which it is formed, or the normal direction to the surface of the thin film. It has the characteristic of being easy to use.

[0157] CAAC-OS (Oxide Semiconductor) is a highly crystalline oxide semiconductor. On the other hand, CAAC-OS has no clear grain boundaries, It can be said that the decrease in electron mobility caused by the grain boundaries is unlikely to occur. Crystallinity can be reduced by the inclusion of impurities or the generation of defects. It can be said that CAA is an oxide semiconductor with few impurities and defects (such as oxygen vacancies). Oxide semiconductors containing C-OS have stable physical properties. The oxide semiconductor has high heat resistance and high reliability.

[0158] In crystallography, the three axes that make up the unit cell, the a-axis, the b-axis, and the c-axis (crystal It is common to take a unit cell with a specific axis as the c-axis for the layer structure. In a crystal with this structure, the two axes parallel to the plane direction of the layers are the a-axis and the b-axis, and the axis intersecting the layers is the The c-axis is generally defined as the plane of the crystal. Graphite is classified as a hexagonal crystal, and the a-axis and b-axis of the unit cell are parallel to the cleavage plane. The c-axis is perpendicular to the cleavage plane. For example, the layered structure of YbFe2O4 type crystal structure The crystal of InGaZnO4 can be classified as a hexagonal system, and the a-axis and The a and b axes are parallel to the plane direction of the layer, and the c axis is perpendicular to the layer (i.e., the a and b axes).

[0159] An example of the crystal structure of a metal oxide will be described below. Sputtering was performed using a Zn oxide target (In:Ga:Zn=4:2:4.1 [atomic ratio]). The following will be explained as an example of a metal oxide film formed by the ring method. Metal oxide formed by sputtering at a plate temperature of 100°C to 130°C is either the nc (nano crystal) structure or the CAAC structure. On the other hand, if the substrate temperature is set to room temperature (RT), Metal oxides formed by sputtering tend to have an nc crystal structure. The term room temperature (RT) as used herein includes the temperature at which the substrate is not intentionally heated.

[0160] [Example of manufacturing method] An example of a method for manufacturing a transistor of one embodiment of the present invention will be described below. The transistor 100 illustrated in the second configuration example will be used as an example.

[0161] The thin films (insulating films, semiconductor films, conductive films, etc.) that constitute the semiconductor device are formed by sputtering. method, chemical vapor deposition (CVD) method , vacuum evaporation, pulsed laser deposition (PLD) ion) method, Atomic Layer Deposition (ALD) The CVD method can be a plasma-enhanced chemical vapor deposition (PECVD) method. There are methods such as VD (Plasma Enhanced CVD) and thermal CVD. One of the thermal CVD methods is metal organic chemical vapor deposition (MOCVD). c CVD) method.

[0162] In addition, thin films (insulating films, semiconductor films, conductive films, etc.) that constitute semiconductor devices are formed by spin coating, Dip, spray coating, droplet ejection method (inkjet, dispense, screen printing , offset printing), doctor knife, slit coat, roll coat, curtain Tools (equipment) such as a stencil coater and knife coater can be used.

[0163] Furthermore, when processing the thin films that make up the semiconductor device, photolithography and other methods are used. Other methods include nanoimprinting, sandblasting, and lift-off. The thin film may be processed by a method such as a masking method. The island-shaped thin film may be directly formed by the film method.

[0164] There are two typical photolithography methods: A resist mask is formed on the thin film to be processed by etching or the like. The other method is to remove the photomask after forming a photosensitive thin film. Then, the thin film is processed into a desired shape by performing development.

[0165] In photolithography, the light used for exposure is, for example, i-line (wavelength 365 nm), It uses g-ray (wavelength 436 nm), h-ray (wavelength 405 nm), or a mixture of these. In addition, ultraviolet light, KrF laser light, ArF laser light, etc. can be used. The exposure may also be performed by immersion exposure. Using extreme ultraviolet (EUV) and X-rays, Also, electron beams can be used instead of light for exposure. The use of light, X-rays or electron beams is preferred because it allows for extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, the photomask It is unnecessary.

[0166] There are three methods for etching thin films: dry etching, wet etching, and sandblasting. Methods such as these can be used.

[0167] 5 and 6 show the transistor 100A at each stage of the manufacturing process. The cross sections in the channel length direction and the channel width direction are shown side by side.

[0168] [Formation of Conductive Layer 106] A conductive film is formed on the substrate 102 and processed by etching to form a gate electrode. A functional conductive layer 106 is formed.

[0169] [Plasma Treatment of Conductive Layer 106] Next, before the insulating layer 103 is formed, a gas containing oxygen and a reducing gas are introduced into the region 106d. A plasma treatment 150 is performed using a mixed gas of gases having the following components (FIG. 5(A)). By performing the plasma treatment on the region 1d, the region 1 The plasma treatment is performed in the same process as the plasma treatment of the conductive layer 112. The plasma treatment is performed. The plasma treatment is described in detail in the section on plasma treatment of the conductive layer 112. will be explained.

[0170] [Formation of insulating layer 103] Next, the insulating layer 103 is formed to cover the substrate 102 and the conductive layer 106. It can be formed by using a PECVD method, an ALD method, a sputtering method, or the like. The formation of the insulating layer 103 is preferably carried out in the same processing chamber as the plasma processing 150. Furthermore, the deposition process of the insulating layer 103 is preferably performed at the same temperature as the plasma treatment. I wish.

[0171] After the insulating layer 103 is formed, a treatment for supplying oxygen to the insulating layer 103 may be performed. For example, plasma treatment or heat treatment can be performed in an oxygen atmosphere. The insulating layer 103 is doped with oxygen by plasma ion doping or ion implantation. Good too.

[0172] [Formation of Semiconductor Layer 108] Next, a metal oxide film is formed on the insulating layer 103 and processed to form island-shaped semiconductor layers. The conductor layer 108 is formed (FIG. 5(B)).

[0173] The metal oxide film is formed by a sputtering method using a metal oxide target. is preferred.

[0174] In addition, when forming a metal oxide film, in addition to oxygen gas, an inert gas (e.g., helium Gases such as argon gas and xenon gas may be mixed. The higher the ratio of oxygen gas to the total deposition gas when depositing a film (hereinafter referred to as the oxygen flow ratio), This can improve the crystallinity of the metal oxide film, resulting in highly reliable transistors. On the other hand, the lower the oxygen flow rate ratio, the lower the crystallinity of the metal oxide film, and the higher the on-current. The transistor may be a transistor having a gate resistance.

[0175] The metal oxide film is formed under the following conditions: the substrate temperature is preferably from room temperature to 200° C. For example, the substrate temperature during film formation may be set to between room temperature and 140°C. If the substrate temperature is set to 100°C or higher but lower than 140°C, productivity will be increased, which is preferable. Alternatively, the crystallinity can be reduced by forming a metal oxide film without intentionally heating it. It is possible.

[0176] In addition, before forming the metal oxide film, water, hydrogen, and organic substances adsorbed on the surface of the insulating layer 103 are removed. It is preferable to perform a treatment for removing the oxides or the like, or a treatment for supplying oxygen into the insulating layer 103. For example, heat treatment can be performed at a temperature of 70°C or higher and 200°C or lower in a reduced pressure atmosphere. Alternatively, plasma treatment may be performed in an atmosphere containing oxygen. When plasma treatment is performed in an atmosphere containing nitrogen gas, organic matter on the surface of the insulating layer 103 is removed. After such a treatment, the surface of the insulating layer 103 is exposed to the atmosphere. It is preferable to form the metal oxide film continuously without any additional steps.

[0177] The metal oxide film is processed by either wet etching or dry etching. In this case, the part of the insulating layer 103 that does not overlap with the semiconductor layer 108 may be used. The part may be etched and thinned.

[0178] After the metal oxide film is formed or processed into the semiconductor layer 108, the metal oxide film or Alternatively, heat treatment may be performed to remove hydrogen or water from the semiconductor layer 108. The temperature is typically between 150°C and below the strain point of the substrate, or between 250°C and 450°C. or 300°C or higher and 450°C or lower.

[0179] The heat treatment can be performed in an atmosphere containing a rare gas or nitrogen. After heating in air, the material may be heated in an atmosphere containing oxygen. It is preferable that the mixture does not contain oxygen, water, etc. The heat treatment is carried out using an electric furnace, an RTA device, etc. By using an RTA device, the heat treatment time can be shortened.

[0180] [Formation of insulating layer 110 and metal oxide film 114f] Next, the insulating layer 110 and the metal oxide film 11 are formed on the insulating layer 103 and the semiconductor layer 108. 4f is laminated to form a film (Figure 5(C)).

[0181] The insulating layer 110 may be an oxide film such as a silicon oxide film or a silicon oxynitride film. The film is deposited in a plasma enhanced chemical vapor deposition (PECVD) system, or simply called a plasma CVD system. It is preferable to form the film by using a PECVD method using microwaves. It may be formed.

[0182] The metal oxide film 114f is preferably formed in an atmosphere containing oxygen, for example. It is preferable to form the film by sputtering in an atmosphere containing oxygen. Oxygen can be supplied to the insulating layer 110 when the metal oxide film 114f is formed.

[0183] The metal oxide film 114f is formed by an oxide film containing the same metal oxide as that of the semiconductor layer 108. When forming a film by a sputtering method using a target, the above method can be used. Cut.

[0184] For example, the metal oxide film 114f is formed under the following conditions: oxygen is used as the film-forming gas; The metal oxide film may be formed by reactive sputtering using a metal target. When aluminum is used as the base, an aluminum oxide film is formed. can be done.

[0185] When forming the metal oxide film 114f, the total flow rate of the film forming gas introduced into the film forming chamber of the film forming apparatus is The higher the oxygen flow rate ratio to the total oxygen flow rate (oxygen flow rate ratio) or the oxygen partial pressure in the deposition chamber, the greater the insulating layer 1 The oxygen supplied in the 10 can be increased. The oxygen flow ratio or oxygen partial pressure can be increased, for example, to 5 0% or more and 100% or less, preferably 65% ​​or more and 100% or less, more preferably 80% or more The oxygen flow rate ratio is preferably 100% or less, and more preferably 90% or more and 100% or less. It is preferable to set the oxygen partial pressure to 0% and to make the oxygen partial pressure as close to 100% as possible.

[0186] In this way, the metal oxide film 114f is formed by sputtering in an atmosphere containing oxygen. By forming the metal oxide film 114f, oxygen is supplied to the insulating layer 110. In addition, it is possible to prevent oxygen from being released from the insulating layer 110. 10 can trap an extremely large amount of oxygen. Then, by the subsequent heat treatment, A large amount of oxygen can be supplied to the conductor layer 108. As a result, the oxygen in the semiconductor layer 108 Defects can be reduced, and highly reliable transistors can be realized.

[0187] After the metal oxide film 114f is formed, a heat treatment is performed to remove the metal oxide film from the insulating layer 110. Oxygen may be supplied to the conductor layer 108. The heat treatment may be performed by using one or more of nitrogen, oxygen, and a rare gas. The heating can be carried out in an atmosphere containing the above-mentioned compound at a temperature of 200°C or higher and 400°C or lower.

[0188] Subsequently, after the metal oxide film 114f is formed, the metal oxide film 114f, the insulating layer 110, and The insulating layer 103 is then partially etched to form an opening reaching the conductive layer 106 . This allows the conductive layer 112 and the conductive layer 106 to be formed later to be electrically connected through the opening. It can be connected.

[0189] [Formation of Conductive Layer 112 and Metal Oxide Layer 114] Subsequently, a conductive film 112f that will become the conductive layer 112 is formed on the metal oxide film 114f ( The conductive film 112f is formed by sputtering using a metal or alloy sputtering target. It is preferable to form the film by sputtering.

[0190] Subsequently, the conductive film 112f and the metal oxide film 114f are partially etched to form the conductive layer 11 2 and a metal oxide layer 114 are formed (FIG. 5(E)). 114f are preferably processed using the same resist mask. The metal oxide film 114f is etched using the etched conductive layer 112 as a hard mask. You may also use the

[0191] This forms the conductive layer 112 and the metal oxide layer 114 whose top surface shapes are roughly the same. It is possible.

[0192] In this way, the top and side surfaces of the semiconductor layer 108 and the insulating layer 110 are removed without etching. By covering the insulating layer 103 with the insulating layer 110, the conductive layer 112 and the like can be etched. During this process, the semiconductor layer 108 and the insulating layer 103 are partially etched and prevented from becoming thinner. It is possible.

[0193] [Fueling of impurity elements] Next, the conductive layer 112 is used as a mask to implant impurity elements into the insulating layer 110 and the semiconductor layer 108. 140 is supplied (also called added or injected) to the region 108n and the region 110. d and region 103d are formed (FIG. 6(A)). That is, in the region overlapping with the conductive layer 112, the conductive layer 112 serves as a mask, and the impurity element 140 is Not supplied.

[0194] The impurity element 140 is preferably supplied by plasma ion doping or ion implantation. These methods can be used to measure the concentration profile in the depth direction by ion acceleration. The plasma ion doping can be controlled with high precision by adjusting the voltage and dose. By using this method, productivity can be improved. By using this, the purity of the impurity element to be supplied can be increased.

[0195] In the supplying process of the impurity element 140, the interface between the semiconductor layer 108 and the insulating layer 110, is a portion of the semiconductor layer 108 near the interface, or a portion of the insulating layer 110 near the interface. It is preferable to control the treatment conditions so that the highest concentration is obtained. The method supplies the impurity element 140 at an optimum concentration to both the semiconductor layer 108 and the insulating layer 110. It is possible.

[0196] The impurity elements 140 include hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, arsenic, Examples include aluminum, magnesium, silicon, and rare gas elements. Representative examples of gas elements include helium, neon, argon, krypton, and xenon. In particular, boron, phosphorus, aluminum, magnesium, or silicon can be used. It is preferable that:

[0197] As a source gas of the impurity element 140, a gas containing the above impurity element can be used. When supplying boron, typically B2H6 gas or BF3 gas can be used. In addition, when supplying phosphorus, PH3 gas can be typically used. Alternatively, a mixed gas obtained by diluting these source gases with a rare gas may be used.

[0198] Other raw material gases include CH4, N2, NH3, AlH3, AlCl3, SiH4, Si2H6, F2, HF, H2, (C5H5)2Mg, and rare gases can be used. In addition, the ion source is not limited to gas, and solids or liquids vaporized by heating can also be used. good.

[0199] The addition of the impurity element 140 affects the composition, density, thickness, etc. of the insulating layer 110 and the semiconductor layer 108. This can be controlled by setting conditions such as acceleration voltage and dose amount, taking into consideration the above.

[0200] For example, when adding boron by ion implantation or plasma ion doping, The acceleration voltage is, for example, 5 kV or more and 100 kV or less, preferably 7 kV or more and 70 kV or less, more preferably 100 kV or more and 50 kV or less. Preferably, the voltage can be in the range of 10 kV to 50 kV. Ba1×10 13 ions / cm 2 More than 1×10 17 ions / cm 2 Below, preferably 1 x10 14 ions / cm 2 5x10 or more 16 ions / cm 2 Below, more preferably 1 x10 15 ions / cm 2 That's it, 3 x 10 16 ions / cm 2 The following range should be met: can be done.

[0201] In addition, when phosphorus ions are added by ion implantation or plasma ion doping, The acceleration voltage is, for example, 10 kV or more and 100 kV or less, preferably 30 kV or more and 90 kV or less. The voltage can be set to a value in the range of 40 kV or more and 80 kV or less, more preferably in the range of 40 kV or more and 80 kV or less. For example, 1 x 10 13 ions / cm 2 More than 1×10 17 ions / cm 2 Below, I prefer Or 1 x 10 14 ions / cm 2 5x10 or more 16 ions / cm 2 The following is more preferred: Or 1 x 10 15 ions / cm 2 That's it, 3 x 10 16 ions / cm2 The following range and It is possible.

[0202] The method of supplying the impurity element 140 is not limited to this, and may be, for example, a plasma treatment or A treatment utilizing thermal diffusion by heating may also be used. In the case of a plasma treatment method, the added Plasma is generated in a gas atmosphere containing impurity elements, and plasma processing is performed. The plasma generating device may be a drive device. Etching equipment, ashing equipment, plasma CVD equipment, high density plasma CVD equipment, etc. can be used.

[0203] In one embodiment of the present invention, the impurity element 140 is supplied to the semiconductor layer 108 through the insulating layer 110. Therefore, even if the semiconductor layer 108 has crystallinity, impurities can be This can prevent the crystallinity from being damaged when the element 140 is supplied. This is suitable when a decrease in the electrical resistance results in an increase in electrical resistance.

[0204] [Plasma Treatment of Conductive Layer 112] Next, before the insulating layer 110 is formed, the region 112d is exposed to a gas containing oxygen and a reducing gas. A plasma treatment 150 is performed using a mixed gas of gases having the following components (FIG. 6(B)). By performing the plasma treatment on the region 11d, the region 11d is The oxidation of 12d is inhibited.

[0205] Furthermore, oxygen can be supplied into the insulating layer 110 by the plasma treatment 150. Therefore, oxygen in the insulating layer 110 can be diffused into the semiconductor layer 108 by a subsequent heat treatment. This allows the carrier density in the channel formation region of the semiconductor layer 108 to be reduced. As described above, the region 110d containing the impurity element is formed in the insulating layer 110. Therefore, the diffusion of oxygen into the region 108n of the semiconductor layer 108 is suppressed, and the channel formation It is possible to selectively supply more oxygen to a region.

[0206] When performing plasma processing, first, a first gas containing oxygen element and not containing hydrogen element is mixed with a under an atmosphere containing a mixed gas of a first gas containing hydrogen element and not containing oxygen element, A plasma treatment is performed on the surface of the conductive layer 112. The first gas is, for example, N2O( Nitrogen such as nitrous oxide (nitrous oxide), NO2 (nitrogen dioxide), and NO (nitric oxide) It is preferable to use a gas containing elemental oxides, O2 (oxygen), O3 (ozone), or the like. The second gas may be, for example, a gas containing NH3 (ammonia) or H2 (hydrogen). It is particularly preferable to use N2O and NH3 as the mixed gas used in the plasma treatment. In addition, it is preferable to use a mixed gas containing a rare gas such as Ar.

[0207] The ratio of the first gas to the second gas in the mixed gas is determined by the ratio of the gases supplied to the plasma processing chamber. This can be controlled by controlling the flow rate of each gas. The ratio of the two gases can be expressed, for example, as a volume ratio, partial pressure ratio, or weight ratio. Here, the flow rate ratio of the two types of gases supplied to the processing chamber is determined by the volume ratio of the two types of gases and The voltage division ratio roughly corresponds to the voltage division ratio.

[0208] If the ratio of the second gas is too low (the flow rate is too small), the oxidation reaction will occur more frequently than the reduction reaction. On the other hand, the ratio of the second gas is If the temperature is too high, excess hydrogen atoms in the second gas may penetrate into the semiconductor layer 108 through the conductive layer 112. There is a risk that the carrier density of the semiconductor layer 108 will increase due to diffusion into the channel formation region. Therefore, it is preferable that the flow rate of the second gas is at least equal to or less than the flow rate of the first gas. This can reduce the amount of hydrogen elements supplied to the semiconductor layer 108. This is because even if there is unreacted excess hydrogen in the second gas, the first gas It is presumed that this is because the hydrogen reacts with the oxygen contained in the hydrogen and is discharged from the treatment chamber in the form of hydroxide. .

[0209] The flow rate ratio of the first gas to the second gas is as follows: The flow rate of the gas is set to 0.5% or more and 100% or less, preferably 1% or more and 90% or less, more preferably Preferably, the ratio is 3% or more and 80% or less, more preferably 3% or more and 60% or less, and even more preferably 3% or more. It can be set to more than 50% or less.

[0210] [Formation of insulating layers 116 and 118] Next, the insulating layer 116 and the insulating layer 118 are formed in this order (FIG. 6(C)). The conductive layer 112 after the plasma treatment is continuously formed without being exposed to the atmosphere. It is preferable that the insulating layer 116 is formed by using a plasma-enhanced chemical vapor deposition (plasma CVD) method. In this case, it is preferable to perform the plasma treatment and the formation of the insulating layer 116 in the same apparatus. It is preferable that the plasma treatment and the formation of the insulating layer 116 are performed successively in the same deposition chamber. It is preferred that the films be performed at the same temperature.

[0211] In addition, the insulating layer 116 containing oxide is formed using a deposition gas containing silicon element or the like. A mixed gas containing a deposition gas and the first gas used in the plasma treatment is used. It is preferable that the same gas containing an oxygen element is used for the plasma treatment and the formation of the insulating layer 116. This allows the interface between the insulating layer 110 and the insulating layer 116 to be excellent. For example, N2O gas is used as the first gas, and a mixture containing N2O gas and SiH4 (silane) gas is used. A silicon oxynitride layer can be deposited using the combined gas as a deposition gas.

[0212] The insulating layer 116 is formed in the same processing chamber as the plasma processing 150. Furthermore, the deposition process of the insulating layer 116 is preferably performed at the same temperature as the plasma treatment 150. It is preferable that

[0213] The insulating layer 118 is preferably formed as a protective layer to protect the transistor 100. That is, it is designed to prevent oxygen that may be released from the insulating layer 110 from diffusing to the outside. The insulating layer 118 is preferably processed in the same processing chamber as the insulating layer 116. There is no limitation.

[0214] When the insulating layer 116 or the insulating layer 118 is formed by the plasma CVD method, the film formation temperature is If the temperature is too high, the impurities contained in the region 108n etc. may cause the channel forming region of the semiconductor layer 108 to There is a risk that the insulating layer may diffuse into the surrounding area, and the electrical resistance of the region 108n may increase. The deposition temperature of the insulating layer 116 or the insulating layer 118 is, for example, 150° C. or higher and 400° C. or lower. Preferably, the temperature is 180°C or higher and 360°C or lower, and more preferably, 200°C or higher and 250°C or lower. By forming the insulating layer 116 or the insulating layer 118 at a low temperature, the channel Even a transistor with a short length can have good electrical characteristics.

[0215] [Heat Treatment] After the insulating layer 116 or the insulating layer 118 is formed, heat treatment is performed. , in an atmosphere containing one or more of rare gases, at 150°C or higher and 450°C or lower, preferably 20 It is preferable to carry out the heat treatment at a temperature of 0°C or higher and 400°C or lower. For example, by performing a heat treatment at the above temperature, The impurity element 140 is diffused appropriately and locally uniformed, and the ideal concentration of the impurity element is obtained. The gradient regions 108n and 110d can be formed. If the temperature is too high (for example, 500° C. or higher), the impurity element 140 will diffuse into the channel forming region. This may cause deterioration in the electrical characteristics and reliability of the transistor. 106d or the region 112d of the conductive layer 112 is prevented from being oxidized even when heat treatment is performed. It is preferable.

[0216] In addition, when the impurity element 140 is supplied to the region 108n, the semiconductor layer 108 and the insulating layer 11 In some cases, defects in the 0 can be repaired by heat treatment.

[0217] Furthermore, oxygen is introduced from the insulating layer 110 to the channel formation region of the semiconductor layer 108 by the heat treatment. At this time, the insulating layer 110 has an impurity concentration near the interface with the region 108n. Since the region 110d to which the pure element 140 is supplied is formed, the element is released from the insulating layer 110. As a result, the oxygen in the region 108n is prevented from diffusing into the region 108n. Furthermore, at this time, the insulating layer 110 can be prevented from becoming highly resistive. The region 110d is not formed in the portion of the semiconductor layer 108 that overlaps with the channel formation region. Therefore, oxygen released from the insulating layer 110 is selectively supplied to the channel forming region. can be done.

[0218] In addition, since the region 108n has more oxygen vacancies than the channel formation region, The heat treatment gets rid of the hydrogen contained in the channel formation region by the oxygen vacancies. This is expected to have the effect of reducing the hydrogen concentration in the channel formation region. This allows for the realization of a more reliable transistor. The hydrogen atoms in the region 108n are bonded to oxygen vacancies in the region 108n to generate carriers. A resistive region 108n can be realized.

[0219] Note that the heat treatment may be performed before the insulating layer 116 is formed. It is more preferable to perform this process after forming the insulating layer 116 or the insulating layer 118. 8, by using an insulating film that does not easily diffuse oxygen, the oxygen is released from the insulating layer 110 by heat treatment. The oxygen is prevented from diffusing to the outside and supplied to the channel forming region of the semiconductor layer 108. This allows for a greater amount of oxygen to be released.

[0220] [Formation of Openings 141a and 141b] Next, a mask is formed by lithography at a desired position on the insulating layer 118, and then the insulating layer 118, insulating layer 116, and part of insulating layer 110 are etched to form region 108n. An opening 141a and an opening 141b are formed.

[0221] [Formation of Conductive Layer 120a and Conductive Layer 120b] Subsequently, a conductive film is formed on the insulating layer 118 so as to cover the openings 141a and 141b. The conductive film is formed and processed into a desired shape to form the conductive layer 120a and the conductive layer 120b. (Figure 6(D)).

[0222] Through the above steps, the transistor 100A can be manufactured. When the stencil 100A is applied to the pixels of a display device, a protective insulating layer, a planarizing layer, A step of forming at least one of the pixel electrodes and the wiring may be added.

[0223] The above is an explanation of an example of the manufacturing method.

[0224] The configuration examples, manufacturing method examples, and corresponding drawings etc. illustrated in this embodiment mode are merely examples. In addition, a part of it may be implemented by appropriately combining it with other configuration examples, manufacturing method examples, drawings, etc. can be done.

[0225] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0226] (Embodiment 2) In this embodiment, an example of a display device including the transistor described in the above embodiment will be described. We will explain the following.

[0227] [Configuration example] FIG. 7A is a top view of a display device 700. The display device 700 is provided with a sealant 712. The device has a first substrate 701 and a second substrate 705 that are twisted together. 1, the second substrate 705, and the area sealed by the sealant 712, the first substrate 70 1, a pixel section 702, a source driver circuit section 704, and a gate driver circuit section 706 are provided. The pixel portion 702 is provided with a plurality of display elements.

[0228] In addition, an FPC 716 (FP C: Flexible Printed Circuit) is connected to the FPC terminal 7 The FPC terminal portion 708 and the signal line 710 are connected by the FPC 716. 7, a pixel section 702, a source driver circuit section 704, and a gate driver circuit section 706. Various signals are supplied to each of these.

[0229] A plurality of gate driver circuit sections 706 may be provided. The path section 706 and the source driver circuit section 704 are separately formed on a semiconductor substrate or the like. The IC chip may be in the form of a packaged IC chip. The IC chip is mounted on the first substrate 70. 1 or can be mounted on FPC716.

[0230] The pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 have The transistor can be a transistor that is a semiconductor device of one embodiment of the present invention. do.

[0231] Examples of display elements provided in the pixel portion 702 include a liquid crystal element and a light-emitting element. The liquid crystal elements used include transmissive liquid crystal elements, reflective liquid crystal elements, and semi-transmissive liquid crystal elements. In addition, LEDs (Light Emitting Diodes) can be used as light emitting elements. Diode), OLED (Organic LED), QLED (Quantum-do Examples of self-luminous light-emitting elements include LEDs, semiconductor lasers, etc. MEMS (Micro Electro Mechanical Systems) using optical interference or optical sensing l Systems) elements, microcapsule type, electrophoresis type, electrowet Display elements that use the LCD technology or the electronic liquid powder technology (registered trademark) can be used. It can also be done as follows.

[0232] The display device 700A shown in FIG. 7B can be suitably used in electronic devices having large screens. For example, a television device, a monitor device, a personal computer, computers (including laptops and desktops), tablets, digital signage, etc. It can be suitably used in the following cases:

[0233] The display device 700A includes a plurality of source driver ICs 721 and a pair of gate driver circuits. It has a section 722.

[0234] The plurality of source driver ICs 721 are attached to respective FPCs 723. In addition, the plurality of FPCs 723 have terminals on one side connected to the first substrate 701 and terminals on the other side connected to the printed circuit board. The FPC 723 is bent to connect the printed circuit board 7 24 can be disposed on the back side of the pixel section 702 and mounted on the electronic device, thereby reducing the space required for the electronic device. It is possible to pace things up.

[0235] On the other hand, the gate driver circuit section 722 is formed on the first substrate 701. This makes it possible to realize electronic devices with narrow frames.

[0236] By adopting such a configuration, a large-sized and high-resolution display device can be realized. The surface size is 30 inches or more, 40 inches or more, 50 inches or more, or 60 inches or more diagonally. It can also be applied to the above display devices. Also, the resolution is 4K2K or 8K4K, etc. Such an extremely high-resolution display device can be realized.

[0237] [Cross-section example] In the following, a configuration using a liquid crystal element and an EL element as a display element will be described with reference to FIGS. 8 to 1. 8 to 10 are the same as those shown in FIG. 7(A) but are not necessarily the same as those shown in FIG. 8 and 9 are cross-sectional views taken along the line R. The configurations shown in FIGS. 8 and 9 use liquid crystal elements as display elements. FIG. 10 shows a configuration using an EL element.

[0238] [Explanation of common parts of the display device] The display device 700 shown in FIGS. 8 to 10 includes a wiring portion 711, a pixel portion 702, and The wiring section 71 includes a source driver circuit section 704 and an FPC terminal section 708. 1 includes a signal line 710. The pixel portion 702 includes a transistor 750 and a capacitor 790. The source driver circuit portion 704 includes a transistor 752. 7 shows the case where the capacitance element 790 is not present.

[0239] The transistor 750 and the transistor 752 are the same as those described in Embodiment 1. can be applied.

[0240] The transistor used in this embodiment is made of a highly purified oxide in which the formation of oxygen vacancies is suppressed. The transistor has a semiconductor film. The off-state current of the transistor can be reduced. The holding time of the image signal can be extended, and the writing interval of the image signal etc. can also be set longer when the power is on. Therefore, the frequency of refresh operations can be reduced, which has the effect of reducing power consumption. Play.

[0241] In addition, the transistor used in this embodiment has a relatively high field-effect mobility. For example, a transistor capable of such high speed driving can be used in a display device. By using this in a device, the switching transistor in the pixel section and the driver used in the drive circuit section can be In other words, a separate driver circuit can be formed on the same substrate. Since it is not necessary to use a semiconductor device formed from a silicon wafer or the like, the part of the semiconductor device The number of parts can be reduced. Also, in the pixel section, transistors that can be driven at high speed are used. By using this data, high quality images can be provided.

[0242] The capacitor 790 shown in FIGS. 8 and 10 has the same semiconductor layer as the transistor 750. The lower electrode is formed by processing the film and has a low resistance, and the source electrode or the drain electrode is and an upper electrode formed by processing the same conductive film. Between them, two insulating films are provided to cover the transistor 750. 90 is a laminated structure in which an insulating film that functions as a dielectric film is sandwiched between a pair of electrodes. .

[0243] In addition, a planarization insulating film is formed on the transistor 750, the transistor 752, and the capacitor 790. A veneer 770 is provided.

[0244] The transistor 750 included in the pixel portion 702 and the transistor 750 included in the source driver circuit portion 704 are A transistor having a different structure from the transistor 752 may be used. A top-gate transistor is applied to one side, and a bottom-gate transistor is applied to the other side. The source driver circuit section 704 may be replaced with a gate driver circuit. It can also be read as road section.

[0245] The signal line 710 is the same as the source and drain electrodes of the transistors 750 and 752. In this case, if a low-resistance material such as a material containing copper is used, the wiring This is preferable because it reduces signal delays caused by line resistance and enables display on a large screen.

[0246] The FPC terminal portion 708 includes a connection electrode 760, an anisotropic conductive film 780, and an FPC 716. The connection electrode 760 is electrically connected to a terminal of the FPC 716 via an anisotropic conductive film 780. Here, the connection electrode 760 is electrically connected to the source electrodes of the transistors 750 and 752. The gate electrode and drain electrode are formed from the same conductive film.

[0247] The first substrate 701 and the second substrate 705 may be, for example, a glass substrate or a plastic substrate. A flexible substrate such as a plastic substrate can be used.

[0248] On the second substrate 705 side, there are a light-shielding film 738, a colored film 736, and an insulating film in contact with these. A velum 734 is provided.

[0249] [Configuration example of a display device using a liquid crystal element] The display device 700 shown in FIG. 8 includes a liquid crystal element 775. The liquid crystal element 775 includes a conductive layer 7 72, a conductive layer 774, and a liquid crystal layer 776 therebetween. The conductive layer 772 is provided on the substrate 705 side and functions as a common electrode. The conductive layer 7 is electrically connected to the source electrode or the drain electrode of the transistor 750. The film 72 is formed on the planarization insulating film 770 and functions as a pixel electrode.

[0250] The conductive layer 772 can be formed using a material that transmits or reflects visible light. The transparent material may be, for example, an oxide material containing indium, zinc, tin, or the like. As the reflective material, for example, a material containing aluminum, silver, etc. is used. It is good.

[0251] If a reflective material is used for the conductive layer 772, the display device 700 becomes a reflective liquid crystal display device. On the other hand, when a light-transmitting material is used for the conductive layer 772, the liquid crystal display device becomes a transmissive type. In the case of a transmissive liquid crystal display device, a polarizing plate is provided on the viewing side. A pair of polarizing plates is provided to sandwich the liquid crystal element.

[0252] The display device 700 shown in FIG. 9 includes a liquid crystal element 775 of a horizontal electric field type (for example, FFS mode). A conductive layer 772 is provided with an insulating layer 773 interposed therebetween, and the conductive layer 772 functions as a common electrode. An electric field is generated between the conductive layer 772 and the conductive layer 774, causing the liquid The orientation of the crystal layer 776 can be controlled.

[0253] In FIG. 9, a storage capacitor is formed by a stacked structure of a conductive layer 774, an insulating layer 773, and a conductive layer 772. Therefore, there is no need to provide a separate capacitance element, and the aperture ratio can be increased. It is possible.

[0254] Although not shown in FIGS. 8 and 9, an alignment film in contact with the liquid crystal layer 776 may be provided. In addition, optical members (optical substrates) such as polarizing members, phase difference members, and anti-reflection members may be used. , and light sources such as backlights and sidelights can be provided as appropriate.

[0255] The liquid crystal layer 776 may include a thermotropic liquid crystal, a low molecular weight liquid crystal, a high molecular weight liquid crystal, a polymer dispersion liquid, or the like. Crystals, polymer network type liquid crystals, ferroelectric liquid crystals, antiferroelectric liquid crystals, etc. can be used. In addition, when the in-plane switching method is adopted, a liquid crystal that exhibits a blue phase without using an alignment film may be used. stomach.

[0256] The liquid crystal element mode is TN (Twisted Nematic) mode, VA (Vertical Alignment) mode, IPS (In-Plane-S witching) mode, FFS(Fringe Field Switching) mode, ASM (Axially Symmetric aligned Micro- cell) mode, OCB (Optical Compensated Birefri) ngence) mode, ECB (Electrically Controlled B You can use modes such as reference mode and guest-host mode.

[0257] [Display device using light-emitting elements] The display device 700 shown in FIG. 10 includes a light-emitting element 782. The light-emitting element 782 includes a conductive layer The EL layer 786 includes an organic compound. has inorganic compounds such as quantum dots.

[0258] Materials that can be used for the organic compound include fluorescent materials and phosphorescent materials. In addition, materials that can be used for quantum dots include colloidal quantum dots. materials, alloy-type quantum dot materials, core-shell-type quantum dot materials, core-type quantum dot materials, Examples include:

[0259] In the display device 700 shown in FIG. 10, a conductive layer 772 is formed on a planarization insulating film 770. An insulating film 730 is provided. Here, the light-emitting element 782 has a light-transmitting conductive film 788. The light-emitting element 782 emits light toward the conductive layer 772. a bottom emission structure in which light is emitted from the bottom of the conductive layer 772 and the conductive film 788; It may also be a dual emission structure.

[0260] The colored film 736 is provided at a position overlapping the light emitting element 782, and the light blocking film 738 is an insulating film. 730, the lead wiring portion 711, and the source driver circuit portion 704. The colored film 736 and the light-shielding film 738 are covered with an insulating film 734. The space between the light emitting element 782 and the insulating film 734 is filled with a sealing film 732. 86 is formed in an island shape for each pixel or in a stripe shape for each pixel row, that is, by painting In some cases, the colored film 736 may not be provided.

[0261] [Configuration example in which an input device is provided on a display device] An input device may be provided in the display device 700 shown in FIGS. Examples of such sensors include touch sensors.

[0262] For example, the sensor types include capacitance type, resistive film type, surface acoustic wave type, and infrared type. Various methods can be used, such as electrical, optical, and pressure-sensitive methods. Or, two or more of these can be used. may be used in combination.

[0263] The touch panel has a so-called in-cell structure, in which the input device is formed inside a pair of substrates. A touch panel of this type, an input device formed on the display device 700, is a so-called on-cell type touch panel. or a so-called out-cell type touch panel that is attached to the display device 700. There are some.

[0264] The configuration examples exemplified in this embodiment and the corresponding drawings etc. are at least partly The above can be implemented in appropriate combination with other configuration examples or drawings, etc.

[0265] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0266] (Embodiment 3) In this embodiment, a display device including a semiconductor device of one embodiment of the present invention will be described with reference to FIG. This will be used to explain.

[0267] The display device shown in FIG. 11A includes a pixel portion 502, a driver circuit portion 504, and a protection circuit 50 6 and a terminal portion 507. Note that the protection circuit 506 may not be provided. .

[0268] The transistors included in the pixel portion 502 and the driver circuit portion 504 are the transistors of one embodiment of the present invention. The protection circuit 506 can also be formed using the transistor of one embodiment of the present invention. may be applied.

[0269] The pixel section 502 is a plurality of pixels arranged in X rows and Y columns (X and Y are each independently a natural number of 2 or more). The display device has a plurality of pixel circuits 501 for driving a number of display elements.

[0270] The driving circuit unit 504 is a gate driver that outputs scanning signals to the gate lines GL_1 to GL_X. a source driver 504a that supplies data signals to the data lines DL_1 to DL_Y; The gate driver 504a includes a driver circuit such as a shift register The source driver 504b may be configured to have, for example, a plurality of analog switches. Also, the source driver 504 is configured using a shift register or the like. b may be configured.

[0271] The terminal unit 507 is used to input power, control signals, image signals, etc. from an external circuit to the display device. This refers to the part where terminals for connecting the power supply to the power source are provided.

[0272] When a potential outside a certain range is applied to the wiring to which the protection circuit 506 is connected, the protection circuit 506 The protection circuit 506 shown in FIG. For example, the scanning line GL, which is the wiring between the gate driver 504a and the pixel circuit 501, Various wirings such as the data line DL which is the wiring between the source driver 504b and the pixel circuit 501 Connected.

[0273] The gate driver 504a and the source driver 504b are connected to the pixel section 502 and The gate driver circuit or the source driver circuit may be provided on the same substrate. A separately formed substrate (for example, a drive circuit substrate formed of a single crystal semiconductor film or a polycrystalline semiconductor film) board) by COG or TAB (Tape Automated Bonding) It may also be configured to be implemented in

[0274] In addition, the plurality of pixel circuits 501 shown in FIG. 11(A) may be, for example, The configuration shown in FIG.

[0275] The pixel circuit 501 shown in FIG. 11B includes a liquid crystal element 570, a transistor 550, and a capacitor. The pixel circuit 501 also includes a data line DL_n, a scanning line GL_ m, a potential supply line VL, etc. are connected.

[0276] The potential of one of the pair of electrodes of the liquid crystal element 570 is set appropriately according to the specifications of the pixel circuit 501. The orientation state of the liquid crystal element 570 is set by the written data. A common potential is applied to one of a pair of electrodes of the liquid crystal element 570 included in each of the pixel circuits 501. A common potential may be applied to the pair of liquid crystal elements 570 of the pixel circuits 501 in each row. One of the electrodes may be given a different potential.

[0277] The pixel circuit 501 shown in FIG. 11C includes transistors 552 and 554 and a capacitor. The pixel circuit 501 also includes a data line DL_n , scanning line GL_m, potential supply line VL_a, potential supply line VL_b, etc. are connected to the pixel electrodes GL_m, GL_m, GL_a, GL_b, etc.

[0278] A high power supply potential VDD is applied to one of the potential supply lines VL_a and VL_b. The other terminal is supplied with a low power supply potential VSS. The current flowing through the light-emitting element 572 is controlled in accordance with the potential applied to the light-emitting element 572. The brightness of the light emitted from 72 is controlled.

[0279] The configuration examples exemplified in this embodiment and the corresponding drawings etc. are at least partly The above can be implemented in appropriate combination with other configuration examples or drawings, etc.

[0280] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0281] (Fourth embodiment) In the following, a pixel circuit having a memory for correcting the gradation displayed in the pixel and a The transistors exemplified in Embodiment 1 will be described below. The present invention can be applied to transistors used in pixel circuits.

[0282] [Circuit configuration] 12A shows a circuit diagram of the pixel circuit 400. The pixel circuit 400 includes a transistor M The pixel circuit 400 includes a transistor M2, a capacitor C1, and a circuit 401. The wiring S1, the wiring S2, the wiring G1, and the wiring G2 are connected.

[0283] The transistor M1 has a gate connected to a wiring G1, a source and a drain connected to a wiring S1, and The other terminal is connected to one electrode of the capacitor C1. The gate of the transistor M2 is connected to the wiring. G2, one of the source and drain is connected to the wiring S2, and the other is connected to the other electrode of the capacitor C1, and 401 and 402, respectively.

[0284] The circuit 401 is a circuit including at least one display element. Representative examples include light-emitting elements such as organic EL elements and LED elements, and liquid crystal element, or MEMS (Micro Electro Mechanical Systems) EMS) elements, etc. can be applied.

[0285] The node connecting the transistor M1 and the capacitor C1 is N1, and the node connecting the transistor M2 and the circuit 40 is N2. Let N2 be the node connecting to 1.

[0286] The pixel circuit 400 maintains the potential of the node N1 by turning off the transistor M1. Furthermore, by turning off the transistor M2, the voltage of the node N2 can be maintained. In addition, when the transistor M2 is in the off state, the transistor By writing a predetermined potential to node N1 via capacitor M1, capacitive coupling via capacitor C1 This allows the potential of the node N2 to be changed in accordance with the change in the potential of the node N1.

[0287] Here, one or both of the transistors M1 and M2 may be The transistor using an oxide semiconductor, as exemplified in 1, can be used. Therefore, the potentials of the nodes N1 and N2 can be maintained for a long period of time due to the extremely low off-state current. In addition, when the period for which the potential of each node is held is short (specifically, when the frame In cases where the system frequency is 30 Hz or more, a transistor using a semiconductor such as silicon is used. A printer may also be used.

[0288] [Drive method example] Next, an example of a method of operating the pixel circuit 400 will be described with reference to FIG. (B) is a timing chart relating to the operation of the pixel circuit 400. For ease of understanding, various resistances such as wiring resistance, parasitic capacitances of transistors and wiring, The influence of the threshold voltage of the transistor and the like is not taken into consideration.

[0289] In the operation shown in FIG. 12B, one frame period is divided into a period T1 and a period T2. T1 is a period during which a potential is written to node N2, and T2 is a period during which a potential is written to node N1. It is a period.

[0290] [Period T1] In the period T1, a potential that turns on the transistor is applied to both the wiring G1 and the wiring G2. In addition, the wiring S1 is connected to a fixed potential V ref The first data is supplied to the wiring S2. Voltage V w supply.

[0291] The node N1 is connected to the line S1 via the transistor M1. ref is given. The node N2 is supplied with a first data potential V w is given. Therefore, the potential difference V across the capacitance C1 w -V ref is maintained.

[0292] [Period T2] Subsequently, in a period T2, a potential that turns on the transistor M1 is applied to the wiring G1. A potential that turns off the transistor M2 is applied to the line G2. Data potential V data A predetermined constant potential is applied to the wiring S2, or a floating potential is applied to the wiring S3. It may be in a locking state.

[0293] The node N1 is supplied with a second data potential V data is given. At this time, due to the capacitive coupling of the capacitor C1, the second data potential V data Depending on node N 2 changes by a potential dV. w and electricity In FIG. 12B, the potential dV is a positive value. However, it may be a negative value. That is, the potential V data is the potential V ref It may be lower.

[0294] Here, the potential dV is roughly determined by the capacitance value of the capacitor C1 and the capacitance value of the circuit 401. When the capacitance value of the capacitor C1 is sufficiently larger than the capacitance value of the circuit 401, the potential dV is Data potential V data The potential is close to

[0295] In this way, the pixel circuit 400 is a circuit including a display element that combines two types of data signals. Since the potential supplied to the line 401 can be generated, the gradation can be corrected in the pixel circuit 400. It will be possible to do this.

[0296] Furthermore, the pixel circuit 400 generates a potential that exceeds the maximum potential that can be supplied to the wirings S1 and S2. For example, when a light-emitting element is used, a high dynamic range ( In addition, when using liquid crystal elements, overdriving is possible. It is possible to realize drive, etc.

[0297] [Application example] [Example using liquid crystal element] The pixel circuit 400LC shown in FIG. 12C includes a circuit 401LC. has a liquid crystal element LC and a capacitor C2.

[0298] The liquid crystal element LC has one electrode connected to the node N2 and one electrode connected to the capacitor C2, and the other electrode connected to the Potential V com2 The capacitor C2 is connected to the wiring where the other electrode is at potential V com1 Connect with the wiring given.

[0299] The capacitor C2 functions as a storage capacitor. If the capacitor C2 is not required, it can be omitted. Cut.

[0300] The pixel circuit 400LC can supply a high voltage to the liquid crystal element LC, so that, for example, Overdrive operation allows for high-speed display, and liquid crystal materials with high drive voltage are used. In addition, by supplying a correction signal to the wiring S1 or wiring S2, The gradation can also be corrected according to the operating temperature and the deterioration state of the liquid crystal element LC.

[0301] [Example using light-emitting element] The pixel circuit 400EL shown in FIG. 12D includes a circuit 401EL. includes a light-emitting element EL, a transistor M3, and a capacitor C2.

[0302] The transistor M3 has a gate connected to the node N2 and one electrode of the capacitor C2, and a source and drain connected to the node N2 and one electrode of the capacitor C2. One of the drains is a wiring to which a potential VH is applied, and the other is one electrode of the light-emitting element EL. The capacitor C2 is connected to the other electrode at a potential V com Connect with the wiring given. The other electrode of the light-emitting element EL is at a potential V L Connect with the wiring given.

[0303] The transistor M3 has a function of controlling the current supplied to the light-emitting element EL. functions as a storage capacitor. Capacitor C2 can be omitted if not required.

[0304] In this example, the anode side of the light-emitting element EL is connected to the transistor M3. However, a transistor M3 may be connected to the cathode side. H and potential V L The value of can be changed as appropriate.

[0305] The pixel circuit 400EL generates a light-emitting element by applying a high potential to the gate of the transistor M3. Since a large current can be passed through the child EL, it is possible to realize, for example, HDR display. In addition, by supplying a correction signal to the wiring S1 or wiring S2, the transistor M3 and It is also possible to correct variations in the electrical characteristics of the light-emitting element EL.

[0306] The circuit is not limited to the circuits shown in FIGS. 12(C) and 12(D), and may include other transistors, capacitors, etc. may be added.

[0307] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0308] (Embodiment 5) In this embodiment, a display module that can be manufactured using one embodiment of the present invention will be described. and explain.

[0309] The display module 6000 shown in FIG. 13(A) includes an upper cover 6001 and a lower cover 6002. Between the display device 6006 and the frame 6009, the FPC 6005 is connected. The device has a main board 6010 and a battery 6011.

[0310] For example, a display device manufactured according to one embodiment of the present invention can be used as the display device 6006. The display device 6006 realizes a display module with extremely low power consumption. It is possible.

[0311] The upper cover 6001 and the lower cover 6002 are designed to fit the size of the display device 6006. The shape and dimensions can be changed as appropriate.

[0312] The display device 6006 may have a function as a touch panel.

[0313] The frame 6009 has a function of protecting the display device 6006 and a function of preventing the display device 6006 from being damaged by the operation of the printed circuit board 6010. The insulating film may have a function of blocking electromagnetic waves generated by the insulating film, a function as a heat sink, etc.

[0314] The printed circuit board 6010 includes a power supply circuit, a signal circuit for outputting a video signal and a clock signal. The power supply circuit includes a signal processing circuit, a battery control circuit, etc. The power source may be a battery 6011 .

[0315] FIG. 13(B) is a schematic cross-sectional view of a display module 6000 equipped with an optical touch sensor. is.

[0316] The display module 6000 includes a light emitting section 6015 and a receiving section 6016 provided on a printed circuit board 6010. The optical unit 6016 is enclosed by an upper cover 6001 and a lower cover 6002. The region has a pair of light guide portions (light guide portion 6017a, light guide portion 6017b).

[0317] The display device 6006 is connected to a printed circuit board 6010 and a battery via a frame 6009. The display device 6006 and the frame 6009 are provided so as to overlap with the light guide unit 6011. 017a and fixed to the light guiding portion 6017b.

[0318] Light 6018 emitted from the light emitting unit 6015 is guided to the display device 600 by the light guiding unit 6017a. 6, and reaches the light receiving part 6016 through the light guiding part 6017b. A touch operation is detected when the light 6018 is blocked by a detection object such as an illustration. It is possible.

[0319] A plurality of light emitting sections 6015 are provided along two adjacent sides of the display device 6006, for example. A plurality of light receiving sections 6016 are provided at positions facing the light emitting sections 6015. It is possible to obtain information about the position where the touch operation was performed.

[0320] The light emitting unit 6015 can use a light source such as an LED element, and in particular, can emit infrared light. It is preferable to use a light source that emits light. A photoelectric element that receives light and converts it into an electrical signal can be used. A photodiode such as a photodiode can be used.

[0321] The light emitting section 6015 and the light guiding section 6017a and the light guiding section 6017b transmit light 6018. The light receiving unit 6016 can be disposed below the display device 6006, and external light is received by the light receiving unit 601. 6 and prevent the touch sensor from malfunctioning. By using a resin that allows wires to pass through, malfunction of the touch sensor can be more effectively suppressed.

[0322] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0323] (Embodiment 6) In this embodiment, electronic devices including a display device manufactured using one embodiment of the present invention will be described. and explain.

[0324] The electronic devices exemplified below include a display device according to one embodiment of the present invention in a display portion. Therefore, it is an electronic device that has achieved high resolution. Also, high resolution and a large screen It is possible to make an electronic device that is compatible with both.

[0325] The display unit of the electronic device according to one embodiment of the present invention may be configured to display, for example, full high-definition, 4K2K, 8K4 It can display images with resolutions of 16K, 16K, 8K, or higher.

[0326] Examples of electronic devices include television sets, notebook personal computers, Equipped with relatively large screens such as monitor devices, digital signage, pachinko machines, and game machines In addition to electronic devices, digital cameras, digital video cameras, digital photo frames, mobile phones, Examples of such devices include mobile phones, portable game machines, personal digital assistants, and audio playback devices.

[0327] An electronic device to which one aspect of the present invention is applied may be installed on the interior or exterior walls of a house or building, or the interior of a car or the like. It can be incorporated along a flat or curved surface of the packaging or exterior.

[0328] FIG. 14(A) shows the appearance of the camera 8000 with the viewfinder 8100 attached. This is a diagram.

[0329] The camera 8000 includes a housing 8001, a display unit 8002, operation buttons 8003, and a shutter. The camera 8000 has a button 8004 and the like. The camera 8000 also has a detachable lens 8006. It is attached.

[0330] The camera 8000 may have the lens 8006 and the housing integrated together.

[0331] The camera 8000 can be operated by pressing the shutter button 8004 or by using the touch panel. An image can be captured by touching the display portion 8002.

[0332] The housing 8001 has a mount with electrodes, and is equipped with a finder 8100 and a strobe. It is possible to connect devices such as

[0333] The finder 8100 includes a housing 8101, a display unit 8102, buttons 8103, etc. .

[0334] The housing 8101 is configured to mount the camera 8000 by a mount that engages with the mount of the camera 8000. The finder 8100 is attached to the camera 8000. It can be displayed on the display unit 8102.

[0335] The button 8103 has a function such as a power button.

[0336] The display unit 8002 of the camera 8000 and the display unit 8102 of the viewfinder 8100 are The display device of one embodiment of the present invention can be applied. It may also be La 8000.

[0337] FIG. 14B is a diagram showing the appearance of the head mounted display 8200.

[0338] The head-mounted display 8200 includes a mounting part 8201, a lens 8202, and a main body 82 8203, a display unit 8204, a cable 8205, etc. It has a built-in 8206 battery.

[0339] A cable 8205 supplies power from a battery 8206 to the main body 8203. 203 is equipped with a wireless receiver and the like, and can display received video information on a display unit 8204. The main body 8203 is also equipped with a camera, and can input information on the movements of the user's eyes and eyelids. It can be used as a step.

[0340] In addition, the attachment part 8201 has a flow sensor that moves in accordance with the movement of the user's eyeball at a position where it comes into contact with the user. A plurality of electrodes capable of detecting the current passing through the sensor may be provided, and the sensor may have a function of recognizing the line of sight. In addition, the device may have a function of monitoring the pulse of the user by measuring the current flowing through the electrodes. The mounting part 8201 is equipped with various sensors such as a temperature sensor, a pressure sensor, and an acceleration sensor. The display unit 8204 may have a function to display the user's biological information, and the head of the user may have a function to display the user's biological information. The display unit 8204 may have a function of changing the image displayed on the display unit 8204 in accordance with the user's movements.

[0341] The display device of one embodiment of the present invention can be applied to the display portion 8204.

[0342] 14(C), (D), and (E) are diagrams showing the appearance of the head-mounted display 8300. The head mounted display 8300 includes a housing 8301, a display portion 8302, and a backlight. The lens 8302 has a braided fixture 8304 and a pair of lenses 8305 .

[0343] A user can view the display on the display unit 8302 through the lens 8305 . If the display unit 8302 is curved, the user can feel a high sense of presence. In addition, it is preferable to display different images in different areas of the display unit 8302 through the lens 8304. By viewing through 305, it is possible to perform a three-dimensional display using parallax. The configuration is not limited to one display unit 8302, but two display units 8302 may be provided, and one of the display units may be One display unit may be arranged for each eye.

[0344] Note that the display device of one embodiment of the present invention can be applied to the display portion 8302. A display device including the semiconductor device of one embodiment of this invention has extremely high definition. Even if the image is enlarged using the lens 8305, the pixels are not visible to the user, and the image is displayed more clearly. This makes it possible to display images with a higher sense of reality.

[0345] The electronic devices shown in FIGS. 15A to 15G include a housing 9000, a display portion 9001, a screen Speaker 9003, operation keys 9005 (including a power switch or an operation switch), connection terminal Child 9006, sensor 9007 (force, displacement, position, velocity, acceleration, angular velocity, number of rotations, distance, Light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, (including functions to measure flow rate, humidity, gradient, vibration, odor or infrared rays), It has 9008, etc.

[0346] The electronic devices shown in FIGS. 15A to 15G have various functions. Function to display various information (still images, videos, text images, etc.) on the display, touch panel function , calendar, date or time display functions, various software (programs) a function to control processing by wireless communication, a program recorded on a recording medium, or The electronic device can have the function of reading and processing data. The electronic device may have a variety of functions, including but not limited to the above. In addition, a camera or the like may be provided in the electronic device to take still images or videos and store them on a recording medium (external). It has functions such as saving the captured image to a memory card (built-in to the camera or the internal memory) and displaying the captured image on the display. It may be possible.

[0347] The electronic devices shown in FIGS. 15A to 15G will be described in detail below.

[0348] FIG. 15A is a perspective view showing a television device 9100. 100 is a display unit 9001 with a large screen, for example, 50 inches or more, or 100 inches or more It is possible to incorporate.

[0349] 15(B) is a perspective view showing a portable information terminal 9101. The portable information terminal 9101 is For example, the mobile information terminal 9101 can be used as a smartphone. A speaker 9003, a connection terminal 9006, a sensor 9007, etc. may be provided. The terminal 9101 can display text and image information on multiple surfaces. (See FIG. 15B.) An example of displaying three icons 9050 is shown in the figure. 051 can also be displayed on another surface of the display unit 9001. An example of the information 9051 is , notifications of incoming emails, SNS, phone calls, etc., subject of emails and SNS, sender Name, date and time, battery level, antenna reception strength, etc. An icon 9050 or the like may be displayed in the position where 51 is displayed.

[0350] 15C is a perspective view showing a portable information terminal 9102. The portable information terminal 9102 is , and has the function of displaying information on three or more surfaces of the display unit 9001. An example is shown in which information 9053 and information 9054 are displayed on different surfaces. The person holds the mobile information terminal 9102 in the breast pocket of his / her clothes. The user can also check the information 9053 displayed in a position that can be observed from above. The display can be checked without taking the mobile information terminal 9102 out of a pocket, and for example, a telephone call can be made. You can decide whether to accept it or not.

[0351] 15(D) is a perspective view showing a wristwatch-type portable information terminal 9200. The display unit 9001 can be used as a smart watch, for example. The display surface is curved, and the display can be performed along the curved display surface. In addition, the mobile information terminal 9200 can be used to communicate with, for example, a wireless headset. The mobile information terminal 9200 can also be used for hands-free conversations. The terminal 9006 allows data transmission to and from other information terminals and charging. Charging can also be performed by wireless power supply.

[0352] 15(E), (F), and (G) are perspective views showing a foldable portable information terminal 9201. 15(E) shows the portable information terminal 9201 in an unfolded state, and FIG. 15(G) shows the portable information terminal 9201 in a folded state. Figure 15(F) shows the state where the two are changing from one to the other, Figure 15(E) and Figure 15(G). The portable information terminal 9201 is highly portable when folded and can be easily carried when unfolded. When the display is turned on, the seamless, wide display area provides excellent visibility of the display. The display unit 9001 of the display device 01 is made up of three housings 9000 connected by hinges 9055. For example, the display unit 9001 is bent with a radius of curvature of 1 mm or more and 150 mm or less. It can be done.

[0353] FIG. 16A shows an example of a television device. The television device 7100 has a housing 7 The display unit 7500 is built into the housing 7101. 101 is shown as a supported configuration.

[0354] The television device 7100 shown in FIG. 16A is operated by an operation switch provided in the housing 7101. This can be done by a separate remote control 7111 or a display unit 75. A touch panel may be applied to the remote control 71, and the remote control 71 may be operated by touching the panel. The device 11 may have a display unit in addition to the operation buttons.

[0355] The television device 7100 may be a television broadcast receiver or a network connection device. The communication device may include:

[0356] FIG. 16B shows a notebook personal computer 7200. The mobile computer 7200 includes a housing 7211, a keyboard 7212, a pointing device, and a The housing 7211 includes a display unit 7500 and an external connection port 7214. It is embedded.

[0357] Figure 16(C) and (D) show the digital signage. An example of a sub-sign is shown below.

[0358] The digital signage 7300 shown in FIG. 16C includes a housing 7301, a display unit 7500, and a speaker 7303. In addition, LED lamps, operation keys (power switch, It may have a variety of functions, including a control switch, connection terminals, various sensors, a microphone, etc. Cut.

[0359] FIG. 16(D) shows a digital signage 740 attached to a cylindrical pillar 7401. The digital signage 7400 is a display unit provided along the curved surface of a pillar 7401. It has 7500.

[0360] The larger the display 7500, the more information can be displayed at once, and the closer it is to the human eye. It is easy to attach to the surface, which has the effect of increasing the advertising effectiveness of advertisements, for example.

[0361] It is preferable that the display unit 7500 be configured as a touch panel so that a user can operate it. This will enable the information to be used not only for advertising purposes but also for route information, traffic information, and commercial facility guidance information. It can also be used to provide information that users are looking for.

[0362] Also, as shown in Fig. 16(C) and (D), the digital signage 7300 or the digital The Signage 7400 is connected wirelessly to an information terminal 7311 such as a smartphone carried by the user. For example, the advertisement displayed on the display unit 7500 can be linked by wired communication. The information is displayed on the screen of the information terminal 7311, and the information terminal 7311 is operated. This allows the display on the display unit 7500 to be switched.

[0363] In addition, the Digital Signage 7300 or Digital Signage 7400 can be used with an information terminal. It is also possible to run games using the 7311 as an operating means (controller). This allows an unspecified number of users to participate in and enjoy the game at the same time.

[0364] The display device of one embodiment of the present invention is applied to the display portion 7500 in FIGS. It is possible.

[0365] Although the electronic device of this embodiment has a display unit, the present invention can also be applied to electronic devices that do not have a display unit. One embodiment of the present invention can also be applied to the above.

[0366] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination. [Explanation of symbols]

[0367] 100: transistor, 100A: transistor, 102: substrate, 103: insulating layer, 10 3d: region, 106: conductive layer, 106c: conductive layer, 106d: region, 108: semiconductor layer, 108c: semiconductor layer, 108n: region, 110: insulating layer, 110d: region, 112: conductive layer, 112d: region, 112f: conductive film, 114: metal oxide layer, 114f: metal oxide Film, 116: insulating layer, 116a: insulating layer, 116b: insulating layer, 118: insulating layer, 120a : conductive layer, 120b: conductive layer, 130A: capacitance element, 130B: capacitance element, 140: impurity physical element, 141a: opening, 141b: opening, 142: opening

Claims

1. forming an oxide semiconductor layer over a substrate; forming a first insulating layer on the oxide semiconductor layer; forming a first conductive layer on the first insulating layer, the first conductive layer overlapping the oxide semiconductor layer; performing a plasma treatment after forming the first conductive layer; forming, after the plasma treatment, a second insulating layer having a region in contact with a top surface of the first insulating layer and a region in contact with a side surface of the first conductive layer, the first conductive layer has a region that functions as a gate electrode of a transistor; the plasma treatment is performed in a mixed gas atmosphere of a first gas containing oxygen element but not containing hydrogen element and a second gas containing hydrogen element but not containing oxygen element; The method for manufacturing a semiconductor device, wherein the second gas is ammonia.

2. forming an oxide semiconductor layer over a substrate; forming a first insulating layer on the oxide semiconductor layer; forming a first conductive layer on the first insulating layer, the first conductive layer overlapping the oxide semiconductor layer; performing a plasma treatment after forming the first conductive layer; forming, after the plasma treatment, a second insulating layer having a region in contact with a top surface of the first insulating layer and a region in contact with a side surface of the first conductive layer, the first conductive layer has a region that functions as a gate electrode of a transistor; the plasma treatment is performed in a mixed gas atmosphere of a first gas containing oxygen element but not containing hydrogen element and a second gas containing hydrogen element but not containing oxygen element; A method for manufacturing a semiconductor device, wherein a flow rate of the second gas is 3% or more and 50% or less when a flow rate of the first gas is 100%.

3. In claim 2, A method for manufacturing a semiconductor device, wherein ammonia is used as the second gas.

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