Semiconductor Devices

Abstract

To improve an aperture ratio of a semiconductor device.SOLUTION: A semiconductor device is provided in which a pixel portion including a first thin film transistor and a driver circuit including a second thin film transistor are provided over one substrate. The thin film transistor of the pixel portion includes: a gate electrode layer; a gate insulation layer; an oxide semiconductor layer having a thin film thickness in a peripheral edge; an oxide insulation layer that is in contact with one part of the oxide semiconductor layer; a source electrode layer and a drain electrode layer; and a pixel electrode layer. Each of the gate electrode layer, the gate insulation layer, the oxide semiconductor layer, the source electrode layer, the drain electrode layer, the oxide insulation layer, and a pixel electrode layer, of the first thin film transistor has a light transmissivity. The source electrode layer and the drain electrode layer of the thin film transistor of the driver circuit are covered with a protection insulation layer and made of a conductive material of which a resistance is lower than that of the source electrode layer and the drain electrode layer of the pixel portion.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device including an oxide semiconductor and a manufacturing method thereof.

[0002] In this specification, a semiconductor device is a device that can function by utilizing semiconductor characteristics. This refers to a general category of semiconductor devices, including electro-optical devices such as display devices, semiconductor circuits, and electronic devices. be. [Background technology]

[0003] Light-transmitting metal oxides are used in semiconductor devices. For example, indium oxide Conductive metal oxides such as ITO (indium tin oxide) (hereinafter referred to as oxide conductors) are used in liquid crystal displays. It is used as a transparent electrode material required for display devices such as displays.

[0004] In addition, metal oxides with optical transparency are attracting attention as materials that exhibit semiconductor properties. For example, In-Ga-Zn-O oxides are required for display devices such as liquid crystal displays. It is expected that this technology will be applied to semiconductor materials that are used in thin film transistors (TFTs). It is expected to be applied to the channel layer of a thin-film transistor (FT).

[0005] TFTs that use metal oxides with semiconducting properties (hereinafter referred to as oxide semiconductors) can be used at low temperatures. Therefore, it is possible to manufacture alumina used in display devices. There is growing expectation that it will be a material that replaces or surpasses rufus silicon.

[0006] In addition, by forming a TFT using a light-transmitting oxide conductor and an oxide semiconductor, This makes it possible to fabricate a light-transmitting TFT (see, for example, Non-Patent Document 1).

[0007] In addition, TFTs that use an oxide semiconductor as a channel layer have high field-effect mobility. The TFT can also be used to configure a driving circuit for a display device or the like (for example, See patent document 2. ). [Prior art documents] [Non-patent literature]

[0008] [Non-Patent Document 1] Tetsuo Nozawa, "Transparent Circuits," Nikkei Electronics, August 27, 2007 (No. 959), pp. 39-52 [Non-patent document 2] T.Osada, and 8 others, SID 09 DIGEST, pp.184-187(2009) Summary of the Invention [Problem to be solved by the invention]

[0009] An object of one embodiment of the present invention is to reduce manufacturing costs of a semiconductor device.

[0010] An object of one embodiment of the present invention is to improve the aperture ratio of a semiconductor device.

[0011] An object of one embodiment of the present invention is to increase the resolution of an image displayed on a display portion of a semiconductor device. do.

[0012] An object of one embodiment of the present invention is to provide a semiconductor device that can be driven at high speed. [Means for solving the problem]

[0013] One embodiment of the present invention is a display device having a driver circuit portion and a display portion (also referred to as a pixel portion) over the same substrate. The driver circuit portion includes a source electrode (also referred to as a source electrode layer) and a drain electrode (also referred to as a drain electrode layer). The driving layer (also referred to as a driving layer) is made of a metal and the semiconductor layer is made of an oxide semiconductor. The display device has a thin film transistor for a driving circuit and wiring for the driving circuit made of metal. The display portion includes a source electrode layer and a drain electrode layer made of an oxide conductor and a semiconductor layer The pixel thin film transistor is made of an oxide semiconductor, and the pixel thin film transistor is made of an oxide conductor. The semiconductor device has wiring for a display portion formed thereon.

[0014] As a thin film transistor for pixels and a thin film transistor for driving circuits, Staggered thin-film transistors are used. The thin-film transistors for pixels have a channel formed in the semiconductor layer. A channel-protected (channel-stop) thin-film transistor with a channel protection layer on the region On the other hand, the thin film transistor for the driver circuit has a source electrode layer and a drain electrode layer. A channel-etched thin-film transistor having an oxide insulating film in contact with a semiconductor layer in the region between the It is Ta.

[0015] In addition, Non-Patent Document 1 does not include a specific process for manufacturing a TFT and other elements constituting a semiconductor device. The structure of the capacitors (for example, capacitor elements) is not disclosed. There is also no description of fabricating a TFT having light-transmitting properties.

[0016] The semiconductor device according to one embodiment of the present invention includes a driver circuit TFT and a driver circuit TFT on the same substrate. A display section having a path section and a pixel TFT is manufactured. Costs can be reduced.

[0017] In the semiconductor device of one embodiment of the present invention, the source electrode and the drain electrode are formed of an oxide. A pixel TFT made of a conductor and having a semiconductor layer made of an oxide semiconductor. and wiring for the display portion made of an oxide conductor. The area where the pixel TFTs and the display wiring are formed is used as the display area of ​​the pixel unit. Therefore, the aperture ratio of the semiconductor device can be improved.

[0018] In the semiconductor device of one embodiment of the present invention, the source electrode and the drain electrode are formed of an oxide. A pixel TFT made of a conductor and having a semiconductor layer made of an oxide semiconductor. and wiring for the display portion made of an oxide conductor. Therefore, the pixel size can be designed without being limited by the size of the pixel TFT. Therefore, the resolution of an image displayed on a display portion of the semiconductor device can be increased.

[0019] In addition, in the semiconductor device of one embodiment of the present invention, a source electrode and a drain electrode of gold are provided in the driver circuit portion. A TFT for a driving circuit, the channel layer of which is made of a metal and an oxide semiconductor. and wiring for a driving circuit made of metal. The driving circuit is composed of TFTs that exhibit high field effect mobility and low resistance wiring. Therefore, the semiconductor device can be a semiconductor device capable of high-speed operation.

[0020] The oxide semiconductor used in this specification is InMO3(ZnO) m (m>0) A thin film is formed on the oxide semiconductor layer, and a thin film transistor is fabricated using the thin film as an oxide semiconductor layer. M is one or more metal elements selected from Ga, Fe, Ni, Mn, and Co. It indicates a metal element. For example, M can be Ga, Ga and Ni, or Ga and Ni. In some cases, the oxide semiconductor may contain other metal elements than Ga, such as Fe. In addition to the metal elements contained as M, Fe, Ni and other transition metals are included as impurity elements. In this specification, the term "In" refers to a transition metal or an oxide thereof. MO3(ZnO) m In the oxide semiconductor layer with a structure represented by (m>0), M is Ga The oxide semiconductor with a structure containing In-Ga-Zn-O is called an In-Ga-Zn-O oxide semiconductor, and its thin film is called an I It is also called n-Ga-Zn-O based non-single crystal film.

[0021] In addition to the above, metal oxides that can be used for the oxide semiconductor layer include In-Sn-Zn-O In-Al-Zn-O system, Sn-Ga-Zn-O system, Al-Ga-Zn-O system, Sn -Al-Zn-O series, In-Zn-O series, Sn-Zn-O series, Al-Zn-O series, In- O-based, Sn-O-based, and Zn-O-based metal oxides can be used. The oxide semiconductor layer may contain silicon oxide. By including silicon oxide (SiOx(x>0)), which is a When heat treatment is performed after the semiconductor layer is formed, crystallization can be suppressed. Note that the oxide semiconductor layer is preferably in an amorphous state, and may be partially crystallized. .

[0022] The oxide semiconductor is preferably an oxide semiconductor containing In, more preferably an oxide semiconductor containing In and In order to make the oxide semiconductor layer i-type (intrinsic), dehydration is performed. Hydrogenation or dehydrogenation is effective.

[0023] Under an inert gas atmosphere of nitrogen or rare gas (argon, helium, etc.), or under reduced pressure By performing heat treatment on the oxide semiconductor layer, the oxide semiconductor layer becomes oxygen-deficient and has low resistance. That is, N-type (N - Then, an oxide insulating film is formed in contact with the oxide semiconductor layer. By forming the oxide semiconductor layer in an oxygen-excess state, the resistance is increased, that is, the I-type This makes it possible to produce a thin film transistor with good electrical properties and high reliability. It is possible to manufacture and provide a semiconductor device having the above structure.

[0024] The heat treatment for dehydration or dehydrogenation may be carried out in the presence of, for example, nitrogen or a rare gas (alan). In an inert gas atmosphere (e.g., argon, helium, etc.) or under reduced pressure, at 350°C or higher, preferably The heat treatment is performed at a temperature of 400°C or higher but below the distortion point of the substrate. The oxide semiconductor layer is dehydrated or dehydrogenated to reduce impurities containing hydrogen such as moisture contained in the oxide semiconductor layer. Reduce.

[0025] The heat treatment for dehydration or dehydrogenation is carried out by dehydrating or dehydrogenating the oxide semiconductor. Thermal Desorption Spectroscopy (TDS) was used to measure the layer. Even when measuring up to 450°C using TDS, two peaks of water were observed. It is preferable to set the heat treatment conditions so that one peak appearing around 300°C is not detected. The oxide semiconductor layer that has been subjected to heat treatment for dehydration or dehydrogenation under these conditions is used. Even when TDS measurements were performed on thin-film transistors up to 450°C, the The water peak that appears around °C is not detected.

[0026] Cooling after heating should be done using the same furnace as used for dehydration or dehydrogenation, without exposing the material to the atmosphere. The oxide semiconductor layer is cooled to a temperature of 1000° C. to prevent the oxide semiconductor layer from coming into contact with water or hydrogen. The oxide semiconductor layer is then heat treated to reduce its resistance, i.e., to become an N-type (N - (e.g., transformation) Then, a thin film transistor is fabricated using the oxide semiconductor layer that has been made high-resistance and i-type. The threshold voltage value of the thin film transistor can be made positive, and so-called normally-off transistors can be realized. The gate voltage of the thin film transistor is set as close to 0V as possible. It is desirable for a display device that a channel is formed at a threshold voltage of 1000 . If the threshold voltage of the transistor is negative, the source and drain electrodes Current flows between the active electrodes, which is called a normally-on state. In such display devices, the electrical characteristics of the thin film transistors that make up the circuits are important. The electrical characteristics of a display device affect its performance. In particular, the electrical characteristics of a thin film transistor Even if the field-effect mobility is high, the threshold voltage value is high, or If the threshold voltage is negative, it is difficult to control the circuit. In the case of a thin film transistor with a high threshold voltage and a large absolute value of the driving voltage When the voltage is low, the TFT cannot perform its switching function and may become a load. In the case of an n-channel thin film transistor, a positive voltage is applied to the gate. A transistor in which a channel is formed first and a drain current starts to flow is desirable. There are transistors in which a channel does not form unless the voltage is high, and transistors in which a channel forms even under negative voltage conditions. The transistor that is formed and drain current flows is a thin film transistor used in circuits. It is not suitable.

[0027] In addition, cooling after heating may be performed after switching the heated gas atmosphere to a different gas. For example, do not expose the material to the atmosphere in the same furnace where the heat treatment for dehydration or dehydrogenation was performed. The inside of the furnace is filled with high-purity oxygen gas or N2O gas, ultra-dry air (dew point below -40°C, preferably The container may be filled with a temperature (preferably -60°C or lower) to perform cooling.

[0028] Impurities containing hydrogen such as moisture contained in the film due to heat treatment for dehydration or dehydrogenation After reducing the temperature, place the container in a moisture-free atmosphere (dew point of -40°C or less, preferably -60°C or less). The electrical characteristics of a thin film transistor are evaluated using an oxide semiconductor film that is slowly cooled (or cooled) under This will improve the characteristics of thin-film transistors and realize thin-film transistors that are both mass-producible and high-performance.

[0029] In this specification, under an inert gas atmosphere of nitrogen or a rare gas (argon, helium, etc.), Alternatively, heat treatment under reduced pressure is referred to as heat treatment for dehydration or dehydrogenation. This heat treatment not only releases H2 but also H, OH, etc. For convenience, this process is referred to as dehydration or dehydrogenation.

[0030] Under an inert gas atmosphere of nitrogen or rare gas (argon, helium, etc.), or under reduced pressure When the heat treatment is performed, the oxide semiconductor layer becomes oxygen-deficient by the heat treatment and has low resistance. , that is, N-type (N - As a result, oxygen-deficient oxides are formed in the area overlapping with the drain electrode layer. A high resistance drain region (also called an HRD region) is formed.

[0031] Specifically, the carrier concentration in the high-resistance drain region is 1×10 17 / cm 3 Within the above range and the carrier concentration in the channel formation region is at least 1×10 17 / cm 3 (less than) The carrier concentration in this specification is determined by Hall effect measurement at room temperature. This refers to the carrier concentration value measured.

[0032] In addition, a low-resistance drain region (L Specifically, the carrier concentration of the low-resistance drain region may be is larger than the high resistance drain region (HRD region), for example, 1×10 20 / cm 3 End 1×10 21 / cm 3 It is within the following range:

[0033] Then, at least a part of the oxide semiconductor layer that has been subjected to heat treatment for dehydration or dehydrogenation is By making the silicon dioxide in an oxygen-excess state, the resistance is increased, i.e., the silicon dioxide becomes an I-type silicon dioxide, and a channel forming region is formed. Note that the oxide semiconductor layer that has been subjected to heat treatment for dehydration or dehydrogenation is heated in an oxygen-excess state. As a treatment for achieving this state, a heat treatment for dehydration or dehydrogenation is performed on an oxide semiconductor layer. Depositing a contacting oxide insulating film by sputtering, or heating for dehydration or dehydrogenation An oxide insulating film is formed so as to be in contact with the treated oxide semiconductor layer, and heat treatment is further performed. Alternatively, the oxide semiconductor layer that has been subjected to heat treatment for dehydration or dehydrogenation is treated with a compound containing oxygen. Oxides that have been heat-treated in an atmosphere containing fluorine, or that have been heat-treated for dehydration or dehydrogenation The semiconductor layer is heated in an inert gas atmosphere and then cooled in an oxygen atmosphere; The oxide semiconductor layer that has been subjected to heat treatment for dehydration or dehydrogenation is heated under an inert gas atmosphere. Heating and then cooling with ultra-dry air (dew point below -40°C, preferably below -60°C). Examples include performing processing such as:

[0034] In addition, at least a part of the oxide semiconductor layer ( In order to form a channel formation region in the region overlapping with the gate electrode (also called a gate electrode layer), By selectively creating an oxygen-excess state, it is possible to make the material highly resistive, i.e., I-type. Alternatively, a metal electrode such as Ti is formed on the oxide semiconductor layer that has been subjected to heat treatment for dehydrogenation. and a source electrode layer and a drain electrode layer are formed by forming a layer not overlapping the source electrode layer and the drain electrode layer. The region where no oxygen is present can be selectively made into an oxygen-excess state to form a channel forming region. When selectively creating an oxygen-excess state, a first high-resistance drain region overlapping the source electrode layer; a second high-resistance drain region overlapping the drain electrode layer; and a first high-resistance drain region. The region between the first high-resistance drain region and the second high-resistance drain region is the channel forming region. A hole forming region is formed between the source electrode layer and the drain electrode layer in a self-aligned manner.

[0035] This allows the fabrication of a semiconductor device having a thin film transistor with good electrical characteristics and high reliability. and can be provided.

[0036] Note that the oxide semiconductor layer overlapping with the drain electrode layer (and the source electrode layer) has a high resistance. By forming a drain region, it is possible to improve reliability when forming a drive circuit. Specifically, by forming a high-resistance drain region, the high-resistance drain can be The structure is such that the conductivity can be changed stepwise from the drain region to the channel formation region. Therefore, the drain electrode layer is connected to a wiring that supplies a high power supply potential VDD. When the transistor is operated with a high resistance, even if a high electric field is applied between the gate electrode layer and the drain electrode layer, The drain region acts as a buffer, preventing the application of a localized high electric field, improving the transistor's breakdown voltage It is possible to have a configuration in which

[0037] In addition, between the drain electrode layer (and source electrode layer) made of a metal material and the oxide semiconductor layer A low-resistance drain region (also called an LRN region) may be formed. By forming a junction region (also called an RN region), the breakdown voltage of the transistor is further improved. It can be said that:

[0038] In addition, a high-resistance drain electrode layer (and a source electrode layer) is formed in the oxide semiconductor layer overlapping the drain electrode layer (and the source electrode layer). By forming a drain region, leakage in the channel formation region when forming a drive circuit is reduced. Specifically, by forming a high-resistance drain region, the drain current can be reduced. The drain electrode layer and the source electrode layer are connected as a path for the leakage current of the transistor. Drain electrode layer, high-resistance drain region on the drain electrode layer side, channel formation region, source electrode The high-resistance drain region on the layer side and the source electrode layer are in this order. The leakage current flowing from the high-resistance drain region on the drain electrode layer side to the channel formation region is called the transistor. The transistor is concentrated near the interface between the gate insulating layer and the channel formation region, which has high resistance when the transistor is off. The back channel portion (the surface of the channel forming region separated from the gate electrode layer) can be formed. This can reduce leakage current in the surface (part of the surface).

[0039] Also, a first high-resistance drain region overlapping the source electrode layer and a second high-resistance drain region overlapping the drain electrode layer. The high resistance drain region is formed so as to overlap a part of the gate electrode layer via the gate insulating layer. By doing so, it is possible to more effectively reduce the electric field strength near the end of the drain electrode layer. .

[0040] Further, a low-resistance drain region is formed between the source electrode layer and the drain electrode layer and the oxide semiconductor layer. This configuration allows for thermally stable operation compared to a Schottky junction. The resistive drain region has a lower resistance than the oxide semiconductor layer and is Since an oxide conductive layer having a higher resistance than the electrode layer is used, the oxide semiconductor layer and the source electrode layer or The contact resistance with the drain electrode layer can be reduced.

[0041] One embodiment of the configuration of the invention disclosed in this specification is a semiconductor device having a first thin film transistor over the same substrate. a pixel portion including a first thin film transistor and a driver circuit including a second thin film transistor, a gate electrode layer on the substrate; a gate insulating layer on the gate electrode layer; An oxide semiconductor layer having a thin region at its periphery and an oxide insulating layer in contact with part of the oxide semiconductor layer a source electrode layer and a drain electrode layer on the oxide insulating layer and the oxide semiconductor layer; a pixel electrode layer electrically connected to the first thin film transistor; The gate electrode layer of the gate insulating layer, the oxide semiconductor layer, the source electrode layer, the drain electrode layer, and the oxide The oxide insulating layer and the pixel electrode layer have light-transmitting properties, and the source electrode layer of the second thin film transistor and The source electrode layer and the drain electrode layer of the first thin film transistor are covered with a protective insulating layer. The material of the source electrode layer and the drain electrode layer of the first thin film transistor is different from that of the drain electrode layer. The semiconductor device is made of a conductive material with a lower resistance than the pole layer.

[0042] In the semiconductor device, the oxide semiconductor layer of the second thin film transistor and the source The source electrode layer and the drain electrode layer of the first thin film transistor are provided between the source electrode layer and the drain electrode layer. The semiconductor device may have a low resistance drain region made of the same material as the drain electrode layer.

[0043] In the semiconductor device, the oxide semiconductor layer of the second thin film transistor and the source A low-resistance drain region is provided between the electrode layer and the drain electrode layer. The portion protrudes from the end face of the low-resistance drain region and serves as a channel forming portion of the second thin film transistor. It may have the same thickness as the film thickness of the region.

[0044] In the semiconductor device, the oxide semiconductor layer of the first or second thin film transistor is At least one of the source and drain electrode layers is provided at a position overlapping with the source electrode layer or the drain electrode layer. It may have a high resistance drain region that has a lower resistance than the drain region.

[0045] In the semiconductor device, the source electrode layer and the drain electrode layer of the second thin film transistor The electrode layer is a film whose main component is an element selected from Al, Cr, Cu, Ta, Ti, Mo, and W. or a laminated film in which these are combined.

[0046] In the semiconductor device, the source electrode layer and the drain electrode of the first thin film transistor are The electrode layer and the pixel electrode layer are made of indium oxide, an indium oxide tin oxide alloy, indium oxide Preferably, the material is made of zinc oxide alloy or zinc oxide.

[0047] Furthermore, the semiconductor device further includes a capacitance section on the same substrate, and the capacitance section is a capacitance wiring. The capacitor wiring and the capacitor electrode may be transparent. good.

[0048] In the semiconductor device, the oxide semiconductor layer of the second thin film transistor has a source a channel formation region having a thickness thinner than a region overlapping with the electrode layer or the drain electrode layer; A conductive layer may be provided on the channel forming region via a protective insulating layer.

[0049] In one embodiment of the structure of the invention disclosed in this specification, a first gate electrode layer and a second gate electrode layer are formed over the same substrate. A gate electrode layer is formed, and a gate insulating layer is formed on the first gate electrode layer and the second gate electrode layer. an oxide semiconductor film is formed over the gate insulating layer; and the oxide semiconductor film is dehydrated or dehydrated. After the heat treatment for oxidation, the oxide semiconductor film is prevented from coming into contact with water or hydrogen. The first oxide semiconductor layer, the second oxide semiconductor layer, and the second oxide semiconductor layer are formed without being exposed to the air. forming first and second low-resistance drain regions on the conductor layer; A second source electrode layer and a second drain electrode layer are formed on the silicon oxide film. a second source electrode layer and a second drain electrode layer; a second oxide insulating layer in contact with the first surface and the side surface of the first oxide semiconductor layer; and a first gate electrode layer. a first oxide insulating layer is formed in a region overlapping the first oxide semiconductor layer and the first oxide insulating layer; forming a first source electrode layer and a first drain electrode layer on the edge layer; a first oxide insulating layer; A protective insulating layer is formed on the first source electrode layer, the first drain electrode layer, and the second oxide insulating layer. and electrically connecting the first drain electrode layer or the first source electrode layer to the protective insulating layer. and a conductive layer overlapping the second oxide semiconductor layer. It is a method.

[0050] In the above structure, the oxide semiconductor layer of the second thin film transistor is a source electrode layer or a drain electrode layer. The second thin film transistor may have a region where the film thickness is thinner than the region where the second thin film transistor overlaps with the drain electrode layer. The oxide semiconductor layer of the transistor has a larger thickness than the region overlapping with the source electrode layer or the drain electrode layer. A thin channel forming region is provided on the channel forming region via a second oxide insulating layer. A structure having a conductive layer may also be used.

[0051] The first oxide insulating layer and the second oxide insulating layer can be formed in the same process, and therefore have the same light-transmitting property. An insulating material having such a property can be used.

[0052] The ordinal numbers such as 1st and 2nd are used for convenience and do not indicate the order of processes or stacking. Furthermore, the specific names used in this specification are not intended to identify the invention. This does not indicate

[0053] In addition to liquid crystal display devices, display devices having a driving circuit include light-emitting devices using light-emitting elements. display devices, and display devices that use electrophoretic display elements and are also called electronic paper. .

[0054] In a light-emitting display device using a light-emitting element, a plurality of thin film transistors are provided in a pixel portion, and a pixel In the element part, the gate electrode of a thin film transistor and the source wiring (s The point where the source wiring layer or drain wiring (also called drain wiring layer) is connected. In addition, in a driving circuit of a light emitting display device using a light emitting element, a thin film transistor The gate electrode of the thin film transistor is connected to the source wiring or drain wiring of the thin film transistor. It has a part that allows you to do this. [Effects of the Invention]

[0055] According to one embodiment of the present invention, a thin film transistor having stable electrical characteristics is manufactured and provided. Therefore, a semiconductor device having a thin film transistor with good electrical characteristics and high reliability can be obtained. An apparatus can be provided. [Brief explanation of the drawings]

[0056] [Figure 1] 1A to 1C illustrate a semiconductor device. [Figure 2] 1A to 1C illustrate a method for manufacturing a semiconductor device. [Figure 3] 1A to 1C illustrate a method for manufacturing a semiconductor device. [Figure 4] 1A to 1C illustrate a method for manufacturing a semiconductor device. [Figure 5] 1A to 1C illustrate a method for manufacturing a semiconductor device. [Figure 6] 1A to 1C illustrate a method for manufacturing a semiconductor device. [Figure 7] 1A to 1C illustrate a semiconductor device. [Figure 8] 1A to 1C illustrate a semiconductor device. [Figure 9] 1A to 1C illustrate a semiconductor device. [Figure 10] 1A to 1C illustrate a semiconductor device. [Figure 11] 1A to 1C illustrate a semiconductor device. [Figure 12] 1A and 1B are diagrams illustrating pixel equivalent circuits of a semiconductor device. [Figure 13]1A to 1C illustrate a semiconductor device. [Figure 14] FIG. 1 is a block diagram illustrating a semiconductor device. [Figure 15] 1A and 1B are circuit diagrams and timing charts of a signal line driver circuit; [Figure 16] FIG. 1 is a circuit diagram showing a configuration of a shift register. [Figure 17] 3A and 3B are a timing chart and a circuit diagram illustrating the operation of a shift register. [Figure 18] 1A to 1C illustrate a semiconductor device. [Figure 19] 1A to 1C illustrate a semiconductor device. [Figure 20] FIG. 1 is an external view showing an example of an electronic book. [Figure 21] FIG. 1 is an external view showing an example of a television device and a digital photo frame. [Figure 22] FIG. 1 is an external view showing an example of a gaming machine. [Figure 23] FIG. 1 is an external view showing an example of a portable computer and a mobile phone. [Figure 24] 1A to 1C illustrate a semiconductor device. [Figure 25] 1A to 1C illustrate a semiconductor device. [Figure 26] 1A to 1C illustrate a semiconductor device. [Figure 27] 1A and 1B are circuit diagrams of a semiconductor device. [Figure 28] 1A to 1C illustrate a semiconductor device. [Figure 29] 1A to 1C illustrate a semiconductor device. [Figure 30] 1A to 1C illustrate a semiconductor device. [Figure 31] 1A and 1B are circuit diagrams of a semiconductor device. [Figure 32] 1A to 1C illustrate a semiconductor device. [Figure 33] 1A to 1C illustrate a semiconductor device. [Figure 34] 1A to 1C illustrate a semiconductor device. [Figure 35] 1A to 1C illustrate a semiconductor device. [Figure 36] 1A to 1C illustrate a semiconductor device. [Figure 37]1A to 1C illustrate a semiconductor device. [Figure 38] 1A to 1C illustrate a semiconductor device. DETAILED DESCRIPTION OF THE INVENTION

[0057] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The present invention is not limited to the following description, and various modifications in form and details are possible by those skilled in the art. Furthermore, the present invention should not be construed as being limited to the description of the following embodiments. It is not something that can be done.

[0058] (Embodiment 1) The semiconductor device and a manufacturing method of the semiconductor device will be described with reference to FIGS. (C) shows one of the cross-sectional structures of two thin film transistors with different structures fabricated on the same substrate. An example of a thin film transistor 460 shown in FIG. The thin film transistor 470 is a channel protection type (channel stop type The thin film transistor 460 and the thin film transistor 461 are one of the bottom gate structures. The transistor 470 is also called an inverted staggered thin film transistor.

[0059] FIG. 1(A1) is a plan view of a thin film transistor 460 disposed in a driving circuit. 2) is a plan view of a thin film transistor 470 disposed in a pixel portion. 1(A1) and the cross-sectional view taken along the line G1-G2 in FIG. 1(A1) and the line H1-H2 in FIG. 1(A2). In addition, FIG. 1(C) shows the relationship between the line G3-G4 in FIG. 1(A1) and the line H3-H4 in FIG. 1(A2). FIG.

[0060] The thin film transistor 460 arranged in the drive circuit is a channel-etch type thin film transistor. A gate electrode layer 461 and a first gate insulating layer 45 are formed on a substrate 450 having an insulating surface. 2a, the second gate insulating layer 452b, at least the channel forming region 463, the first high resistance an oxide semiconductor layer having a drain region 464a and a second high-resistance drain region 464b; 462, the first low-resistance drain region 408a, the second low-resistance drain region 408b, The thin film transistor 460 includes a source electrode layer 465a and a drain electrode layer 465b. An oxide insulating layer 466 is provided to cover the channel formation region 463 and to be in contact with the channel formation region 463.

[0061] The first high-resistance drain region 464a is in contact with the lower surface of the first low-resistance drain region 408a. The second low-resistance drain region 408b is formed in a self-aligned manner. The second high-resistance drain region 464b is formed in a self-aligned manner. The region 463 is in contact with the oxide insulating layer 466 and includes a first high-resistance drain region 464a and a second high-resistance drain region 464b. The thickness of the first high-resistance drain region 464b is thinner than that of the second high-resistance drain region 464c. A region (I-type region) having a higher resistance than the region 464a and the second high-resistance drain region 464b Let's say.

[0062] The thin film transistor 460 has a source electrode layer 465a and a The drain electrode layer 465b is preferably formed using a metal material.

[0063] In addition, in a liquid crystal display device, when a pixel portion and a driver circuit are formed on the same substrate, In this case, logic gates such as inverter circuits, NAND circuits, NOR circuits, and latch circuits are used. thin-film transistors, sense amplifiers, constant voltage generators, and voltage-controlled oscillators (VC Thin-film transistors that make up analog circuits such as O) have a gate electrode between the source and drain electrodes. Therefore, only positive or negative polarity is applied to the second high resistance transistor, which requires high withstand voltage. The width of the anti-drain region 464b is designed to be wider than the width of the first high-resistance drain region 464a. In addition, the first high-resistance drain region 464a and the second high-resistance drain region 4 The width of the portion 64b overlapping the gate electrode layer may be increased.

[0064] The thin film transistor 460 disposed in the driving circuit is a thin film transistor with a single gate structure. Although the explanation has been given using a transistor, a multi-gate transistor having multiple channel forming regions may be used as needed. A thin film transistor having the same structure can also be formed.

[0065] A conductive layer 467 is provided above and overlapping the channel forming region 463. By electrically connecting the gate electrode layer 461 and the conductive layer 462 to each other and setting them at the same potential, the gate electrode layer 461 and the conductive layer 462 are electrically connected to each other and set at the same potential. A gate voltage can be applied from above and below to the oxide semiconductor layer 462 disposed between the gate electrodes 67. In addition, the gate electrode layer 461 and the conductive layer 467 are set to different potentials, for example, a fixed potential, GND, When the voltage is set to 0 V, the electrical characteristics of the TFT, such as the threshold voltage, can be controlled. That is, the gate electrode layer 461 functions as a first gate electrode layer, and the conductive layer 467 The thin film transistor 460 is configured as a four-terminal thin film transistor by using the second gate electrode layer as a second gate electrode layer. It can be used as a transistor.

[0066] In addition, a protective insulating layer 453 and a planarizing insulating layer 454 are provided between the conductive layer 467 and the oxide insulating layer 466. 54 and are laminated.

[0067] The protective insulating layer 453 is formed by insulating a first gate insulating layer 452 provided under the protective insulating layer 453. It is preferable that the insulating film is in contact with the insulating film that serves as the base. , hydrogen ions, OH - In particular, the protective insulating layer The first gate insulating layer 452a in contact with 453 or the insulating film serving as the base is made of silicon nitride. is valid.

[0068] The thin film transistor 470 disposed in the pixel is a channel stop type thin film transistor. A gate electrode layer 471, a first gate insulating layer 472, and a second gate insulating layer 473 are formed on a substrate 450 having an insulating surface. 452a, the second gate insulating layer 452b, and the oxide semiconductor layer 472 including the channel formation region , a source electrode layer 475a, and a drain electrode layer 475b. 470, a channel protection layer 476, a source electrode layer 475a, and a drain electrode layer 47 A protective insulating layer 453 and a planarization insulating layer 454 are stacked in contact with the insulating layer 5b. A pixel electrode layer 477 in contact with the drain electrode layer 475b is provided on the planar insulating layer 454. It is electrically connected to the thin film transistor 470. The first low-resistance drain region 408a and the second low-resistance drain region 408b of the resistor 460 and the source electrode layer 475a and the drain electrode layer 475b of the thin film transistor for the pixel. Preferably, the material of 5b is the same.

[0069] However, liquid crystal display devices are driven by alternating current to prevent deterioration of the liquid crystal. By this operation, the polarity of the signal potential applied to the pixel electrode layer is changed to positive or negative at regular intervals. The TFT connected to the pixel electrode layer has a pair of electrodes that alternately connects the source electrode layer and the drain electrode layer. In this specification, for convenience, one electrode of the thin film transistor of the pixel is The first electrode is called the source electrode layer, and the other electrode is called the drain electrode layer. In this case, one electrode alternately functions as a source electrode layer and a drain electrode layer. In order to reduce the current, the width of the gate electrode layer 471 of the thin film transistor 470 disposed in the pixel is may be narrower than the width of the gate electrode layer 461 of the thin film transistor 460 in the driver circuit. In order to reduce the leakage current, the gate voltage of the thin film transistor 470 disposed in the pixel is The electrode layer 471 is set so as not to overlap with the source electrode layer 475a or the drain electrode layer 475b. It may be calculated.

[0070] The thin film transistor 470 disposed in the pixel is a thin film transistor with a single gate structure. However, if necessary, a multi-gate structure having a plurality of channel forming regions may be used. A thin film transistor can also be formed.

[0071] After the formation of the oxide semiconductor film, heat treatment (dehydration) is performed to reduce impurities such as moisture. Heat treatment for dehydration or dehydrogenation) is carried out. After the oxide semiconductor layer is heated and slowly cooled, an oxide insulating film is formed in contact with the oxide semiconductor layer. Reducing the carrier concentration of the conductor layer improves the electrical characteristics of the thin film transistor 470. This leads to improved reliability.

[0072] Note that the oxide semiconductor layer 472 is a gate insulating film between the source electrode layer 475a and the drain electrode layer 475b. The oxide semiconductor layer 472 is formed below and partially overlaps the gate electrode layer 471. and overlap with the first gate insulating layer 452a and the second gate insulating layer 452b interposed therebetween. The channel formation region of the thin film transistor 470 disposed in the pixel is formed by the oxide semiconductor layer 472. Among these, the side surface of the source electrode layer 475a and the drain electrode layer 475b facing the side surface The region sandwiched between the side surface and the second gate insulating layer 452b, i.e., the region in contact with the second gate insulating layer 452b and the gate electrode layer 4 This is the area that overlaps with 71.

[0073] In addition, the thin film transistor 470 has a high aperture ratio as a light-transmitting thin film transistor. In order to realize a display device that can transmit light, the source electrode layer 475a and the drain electrode layer 475b are A conductive film having optical properties is used.

[0074] A light-transmitting conductive film is also used for a gate electrode layer 471 of the thin film transistor 470.

[0075] In addition, the pixel in which the thin film transistor 470 is disposed is provided with a pixel electrode layer 477 or other The electrode layer (such as the capacitance electrode) and other wiring layers (such as the capacitance wiring layer) are transparent to visible light. By using a conductive film having high electrical conductivity, a display device having a high aperture ratio can be realized. The edge layer 452a, the second gate insulating layer 452b, and the channel protection layer 476 are also transparent to visible light. It is preferable to use a film having optical properties.

[0076] In this specification, a light-transmitting film refers to a film having a visible light transmittance of 75 to 100%. When the film has conductivity, it is also called a transparent conductive film. Applied to electrode layer, drain electrode layer, pixel electrode layer, other electrode layer, and other wiring layer A conductive film that is semi-transparent to visible light may be used as the metal oxide. Translucent refers to a visible light transmittance of 50-75%.

[0077] Hereinafter, referring to FIGS. 2(A) to 2(E) and 3(A) to 3(E), a thin film transistor is formed on the same substrate. A manufacturing process of the thin film transistor 460 and the thin film transistor 470 will be described.

[0078] First, a light-transmitting conductive film is formed on a substrate 450 having an insulating surface, and then a first photo Gate electrode layers 461 and 471 are formed by a lithography process. The capacitor wiring is formed using the same material as the gate electrode layers 461 and 471 and the same first photolithography process. In addition, if capacitance is required not only in the pixel section but also in the driver circuit, A capacitor wiring (also called a capacitor wiring layer) is formed. A resist mask is formed by an ink-jet method. If the resist mask is formed by the inkjet method, a photomask can be used. Therefore, the manufacturing cost can be reduced.

[0079] There is no significant limitation on the substrate that can be used for the substrate 450 having an insulating surface, but at least In any case, it is necessary for the insulating surface to have heat resistance to the extent that it can withstand the subsequent heat treatment. The substrate 450 is made of glass such as barium borosilicate glass or aluminoborosilicate glass. A substrate can be used.

[0080] In addition, when a glass substrate is used as the substrate 450, if the temperature of the subsequent heat treatment is high, It is preferable to use a substrate having a strain point of 730° C. or higher. In cases where glass is used, for example, aluminosilicate glass, aluminoborosilicate glass, barium silicate glass, Glass materials such as borosilicate glass are used. By adding more sodium (BaO), a more practical heat-resistant glass can be obtained. It is preferable to use a glass substrate containing more BaO than B2O3.

[0081] Instead of the glass substrate, an insulating substrate such as a ceramic substrate, a quartz substrate, or a sapphire substrate may be used. A substrate made of an insulating material may be used as the substrate 450. Alternatively, crystallized glass or the like may be used. This can be done.

[0082] In addition, an insulating film serving as a base film may be provided between the substrate 450 and the gate electrode layers 461 and 471. The underlayer film has a function of preventing the diffusion of impurity elements from the substrate 450. A stack of one or more films selected from a silicon oxide film, a silicon nitride oxide film, and a silicon oxynitride film. It can be formed in a layer structure.

[0083] The gate electrode layers 461 and 471 are made of a conductive material that is transparent to visible light, such as In-Sn-Zn-O system, In-Al-Zn-O system, Sn-Ga-Zn-O system, Al-G a-Zn-O series, Sn-Al-Zn-O series, In-Zn-O series, Sn-Zn-O series, Al -Zn-O, In-O, Sn-O, and Zn-O metal oxides can be used. The thickness of the gate electrode layer 461 is appropriately selected within the range of 50 nm to 300 nm. The metal oxide film formation method used for 71 is the sputtering method or vacuum deposition method (electron beam deposition method, etc.). ), arc discharge ion plating method, and spray method are used. Also, sputtering method is used. When using a target containing SiO2 in an amount of 2% by weight or more and 10% by weight or less, the film is formed. In the subsequent process, SiOx (X>0) that inhibits crystallization is contained in the conductive film having light-transmitting properties. It is preferable to suppress crystallization during the heat treatment for dehydration or dehydrogenation. Desirable.

[0084] Next, a gate insulating layer is formed on the gate electrode layers 461 and 471 .

[0085] The gate insulating layer is formed by depositing a silicon oxide layer, a nitride layer, or the like using a plasma CVD method or a sputtering method. The silicon layer, the silicon oxynitride layer, or the silicon nitride oxide layer can be formed as a single layer or a stacked layer. For example, SiH4, oxygen, and nitrogen are used as film-forming gases to form an oxide film by plasma CVD. A silicon nitride layer may be formed.

[0086] In this embodiment, a first gate insulating layer 452a having a thickness of 50 nm to 200 nm is provided. a second gate insulating layer 452b having a thickness of 50 nm or more and 300 nm or less; The first gate insulating layer 452a is a silicon nitride film or a nitride oxide film having a thickness of 100 nm. The second gate insulating layer 452b is a silicon oxide film having a thickness of 100 nm. A bare membrane is used.

[0087] Next, an oxide semiconductor film having a thickness of 2 nm to 200 nm is deposited on the second gate insulating layer 452b. After the oxide semiconductor film is formed, the oxide semiconductor film 480 is dehydrated or dehydrogenated. In order to make the oxide semiconductor layer amorphous even after heat treatment for the purpose of It is preferable to make the oxide semiconductor layer as thin as or less. When a heat treatment is performed after the formation of the film, crystallization can be suppressed.

[0088] Before forming the oxide semiconductor film by a sputtering method, argon gas was introduced to form a plasma. The reverse sputtering is performed to generate a metal, and the metal adhering to the surface of the second gate insulating layer 452b is removed. It is preferable to remove aluminum. Reverse sputtering is a method of removing aluminum without applying voltage to the target side. In a nitrogen atmosphere, a voltage is applied to the substrate side using an RF power supply to form plasma near the substrate. This is a method for modifying the surface. Note that nitrogen, helium, oxygen, etc. can be used instead of argon atmosphere. It may be used.

[0089] The oxide semiconductor film is an In-Ga-Zn-O based non-single crystal film, an In-Sn-Zn-O based film, an In -Al-Zn-O system, Sn-Ga-Zn-O system, Al-Ga-Zn-O system, Sn-Al- Zn-O series, In-Zn-O series, Sn-Zn-O series, Al-Zn-O series, In-O series, S In this embodiment, an In—Ga—Zn oxide semiconductor film is used. The film is formed by sputtering using an -O-based oxide semiconductor target. The film is formed under a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a rare gas (typically It can be formed by sputtering in an atmosphere of argon and oxygen. When using the sputtering method, a target containing 2% to 10% by weight of SiO2 is used. The oxide semiconductor film is formed by adding SiOx (X>0) which inhibits crystallization. To suppress crystallization during the heat treatment for dehydration or dehydrogenation performed in the above is preferred.

[0090] Next, the oxide semiconductor film 480 is dehydrated or dehydrogenated. The temperature of the first heat treatment is 350° C. or higher and lower than the strain point of the substrate, preferably 400° C. or higher. The substrate is placed in an electric furnace, which is a type of heat treatment device, and the temperature is set to be lower than the distortion point of the substrate. After the oxide semiconductor layer is subjected to heat treatment under a nitrogen atmosphere, In order to prevent water and hydrogen from re-entering the oxide semiconductor layer, the oxide semiconductor layer is slowly cooled without being exposed to the air. In this embodiment, the oxide semiconductor layer is dehydrated. Or, heat the same furnace from the heating temperature T for dehydrogenation to a temperature high enough to prevent water from entering again. Specifically, the temperature is gradually cooled in a nitrogen atmosphere until it drops by 100°C or more below the heating temperature T. The atmosphere is not limited to nitrogen, and may be a rare gas atmosphere such as helium, neon, or argon, or a reduced pressure atmosphere. A heat treatment is carried out under pressure for dehydration or dehydrogenation.

[0091] In the first heat treatment, nitrogen or a rare gas such as helium, neon, or argon is used. It is preferable that the nitrogen introduced into the heat treatment device does not contain water, hydrogen, etc. Or the purity of rare gases such as helium, neon, and argon must be 6N (99.9999%) or higher. Preferably, the impurity concentration is 7N (99.99999%) or more (i.e., the impurity concentration is 1 ppm or less, It is preferable to set the concentration to 0.1 ppm or less.

[0092] Depending on the conditions of the first heat treatment or the material of the oxide semiconductor film, the oxide semiconductor film may be crystallized and microcrystalline. It may also be a crystalline or polycrystalline film.

[0093] Note that the first heat treatment of the oxide semiconductor film 480 is performed after the oxide semiconductor layer is processed into an island shape. It can also be done.

[0094] In addition, before the formation of the oxide semiconductor film, an inert gas atmosphere (nitrogen, helium, neon, Heat treatment (400°C or higher) in an oxygen atmosphere or reduced pressure (argon, etc.) impurities such as hydrogen and water contained in the gate insulating layer may be removed by performing a annealing treatment (below the annealing point).

[0095] Next, an oxide conductive film for use as a low-resistance drain region is formed on the oxide semiconductor layer 481. A layer and a conductive layer are formed.

[0096] The oxide conductive layer is formed by a method such as sputtering, vacuum deposition (electron beam deposition, etc.), or arc deposition. The low-resistance drain region is made of a material such as a silicon dioxide (SiO2) thin film. For example, an oxide conductive material such as In-Sn-Zn-O or In-Al -Zn-O series, Sn-Ga-Zn-O series, Al-Ga-Zn-O series, Sn-Al-Zn- O series, In-Zn-O series, Sn-Zn-O series, Al-Zn-O series, In-O series, Sn-O In addition, a low-resistance drain region can be formed by using a metal oxide such as Zn-O. The oxide conductive material used has lower resistance than the oxide semiconductor layer 483 and lower resistance than the conductive layer 484. A material with high resistance can be appropriately selected and used. When using the sputtering method, S The film is formed using a target containing 2% by weight or more and 10% by weight or less of iO2, and has transparency. The conductive film contains SiOx (X>0) which inhibits crystallization, and the dehydration or It is preferable to suppress crystallization during the heat treatment for dehydrogenation.

[0097] The conductive layer is made of an element selected from Al, Cr, Cu, Ta, Ti, Mo, and W. The alloys are made of the above elements, or alloys that combine the above elements. .

[0098] The conductive layer is formed by laminating an aluminum layer on a titanium layer and another titanium layer on the aluminum layer. or a molybdenum layer on an aluminum layer and a It is preferable to use a three-layer laminate structure in which a molybdenum layer is laminated on the conductive layer. It may have a layer structure, a two-layer structure, or a laminated structure of four or more layers.

[0099] After forming the oxide conductive layer and the conductive layer, a resist used in the second photolithography process is formed. Masks 482a and 482b are formed. The mask 482b may be formed by an ink-jet method. When the film is formed by this method, no photomask is used, and therefore the manufacturing cost can be reduced.

[0100] The resist mask 482a in this embodiment is a resist mask having recesses or protrusions. In other words, the resist is made up of multiple regions (two regions in this case) with different thicknesses. In the resist mask 482a, the thick region is made of the resist mask. The thin areas are called the convex portions of the resist mask 482a, and the thin areas are called the concave portions of the resist mask 482a. .

[0101] In the resist mask 482a, a portion where a source electrode layer and a drain electrode layer will be formed later is A protrusion is formed in the portion, and the portion is sandwiched between the source electrode layer and the drain electrode layer. A recess is formed in the area.

[0102] The resist mask 482a can be formed using a multi-tone mask. A mask is a mask that can perform exposure with multiple levels of light intensity, and typically has an exposure area of The mask is used to expose the photoresist to light in three levels: the light exposure area, the half-exposed area, and the unexposed area. By using this, multiple thicknesses (typically two types) can be effectively produced by a single exposure and development process. Therefore, by using a multi-tone mask, The number of photomasks can be reduced.

[0103] By using a multi-tone mask and then performing exposure and development, a resist mask with regions of different thickness can be produced. However, the present invention is not limited to this, and a multi-tone mask may be used to form the mask 482a. Alternatively, the resist mask 482a may be formed without etching.

[0104] Next, a conductive layer, a low-resistance layer, and a resist mask 482a and a resist mask 482b are formed using the resist mask 482a and the resist mask 482b. The drain region and the oxide semiconductor layer 481 are selectively and simultaneously etched to form an island-like The oxide semiconductor layers 483 and 485 and the low-resistance drain regions 406 and 407 are oxide semiconductor layers. 07, and conductive layers 484 and 486 are formed (FIG. 2(C)). When a laminated conductive film of an aluminum film and a titanium film is used, dry etching using chlorine gas is performed. The etching can be performed by the etching method.

[0105] Next, the resist masks 482a and 482b are retracted (reduced). The resist masks 487a, 487b, and 487c are formed. The resist masks are recessed (reduced). To do this, ashing with oxygen plasma or the like may be performed. By this, the conductive portion between the resist mask 487a and the resist mask 487b is The conductive layer 484 is exposed.

[0106] Next, the conductive layer 48 between the resist masks 487a and 487b is 4 and the low-resistance drain region 406 in contact with the region are covered with a resist mask 487a and a resist By selectively etching using the mask 487b, the source electrode layer 465a and drain electrode layer 465b, the first low-resistance drain region 408a and the second low-resistance drain In this case, the oxide semiconductor layer is only partially removed. The oxide semiconductor layer 488 is etched to have a groove (depression).

[0107] As shown in FIG. 2(D), the resist masks 482a and 482b are recessed (reduced). The resist masks 487a and 487b are used to etch the resist film 487a. Thin regions are formed at the peripheries of the oxide semiconductor layers 483 and 485. The ends of the body layer 488 are closer to the ends of the first and second low-resistance drain regions 408a and 408b. The end of the oxide semiconductor layer 489 also protrudes more than the end of the low-resistance drain region 409. Note that the periphery of the oxide semiconductor layer 483 and the oxide semiconductor layer 484 that will later become a channel formation region are The groove (recess) of the semiconductor layer 488 has the same film thickness.

[0108] Next, the resist masks 487a, 487b, and 487c are removed, and a third photolithography A resist mask 491 is formed by a photolithography process, and selective etching is performed to remove the acid from the pixel area. The low-resistance drain region 409 and the conductive layer 490 formed on the nitride semiconductor layer 489 are removed. (Figure 2(E)).

[0109] Note that the low-resistance drain region overlapping with the oxide semiconductor layer 489 is formed in the third photolithography step. In order to selectively remove the region 409 and the conductive layer 490, the oxide semiconductor layer The materials and etching conditions are adjusted appropriately so that the 489 is not removed. The resist mask 491 may be formed by an ink-jet method. When the film is formed by the jet method, no photomask is used, and therefore the manufacturing cost can be reduced.

[0110] Next, the resist mask 491 is removed, and a metal film is formed in contact with the groove (depression) of the oxide semiconductor layer 488. The oxide insulating film 492 is formed as a protective insulating film in contact with the top surface and side surfaces of the oxide semiconductor layer 489. Complete.

[0111] The oxide insulating film 492 has a thickness of at least 1 nm and is formed by an oxide method such as a sputtering method. The insulating film 492 can be formed by using an appropriate method that does not allow impurities such as water and hydrogen to be mixed in. In this embodiment, a silicon oxide film having a thickness of 300 nm is used as the oxide insulating film 492. The substrate temperature during film formation should be between room temperature and 300°C. In this embodiment, the temperature is set to 100° C. The silicon oxide film is formed by sputtering. Gas (typically argon) atmosphere, oxygen atmosphere, or rare gas (typically argon) atmosphere The target can be a silicon oxide target. A get or silicon target can be used. For example, a silicon target can be used to A silicon oxide film can be formed by sputtering in an oxygen and nitrogen atmosphere. The oxide insulating film 492 formed in contact with the low-resistance oxide semiconductor layer is resistant to moisture and hydrogen ions. Nya, OH - It does not contain impurities such as chlorine, and blocks them from entering from the outside. An insulating film is used, typically a silicon oxide film, a silicon nitride oxide film, an aluminum oxide film, or an oxide film. An aluminum nitride film or the like is used.

[0112] Next, a second heat treatment (preferably 2 The temperature is between 00°C and 400°C, for example, between 250°C and 350°C (Figure 3(A)). For example, the second heat treatment is performed at 250° C. for 1 hour in a nitrogen atmosphere. The grooves of the oxide semiconductor layer 488 and the top and side surfaces of the oxide semiconductor layer 489 are covered with an oxide insulating film. It is heated in contact with 492.

[0113] Through the above steps, the oxide semiconductor film after deposition is dehydrated or dehydrogenated. After the heat treatment for reducing the resistance, a part of the oxide semiconductor film is selectively treated with an oxygen-excess As a result, the channel formation region 463 overlapping with the gate electrode layer 461 has an i-type structure. The first high-resistance drain region 464a overlaps the source electrode layer 465a, and the drain electrode A second high-resistance drain region 464b overlapping the pole layer 465b is formed in a self-aligned manner. In addition, the oxide semiconductor layer 472 overlapping with the gate electrode layer 471 has an i-type structure as a whole.

[0114] Note that the oxide semiconductor layer overlapping with the drain electrode layer 465b (and the source electrode layer 465a) In the second high-resistance drain region 464b (or the first high-resistance drain region 464a By forming the wiring layer 100, reliability can be improved when a driving circuit is formed. Specifically, by forming the second high-resistance drain region 464b, the first high-resistance drain region 464b is formed. The conductivity is gradually changed from the high resistance drain region 464b to the channel forming region. Therefore, a high power supply potential can be applied to the drain electrode layer 465b. When connected to a wiring that supplies VDD, the gate electrode layer 461 and the drain electrode layer Even if a high electric field is applied between 465b and the high-resistance drain region, the high-resistance drain region acts as a buffer and prevents local high A structure can be obtained in which no electric field is applied and the withstand voltage of the transistor is improved.

[0115] In addition, the oxide semiconductor layer overlapping with the drain electrode layer 465b (and the source electrode layer 465a) In the second high-resistance drain region 464b (or the first high-resistance drain region 464a ) is formed, the leakage current in the channel forming region 463 when the driver circuit is formed is It is possible to reduce the flow.

[0116] In addition, between the drain electrode layer 465b (and the source electrode layer 465a) and the oxide semiconductor layer The second low-resistance drain region 408b (and the first low-resistance drain region 408a) This configuration allows the device to operate more thermally and stably than a Schottky junction. The high-resistance drain region 408a and the second low-resistance drain region 408b are made of an oxide semiconductor layer. and has a lower resistance than the drain electrode layer 465b (and the source electrode layer 465a). Since the oxide semiconductor layer has a high conductivity, the contact resistance between the oxide semiconductor layer and the drain or source electrode layer can be reduced. It is possible.

[0117] Next, resist masks 493a and 493b are formed by a fourth photolithography process. The oxide insulating film 492 is selectively etched to remove the chalcogenide from the oxide semiconductor layer 472 in the pixel portion. An oxide insulating layer (channel protection layer) 476 is formed on the channel formation region (FIG. 3(B)). By providing the channel protective layer 476, a channel formation region of the oxide semiconductor layer 472 Damage during the etching process (such as film loss due to plasma or etching agents) Therefore, the reliability of the thin film transistor can be improved. Note that in the case where an oxide insulating layer is used as the gate insulating layer 452b as in this embodiment, Part of the gate insulating layer 452b is also etched by the etching process of the oxide insulating film 492. The oxide insulating layer 452b may be formed as a thin film. When a nitride insulating film having a lower etching rate than the insulating film 492 is used, the gate insulating layer 45 This can prevent part of 2b from being etched.

[0118] After dehydration or dehydrogenation, the channel protection layer 476 is continuously formed without exposure to the atmosphere. By continuously treating the surface without exposing it to the air, the interface can be formed as follows. Contamination by atmospheric components or impurities suspended in the air, such as water or hydrocarbons Since the interfaces of the layers can be formed without any problems, the variations in the characteristics of thin film transistors can be reduced. It is possible.

[0119] The resist masks 493a and 493b may be formed by an ink-jet method. When the photomask is formed by the inkjet method, no photomask is used, so the manufacturing cost is reduced. It can be reduced.

[0120] Next, the second gate insulating layer 452b, the oxide semiconductor layer 472, and the channel protecting layer 452b in the pixel portion are formed. After forming a light-transmitting conductive film on the protective layer 476, a fifth photolithography process is performed. Thus, a source electrode layer 475a and a drain electrode layer 475b are formed (FIG. 3C). The methods for forming conductive films with optical properties include sputtering, vacuum deposition (electron beam deposition, etc.), The arc discharge ion plating method and the spray method are used. The conductive film material is: Conductive materials that are transparent to visible light, such as In-Sn-Zn-O, In-Al- Zn-O series, Sn-Ga-Zn-O series, Al-Ga-Zn-O series, Sn-Al-Zn-O system, In-Zn-O system, Sn-Zn-O system, Al-Zn-O system, In-O system, Sn-O system Zn-O based metal oxides can be used, and the film thickness is 50 nm to 300 nm. When sputtering is used, SiO2 is added in an amount of 2% by weight or more and 10% by weight or less. A film is formed using a target containing 10% or less of the compound, and the target is formed into a light-transmitting conductive film having a crystallization inhibiting property. It is preferable to include SiOx (x>0).

[0121] Note that a resist mask for forming the source electrode layer 475a and the drain electrode layer 475b was used. The resist mask may be formed by an ink-jet method. This reduces manufacturing costs because no photomask is required.

[0122] Next, the oxide insulating layer 466, the channel protection layer 476, the source electrode layer 475a, and the drain electrode layer 475b are formed. A protective insulating layer 453 is formed over the inner electrode layer 475b (FIG. 3D). The silicon nitride film is formed by RF sputtering. RF sputtering is suitable for mass production. This is a preferable method for forming the protective insulating layer 453. The protective insulating layer 453 is formed by removing moisture and hydrogen ions. Nya, OH - It does not contain impurities such as chlorine, and blocks them from entering from the outside. Using insulating films, silicon nitride films, aluminum nitride films, silicon nitride oxide films, aluminum oxynitride films, Of course, the protective insulating layer 453 is a light-transmitting insulating film.

[0123] The protective insulating layer 453 is formed by insulating a first gate insulating layer 452 provided under the protective insulating layer 453. a) or a structure in contact with the underlying insulating film, and Molecules, hydrogen ions, and OH - In particular, it blocks the intrusion of impurities such as The first gate insulating layer 452a in contact with the edge layer 453 or the underlying insulating film is made of a silicon nitride film. That is, it is effective to form a silicon nitride film so as to surround the bottom surface, top surface, and side surfaces of the oxide semiconductor layer. The provision of the film improves the reliability of the display device.

[0124] Next, a planarization insulating layer 454 is formed over the protective insulating layer 453. Examples include acrylic resin, polyimide, benzocyclobutene resin, polyamide, and epoxy resin. In addition to the above organic materials, organic materials having low dielectric constant such as low-k materials, siloxane resins, PSG (phosphor glass), BPSG (phosphor In addition, the insulating film formed by these materials can be used in multiple layers. The planarization insulating layer 454 may be formed by stacking.

[0125] Siloxane-based resin is a Si-OS compound formed using siloxane-based materials as starting materials. The siloxane resin corresponds to a resin containing an i bond. Alternatively, an organic group having a fluoro group may be used. That's fine.

[0126] The method for forming the planarization insulating layer 454 is not particularly limited, and may be a sputtering method, a SO 4 method, or the like, depending on the material. G method, spin coating, dip coating, spray coating, droplet ejection method (inkjet method, screen Printing methods such as inkjet printing, offset printing, doctor knife, roll coater, A tool such as a spool coater or a knife coater can be used.

[0127] Next, a sixth photolithography step is performed to form a resist mask, and a planarization insulating layer 4 54 and the protective insulating layer 453 are etched to form a contact that reaches the drain electrode layer 475b. The etching here also forms a hole 494. A contact hole reaching the drain electrode layer 475b is also formed. A resist mask for forming the resist holes may be formed by an ink-jet method. When a photomask is formed by the inkjet method, no photomask is used, reducing manufacturing costs. can be reduced.

[0128] Next, after removing the resist mask, a light-transmitting conductive film is formed. The conductive film material is indium oxide (In2O3) or an indium oxide tin oxide alloy. (In2O3-SnO2, abbreviated as ITO) using sputtering or vacuum deposition methods As another material for the conductive film having light-transmitting properties, an Al-Zn-O system containing nitrogen is used. Non-single crystal film, i.e. Al-Zn-ON non-single crystal film and Zn-O non-single crystal film containing nitrogen Crystalline films, i.e., Zn-ON type non-single crystal films and nitrogen-containing Sn-Zn-O type non-single crystal films, That is, a Sn-Zn-ON based non-single crystal film may be used. The zinc composition ratio (atomic %) of the crystalline film is 47 atomic % or less, and the aluminum content in the non-single crystalline film is 47 atomic % or less. The composition ratio (atomic %) of aluminum in the non-single crystal film is larger than that of The composition ratio (atomic percentage) of nitrogen in the single crystal film is larger than that in the single crystal film. It is done with an acid solution. However, since etching of ITO is particularly prone to leaving residue, In order to improve the etching processability, indium oxide zinc oxide alloy (In2O3-ZnO) was used. You can use it.

[0129] The composition ratio of the light-transmitting conductive film is expressed in atomic percent, and is measured by an electron probe microanalyzer. (EPMA:Electron Probe X-ray MicroAnalyzer ) will be evaluated by analysis.

[0130] Next, a seventh photolithography step is performed to form a resist mask and then etch the Then, unnecessary portions are removed to form a pixel electrode layer 477 and a conductive layer 467 (see FIG. 3(E)). .).

[0131] Through the above process, the thin film transistor 460 and the thin film transistor 461 are formed on the same substrate using seven masks. The film transistor 470 can be fabricated separately for the driver circuit or the pixel portion. The thin film transistor 460 for the driving circuit has a first high-resistance drain region 464a, a second The oxide semiconductor layer includes the high-resistance drain region 464b and the channel formation region 463. The pixel thin film transistor 470 is a channel-etched thin film transistor. The channel protective thin film transistor includes the oxide semiconductor layer 472 which has been made i-type. It is a channel-stop type thin-film transistor.

[0132] In addition, the first gate insulating layer 452a and the second gate insulating layer 452b are used as dielectrics, and the capacitance wiring The storage capacitor formed by the thin film transistor and the capacitor electrode can also be formed on the same substrate. The pixel section is configured by arranging the capacitors 470 and the storage capacitors in a matrix corresponding to each pixel, By disposing a driving circuit having a thin film transistor 460 around the pixel portion, active It can be used as one of the substrates for manufacturing a sub-matrix type display device. For convenience, such a substrate is called an active matrix substrate.

[0133] Note that the pixel electrode layer 477 is formed on the planarization insulating layer 454 and the protective insulating layer 453. The capacitor electrode is electrically connected to the source electrode 47 through a contact hole. The drain electrode layer 5a and the drain electrode layer 475b can be formed using the same material and process.

[0134] The conductive layer 467 is provided so as to overlap with the channel formation region 463 of the oxide semiconductor layer. Therefore, a bias-thermal stress test (hereinafter referred to as BT) is conducted to check the reliability of thin film transistors. In the test, the threshold voltage of the thin film transistor 460 before and after the BT test was In addition, the conductive layer 467 has a potential that is the same as that of the gate electrode layer 461. It may be the same as or different from the first gate electrode layer and may also function as a second gate electrode layer. The potential of the conductive layer 467 may be GND, 0V, or may be in a floating state. .

[0135] In addition, a resist mask for forming the pixel electrode layer 477 is formed by an ink-jet method. If the resist mask is formed by the inkjet method, no photomask is required. , and manufacturing costs can be reduced.

[0136] This embodiment mode can be freely combined with other embodiment modes.

[0137] (Embodiment 2) In this embodiment mode, a semiconductor device and a manufacturing method of the semiconductor device which are different from those in Embodiment Mode 1 will be described with reference to FIGS. Specifically, in the semiconductor device shown in FIG. Both the thin film transistor and the thin film transistor arranged in the pixel portion have at least a channel. an oxide semiconductor having a hole formation region, a first high-resistance drain region, and a second high-resistance drain region; A semiconductor device having a structure in which a conductor layer is used as an active layer will be described. The thin film transistor arranged in the driver circuit is the thin film transistor shown in Embodiment 1. It has the same structure as 460 and can be manufactured by the same process. In this embodiment, the same parts as those in the first embodiment or parts and steps having similar functions are This can be done in the same manner as in form 1, and a repeated explanation will be omitted.

[0138] On a substrate 450 having an insulating surface, gate electrode layers 461 and 471, a first gate insulating layer 4 52a, a second gate insulating layer 452b are formed, and in the driver circuit area, a channel forming region The drain region 463 includes a first high-resistance drain region 464a and a second high-resistance drain region 464b. The oxide semiconductor layer, the first low-resistance drain region 408a, the second low-resistance drain region 40 8b, a source electrode layer 465a, a drain electrode layer 465b, and an oxide insulating layer 466 are formed. In the pixel portion, an oxide semiconductor layer 472 and a channel protection layer 476 are formed (see FIG. 4(A)). The oxide semiconductor layer 472 is an i-type oxide semiconductor layer with high resistance.

[0139] Note that the oxide semiconductor layer of the thin film transistor 460 provided in the driver circuit portion and the oxide semiconductor A thin film region is formed at the periphery of the conductor layer 472. The end of the oxide semiconductor layer 400 is connected to the first low-resistance drain region 408a and the second low-resistance drain region 408b. The oxide semiconductor of the thin film transistor 460 protrudes from the end of the gate region 408b. The peripheral portion of the oxide semiconductor layer and the groove (recess) of the oxide semiconductor layer, which will later become the channel formation region, are aligned in the same direction. The film has the same thickness.

[0140] In this embodiment, the oxide semiconductor layer 472 is exposed to nitrogen. Heat treatment is carried out under an inert gas atmosphere such as SiO2 or under reduced pressure. and) performing a thermal decomposition process under an inert gas atmosphere such as nitrogen while the oxide semiconductor layer 472 is partly exposed. When heat treatment is performed under reduced pressure, the exposed high-resistance oxide semiconductor layer 472 is The resistivity of the (i-type) region is reduced, and the region can be made into a high-resistance drain region.

[0141] In the oxide semiconductor layer 472, a high-resistance (i-type) region is changed to a low-resistance region. The heat treatment is preferably carried out at a temperature of 200°C or higher and 400°C or lower, for example, 250°C or higher and 350°C or lower. For example, heat treatment is performed in a nitrogen atmosphere at 250° C. for 1 hour.

[0142] In this embodiment, the substrate is introduced into an electric furnace, which is one of the heat treatment devices, and the oxide semiconductor layer 4 After heat treatment under nitrogen atmosphere, 72 was heated at a temperature of 1000 K without contact with air. The temperature is gradually cooled from T to 100°C below the heating temperature T in a nitrogen atmosphere. The decomposition is not limited to an oxygen atmosphere, but may be carried out under an atmosphere of helium, neon, argon, or the like, or under reduced pressure. The heat treatment is carried out by hydration or dehydrogenation. It is preferable that the rare gas such as argon does not contain water, hydrogen, etc. The purity of nitrogen or rare gases such as helium, neon, and argon introduced into the equipment is 6N (9 9.9999%) or more, preferably 7N (99.99999%) or more (i.e., impurity concentration It is preferable to set the concentration of the HCl-containing compound to 1 ppm or less, preferably 0.1 ppm or less.

[0143] Heat treatment on the oxide semiconductor layer 472 in an inert gas atmosphere such as nitrogen or under reduced pressure As a result, the exposed region of the oxide semiconductor layer 472 has a low resistance, and the first high-resistance drain region 4 The oxide semiconductor layer 472 is formed on the first high-resistance drain region 474a and the second high-resistance drain region 474b. In this case, the region covered by the channel protection layer 476 remains as a high resistance region. This results in an I-type channel formation region 473. Therefore, the first high-resistance drain region 474 a, the second high-resistance drain region 474b, and the oxide semiconductor including the channel forming region 473. A layer 495 is formed (see FIG. 4(B)).

[0144] Next, a light-transmitting conductive film was formed over the oxide semiconductor layer 495 and the channel protective layer 476. After forming the source electrode layer 475a and the drain electrode layer 475b, a fifth photolithography process is performed. An electrode layer 475b is formed (FIG. 4(C)).

[0145] Next, the oxide insulating layer 466, the source electrode layer 475a, the drain electrode layer 475b, and the channel electrode layer 475a are A protective insulating layer 453 and a planarization insulating layer 454 are stacked over the panel protective layer 476 .

[0146] Next, a sixth photolithography step is performed to form a resist mask, and a planarization insulating layer 4 54, and the protective insulating layer 453 is etched to form a contact that reaches the drain electrode layer 475b. A cut hole 494 is formed (FIG. 4(D)).

[0147] Next, after removing the resist mask, a light-transmitting conductive film is formed.

[0148] Next, a seventh photolithography step is performed to form a resist mask and then etch the Then, unnecessary portions are removed to form a pixel electrode layer 477 and a conductive layer 467 (FIG. 4(E)).

[0149] Through the above process, the thin film transistor 460 and the thin film transistor 461 are formed on the same substrate using seven masks. The film transistor 498 can be fabricated separately for the driver circuit or pixel portion. The thin film transistor 460 disposed in the driving circuit has a first high-resistance drain region 464 a, the second high-resistance drain region 464b, and the oxide semiconductor including the channel forming region 463. The thin film transistor is a channel-etched type including a dielectric layer, and the thin film transistor arranged in the pixel portion The first high-resistance drain region 474a and the second high-resistance drain region 474b are also formed in the saturation region 498. and a channel-protective thin film transistor including an oxide semiconductor layer 495 including a channel formation region 473. Therefore, the thin film transistors 460 and 498 are transistors. The high-resistance drain region acts as a buffer, preventing localized high electric fields from being applied, and the breakdown voltage of the transistor It has been configured to improve the following.

[0150] In the thin film transistor 460, the drain electrode layer 465b (and the source electrode layer 46 5a) and the oxide semiconductor layer, a second low-resistance drain region 408b (and a first low-resistance By using a structure having a drain region 408a, it is possible to improve thermal The first low-resistance drain region 408a and the second low-resistance drain region 408b have a stable operation. The region 408b has a lower resistance than the oxide semiconductor layer and is Since the resistance of the oxide semiconductor layer and the drain or source electrode layer 465a is higher than that of the oxide semiconductor layer and the drain or source electrode layer 465b, The contact resistance with the layer can be reduced.

[0151] In addition, the first gate insulating layer 452a and the second gate insulating layer 452b are used as dielectrics, and the capacitance wiring The storage capacitor formed by the layer and the capacitor electrode can also be formed on the same substrate. The pixel section is composed of a matrix of registers 498 and storage capacitors corresponding to each pixel. By disposing a driving circuit having a thin film transistor 460 around the pixel portion, The substrate can be used as one of the substrates for manufacturing a display device of a passive matrix type.

[0152] The conductive layer 467 is provided so as to overlap with the channel formation region 463 of the oxide semiconductor layer. Therefore, a bias-thermal stress test (hereinafter referred to as BT) is conducted to check the reliability of thin film transistors. In the test, the threshold voltage of the thin film transistor 460 before and after the BT test was In addition, the conductive layer 467 has a potential that is the same as that of the gate electrode layer 461. It may be the same as or different from the first gate electrode layer and may also function as a second gate electrode layer. The potential of the conductive layer 467 may be GND, 0V, or may be in a floating state. .

[0153] Note that this embodiment mode can be freely combined with other embodiment modes.

[0154] (Embodiment 3) In this embodiment mode, a semiconductor device and a manufacturing method of the semiconductor device different from those in Embodiment Modes 1 and 2 are described. 5 will be used for explanation. Specifically, in the semiconductor device shown in FIG. Both the thin film transistor disposed in the pixel portion and the thin film transistor disposed in the pixel portion have a gate electrode layer. The entire channel formation region overlapping with the oxide semiconductor layer is an I-type active layer. The semiconductor device will be described. In this embodiment, the same parts as those in the first embodiment and The parts and steps having the same functions as those in the first embodiment can be carried out in the same manner as in the first embodiment, and can be repeated. The explanation of this will be omitted.

[0155] 5A to 5C are cross-sectional views showing a manufacturing process of a thin film transistor 498. According to the first embodiment, after forming a light-transmitting conductive film on a substrate 450 having an insulating surface, Gate electrode layers 461 and 471 are formed by a first photolithography process.

[0156] Next, a first gate insulating layer 452a and a second gate insulating layer 452b are formed on the gate electrode layers 461 and 471. Next, a 2 nm thick insulating film is formed on the second gate insulating layer 452b. The oxide semiconductor film 480 having a thickness of 200 nm or less is formed (FIG. 5A). The process is the same as that in the first embodiment, and FIG. 5(A) corresponds to FIG. 2(A).

[0157] Next, the oxide semiconductor film 480 is dehydrated or The temperature of the first heat treatment for dehydration or dehydrogenation is 350°C or higher. The temperature is set to be lower than the distortion point of the substrate, preferably 400°C or higher. The substrate was placed in an electric furnace, and the oxide semiconductor film was subjected to heat treatment in a nitrogen atmosphere. After that, the oxide semiconductor film is not exposed to the air, preventing water and hydrogen from re-entering the oxide semiconductor film. The membrane is oxygen-deficient to reduce resistance, i.e., N-type (N -After that, in the same furnace High-purity oxygen gas or high-purity N2O gas, or ultra-dry air (dew point below -40°C) Cooling is performed by introducing oxygen gas or N2O gas into the reactor. It is preferable that hydrogen and the like are not contained. Alternatively, oxygen gas or The purity of the NO gas is 6N (99.9999%) or more, preferably 7N (99.9999%). 9%) or more (i.e., the impurity concentration in oxygen gas or N2O gas is 1 ppm or less, preferably It is preferable that the concentration is 0.1 ppm or less.

[0158] After the first heat treatment for dehydration or dehydrogenation, the temperature is preferably 200° C. or higher and 400° C. or lower. Or, at a temperature between 200°C and 300°C, in an oxygen gas atmosphere or in an N2O gas atmosphere. or heating in an atmosphere of ultra-dry air (dew point below -40°C, preferably below -60°C) Processing may be performed.

[0159] By going through the above steps, the entire oxide semiconductor film 496 is made to have an oxygen-excess state. , the resistance is increased, i.e., the I-type structure is formed (FIG. 5(B)).

[0160] As a result, the reliability of the thin film transistors to be formed later can be improved.

[0161] Next, the oxide semiconductor film is subjected to a photolithography process to form an oxide semiconductor layer having an island shape. The resulting semiconductor layers are then processed into nitride semiconductor layers 497 and 472 .

[0162] Note that the oxide semiconductor film is dehydrated or dehydrogenated under an inert gas atmosphere or reduced pressure. After cooling under an inert gas atmosphere, island-shaped oxide layers are formed by a photolithography process. Then, the oxide semiconductor layers 497 and 472 are processed into the oxide semiconductor layers 497 and 472. ℃ or less, preferably 200℃ to 300℃ in an oxygen gas atmosphere or N2O gas atmosphere. Under a dry atmosphere or under an ultra-dry air atmosphere (dew point below -40°C, preferably below -60°C) Heat treatment at 400°C may also be carried out.

[0163] In addition, before the formation of the oxide semiconductor film, an inert gas atmosphere (nitrogen, helium, neon, Heat treatment (400°C or higher) in an oxygen atmosphere or reduced pressure (argon, etc.) The gate insulating layer is then formed by removing impurities such as hydrogen and water contained in the layer. Good too.

[0164] However, the high-resistance (i-type) oxide semiconductor layers 497 and 472 are exposed. When heat treatment is performed under nitrogen, inert gas atmosphere, or reduced pressure in this state, the resistance becomes high ( The resistance of the (i-type) oxide semiconductor layers 497 and 472 is reduced to form a high-resistance drain region. Therefore, the heat treatment performed in the state where the oxide semiconductor layers 497 and 472 are exposed is performed with oxygen. Gas, N2O gas atmosphere, or ultra-dry air (dew point below -40°C, preferably -60°C) (See below).

[0165] Note that in this embodiment, an example in which dehydration or dehydrogenation is performed after the oxide semiconductor film is formed will be described. However, the first heat treatment of the oxide semiconductor layer is not particularly limited, and the first heat treatment of the oxide semiconductor layer is performed to form an island-shaped oxide semiconductor layer. Alternatively, the oxide semiconductor film may be processed into a thin film.

[0166] Next, similarly to FIGS. 2(C) to 2(E) and 3(A) to 3(E) in the first embodiment, In the peripheral driver circuit area, only a part of the oxide semiconductor layer 497 is etched to form a groove. The oxide semiconductor layer 497 having a recessed portion is formed, and the first low-resistance drain region 408a and the second low-resistance drain region 408b are formed. The second low-resistance drain region 408b, the source electrode layer 465a which is a conductive layer, the drain electrode The oxide insulating layer 466 is formed in contact with the oxide semiconductor layer 497. On the other hand, in the pixel portion, the oxide semiconductor layer 472 A channel protection layer 476 is formed on the channel formation region, and a conductive layer having light-transmitting properties is formed. A source electrode layer 475a and a drain electrode layer 475b are formed, and a thin film transistor 47 for a pixel is formed. Create 0.

[0167] Note that thin regions are formed around the peripheries of the oxide semiconductor layers 497 and 472. The end portions of the oxide semiconductor layer 483 are connected to the first low-resistance drain region 408a and the second low-resistance drain region 408b. The oxide semiconductor layer 483 and the oxide semiconductor layer 484 are formed on the surface of the oxide semiconductor layer 483. The thickness of the oxide semiconductor layer 483 is the same as that of the groove (depression) of the oxide semiconductor layer 483 which will later become a channel formation region. is doing.

[0168] Next, a second heat treatment (preferably 2 For example, the temperature is increased by heating in a nitrogen atmosphere. A second heat treatment is carried out at 250°C under atmospheric pressure for 1 hour.

[0169] Next, the thin film transistors 499 and 470 are covered with an oxide insulating layer 466 and a channel protection layer 476, and a protective insulating layer 453 in contact with the source electrode layer 475a and the drain electrode layer 475b. A protective insulating layer 453 and a planarization insulating layer 454 are stacked. A contact hole reaching the drain electrode layer 475b is formed in the contact hole and A light-transmitting conductive film is deposited over the planarization insulating layer 454. a pixel electrode layer 477 that is selectively etched to electrically connect to the thin film transistor 470; A conductive layer 467 is formed (FIG. 5(C)).

[0170] Through the above process, seven masks are used to form a thin film transistor 499 and a thin film transistor 500 on the same substrate. The film transistor 470 can be fabricated separately for the driver circuit or the pixel portion. The thin film transistor 499 for the driver circuit has an oxide semiconductor layer 497 which is entirely i-type. The thin film transistor 470 for the pixel is also a channel-etched thin film transistor including The channel protective thin film transistor includes an oxide semiconductor layer 472 whose body is i-type.

[0171] In the thin film transistor 499, the drain electrode layer 465b (and the source electrode layer 46 5a) and the oxide semiconductor layer, a second low-resistance drain region 408b (and a first low-resistance By using a structure having a drain region 408a, it is possible to improve thermal The first low-resistance drain region 408a and the second low-resistance drain region 408b have a stable operation. The region 408b has a lower resistance than the oxide semiconductor layer and is Since the resistance of the oxide semiconductor layer and the drain or source electrode layer 465a is higher than that of the oxide semiconductor layer and the drain or source electrode layer 465b, The contact resistance with the layer can be reduced.

[0172] In addition, the first gate insulating layer 452a and the second gate insulating layer 452b are used as dielectrics, and the capacitance wiring The storage capacitor formed by the layer and the capacitor electrode can also be formed on the same substrate. The pixel section is composed of a matrix of resistors 470 and storage capacitors corresponding to each pixel. By disposing a driver circuit having a thin film transistor 499 around the pixel portion, The substrate can be used as one of the substrates for manufacturing a display device of a passive matrix type.

[0173] The conductive layer 467 is provided so as to overlap with a channel formation region of the oxide semiconductor layer 497. Therefore, a bias-thermal stress test (hereinafter referred to as BT) is conducted to check the reliability of thin film transistors. In the test, the threshold voltage of the thin film transistor 499 before and after the BT test was In addition, the conductive layer 467 has a potential that is the same as that of the gate electrode layer 461. It may be the same as or different from the first gate electrode layer and may also function as a second gate electrode layer. The potential of the conductive layer 467 may be GND, 0V, or may be in a floating state. .

[0174] Note that this embodiment mode can be freely combined with other embodiment modes.

[0175] (Fourth embodiment) In this embodiment mode, a semiconductor device and a manufacturing method of the semiconductor device which are different from those in Embodiment Modes 1 to 3 will be described. This will be explained with reference to FIG. 6. Specifically, in the semiconductor device shown in FIG. In the thin film transistor to be used, the entire channel forming region overlapping with the gate electrode layer is I-type. The thin film transistors, which have an oxide semiconductor layer as an active layer and are arranged in the pixel section, are an oxide having a channel forming region, a first high resistance drain region and a second high resistance drain region; The following describes a semiconductor device having a structure in which a semiconductor layer is an active layer. In this embodiment, the same parts as those in the first embodiment or parts and steps having similar functions are the same as those in the first embodiment. This can be done in the same way as in Mode 1, and a repeated explanation will be omitted.

[0176] 6A to 6D show cross-sectional views of manufacturing steps of thin film transistors 499 and 498. FIG.

[0177] First, the steps up to FIG. 5(B) in the third embodiment are carried out in accordance with the third embodiment. A) is the same as the process in FIG. 5(B).

[0178] On a substrate 450 having an insulating surface, gate electrode layers 461 and 471, a first gate insulating layer 4 52a, a second gate insulating layer 452b is formed, and an oxide film is formed on the second gate insulating layer 452b. An oxide semiconductor film 496 is formed on the surface of the semiconductor substrate 491 (FIG. 6(A)). The oxide semiconductor film 496 is made to have a high resistance. It is type I.

[0179] Next, the oxide semiconductor film 496 is formed into an island-shaped oxide semiconductor layer by a photolithography process. The oxide semiconductor layers 497 and 472 are processed.

[0180] Next, similarly to FIGS. 2(C) to 2(E) and 3(A) to 3(E) in the first embodiment, In the peripheral driver circuit area, only a part of the oxide semiconductor layer 497 is etched to form a groove. The oxide semiconductor layer 497 having a recessed portion is formed, and the first low-resistance drain region 408a and the second low-resistance drain region 408b are formed. The second low-resistance drain region 408b, the source electrode layer 465a which is a conductive layer, the drain electrode The oxide insulating layer 466 is formed in contact with the oxide semiconductor layer 497. On the other hand, in the pixel portion, the oxide semiconductor layer 472 A channel protection layer 476 is formed on the channel formation region (FIG. 6(B)).

[0181] Note that thin regions are formed around the peripheries of the oxide semiconductor layers 497 and 472. The end portions of the oxide semiconductor layer 483 are connected to the first low-resistance drain region 408a and the second low-resistance drain region 408b. The oxide semiconductor layer 483 and the oxide semiconductor layer 484 are formed on the surface of the oxide semiconductor layer 483. The thickness of the oxide semiconductor layer 483 is the same as that of the groove (depression) of the oxide semiconductor layer 483 which will later become a channel formation region. is doing.

[0182] In this embodiment, as in Embodiment 2, at least a part of the oxide semiconductor layer 472 is exposed. In this state, heat treatment is carried out in an inert gas atmosphere such as nitrogen or under reduced pressure. In the state where the oxide semiconductor layer 472 is exposed, an inactive element such as nitrogen is When heat treatment is performed under an atmosphere of an organic gas or under reduced pressure, the exposed oxide semiconductor layer 472 The high-resistance (I-type) region is then made low-resistance to become a high-resistance drain region. This can be done.

[0183] In the oxide semiconductor layer 472, a high-resistance (i-type) region is changed to a low-resistance region. The heat treatment is preferably carried out at a temperature of 200°C or higher and 400°C or lower, for example, 250°C or higher and 350°C or lower. For example, heat treatment is performed in a nitrogen atmosphere at 250° C. for 1 hour.

[0184] In this embodiment, the substrate is introduced into an electric furnace, which is one of the heat treatment devices, and the oxide semiconductor layer 4 After heat treatment under nitrogen atmosphere, 72 was heated at a temperature of 1000 K without contact with air. The temperature is gradually cooled from T to 100°C below the heating temperature T in a nitrogen atmosphere. Dehydration is carried out under an atmosphere other than nitrogen (helium, neon, argon, etc.) or under reduced pressure. In the heat treatment, nitrogen, helium, neon, or argon is used. It is preferable that the rare gas such as argon does not contain water, hydrogen, etc. The purity of nitrogen or rare gases such as helium, neon, and argon introduced into the reactor must be 6N (99. 9999%) or more, preferably 7N (99.99999%) or more (i.e., impurity concentration is 1 ppm or less, preferably 0.1 ppm or less).

[0185] The oxide semiconductor layer 472 is subjected to heat treatment in an inert gas atmosphere such as nitrogen or under reduced pressure. By the heat treatment, the resistance of the exposed region of the oxide semiconductor layer 472 is reduced, and the first high-resistance drain A second high-resistance drain region 474a and a second high-resistance drain region 474b are formed. The region of the layer 472 covered by the channel protection layer 476 is a high-resistance region. The first high-resistance drain region 473 remains as it is, forming an I-type channel formation region. The oxide layer including the second high-resistance drain region 474a, the second high-resistance drain region 474b, and the channel forming region 473. A compound semiconductor layer 495 is formed (FIG. 6(C)).

[0186] Next, a light-transmitting conductive film was formed over the oxide semiconductor layer 495 and the channel protective layer 476. After forming the source electrode layer 475a and the drain electrode layer 475b, a fifth photolithography process is performed. An electrode layer 475b is formed.

[0187] Next, the oxide insulating layer 466, the source electrode layer 475a, the drain electrode layer 475b, and the channel electrode layer 475a are A protective insulating layer 453 and a planarization insulating layer 454 are stacked over the panel protective layer 476 .

[0188] Next, a sixth photolithography step is performed to form a resist mask, and a planarization insulating layer 4 54, and the protective insulating layer 453 is etched to form a contact that reaches the drain electrode layer 475b. Forming a cut hole 494.

[0189] Next, after removing the resist mask, a light-transmitting conductive film is formed.

[0190] Next, a seventh photolithography step is performed to form a resist mask and then etch the Then, unnecessary portions are removed to form a pixel electrode layer 477 and a conductive layer 467 (FIG. 6(D)).

[0191] Through the above process, seven masks are used to form a thin film transistor 499 and a thin film transistor 500 on the same substrate. The film transistor 498 can be fabricated separately for the driver circuit or pixel portion. The thin film transistor 499 for the driver circuit has an oxide semiconductor layer 497 which is entirely i-type. The pixel thin film transistor 498 is a channel-etched thin film transistor including the first The first high-resistance drain region 474a, the second high-resistance drain region 474b, and the channel-type The channel-protective thin film transistor includes an oxide semiconductor layer 472 including a semiconductor region 473. The thin film transistor 498 has a high resistance drain region that acts as a buffer even when a high electric field is applied. This prevents the application of a local high electric field, improving the breakdown voltage of the transistor.

[0192] In the thin film transistor 499, the drain electrode layer 465b (and the source electrode layer 46 5a) and the oxide semiconductor layer, a second low-resistance drain region 408b (and a first low-resistance By using a structure having a drain region 408a, it is possible to improve thermal The first low-resistance drain region 408a and the second low-resistance drain region 408b have a stable operation. The region 408b has a lower resistance than the oxide semiconductor layer and is Since the resistance of the oxide semiconductor layer and the drain or source electrode layer 465a is higher than that of the oxide semiconductor layer and the drain or source electrode layer 465b, The contact resistance with the layer can be reduced.

[0193] In addition, the first gate insulating layer 452a and the second gate insulating layer 452b are used as dielectrics, and the capacitance wiring The storage capacitor formed by the layer and the capacitor electrode can also be formed on the same substrate. The pixel section is composed of a matrix of registers 498 and storage capacitors corresponding to each pixel. By disposing a driver circuit having a thin film transistor 499 around the pixel portion, The substrate can be used as one of the substrates for manufacturing a display device of a passive matrix type.

[0194] The conductive layer 467 is provided so as to overlap with a channel formation region of the oxide semiconductor layer 497. Therefore, a bias-thermal stress test (hereinafter referred to as BT) is conducted to check the reliability of thin film transistors. In the test, the threshold voltage of the thin film transistor 499 before and after the BT test was In addition, the conductive layer 467 has a potential that is the same as that of the gate electrode layer 461. It may be the same as or different from the first gate electrode layer and may also function as a second gate electrode layer. The potential of the conductive layer 467 may be GND, 0V, or may be in a floating state. .

[0195] Note that this embodiment mode can be freely combined with other embodiment modes.

[0196] (Embodiment 5) In this embodiment mode, the active matrix substrate shown in Embodiment Mode 1 is used to This embodiment shows an example of manufacturing a sub-matrix liquid crystal display device. The present invention can also be applied to the active matrix substrates shown in 2 to 4.

[0197] An example of the cross-sectional structure of an active matrix substrate is shown in FIG.

[0198] In the first embodiment, the thin film transistors of the driver circuit and the thin film transistors of the pixel section are formed on the same substrate. In this embodiment, in addition to the thin film transistors, a storage capacitor, a gate The terminals of the wiring and the source wiring are also shown in the figures. can be formed by the same manufacturing steps as those described in Embodiment 1, and the number of photomasks is This can be fabricated without increasing the number of steps or the number of wirings. In the area where the gate wiring, the source wiring, and the capacitance wiring layer are all made of a conductive material having light transmission properties. The film is made of a thin film, which realizes a high aperture ratio. The wiring layer can be made of metal wiring to reduce the wiring resistance.

[0199] In FIG. 7A, a thin film transistor 210 is a channel etched thin film transistor (TFT) provided in a driving circuit. thin film transistor 227 is a thin film transistor of the type electrically connected to the pixel electrode layer 227 Reference numeral 20 denotes a channel protection type thin film transistor provided in the pixel portion.

[0200] In this embodiment, the thin film transistor 220 formed above the substrate 200 is The same structure as the thin film transistor 470 of the first embodiment is used.

[0201] The gate electrode layer of the thin film transistor 220 is formed of the same material and in the same process as the gate electrode layer of the thin film transistor 220. The capacitor wiring layer 230 is made up of a first gate insulating layer 202a and a second gate insulating layer 202b, which are dielectrics. The capacitor electrode 231 overlaps with the insulating layer 202b, forming a storage capacitor. The thin film transistor 220 has a light-transmitting property similar to that of the source electrode layer or the drain electrode layer. Therefore, the thin film transistor 220 has a light-transmitting property. In addition, each storage capacitor is transparent, which improves the aperture ratio. can be done.

[0202] It is important for the storage capacitor to have light transmittance in order to improve the aperture ratio. In the following small LCD panels, the number of gate wirings is increased to improve the resolution of the displayed image. Even if the pixel size is made smaller to achieve higher resolution, a high aperture ratio can be achieved. By using a light-transmitting film as a component of the thin film transistor 220 and the storage capacitor, To achieve a wide viewing angle, a high aperture ratio is achieved even when one pixel is divided into multiple sub-pixels. That is, even if a group of high-density thin film transistors is arranged, a large aperture ratio can be obtained. For example, if two to four pixels are arranged in one pixel, the area of ​​the display region can be sufficiently secured. When there are four sub-pixels and a storage capacitor, the thin film transistor is transparent. In addition, each storage capacitor is also transparent, which can improve the aperture ratio. do.

[0203] The storage capacitor is provided below the pixel electrode layer 227, and the capacitor electrode 231 is connected to the pixel electrode layer 2 27 is electrically connected to the

[0204] In this embodiment, a storage capacitor is formed using a capacitor electrode 231 and a capacitor wiring layer 230. However, the structure for forming the storage capacitor is not particularly limited. The pixel electrode layer is not provided with a gate wiring of an adjacent pixel, a planarizing insulating layer, a protective insulating layer, and A storage capacitor may be formed by overlapping the first gate insulating layer and the second gate insulating layer therebetween.

[0205] Also, a plurality of gate wirings, source wirings, and capacitance wiring layers are provided depending on the pixel density. In the terminal section, a first terminal electrode having the same potential as the gate wiring, a source wiring, a second terminal electrode having the same potential as the capacitor wiring layer, a third terminal electrode having the same potential as the capacitor wiring layer, and so on are arranged in a row. The number of each terminal electrode may be any number. The contractor should make the appropriate decision.

[0206] In the terminal portion, the first terminal electrode having the same potential as the gate wiring is formed of the same light-transmitting material as the pixel electrode layer 227. The first terminal electrode can be formed of a material having a good electrical conductivity. The contact hole is electrically connected to the gate wiring. The wiring electrically connects the drain electrode layer of the thin film transistor 220 and the pixel electrode layer 227. The same photomask as that used for the contact holes for connecting the planarization insulating layer 204 and the protective insulating layer 205 is used. The edge layer 203, the oxide insulating layer 216, the second gate insulating layer 202b, and the first gate insulating layer 202c. Layer 202a is formed by selective etching.

[0207] The gate electrode layer of the thin film transistor 210 of the driving circuit is provided above the oxide semiconductor layer. In this case, the thin film transistor 216 may be electrically connected to the conductive layer 217. A contact for electrically connecting the drain electrode layer of the transistor 220 and the pixel electrode layer 227. Using the same photomask as the tact hole, the planarization insulating layer 204, the protective insulating layer 203, and the oxide The gate insulating layer 216, the second gate insulating layer 202b, and the first gate insulating layer 202a are selected. A contact hole is formed by selectively etching the conductive layer through the contact hole. 217 and the gate electrode layer of the thin film transistor 210 of the driving circuit are electrically connected.

[0208] The second terminal electrode 235, which has the same potential as the source wiring 234c of the driving circuit, is connected to the pixel electrode layer 2 The source wiring 234c can be formed of the same light-transmitting material as the thin film transistor 27. The source electrode and drain electrode layer of the transistor 210 can be fabricated in the same process. Between the source wiring 234c and the substrate, an oxide semiconductor layer 234a and a low-resistance drain region 234 The second terminal electrode 235 is connected to a contact that reaches the source wiring 234c. The source wiring is electrically connected to the source electrode via a contact hole. The source wiring is a metal wiring. It is formed of the same material and in the same process as the source electrode layer of the thin film transistor 210 and has the same potential. .

[0209] The third terminal electrode, which has the same potential as the capacitor wiring layer 230, has the same light-transmitting property as the pixel electrode layer 227. In addition, the contact hole reaching the capacitor wiring layer 230 can be formed of a material having the above-mentioned properties. The contact holes are formed at the same time as the contact holes for electrically connecting the capacitor electrodes 231 to the pixel electrode layer 227. The same photomask can be used in the same process.

[0210] In addition, when an active matrix type liquid crystal display device is manufactured, A liquid crystal layer is provided between a substrate and an opposing substrate on which an opposing electrode (also called an opposing electrode layer) is provided. The active matrix substrate and the counter substrate are fixed together. A common electrode electrically connected to the electrode is provided on the active matrix substrate. A fourth terminal electrode is provided on the terminal portion, which is electrically connected to the common electrode. The fourth terminal electrode is a terminal for setting the potential, for example, GND, 0V, etc. It can be made of the same light-transmitting material as the pole layer 227 .

[0211] In addition, the source electrode layer of the thin film transistor 220 and the source electrode layer of the thin film transistor 210 The configuration for electrically connecting the source of the thin film transistor 220 is not particularly limited. A connection electrode that connects the electrode layer and the source electrode layer of the thin film transistor 210 is formed on the pixel electrode layer 227. In addition, in the portion other than the display area, the thin film transistor 2 may be formed in the same process. The source electrode layer of the thin film transistor 20 and the source electrode layer of the thin film transistor 210 are overlapped in contact with each other. That's fine.

[0212] The cross-sectional structure of the gate wiring layer 232 of the driving circuit is shown in FIG. This example is an example of a small LCD panel of 10 inches or less, so the gate wiring layer of the drive circuit The layer 232 is made of the same light-transmitting material as the gate electrode layer of the thin film transistor 220. do.

[0213] Also, a gate electrode layer, a source electrode layer, a drain electrode layer, a pixel electrode layer, or other electrodes If the same material is used for the wiring layers, a common sputtering target and common manufacturing equipment can be used. The cost of the material and the etchant (or This reduces the cost of etching gases, resulting in reduced manufacturing costs. It is possible.

[0214] In the structure of FIG. 7A, a photosensitive resin material is used as the planarization insulating layer 204. In this case, the step of forming a resist mask can be omitted.

[0215] FIG. 7(B) shows a cross-sectional structure that is partially different from that shown in FIG. 7(A). A) is the same as A) except that the planarization insulating layer 204 is not present, and therefore the same parts are designated by the same reference numerals. 7B, the protective insulating layer 203 is in contact with the protective insulating layer 203. The pixel electrode layer 227, the conductive layer 217, and the second terminal electrode 235 are formed.

[0216] With the structure of FIG. 7B, the step of forming the planarization insulating layer 204 can be omitted.

[0217] This embodiment mode can be freely combined with other embodiment modes.

[0218] (Sixth embodiment) In this embodiment, the size of the liquid crystal display panel exceeds 10 inches, and is 60 inches or even When using a 120-inch screen, the wiring resistance of the light-transmitting wiring may become a problem. An example in which a part of the gate wiring is made into a metal wiring to reduce wiring resistance will be shown.

[0219] In FIG. 8(A), the same parts as those in FIG. 7(A) are designated by the same reference numerals, and detailed explanations of the same parts will be omitted. Omitted.

[0220] FIG. 8A shows a gate wiring of the driving circuit made of metal, and a thin film transistor 210 In this example, the gate electrode layer is formed in contact with a wiring having the same light-transmitting property as the gate electrode layer. Therefore, the number of photomasks increases compared to the first embodiment.

[0221] First, a layer capable of withstanding the first heat treatment for dehydration or dehydrogenation is formed on the substrate 200. A heat-resistant conductive material film (thickness: 100 nm or more and 500 nm or less) is formed.

[0222] In this embodiment, a tungsten film with a thickness of 370 nm and a tantalum nitride film with a thickness of 50 nm are used. Here, the conductive film is a stack of a tantalum nitride film and a tungsten film. It is not limited to Ta, W, Ti, Mo, Al, Cu, or the above-mentioned elements. Alloys containing the above elements, or alloys combining the above elements, or alloys containing the above elements The heat-resistant conductive material film is not limited to a single layer containing the above-mentioned elements, but may be a two-layer film. The above stacked layers can be used.

[0223] A metal wiring is formed by a first photolithography process, and a first metal wiring layer 236 and a second The metal wiring layer 237 is formed. The tungsten film and the tantalum nitride film are etched using I CP (Inductively Coupled Plasma) It is recommended to use the etching method. The ICP etching method is used, and the etching conditions (coil type) The amount of power applied to the electrode, the amount of power applied to the electrode on the substrate side, the temperature of the electrode on the substrate side, etc. By adjusting the etching rate appropriately, the film can be etched into a desired tapered shape. The metal wiring layer 236 and the second metal wiring layer 237 are tapered to form a contact on top. Defective film formation of a light-transmitting conductive film can be reduced.

[0224] Next, a light-transmitting conductive film is formed, and then a gate is formed by a second photolithography process. the gate wiring layer 238, the gate electrode layer of the thin film transistor 210, the gate electrode layer of the thin film transistor 220, The light-transmitting conductive film is a light-transmitting conductive film that transmits light to visible light as described in Embodiment 1. A light-transmitting conductive material is used.

[0225] Note that depending on the material of the light-transmitting conductive film, for example, the gate wiring layer 238 may be made of a first gold At the interface where the metal wiring layer 236 or the second metal wiring layer 237 is in contact, the metal wiring layer 236 or the second metal wiring layer 237 is formed by a subsequent heat treatment or the like. Since an oxide film may be formed and the contact resistance may increase, the second metal wiring layer 237 is It is preferable to use a metal nitride film that prevents oxidation of the metal wiring layer 236 .

[0226] Next, a gate insulating layer, an oxide semiconductor layer, and the like are formed in the same steps as those in Embodiment 1. In this step, an active matrix substrate is manufactured according to the first embodiment.

[0227] In this embodiment, after the planarization insulating layer 204 is formed, a photomask is used to This shows an example of selectively removing the planarizing insulating layer in the terminal area. It is preferable not to do this in order to ensure a good connection with the FPC.

[0228] In FIG. 8A, the second terminal electrode 235 is formed on the protective insulating layer 203. 8(A) shows the gate wiring layer 238 overlapping a part of the second metal wiring layer 237. It can also be used as a gate wiring layer that covers the entire first metal wiring layer 236 and the second metal wiring layer 237. That is, the first metal wiring layer 236 and the second metal wiring layer 237 are formed on the gate wiring layer 23. 8 can be called an auxiliary wiring for reducing resistance.

[0229] In the terminal portion, the first terminal electrode having the same potential as the gate wiring is disposed on the protective insulating layer 203. The wiring from the terminal portion is also made of metal. Formed by wiring.

[0230] In addition, the gate wiring layer and the capacitance wiring layer in the non-display area are Metal wiring, that is, the first metal wiring layer 236 and the second metal wiring layer 237 are used as auxiliary wiring. It can also be used.

[0231] FIG. 8(B) shows a cross-sectional structure that is partly different from that shown in FIG. 8(A). A) and the drive circuit are the same except for the material of the gate electrode layer of the thin film transistor. Therefore, the same parts are designated by the same reference numerals, and detailed explanations of the same parts will be omitted.

[0232] FIG. 8B shows an example in which the gate electrode layer of the thin film transistor of the driver circuit is made of metal wiring. In the driver circuit, the material for the gate electrode layer is not limited to a light-transmitting material.

[0233] In FIG. 8B, the thin film transistor 240 of the driving circuit is formed on the first metal wiring layer 242. The second metal wiring layer 241 is stacked as a gate electrode layer. The second metal wiring layer 236 can be formed using the same material and process as the first metal wiring layer 236. The second metal wiring layer 241 is formed using the same material and in the same process as the second metal wiring layer 237. can be done.

[0234] In addition, when the first metal wiring layer 242 is electrically connected to the conductive layer 217, the first metal wiring The second metal wiring layer 241 is preferably a metal nitride film to prevent oxidation of the layer 242. .

[0235] In this embodiment, the wiring resistance is reduced by using a part of the metal wiring, and the size of the liquid crystal display panel is Even if the display size exceeds 10 inches and is set to 60 inches or even 120 inches, High definition and a high aperture ratio can be achieved.

[0236] This embodiment mode can be freely combined with other embodiment modes.

[0237] (Embodiment 7) In this embodiment, an example of the configuration of the storage capacitor that is different from that of the fifth embodiment is shown in FIG. 9(A) and This is shown in Figure 9(B). Figure 9(A) is the same as Figure 7(A) except for the configuration of the storage capacitor. Therefore, the same parts are designated by the same reference numerals, and detailed explanations of the same parts will be omitted. 1A shows the cross-sectional structure of a thin film transistor 220 and a storage capacitor disposed in a pixel.

[0238] FIG. 9(A) shows the dielectric layer consisting of an oxide insulating layer 216, a protective insulating layer 203, and a planarizing insulating layer 20 4, the pixel electrode layer 227 and the capacitor wiring layer 250 overlapping the pixel electrode layer 227 form a storage capacitor. The capacitor wiring layer 250 is an example of forming a capacitor. Since the source electrode layer is formed of the same material and in the same process as the source electrode layer, The layout is such that it does not overlap with the source wiring layer of the resistor 220.

[0239] The storage capacitor shown in FIG. 9A has a pair of electrodes and a dielectric material that are transparent, and the entire storage capacitor The body is translucent.

[0240] FIG. 9B shows an example of a storage capacitor configuration different from that shown in FIG. 9A. Since this is the same as 7(A) except for the difference in the storage capacitor configuration, the same symbols are used for the same parts. Detailed explanations of the same parts will be omitted.

[0241] FIG. 9(B) shows a structure in which the dielectric is a first gate insulating layer 202a and a second gate insulating layer 202b. The capacitor wiring layer 230 and the oxide semiconductor layer 251 and the capacitor wiring layer 230 overlap each other. In this example, a storage capacitor is formed by laminating the capacitor electrode 231 with an oxide semiconductor. It is laminated on the layer 251 in contact with the layer 251 and functions as one electrode of the storage capacitor. The electrode 231 has the same light-transmitting property as the source electrode layer or the drain electrode layer of the thin film transistor 220. The capacitor wiring layer 230 is formed in the same process as the thin film transistor 2. Since the gate electrode layer 20 is formed using the same material and process as the gate electrode layer 20, The layout is such that it does not overlap with the gate wiring layer of the resistor 220.

[0242] In addition, the capacitance electrode 231 is electrically connected to the pixel electrode layer 227 .

[0243] The storage capacitor shown in FIG. 9B also has a pair of electrodes and a dielectric material that are transparent, and the entire storage capacitor The body is translucent.

[0244] The storage capacitors shown in FIGS. 9A and 9B are transparent and have the number of gate wirings. In order to increase the resolution of the displayed image by increasing the number of pixels, it is necessary to provide sufficient capacity even if the pixel size is reduced. It is possible to obtain a high aperture ratio.

[0245] This embodiment mode can be freely combined with other embodiment modes.

[0246] (Embodiment 8) In this embodiment, at least a part of the driver circuit and a thin film transistor disposed in the pixel portion are formed on the same substrate. An example of fabricating a transistor will be described below.

[0247] The thin film transistors disposed in the pixel portion are formed according to any one of Embodiments 1 to 4. The thin film transistors shown in the first to fourth embodiments are n-channel TFTs, so that the Among them, part of the driver circuit can be configured with n-channel TFTs. It is formed on the same substrate as the resistor.

[0248] An example of a block diagram of an active matrix display device is shown in FIG. A pixel portion 5301, a first scanning line driver circuit 5302, a second scanning line driver circuit 5303, and a third scanning line driver circuit 5304 are provided on a substrate 5300. The pixel portion 5301 has a plurality of signal lines. are arranged extending from the signal line driver circuit 5304, and a plurality of scanning lines are arranged in the first scanning line driver circuit The scanning line driver circuit 5302 and the second scanning line driver circuit 5303 are arranged to extend from each other. In the intersections of the signal lines and the wiring, pixels each having a display element are arranged in a matrix. The substrate 5300 of the display device is made of FPC (Flexible Printed Circuit). A timing control circuit 5305 (controller, control I) is connected to the timing control circuit 5305 via a connection part such as a C).

[0249] In FIG. 14A, a first scanning line driver circuit 5302, a second scanning line driver circuit 5303, a signal The signal line driver circuit 5304 is formed on the same substrate 5300 as the pixel portion 5301. This reduces the number of externally provided components such as drive circuits, thereby reducing costs. In addition, when a driving circuit is provided outside the substrate 5300, the wiring is extended to provide a connection portion. The number of connections can be reduced, and the reliability or yield can be improved.

[0250] The timing control circuit 5305 controls the first scanning line driver circuit 5302 as follows: The first scanning line driving circuit start signal (GSP1) (the start signal is a start pulse Also referred to as a timing signal, it supplies a clock signal (GCK1) for the scanning line driver circuit. The control circuit 5305 controls the second scanning line driver circuit 5303 to control the second scanning line It provides the start signal (GSP2) for the driver circuit and the clock signal (GCK2) for the scanning line driver circuit. A signal line driver circuit 5304 receives a start signal (SSP) for the signal line driver circuit, Clock signal for driver circuit (SCK), data for video signal (DATA) (simply video signal Each clock signal has a period of It may be a plurality of clock signals with different timings, or an inverted clock signal (CKB) and The first scanning line driver circuit 5302 and the second scanning line driver circuit 5303 may be supplied together. It is possible to omit one of the line driver circuit 5302 and the line driver circuit 5303 .

[0251] In FIG. 14B, a first scanning line driver circuit 5302 and a second scanning line driver circuit 5303 are shown. The signal line driver circuit 5304 is formed on the same substrate 5300 as the pixel portion 5301. shows a configuration formed on a separate substrate.

[0252] The thin film transistors described in Embodiments 1 to 4 are n-channel TFTs. 5(A) and 15(B) show the configuration and operation of a signal line driver circuit configured with n-channel TFTs. An example will be given below.

[0253] The signal line driver circuit includes a shift register 5601 and a switching circuit 5602 . The switching circuit 5602 is composed of switching circuits 5602_1 to 5602_N (N is a natural number). The switching circuits 5602_1 to 5602_N each have a plurality of circuits. , a plurality of thin film transistors 5603_1 to 5603_k (k is a natural number) The thin film transistors 5603_1 to 5603_k are N-channel TFTs. An example will be explained.

[0254] The connection relationship of the signal line driver circuit will be described using the switching circuit 5602_1 as an example. The first terminals of the thin film transistors 5603_1 to 5603_k are connected to the wirings 5604_1 The second terminals of the thin film transistors 5603_1 to 5603_k are connected to the first terminals of the thin film transistors 5603_1 to 5603_k. are connected to the signal lines S1 to Sk, respectively. The gate of k is connected to the wiring 5605_1.

[0255] The shift register 5601 sequentially outputs H level (H signal) to the wirings 5605_1 to 5605_N. , also referred to as a high power supply potential level), and the switching circuits 5602_1 to 56 It has the function of selecting 02_N in order.

[0256] The switching circuit 5602_1 is connected to the wirings 5604_1 to 5604_k and the signal lines S1 to Sk. The function of controlling the conduction state (conduction between the first terminal and the second terminal) with the wiring 5604_ The switches have the function of controlling whether or not the potentials of 1 to 5604_k are supplied to the signal lines S1 to Sk. In this way, the switching circuit 5602_1 has a function as a selector. The film transistors 5603_1 to 5603_k are connected to the wirings 5604_1 to 5604_k, respectively. and the signal lines S1 to Sk, that is, the wirings 5604_1 to 5604_k. The thin film transistor 56 has a function of supplying the potential of the signal lines S1 to Sk. Each of 03_1 to 5603_k functions as a switch.

[0257] The wirings 5604_1 to 5604_k each carry video signal data (DATA). The video signal data (DATA) is an analog signal corresponding to the image information or image signal. This is often a signal.

[0258] Next, the operation of the signal line driver circuit of FIG. 15(A) will be explained with reference to the timing chart of FIG. 15(B). 15B shows signals Sout_1 to Sout_N and An example of Vdata_1 to Vdata_k is shown. are examples of output signals of the shift register 5601, and signals Vdata_1 to Vdata _k are examples of signals input to the wirings 5604_1 to 5604_k, respectively. One operation period of the signal line driving circuit corresponds to one gate selection period in the display device. The selection period is divided into periods T1 to TN, for example. This is the period for writing video signal data (DATA) to the pixels belonging to the selected row. be.

[0259] In the drawings of the present embodiment, the signal waveforms of the components are rounded for clarity. Therefore, the scale may not necessarily be limited to that shown. It should be noted that

[0260] During the period T1 to the period TN, the shift register 5601 outputs a high-level signal to the wiring 560 For example, in the period T1, the shift registers 5 601 outputs a high-level signal to the wiring 5605_1. 5603_1 to 5603_k are turned on, so the wiring 5604_1 to 5604_k and the signal At this time, the wirings 5604_1 to 5604_k are in a conductive state. Data(S1)~Data(Sk) are input. Data(S1)~Data(Sk ) belong to the selected row via thin film transistors 5603_1 to 5603_k. In this way, during the periods T1 to TN, the pixels in the first to k-th columns are written. Then, the video signal data (DATA) is sent to the pixels belonging to the selected row in order of k columns. It will be written.

[0261] As described above, video signal data (DATA) is written to pixels in multiple columns. This makes it possible to reduce the number of video signal data (DATA) or the number of wirings. This reduces the number of connections to external circuits. By writing directly to the memory, the writing time can be increased, and the video signal can be written This can prevent under-crowding.

[0262] The shift register 5601 and the switching circuit 5602 are the same as those in the first embodiment. It is possible to use circuits configured with thin film transistors shown in the above to 4.

[0263] Regarding one form of a shift register used in a part of a scanning line driver circuit and / or a signal line driver circuit, This will be explained with reference to FIGS. 16 and 17.

[0264] The scanning line driving circuit has a shift register. In some cases, it may also have a level shifter or a buffer. In the scanning line driver circuit, a clock signal is input to the shift register. The selection signal is generated by inputting the (CLK) and start pulse signal (SP). The generated selection signal is buffered and amplified in a buffer and then supplied to the corresponding scanning line. The gate electrodes of the transistors of one line of pixels are connected to the scanning line. Since the transistors of the pixels in one line must be turned on simultaneously, a buffer is required. The capacitor used is one that can pass a large current.

[0265] The shift register includes the first pulse output circuit 10_1 to the N-th pulse output circuit 10_N ( N is a natural number of 3 or more (see FIG. 16(A)). The first pulse output circuit 10_1 to the N-th pulse output circuit 10_N of the register are A first clock signal CK1 is transmitted from a wiring 11, and a second clock signal CK2 is transmitted from a second wiring 12. , a third clock signal CK3 is transmitted from the third wiring 13, and a fourth clock signal CK4 is transmitted from the fourth wiring 14. In the first pulse output circuit 10_1, a signal CK4 is supplied from the fifth wiring 15. A start pulse SP1 (first start pulse) is input. In the pulse output circuit 10_n (n is a natural number between 2 and N), A signal from the previous stage signal OUT(n-1) is input. The circuit 10_1 receives a signal from a third pulse output circuit 10_3 located two stages later. Similarly, in the n-th pulse output circuit 10_n at the second stage or later, the (n+2)-th pulse A signal from the pulse output circuit 10_(n+2) (called the next stage signal OUT(n+2)) is input. Therefore, the pulse output circuit of each stage outputs a pulse to the pulse output circuit of the subsequent stage and / or the previous stage. The first output signal (OUT(1)(SR)~OUT(N)(SR)) for inputting, The second output signals (OUT(1) to OUT(N)) are outputted and inputted to a circuit or the like. As shown in FIG. 16(A), the last two stages of the shift register receive the next stage signal OUT Since (n+2) is not input, for example, the second start pulse SP2 and the third The start pulse SP3 may be input to each of the inputs.

[0266] The clock signal (CK) alternates between H level and L level (L signal, low power supply potential) at regular intervals. Here, the first clock signal (CK1) to the second clock signal (CK2) are signals that repeat a cycle of 1 / 2 levels. The fourth clock signal (CK4) is delayed by 1 / 4 cycle in order. The first clock signal (CK1) to the fourth clock signal (CK4) are used to generate a pulse output circuit. The clock signal is controlled by the GCK It is sometimes called SCK, but here we will explain it as CK.

[0267] FIG. 16(B) shows one of the pulse output circuits 10_N shown in FIG. 16(A). The terminal 21, the second input terminal 22, and the third input terminal 23 are connected to the first wiring 11 to the fourth wiring 12. 14. For example, in FIG. 16(A), the first pulse The output circuit 10_1 has a first input terminal 21 electrically connected to the first wiring 11, and a second The input terminal 22 is electrically connected to the second wiring 12, and the third input terminal 23 is electrically connected to the third wiring 13. The second pulse output circuit 10_2 is electrically connected to the first input terminal The second input terminal 21 is electrically connected to the second wiring 12, and the second input terminal 22 is electrically connected to the third wiring 13. The third input terminal 23 is electrically connected to the fourth wiring 14 .

[0268] Each of the first pulse output circuit 10_1 to the N-th pulse output circuit 10_N has a first input terminal 21, a second input terminal 22, a third input terminal 23, a fourth input terminal 24, a fifth input terminal 16B, the input terminal 25, the first output terminal 26, and the second output terminal 27. In the first pulse output circuit 10_1, a first clock signal is input to a first input terminal 21. A first clock signal CK1 is input to the first input terminal 21, a second clock signal CK2 is input to the second input terminal 22, and a third clock signal CK3 is input to the third input terminal 23. A third clock signal CK3 is input to the input terminal 23 of the clock generator 10, and a start signal CK4 is input to the fourth input terminal 24 of the clock generator 10. A pulse is input, the subsequent signal OUT(3) is input to the fifth input terminal 25, and the first output The first output signal OUT(1)(SR) is output from the terminal 26, and the second output signal OUT(1)(SR) is output from the second output terminal 27. The second output signal OUT(1) is output.

[0269] The first pulse output circuit 10_1 to the N-th pulse output circuit 10_N are three-terminal thin film transistors. In addition to transistors (also called TFTs: Thin Film Transistors), The four-terminal thin film transistors described in the above embodiments can be used. In the document, when a thin film transistor has two gate electrodes via a semiconductor layer, The gate electrode below the semiconductor layer is called the lower gate electrode, and the gate electrode above the semiconductor layer is called the upper gate electrode. It is also called the gate electrode.

[0270] When an oxide semiconductor is used for a semiconductor layer including a channel formation region of a thin film transistor, The threshold voltage may shift to the negative or positive side depending on the process. Therefore, in a thin film transistor using an oxide semiconductor for a semiconductor layer including a channel formation region, A configuration that allows for control of the threshold voltage is preferable. The threshold voltage is determined by the gate insulating film above and below the channel forming region of the thin film transistor. By providing a gate electrode and controlling the potential of the upper and / or lower gate electrodes, a desired The value can be controlled.

[0271] Next, an example of a specific circuit configuration of the pulse output circuit shown in FIG. 16(B) will be described with reference to FIG. This is explained in (C).

[0272] The pulse output circuit shown in FIG. 16(C) includes a first transistor 31 to a thirteenth transistor 16(D)). In addition, the first input terminal 21 to the fifth input terminal 43 are In addition to the input terminal 25, the first output terminal 26, the second output terminal 27, a first high power supply potential V A power supply line 51 to which DD is supplied, a power supply line 52 to which a second high power supply potential VCC is supplied, The first transistor 31 to the thirteenth transistor are connected to the power supply line 53 to which the potential VSS is supplied. A signal or a power supply potential is supplied to the power supply 43. Here, the voltage of each power supply line in FIG. The magnitude relationship of the power supply potentials is such that the first power supply potential VDD is equal to or higher than the second power supply potential VCC, and the third power supply potential VDD is equal to or higher than the second power supply potential VCC. The second power supply potential VCC is set to a potential higher than the third power supply potential VSS. The fourth clock signal (CK1) to the fourth clock signal (CK4) change between H level and L level at regular intervals. It is a signal that repeats this, and when it is at H level it is VDD and when it is at L level it is VSS. By making the potential VDD of the power supply line 51 higher than the potential VCC of the power supply line 52, The potential applied to the gate electrode of the transistor can be kept low without affecting the This makes it possible to reduce the shift in the threshold voltage of the transistor and suppress degradation. Among the first transistor 31 to the thirteenth transistor 43, the first transistor 31 The sixth transistor 36 to the ninth transistor 39 are four-terminal thin film transistors. It is preferable to use the first transistor 31 and the sixth to ninth transistors 36 to 39. The operation of the transistor 39 is controlled by the node to which one of the electrodes serving as the source or drain is connected. The potential of the transistor is required to be switched by a control signal of the gate electrode. This allows for a fast response to the control signal input to the gate electrode (a steep rise in the on-current). ) is a transistor that can reduce malfunctions in pulse output circuits. Therefore, the threshold voltage can be controlled by using a four-terminal thin film transistor. This makes it possible to provide a pulse output circuit that can further reduce malfunctions.

[0273] In FIG. 16C, the first transistor 31 has a first terminal electrically connected to the power supply line 51. a second terminal electrically connected to a first terminal of a ninth transistor 39; (the lower gate electrode and the upper gate electrode) are electrically connected to the fourth input terminal 24. The second transistor 32 has a first terminal electrically connected to the power supply line 53 and a second terminal the gate electrode of the ninth transistor 39 is electrically connected to the first terminal of the fourth transistor The third transistor 33 is electrically connected to the gate electrode of the first terminal is electrically connected to the first input terminal 21, and the second terminal is electrically connected to the first output terminal 26. The fourth transistor 34 has a first terminal electrically connected to the power supply line 53, The second terminal is electrically connected to the first output terminal 26. The fifth transistor 35 is The first terminal is electrically connected to the power supply line 53, and the second terminal is connected to the gate of the second transistor 32. and the gate electrode of the fourth transistor 34, the gate electrode of which is electrically connected to the fourth The sixth transistor 36 has a first terminal electrically connected to the input terminal 24. 52, and the second terminal is electrically connected to the gate electrode of the second transistor 32 and the fourth transistor The gate electrode (the lower gate electrode and the upper gate electrode) of the transistor 34 is electrically connected to the gate electrode of the transistor 34. The seventh transistor (the gate electrode) is electrically connected to the fifth input terminal 25. The eighth transistor 37 has a first terminal electrically connected to the power supply line 52 and a second terminal electrically connected to the eighth transistor 38. and a gate electrode (lower gate electrode and upper gate electrode) electrically connected to the second terminal of the is electrically connected to the third input terminal 23. The eighth transistor 38 is is electrically connected to the gate electrode of the second transistor 32 and the gate electrode of the fourth transistor 34. and the gate electrodes (the lower gate electrode and the upper gate electrode) are connected to the second input terminal The ninth transistor 39 has a first terminal electrically connected to the first transistor 22. The second terminal is electrically connected to the second terminal of the first transistor 31 and the second terminal of the second transistor 32. The gate electrode of the third transistor 33 and the gate electrode of the tenth transistor 40 are connected to each other. The gate electrodes (lower gate electrode and upper gate electrode) are electrically connected to the power supply line 51. The tenth transistor 40 has a first terminal electrically connected to the first input terminal 2. 1, the second terminal is electrically connected to the second output terminal 27, and the gate electrode is electrically connected to the second terminal of the ninth transistor 39. 41 has a first terminal electrically connected to the power supply line 53 and a second terminal electrically connected to the second output terminal 27. The gate electrodes of the second transistor 32 and the fourth transistor 33 are electrically connected to each other. The twelfth transistor 42 is electrically connected to the gate electrode of the first terminal of the twelfth transistor 42. The first terminal is electrically connected to the power supply line 53, and the second terminal is electrically connected to the second output terminal 27. The gate electrode of the seventh transistor 37 (the lower gate electrode and the upper gate electrode) The thirteenth transistor 43 has a first terminal electrically connected to the power supply line 5. 3, the second terminal is electrically connected to the first output terminal 26, and the gate electrode The gate electrodes (lower gate electrode and upper gate electrode) of the seventh transistor 37 are electrically connected. are electrically connected.

[0274] In FIG. 16C, the gate electrode of the third transistor 33, the gate electrode of the tenth transistor 4 The connection point of the gate electrode of the ninth transistor 30 and the second terminal of the ninth transistor 39 is referred to as node A. The gate electrode of the second transistor 32, the gate electrode of the fourth transistor 34, the second terminal of the fifth transistor 35, the second terminal of the sixth transistor 36, the second terminal of the eighth transistor The connection point of the first terminal of the eleventh transistor 38 and the gate electrode of the eleventh transistor 41 is node B. Let's say.

[0275] FIG. 17(A) shows the pulse output circuit described in FIG. 16(C) as a first pulse output circuit 10_ 1, the first input terminal 21 to the fifth input terminal 25 and the first output terminal 26 and the signals input to or output from the second output terminal 27.

[0276] Specifically, a first clock signal CK1 is input to the first input terminal 21, and a second clock signal CK2 is input to the second input terminal 22. A second clock signal CK2 is input to the third input terminal 22, and a third clock signal CK3 is input to the third input terminal 23. A start pulse (SP1) is input to the fourth input terminal 24, and a signal CK3 is input to the fifth input terminal 25. The next stage signal OUT(3) is input to the input terminal 25 of the The signal OUT(1)(SR) is output, and the second output signal OUT( 1) is output.

[0277] A thin film transistor is a transistor having at least three elements including a gate, a drain, and a source. The gate is a semiconductor element in which a channel region is formed in the region overlapping the gate. By controlling the gate potential, the drain and source are connected via the channel region. The source and drain are thin film transistors. Which is the source or drain depends on the transistor structure and operating conditions. Therefore, it is difficult to define the regions that function as the source and drain. In some cases, they are not called sources or drains. In such cases, for example, they are called first It may be written as terminal or second terminal.

[0278] In FIG. 16(C) and FIG. 17(A), the node A is set to the floating state. A capacitor may be provided separately to perform a strap operation. To achieve this, a capacitor having one electrode electrically connected to the node B may be provided separately.

[0279] Here, the timing of the shift register having a plurality of pulse output circuits shown in FIG. A shift chart is shown in FIG. 17(B). In this case, the period 61 in FIG. 17(B) corresponds to the vertical blanking period, and the period 62 corresponds to the gate selection period. do.

[0280] As shown in FIG. 17A, the ninth power supply voltage Vcc is applied to the gate electrode. By providing the transistor 39, the following occurs before and after the bootstrap operation: The advantages are as follows:

[0281] If the ninth transistor 39, to whose gate electrode the second power supply potential VCC is applied, is not present, When the potential of the node A rises due to the base strap operation, the second transistor 31 The potential of the source terminal rises and becomes greater than the first power supply potential VDD. The source of the first transistor 31 is switched to the first terminal side, that is, the power supply line 51 side. Therefore, in the first transistor 31, the gate and source, the gate and drain In both cases, a large bias voltage is applied, which causes a large stress on the transistor. Therefore, the ninth power supply potential VCC is applied to the gate electrode. By providing the transistor 39, the voltage of the node A is increased by the bootstrap operation. The potential of the second terminal of the first transistor 31 rises, but the potential of the second terminal of the first transistor 31 does not rise. That is, by providing the ninth transistor 39, the first transistor The negative bias voltage applied between the gate and source of the transistor 31 can be reduced. Therefore, by using the circuit configuration of this embodiment, the first transistor 31 The negative bias voltage applied between the gate and source can also be reduced, reducing the stress-induced Deterioration of the first transistor 31 can be suppressed.

[0282] The ninth transistor 39 is provided at a location corresponding to the second gate of the first transistor 31. and a gate of the third transistor 33 via a first terminal and a second terminal. In this embodiment, a system having a plurality of pulse output circuits may be provided. In the case of a soft register, the signal line driver circuit has more stages than the scanning line driver circuit. The resistor 39 may be omitted, which has the advantage of reducing the number of transistors.

[0283] Note that the semiconductor layers of the first to thirteenth transistors 31 to 43 are made of oxide semiconductor. By using a conductor, the off-current of the thin film transistor is reduced, and the on-current and This allows for increased field effect mobility and reduced degradation. In addition, a transistor including an oxide semiconductor can: Compared to transistors using amorphous silicon, a high potential is applied to the gate electrode. Therefore, the degree of deterioration of the transistor due to the second power supply potential VCC is small. The same operation can be obtained by supplying the first power supply potential VDD to the power supply line. Since the number of power supply lines can be reduced, the circuit can be made smaller.

[0284] The gate electrodes (lower gate electrode and upper gate electrode) of the seventh transistor 37 a clock signal CK3 provided by the third input terminal 23 to the eighth transistor 38 The gate electrodes (lower gate electrode and upper gate electrode) of The supplied clock signal CK2 is applied to the gate electrode of the seventh transistor 37 (the lower gate A clock signal CK is supplied by a second input terminal 22 to the 2. The gate electrodes (lower gate electrode and upper gate electrode) of the eighth transistor 38 The wiring is input so that the clock signal CK3 is supplied from the third input terminal 23. In this case, in the shift register shown in FIG. The seventh transistor 37 and the eighth transistor 38 are both in an on state. The seventh transistor 37 is turned off, the eighth transistor 38 is turned on, and then the seventh transistor 39 is turned on. By turning off the eighth transistor 37 and the eighth transistor 38, the second input terminal The potential at the node B decreases due to the potential at the third input terminal 22 and the potential at the third input terminal 23 decreasing. The potential of the gate electrode of the seventh transistor 37 is decreased, and the potential of the gate electrode of the eighth transistor 38 is decreased. This occurs twice due to a drop in the electrode potential. 17(B), the seventh transistor 37 and the eighth transistor From the state where both the seventh transistor 37 and the eighth transistor 38 are on, In the OFF state, the seventh transistor 37 is OFF and the eighth transistor 38 is OFF. By setting the state, the potentials of the second input terminal 22 and the third input terminal 23 decrease. The potential drop at node B caused by this is compensated by the potential drop at the gate electrode of the eighth transistor 38. Therefore, the gate electrode of the seventh transistor 37 (lower gate electrode and upper gate electrode) from the third input terminal 23 to the clock signal CK 3 is supplied to the gate electrode of the eighth transistor 38 (the lower gate electrode and the upper gate electrode The clock signal CK2 is supplied from the second input terminal 22 to the output electrode. is preferable because it reduces the number of fluctuations in the potential of node B and reduces noise. Because it is possible.

[0285] In this way, the potentials of the first output terminal 26 and the second output terminal 27 are maintained at the L level. By configuring the node B to periodically receive a high-level signal during this period, the pulse output This can suppress malfunction of the power circuit.

[0286] (Embodiment 9) A thin film transistor is manufactured according to one embodiment of the present invention, and the thin film transistor is used in a pixel portion, In order to manufacture a semiconductor device (also called a display device) having a display function by using the driver circuit, In addition, a part or the whole of a driver circuit using thin film transistors can be mounted on the same substrate as the pixel portion. It can be integrally formed on a substrate to form a system-on-panel.

[0287] The display device includes a display element. The display element includes a liquid crystal element (also called a liquid crystal display element), a light-emitting element, A light-emitting element (also called a light-emitting display element) can be used. This category includes elements whose brightness is controlled by the light emitted from the light source, specifically inorganic EL (Electroluminescent) luminescence elements, organic EL elements, etc. Also, electronic ink A display medium whose contrast changes due to an electrical effect can also be applied.

[0288] The display device also includes a panel in which a display element is sealed, and a controller for the panel. Furthermore, the display device is manufactured by a method for manufacturing the display device. In the process, the element substrate, which corresponds to a form before the display element is completed, is used to transmit the current to the display element. The element substrate is specifically provided with a means for supplying a voltage to each of the pixels of the display element. The electrode (also called pixel electrode layer) may be formed alone, or the electrode layer may be formed by forming a layer of the electrode that will become the pixel electrode. It may be in a state after the conductive film is formed but before the pixel electrode is formed by etching. And all forms apply.

[0289] In this specification, the term "display device" refers to an image display device, a display device, or an optical device. It also refers to connectors, such as FPC (Flexible Printed Circuit) integrated circuit) or TAB (Tape Automated Bon ding) tape or TCP (Tape Carrier Package) Modules with printed wiring boards attached to the end of TAB tape or TCP or the display element is mounted on an IC (integrated circuit) by the COG (Chip On Glass) method. The display device also includes all modules in which the display device (circuit) is directly mounted.

[0290] The appearance and cross section of a liquid crystal display panel, which is one mode of a semiconductor device, will be described with reference to FIG. 10(A1) and 10(A2) show the thin film transistors 4010 and 4011 and the liquid crystal display device. The element 4013 is disposed between the first substrate 4001 and the second substrate 4006 by a sealant 4005. 10(A1) and 10(A2) are plan views of the panel sealed by the above method. Equivalent to the cross-sectional view at -N.

[0291] A pixel portion 4002 and a scanning line driver circuit 4004 are provided on a first substrate 4001. In this way, a sealing material 4005 is provided. A second substrate 4006 is provided on the path 4004. The line driver circuit 4004 is made up of a first substrate 4001, a sealing material 4005, and a second substrate 4006. The first substrate 4001 is sealed together with the liquid crystal layer 4008. In a region different from the region surrounded by the material 4005, a single crystal is formed on a separately prepared substrate. A signal line driver circuit 4003 formed of a semiconductor film or a polycrystalline semiconductor film is mounted.

[0292] The method of connecting the separately formed drive circuit is not particularly limited, and may be a COG method, Wire bonding or TAB method can be used. is an example of mounting a signal line driver circuit 4003 by the COG method, and FIG. 10(A2) is This is an example in which a signal line driver circuit 4003 is mounted by the TAB method.

[0293] A pixel portion 4002 and a scanning line driver circuit 4004 are provided on a first substrate 4001. In FIG. 10B, the thin film transistor included in the pixel portion 4002 A transistor 4010 and a thin film transistor 4011 included in the scanning line driver circuit 4004 An insulating layer 4041 and a protective insulating layer 4042 are formed on the thin film transistors 4010 and 4011. An insulating layer 4020 and an insulating layer 4021 are provided. It has a channel protection layer 4042 .

[0294] The thin film transistors 4010 and 4011 each include the oxide semiconductor layer described in any of Embodiments 1 to 4. Highly reliable thin film transistors including the thin film transistors for the driver circuits can be applied. The transistor 4011 may be the thin film transistors 460 and 499 described in any of Embodiments 1 to 4. The thin film transistor 4010 for a pixel is a combination of thin film transistors 470 and 498. In this embodiment, the thin film transistors 4010 and 401 1 is an n-channel thin film transistor.

[0295] The oxide semiconductor layer of the thin film transistor 4011 for the driver circuit is formed on the insulating layer 4021. A conductive layer 4040 is provided in a position overlapping with the channel formation region. By providing the layer at a position overlapping the channel forming region of the nitride semiconductor layer, In this case, the amount of change in the threshold voltage of the thin film transistor 4011 can be reduced. The conductive layer 4040 may have the same potential as the gate electrode layer of the thin film transistor 4011. The conductive layer may be different from the first gate electrode layer and may function as the second gate electrode layer. The potential of 4040 may be GND, 0V, or may be in a floating state.

[0296] The pixel electrode layer 4030 of the liquid crystal element 4013 is connected to the thin film transistor 4010. The counter electrode layer 4031 of the liquid crystal element 4013 is electrically connected to the second substrate 40. 06. The pixel electrode layer 4030, the counter electrode layer 4031, and the liquid crystal layer 4008 are The overlapping portion corresponds to the liquid crystal element 4013. The electrode layer 4031 is provided with insulating layers 4032 and 4033 which function as alignment films. A liquid crystal layer 4008 is sandwiched between insulating layers 4032 and 4033 .

[0297] The first substrate 4001 and the second substrate 4006 may be light-transmitting substrates. Glass, ceramics, and plastics can be used. , FRP (Fiberglass-Reinforced Plastics) board, PV F (polyvinyl fluoride) film, polyester film or acrylic resin film A room can be used.

[0298] The spacers 4035 are columnar spacers obtained by selectively etching the insulating film. and the distance (cell gap) between the pixel electrode layer 4030 and the counter electrode layer 4031 is controlled. A spherical spacer may be used. 4031 is electrically connected to a common potential line provided on the same substrate as the thin film transistor 4010. The common connection portion is used to connect the opposing electrodes via conductive particles disposed between the pair of substrates. The electrode layer 4031 can be electrically connected to a common potential line. It is contained in material 4005.

[0299] Alternatively, a liquid crystal that exhibits a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases. When the temperature of cholesteric liquid crystal is increased, the phase immediately transitions from the cholesteric phase to the isotropic phase. The blue phase appears within a relatively narrow temperature range, so it is necessary to improve the temperature range. In order to improve the liquid crystal layer 4008, a liquid crystal composition containing 5% by weight or more of a chiral agent is used. The liquid crystal composition containing the liquid crystal exhibiting the blue phase and the chiral agent has a response speed of 1 msec. It is optically isotropic, so alignment treatment is not required, and viewing angle dependency is small.

[0300] In addition to the transmissive liquid crystal display device, the present invention can also be applied to a semi-transmissive liquid crystal display device.

[0301] In addition, in a liquid crystal display device, a polarizing plate is provided on the outer side (viewing side) of the substrate, and a colored layer (color The polarizing plate is placed on the inner side of the substrate. The laminated structure of the polarizing plate and the colored layer is not limited to the present embodiment, and the polarizing plate may be provided on the The settings may be made appropriately depending on the materials of the colored layers and the manufacturing process conditions. A light-shielding film that functions as a block matrix may be provided.

[0302] In addition, a protective insulating layer 4020 is formed on the thin film transistors 4010 and 4011. Here, a silicon nitride film is formed as the protective insulating layer 4020 by an RF sputtering method. Note that the protective insulating layer 4020 is formed using a material similar to that of the protective insulating layer 453 described in Embodiment 1. It may be formed by the method.

[0303] An insulating layer 4021 is formed as a planarization insulating film. The planarization insulating layer 454 may be formed using the same material and method as the planarization insulating layer 454 shown in the first embodiment. Heat resistance of resins such as grease, polyimide, benzocyclobutene resin, polyamide, and epoxy resin. In addition to the above organic materials, low dielectric constant materials (low -k materials), siloxane resin, PSG (phosphor glass), BPSG (borophosphor glass) It is possible to use a plurality of insulating films made of these materials. Then, the insulating layer 4021 may be formed.

[0304] In this embodiment, a plurality of thin film transistors in a pixel portion are collectively surrounded by a nitride insulating film. A nitride insulating film may be used for the protective insulating layer 4020 and the gate insulating layer, as shown in FIG. As shown in the figure, a protective insulating layer is formed so as to surround at least the periphery of the pixel portion of the active matrix substrate. The structure may be such that a region where the gate insulating layer 4020 is in contact with the gate insulating layer is provided. In addition, when a semiconductor device, for example a display device, is used, the insulating film can be formed on the surface of the insulating film. This will prevent moisture from entering from the outside for a long period of time even after the device is completed. This can improve the long-term reliability of the device.

[0305] Siloxane-based resin is a Si-OS compound formed using siloxane-based materials as starting materials. The siloxane resin corresponds to a resin containing an i bond. Alternatively, an organic group having a fluoro group may be used. That's fine.

[0306] The method for forming the insulating layer 4021 is not particularly limited, and may be a sputtering method, an SOG method, or the like, depending on the material. , spin coating, dip coating, spray coating, droplet ejection method (inkjet method, screen Printing, offset printing, etc.), doctor knife, roll coater, curtain coater, etc. The insulating layer 4021 can be baked and semi-baked using a tool such as a knife coater. By also annealing the conductor layer, it becomes possible to efficiently manufacture a semiconductor device.

[0307] The pixel electrode layer 4030 and the counter electrode layer 4031 are made of indium oxide containing tungsten oxide. , indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, Indium tin oxide containing titanium oxide, indium tin oxide (hereinafter referred to as ITO), Translucent materials such as indium zinc oxide and indium tin oxide doped with silicon oxide A conductive material can be used.

[0308] The pixel electrode layer 4030 and the counter electrode layer 4031 are made of a conductive polymer (conductive polymer The conductive composition can be used to form the conductive film. The pixel electrode has a sheet resistance of 10,000 Ω / □ or less and a light transmittance of 550 nm. It is preferable that the resistance of the conductive polymer contained in the conductive composition is 70% or more. It is preferable that the electrical conductivity is 0.1 Ω·cm or less.

[0309] As the conductive polymer, a so-called π-electron conjugated conductive polymer can be used. For example, polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene or or a derivative thereof, or a copolymer of two or more of these.

[0310] A signal line driver circuit 4003 and a scanning line driver circuit 4004 or a pixel section 4 Various signals and potentials applied to 002 are supplied from FPC4018.

[0311] The connection terminal electrode 4015 is made of the same conductive film as the pixel electrode layer 4030 of the liquid crystal element 4013. The terminal electrode 4016 is formed from the source electrode layer and the drain electrode layer of the thin film transistor 4011. It is formed of the same conductive film as the gate electrode layer.

[0312] The connection terminal electrode 4015 is connected to the terminal of the FPC 4018 via the anisotropic conductive film 4019. are electrically connected.

[0313] In FIG. 10, a signal line driver circuit 4003 is formed separately and mounted on the first substrate 4001. The present invention is not limited to this configuration. Alternatively, only a part of the signal line driver circuit or a part of the scanning line driver circuit may be separately formed. It may be implemented.

[0314] FIG. 19 shows a semiconductor device using a TFT substrate 2600 fabricated by the fabrication method disclosed herein. 1 shows an example of a semiconductor device configured as a liquid crystal display module.

[0315] FIG. 19 shows an example of a liquid crystal display module, in which a TFT substrate 2600 and an opposing substrate 2601 are connected. The substrate is fixed by a bonding material 2602, and a pixel portion 2603 including a TFT and the like and a liquid crystal layer are disposed between the substrate and the bonding material 2602. A display element 2604 and a colored layer 2605 are provided to form a display area. is required for color display, and in the case of the RGB method, it corresponds to each color of red, green, and blue. A colored layer is provided corresponding to each pixel. On the outside, a polarizing plate 2606, a polarizing plate 2607, and a diffusion plate 2613 are arranged. It is composed of a cathode ray tube 2610 and a reflector 2611, and a circuit board 2612 is a flexible wiring board. The wiring board 2609 is connected to the wiring circuit section 2608 of the TFT substrate 2600, and the controller It also incorporates external circuits such as a polarizing plate and a power supply circuit. The layers may be laminated with a retardation film interposed therebetween.

[0316] The LCD module is available in TN (Twisted Nematic) mode, IPS (In-Plane Switching) mode, n-Plane-Switching mode, FFS (Fringe Field Switching) Switching mode, MVA (Multi-domain Vertical A alignment) mode, PVA(Patterned Vertical Alignment) mode nment) mode, ASM(Axially Symmetric aligned Micro-cell mode, OCB (Optically Compensated) Birefringence mode, FLC (Ferroelectric Liquid Crystal uid Crystal) mode, AFLC(AntiFerroelectric L You can use modes such as IQID Crystal.

[0317] By the above steps, a highly reliable liquid crystal display panel can be manufactured as a semiconductor device. do.

[0318] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0319] (Embodiment 10) An example of electronic paper will be shown as one mode of the semiconductor device.

[0320] Electronic paper that uses elements electrically connected to switching elements to drive electronic ink Electronic paper is also called an electrophoretic display. It is as easy to read as paper, consumes less power than other display devices, and is thin and light. This has the advantage that it is possible to

[0321] Electrophoretic displays can be of various forms, but the first particle has a positive charge. A microcapsule containing a negatively charged particle and a second particle is immersed in a solvent or solute. By applying an electric field to the microcapsules, The particles in the capsule are moved in opposite directions to each other, and only the color of the particles that have gathered on one side is displayed. The first particles or the second particles contain a dye, and in the absence of an electric field, The first particle and the second particle have different colors (colorless). (including

[0322] Thus, electrophoretic displays allow materials with high dielectric constants to migrate to areas of high electric field. This is a display that utilizes the so-called dielectrophoretic effect. No polarizers are required for the display.

[0323] The microcapsules dispersed in a solvent are called electronic ink. The electronic ink can be printed on surfaces such as glass, plastic, fabric, and paper. Color display is also possible by using color filters or particles containing pigments.

[0324] Furthermore, the microphone is appropriately placed on the active matrix substrate so as to be sandwiched between two electrodes. By arranging multiple microcapsules, an active matrix display device is completed. By applying an electric field to the cell, display can be performed. An active matrix substrate obtained by using transistors can be used.

[0325] The first particles and the second particles in the microcapsules may be made of a conductive material, an insulating material, Semiconductor materials, magnetic materials, liquid crystal materials, ferroelectric materials, electroluminescent materials, A material selected from magnetochromic materials, magnetophoretic materials, or a composite material thereof Just use it.

[0326] Figure 18 shows an active matrix electronic paper as an example of a semiconductor device. The thin film transistor 581 used in the device is the thin film transistor shown in Embodiment 1. The thin film transistor can be fabricated in the same manner as the oxide semiconductor layer, and is highly reliable. The thin film transistors shown in any of the second to fourth embodiments may also be used as the thin film transistor 581 of this embodiment. It can also be applied.

[0327] The electronic paper in Figure 18 is an example of a display device that uses the twisting ball display method. The spherical display method is an electrode layer that uses spherical particles painted in black and white as display elements. and a potential difference is applied between the first electrode layer and the second electrode layer. This is a method of displaying by controlling the orientation of spherical particles by generating a magnetic field.

[0328] The thin film transistor 581 formed on the substrate 580 is a thin film transistor of a bottom gate structure. The thin film transistor 581 is covered with an insulating film 583 that is in contact with the semiconductor layer. The source or drain electrode layer is formed by a first electrode layer 587, an insulating film 583, and an insulating layer 585. The first electrode layer 587 and the substrate 596 are in contact with each other through an opening formed in the substrate 596 and are electrically connected. Between the second electrode layer 588 formed on top are black areas 590a and white areas 590b. and a spherical particle 589 having a cavity 594 therearound that is filled with liquid. The spherical particles 589 are surrounded by a filler 595 such as a resin. 587 corresponds to the pixel electrode, and the second electrode layer 588 corresponds to the common electrode. 88 is electrically connected to a common potential line provided on the same substrate as the thin film transistor 581. The common connection portion is used to connect the second electrode layer to the second electrode layer via conductive particles disposed between the pair of substrates. 588 can be electrically connected to a common potential line.

[0329] Also, instead of the element using the twist ball, an electrophoretic element can be used. A transparent liquid, positively charged white particles, and negatively charged black particles are enclosed in a 1 mm diameter container. Microcapsules with a size of about 0 μm to 200 μm are used. The microcapsules placed between the first and second electrode layers are subjected to an electric field. When the screen is turned on, the white particles and black particles move in opposite directions, resulting in a white or black display. The display element that applies this principle is an electrophoretic display element. The device is generally called electronic paper. Electrophoretic display elements are liquid crystal display elements. Because it has a higher reflectivity than the children, auxiliary lights are not required, and it consumes less power and is dim. The display can be recognized even in a location where power is not supplied to the display. Even if the image is displayed, it is possible to retain the image once it has been displayed, so it is possible to The semiconductor device (also simply referred to as a display device or a semiconductor device equipped with a display device) was kept away from the Even if the image is not displayed correctly, it is possible to store the displayed image.

[0330] Through the above steps, electronic paper with high reliability as a semiconductor device can be manufactured. .

[0331] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0332] (Embodiment 11) An example of a light-emitting display device is shown as a semiconductor device. is shown using a light-emitting element that utilizes electroluminescence. The light-emitting element that uses the light-emitting material is classified into two types depending on whether the light-emitting material is an organic compound or an inorganic compound. Generally, the former is called an organic EL element and the latter an inorganic EL element.

[0333] In an organic EL element, electrons and holes are released from a pair of electrodes by applying a voltage to the light-emitting element. are injected into the layers containing the light-emitting organic compounds, causing a current to flow. The recombination of the electrons and holes creates an excited state in the light-emitting organic compound. The excited state is then converted to the ground state, at which point light is emitted. Such a light-emitting element is called a current-excited light-emitting element.

[0334] Inorganic EL elements are divided into dispersion-type inorganic EL elements and thin-film-type inorganic EL elements depending on the element structure. Dispersion-type inorganic EL elements have a light-emitting layer in which particles of a light-emitting material are dispersed in a binder. The emission mechanism is a donor-acceptor interaction that utilizes the donor and acceptor levels. Thin-film inorganic EL devices sandwich the light-emitting layer between dielectric layers. Furthermore, this structure is sandwiched between electrodes, and the light emission mechanism utilizes the inner-shell electron transition of metal ions. In this example, the light-emitting element is an organic EL element. do.

[0335] FIG. 12 shows an example of a pixel configuration to which digital time gray scale driving can be applied as an example of a semiconductor device. This is a diagram.

[0336] The configuration and operation of a pixel to which digital time gray scale driving can be applied will be described. The figure shows an n-channel transistor using an oxide semiconductor layer as a channel formation region in one pixel. Here is an example of using two of them.

[0337] The pixel 6400 includes a switching transistor 6401 and a light-emitting element driving transistor 6402. 402, a light emitting element 6404 and a capacitor element 6403. The gate of the gate electrode 6401 is connected to the scanning line 6406, and the first electrode (the source electrode and the drain electrode) The second electrode (one of the source and drain electrodes) is connected to a signal line 6405, and the second electrode (the other of the source and drain electrodes) is connected to a signal line 6405. The other end is connected to the gate of the light-emitting element driving transistor 6402. The transistor 6402 has a gate connected to a power supply line 6407 through a capacitor element 6403. The first electrode is connected to a power supply line 6407, and the second electrode is connected to a first electrode (pixel The second electrode of the light emitting element 6404 corresponds to the common electrode 6408. The common electrode 6408 is electrically connected to a common potential line formed on the same substrate.

[0338] A low power supply potential is set to the second electrode (common electrode 6408) of the light emitting element 6404. The low power supply potential is a low power supply potential with respect to the high power supply potential set to the power supply line 6407. Potential < High power supply potential. For example, GND, 0V, etc. are set as low power supply potential. The potential difference between the high power supply potential and the low power supply potential is applied to the light emitting element 6404. Then, in order to make the light emitting element 6404 emit light by passing a current through the light emitting element 6404, a high power supply potential and the low power supply potential is set to be equal to or greater than the forward threshold voltage of the light emitting element 6404. Each potential is set.

[0339] The capacitor element 6403 is substituted for the gate capacitance of the light-emitting element driving transistor 6402. It is possible to omit it. Regarding the gate capacitance of the light-emitting element driving transistor 6402 Alternatively, a capacitance may be formed between the channel region and the gate electrode.

[0340] In the case of a voltage input voltage driving method, the gate of the light emitting element driving transistor 6402 In the test, there are two conditions: whether the light emitting element driving transistor 6402 is fully turned on or off. In other words, the light emitting element driving transistor 6402 The light emitting element driving transistor 6402 is operated in the linear region. Therefore, a voltage higher than the voltage of the power supply line 6407 is applied to the gate of the light emitting element driving transistor 6402. The signal line 6405 is connected to the power supply line voltage + transistor for driving the light emitting element. Apply a voltage higher than the Vth of 6402.

[0341] Furthermore, when analog grayscale driving is performed instead of digital time grayscale driving, the input of the signal is different. By doing so, the same pixel configuration as in FIG. 12 can be used.

[0342] When analog gradation driving is performed, a light emitting element is connected to the gate of the light emitting element driving transistor 6402. Apply a voltage equal to or greater than the forward voltage of 6404 and the Vth of the light-emitting element driving transistor 6402. The forward voltage of the light emitting element 6404 refers to the voltage required to achieve a desired luminance. At least it is larger than the forward threshold voltage. By inputting a video signal that operates in the saturation region, a current flows in the light emitting element 6404. In order to operate the light-emitting element driving transistor 6402 in a saturation region, The potential of the power supply line 6407 is set higher than the gate potential of the light emitting element driving transistor 6402. By converting the video signal into an analog signal, a current corresponding to the video signal is supplied to the light emitting element 6404. It is possible to perform analog gradation driving.

[0343] Note that the pixel configuration shown in Fig. 12 is not limited to this. For example, A switch, a resistor, a capacitor, a transistor, a logic circuit, or the like may be added.

[0344] Next, the configuration of the light emitting element will be described with reference to FIG. The cross-sectional structure of a pixel will be described using an example in which FT is n-type. (C) TFTs 7001 and 7011 are TFTs for driving light emitting elements used in the semiconductor device The thin film transistor 7021 can be manufactured in the same manner as the thin film transistor arranged in the pixel shown in Embodiment 1. In addition, the thin film transistor according to any one of the embodiments 2 to 5 includes an oxide semiconductor layer. The thin film transistors arranged in the pixel indicated by 4 are TFTs 7001, 7011, and 7021. It can also be applied.

[0345] The light emitting element only needs to have at least one of the anode and cathode transparent in order to extract light. Then, a thin film transistor and a light emitting element are formed on the substrate, and light is taken from the surface opposite to the substrate. Top emission, bottom emission, and top emission. There are light-emitting elements with a double-sided emission structure that emits light from the side, and the pixel configuration is It can also be applied to optical elements.

[0346] A light emitting element with a top emission structure will be described with reference to FIG.

[0347] In FIG. 13A, a TFT 7001 for driving a light emitting element is an n-type TFT, and a light emitting element 700 13(A) shows a cross-sectional view of a pixel when light emitted from the cathode 2 exits to the anode 7005 side. ) is a cathode 7003 of a light emitting element 7002 and a TFT 7001 which is a TFT for driving the light emitting element. are electrically connected, and a light-emitting layer 7004 and an anode 7005 are stacked in this order on a cathode 7003. The cathode 7003 can be made of any conductive film as long as it has a small work function and reflects light. Various materials can be used. For example, Ca, Al, MgAg, AlLi, etc. are preferable. The light-emitting layer 7004 may be made up of a single layer or a plurality of layers stacked together. When it is made up of multiple layers, an electrode is placed on the cathode 7003. The electron injection layer, electron transport layer, light emitting layer, hole transport layer, and hole injection layer are laminated in this order. It is not necessary to provide all of these layers. The anode 7005 is made of a conductive material that is transparent to light. For example, indium oxide containing tungsten oxide, tungsten oxide Indium zinc oxide containing titanium oxide, indium oxide containing titanium oxide Indium tin oxide, indium tin oxide (hereinafter referred to as ITO), indium zinc oxide Alternatively, a light-transmitting conductive film such as indium tin oxide to which silicon oxide is added may be used. .

[0348] In addition, a partition wall is formed between the cathode 7003 and the cathode 7008 of the adjacent pixel, covering each end portion. The partition wall 7009 is made of polyimide, acrylic resin, polyamide, or epoxy. The partition wall 70 is formed using an organic resin film such as a resin, an inorganic insulating film, or an organic polysiloxane. 09 is made of a photosensitive resin material, and the side of the partition wall 7009 is formed with a continuous curvature. It is preferable to form the partition wall 7009 as an inclined surface. When the material is used, the step of forming a resist mask can be omitted.

[0349] The region where the light-emitting layer 7004 is sandwiched between the cathode 7003 and the anode 7005 is the light-emitting element 7002. In the case of the pixel shown in FIG. 13(A), the light emitted from the light emitting element 7002 is The light is emitted toward the anode 7005 as shown by the mark.

[0350] Next, a light emitting element with a bottom emission structure will be described with reference to FIG. The TFT 7011 is n-type, and light emitted from the light-emitting element 7012 is emitted to the cathode 7013 side. FIG. 13(B) shows a cross-sectional view of a pixel in the case where a light-emitting element driving TFT 7011 and a The cathode 7013 of the light-emitting element 7012 is formed on the electrically conductive film 7017 having light-transmitting properties. A light-emitting layer 7014 and an anode 7015 are laminated in this order on the cathode 7013. In addition, when the anode 7015 is light-transmitting, a light-reflecting or light-blocking layer is provided so as to cover the anode. A shielding film 7016 for shielding may be formed on the cathode 7013. As in the case of the first embodiment, various conductive materials with small work functions can be used. However, the film thickness should be such that light can pass through (preferably about 5 nm to 30 nm). For example, an aluminum film having a thickness of 20 nm can be used as the cathode 7013. The light-emitting layer 7014 may be composed of a single layer or a plurality of layers, as in FIG. The anode 7015 is a light-transmitting layer. Although not necessary, the insulating film 11 may be formed using a light-transmitting conductive material as in FIG. 13(A). The shielding film 7016 can be made of, for example, a metal that reflects light. The material is not limited to a metal film, and for example, a resin to which a black pigment is added may also be used.

[0351] In addition, a conductive film 7017 and a conductive film 7018 of an adjacent pixel are provided between the conductive film 7017 and the conductive film 7018 of an adjacent pixel, covering the respective edges. A partition wall 7019 is provided. The partition wall 7019 is made of polyimide, acrylic resin, polyamide, epoxy, or the like. The partition wall is formed using an organic resin film such as an acrylic resin film, an inorganic insulating film, or an organic polysiloxane. 7019 is made of a photosensitive resin material, and the side of the partition wall 7019 has a continuous curvature. It is preferable to form the partition wall 7019 so that the inclined surface is formed. When a resin material is used, the step of forming a resist mask can be omitted.

[0352] The region where the light-emitting layer 7014 is sandwiched between the cathode 7013 and the anode 7015 is the light-emitting element 7012. In the case of the pixel shown in FIG. 13B, light emitted from the light-emitting element 7012 corresponds to The light is emitted toward the cathode 7013 as shown by the arrow.

[0353] Next, a light emitting element with a dual emission structure will be described with reference to FIG. In the example, a light-transmitting conductive film 702 electrically connected to a light-emitting element driving TFT 7021 is A cathode 7023 of the light-emitting element 7022 is formed on the cathode 7023. 7024 and an anode 7025 are laminated in this order. The cathode 7023 is the same as in FIG. Similarly, various conductive materials with small work functions can be used. The thickness of the cathode 702 is set to a level that allows light to pass through. For example, Al having a thickness of 20 nm is used as the cathode 702. 3. The light-emitting layer 7024 can be formed as a single It may be configured as a layer or as a laminate of multiple layers. The anode 7025 is made of a light-transmitting conductive material, similar to that shown in FIG. 13(A). It can be formed by

[0354] In addition, a conductive film 7027 and a conductive film 7028 of an adjacent pixel are provided between the conductive film 7027 and the conductive film 7028 of an adjacent pixel, covering the respective edges. A partition wall 7029 is provided. The partition wall 7029 is made of polyimide, acrylic resin, polyamide, epoxy, or the like. The partition wall is formed using an organic resin film such as an acrylic resin film, an inorganic insulating film, or an organic polysiloxane. 7029 is made of a photosensitive resin material, and the side of the partition wall 7029 has a continuous curvature. It is preferable to form the partition wall 7029 so that the inclined surface is formed. When a resin material is used, the step of forming a resist mask can be omitted.

[0355] The overlapping portion of the cathode 7023, the light-emitting layer 7024, and the anode 7025 is the light-emitting element 70. In the case of the pixel shown in FIG. 13C, the light emitted from the light emitting element 7022 is emitted to both the anode 7025 side and the cathode 7023 side as shown by the arrows.

[0356] Although organic EL elements have been described as light-emitting elements here, inorganic EL elements can also be used as light-emitting elements. It is also possible to provide an L element.

[0357] In addition, a thin film transistor (TFT for driving light-emitting elements) that controls the driving of light-emitting elements and a light-emitting element However, if a current flows between the light-emitting element driving TFT and the light-emitting element, A control TFT may be connected.

[0358] The semiconductor device is not limited to the configuration shown in FIG. 13, and may be any of the semiconductor devices disclosed in this specification. Various modifications based on the technical concept are possible.

[0359] Next, the appearance and structure of a light-emitting display panel (also referred to as a light-emitting panel), which is one mode of a semiconductor device, will be described. The cross section will be explained with reference to FIG. 11. FIG. 11(A) shows a thin film formed on a first substrate. A panel in which a film transistor and a light-emitting element are sealed between a second substrate and the panel by a sealant. 11(B) is a plan view of the device, and FIG. 11(B) corresponds to a cross-sectional view taken along line HI in FIG. 11(A).

[0360] A pixel portion 4502, a signal line driver circuit 4503a, and a signal line driver circuit 4504 are provided on a first substrate 4501. 3b and the scanning line driver circuits 4504a and 4504b. In addition, a pixel portion 4502, signal line driver circuits 4503a and 4503b, and A second substrate 4506 is provided on the scanning line driver circuits 4504a and 4504b. The pixel portion 4502, the signal line driver circuits 4503a and 4503b, and the scanning line driver circuit 45 4504a and 4504b are a first substrate 4501, a sealing material 4505, and a second substrate 4506. The seal is sealed together with the filler 4507 by the sealant. Highly airtight protective film with little outgassing (lamination film, UV curable resin film) It is preferable to package (enclose) the product in a protective film (such as a film) or a cover material.

[0361] A pixel portion 4502, a signal line driver circuit 4503a, and a fourth 503b and the scanning line driver circuits 4504a and 4504b have a plurality of thin film transistors. In FIG. 11B, a thin film transistor 4510 included in a pixel portion 4502 and a signal 45 shows an example of a thin film transistor 4509 included in a line driver circuit 4503a.

[0362] The thin film transistors 4509 and 4510 each include the oxide semiconductor layer described in any of Embodiments 1 to 4. A highly reliable thin film transistor including a thin film transistor disposed in a driving circuit can be applied. The transistor 4509 can be the thin film transistor 460 described in any of Embodiments 1 to 4. 499, as a thin film transistor 4510 arranged in a pixel, a thin film transistor 470 , 498 can be used in combination. 4509 and 4510 are n-channel thin film transistors.

[0363] The oxide semiconductor layer of the thin film transistor 4509 for the driver circuit is formed over the insulating layer 4544. A conductive layer 4540 is provided in a position overlapping the channel forming region. By placing the gate electrode at a position overlapping the channel formation region of the semiconductor layer, the The amount of change in the threshold voltage of the thin film transistor 4509 can be reduced. The potential of the gate electrode layer 4540 may be the same as that of the gate electrode layer of the thin film transistor 4509 or may be different. The conductive layer 4 may be formed of a metal or a silicon dioxide film, and may function as a second gate electrode layer. The potential of 540 may be GND, 0V, or may be in a floating state.

[0364] In addition, an insulating layer 4543 is formed over the thin film transistors 4509 and 4510 . Here, a silicon nitride film is formed by RF sputtering as the insulating layer 4543. The insulating layer 4543 is formed using a material and a method similar to those of the protective insulating layer 453 described in Embodiment 1. That's fine.

[0365] An insulating layer 4544 is formed as a planarization insulating film. The planarization insulating layer 454 may be formed using a material and a method similar to those of the planarization insulating layer 454 described in Mode 1. Acrylic is used as the insulating layer 4544 .

[0366] In this embodiment, a plurality of thin film transistors in a pixel portion are collectively surrounded by a nitride insulating film. The insulating layer 4543 and the gate insulating layer may be formed using a nitride insulating film. In order to achieve this, an insulating layer 4543 is formed so as to surround at least the periphery of the pixel portion of the active matrix substrate. In this manufacturing process, an area where the external insulating layer is in contact with the gate insulating layer is provided. In addition, when a semiconductor device, for example, a device as a display device, is used, the device can be prevented from entering moisture. This prevents moisture from entering from the outside for a long period of time even after the device is completed, ensuring long-term reliability of the device. This can improve reliability.

[0367] Further, 4511 corresponds to a light-emitting element, and a first electrode which is a pixel electrode of the light-emitting element 4511 The layer 4517 is electrically connected to the source electrode layer or the drain electrode layer of the thin film transistor 4510. The light-emitting element 4511 is configured by a first electrode layer 4517, an electroluminescent layer The light emitting element 4512 and the second electrode layer 4513 are stacked together, but the structure is not limited to the one shown. The configuration of the light emitting element 4511 can be changed appropriately according to the direction of the light extracted from the element 4511. It is possible.

[0368] The partition wall 4520 is formed using an organic resin film, an inorganic insulating film, or organic polysiloxane. In particular, a photosensitive material is used to form an opening on the first electrode layer 4517, and the sidewall of the opening It is preferable to form the inclined surface so that the inclined surface has a continuous curvature.

[0369] The electroluminescent layer 4512 may be composed of a single layer or a plurality of layers stacked. It doesn't matter whether it's done or not.

[0370] The second electrode layer is formed to prevent oxygen, hydrogen, moisture, carbon dioxide, and the like from entering the light-emitting element 4511. A protective film may be formed on the partition wall 4513 and the partition wall 4520. The protective film may be a silicon nitride film, A silicon nitride oxide film, a DLC film, or the like can be formed.

[0371] In addition, signal line driver circuits 4503a and 4503b, scanning line driver circuits 4504a and 4504b Various signals and potentials applied to the pixel portion 4502 are transmitted through the FPC 4518a, 4518b, and It is supplied by b.

[0372] The connection terminal electrode 4515 is formed of the same conductive film as the first electrode layer 4517 of the light-emitting element 4511. The terminal electrode 4516 is formed from a source electrode layer and a The drain electrode layer is formed from the same conductive film as the drain electrode layer.

[0373] The connection terminal electrode 4515 is connected to the terminal of the FPC 4518a via the anisotropic conductive film 4519. are electrically connected to each other.

[0374] The second substrate is not transparent to light, and is positioned in the direction of light extraction from the light emitting element 4511. In this case, glass plates, plastic plates, polyester films or A light-transmitting material such as an acrylic film is used.

[0375] In addition to inert gases such as nitrogen and argon, filler 4507 can also be used as UV-curable resin. It can be made of PVC (polyvinyl chloride), acrylic resin or thermosetting resin. Oil, polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral) or EVA (ethylene and vinyl acetate copolymer) can be used. Nitrogen may be used as the material.

[0376] If necessary, a polarizing plate or a circular polarizing plate (including an elliptical polarizing plate) may be provided on the light-emitting surface of the light-emitting element. Optical films such as retardation plates (λ / 4 plates, λ / 2 plates) and color filters may be provided as appropriate. In addition, an anti-reflection film may be provided on the polarizing plate or the circular polarizing plate. Anti-glare treatment can be applied to diffuse reflected light and reduce glare.

[0377] The signal line driver circuits 4503a and 4503b and the scanning line driver circuits 4504a and 4504b are A driving circuit formed of a single crystal semiconductor film or a polycrystalline semiconductor film on a separately prepared substrate is Alternatively, only the signal line driver circuit, or a part of the signal line driver circuit, or the scanning line driver circuit may be mounted. Only the path or only a part of the path may be separately formed and mounted, and the configuration is not limited to that of FIG.

[0378] Through the above steps, a highly reliable light-emitting display device (display panel) can be manufactured as a semiconductor device. It is possible.

[0379] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0380] (Embodiment 12) The semiconductor device disclosed in this specification can be applied as electronic paper. Par can be used in any electronic device that displays information. For example, electronic paper can be used for electronic books, posters, trains, etc. It can be used for in-car advertising, displaying on various cards such as credit cards, etc. An example of an electronic device is shown in Figure 20.

[0381] 20 shows an electronic book 2700. For example, the electronic book 2700 includes a housing 2701 The housing 2701 and the housing 2703 are The shaft 2711 is an integral part of the opening and closing operation. This configuration makes it possible to operate like a paper book.

[0382] A display unit 2705 is incorporated in the housing 2701, and a display unit 2707 is incorporated in the housing 2703. The display unit 2705 and the display unit 2707 are configured to display a continuous screen. Alternatively, a different screen may be displayed. For example, a sentence is displayed on the right display unit (display unit 2705 in FIG. 20) and An image can be displayed on the display unit 2707 in FIG.

[0383] 20 shows an example in which the housing 2701 is provided with an operation unit. 701 includes a power supply 2721, operation keys 2723, a speaker 2725, etc. The operation keys 2723 can be used to turn pages. It may also be configured to include a board, a pointing device, etc. On the side, there are external connection terminals (earphone terminal, USB terminal, or AC adapter and USB A configuration including a terminal that can be connected to various cables, a recording medium insertion section, etc. Furthermore, the electronic book 2700 may be configured to have the function of an electronic dictionary. That's fine.

[0384] The electronic book 2700 may also be configured to be able to send and receive information wirelessly. The desired book data can be purchased and downloaded from the e-book server. is also possible.

[0385] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0386] (Embodiment 13) The semiconductor device disclosed in this specification can be applied to various electronic devices (including gaming machines). The electronic device can be, for example, a television device (television or television receivers), computer monitors, digital cameras, digital video cameras cameras, digital photo frames, mobile phones (also known as mobile phones or mobile phone devices), (c), portable game machines, personal digital assistants, audio playback devices, large game machines such as pachinko machines, etc. Examples include:

[0387] FIG. 21(A) shows a television device 9600. The television device 9600 A display portion 9603 is incorporated in the housing 9601. The display portion 9603 displays images. In addition, the housing 9601 is supported by a stand 9605. This shows the configuration.

[0388] The television device 9600 can be operated using an operation switch on the housing 9601 or a separate remote control. This can be done by the remote control operation device 9610. The channel and volume can be controlled by the 9609, and the information displayed on the display 9603 is In addition, the remote control operation device 9610 can operate the video. A display unit 9607 for displaying information output from 9610 may be provided.

[0389] The television device 9600 is configured to include a receiver, a modem, and the like. It can receive more general TV broadcasts and can also receive them via wired or wireless modems. By connecting to a communication network, it can be one-way (sender to receiver) or two-way. It is also possible to communicate information (between a sender and a receiver, or between receivers).

[0390] FIG. 21(B) shows a digital photo frame 9700. For example, The display frame 9700 has a display unit 9703 built into a housing 9701. 03 can display various images, such as images taken with a digital camera. By displaying image data, it can function like a regular photo frame.

[0391] The Digital Photo Frame 9700 has an operation panel, external connection terminals (USB terminal, US A terminal that can be connected to various cables such as B cable, etc., and a recording medium insertion section. These components may be incorporated on the same surface as the display unit, but they may be incorporated on the side or back. It is desirable to have it because it improves the design. For example, the Digital Photo Frame 9700 Insert a memory that stores image data taken with a digital camera into the recording medium insertion section of the Image data can be captured and displayed on the display unit 9703. do.

[0392] The digital photo frame 9700 may also be configured to be capable of transmitting and receiving information wirelessly. It is also possible to configure the device so that desired image data is wirelessly acquired and displayed.

[0393] FIG. 22(A) shows a portable gaming machine, which is composed of two cabinets, a cabinet 9881 and a cabinet 9891. The housing 9881 is connected to a connector 9893 so as to be openable and closable. A display unit 9883 is incorporated in the housing 9891. The portable gaming machine shown in 22(A) also includes a speaker unit 9884, a recording medium insertion unit 988 6, LED lamp 9890, input means (operation key 9885, connection terminal 9887, sensor 9 888 (force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, Chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration (including functions for measuring movement, smell, or infrared rays), microphone 9889) Of course, the configuration of the portable gaming machine is not limited to the above, and It is sufficient if the semiconductor device disclosed in the above is included, and other auxiliary equipment is appropriately provided. The portable gaming machine shown in FIG. 22(A) can be The function of reading out programs or data and displaying them on the display, and wireless communication with other portable gaming machines The portable gaming machine shown in FIG. 22(A) has the function of sharing information by performing the above. The functions are not limited to these, and various functions can be provided.

[0394] FIG. 22(B) shows a slot machine 9900, which is a large gaming machine. 9900 has a display unit 9903 built into a housing 9901. The 9900 also has other controls such as a start lever and stop switch, and a coin slot. , speakers, etc. Of course, the configuration of the slot machine 9900 is the same as that described above. There is no limitation, and it is sufficient that the configuration includes at least the semiconductor device disclosed in this specification. Other auxiliary equipment may be provided as appropriate.

[0395] FIG. 23A is a perspective view showing an example of a portable computer.

[0396] The portable computer of FIG. 23(A) has an upper housing 9301 and a lower housing 9302 connected to each other. The hinge unit is closed to form an upper housing 9301 having a display portion 9303 and a keyboard. The lower housing 9302 having the card 9304 can be stacked on top of each other, making it easy to carry. This is convenient, and when the user wants to input data on the keyboard, the hinge unit can be opened. The user can perform input operations by looking at the display portion 9303.

[0397] The lower housing 9302 also includes a keyboard 9304 and a pointing device for inputting data. If the display portion 9303 is a touch input panel, Input operations can be performed by touching the lower housing 9302. The lower housing 9302 has a computing function unit such as a hard disk. It has an external connection port 9305 into which a communication cable conforming to the SB communication standard is inserted. There are.

[0398] The upper housing 9301 further includes a display unit 93 that can be slid into the upper housing 9301 and stored therein. 07, which allows for a wide display screen. The orientation of the screen of the 9307 can be adjusted by the user. If it is a panel, input operations can be performed by touching a part of the retractable display section.

[0399] The display portion 9303 or the storable display portion 9307 may be a liquid crystal display panel, an organic light emitting element, or The display device uses a light-emitting display panel made of inorganic light-emitting elements.

[0400] The portable computer shown in FIG. 23(A) is configured with a receiver and the like, and is also used for television broadcasting. It is possible to receive broadcasts and display the images on the display unit or the display unit. The hinge unit connecting the display unit 9301 and the lower housing 9302 is closed. Slide the 7 to expose the entire screen, and adjust the screen angle to watch TV. In this case, the hinge unit can be opened to display the display portion 9303. Furthermore, it only activates the circuitry that displays the TV broadcast, so it consumes minimal power. This is useful for portable computers with limited battery capacity. do.

[0401] FIG. 23(B) shows a portable telephone that can be worn on the user's arm like a wristwatch. FIG. 10 is a perspective view showing an example of a story.

[0402] This mobile phone includes a main body having at least a communication device with a telephone function and a battery, A band part 9204 for attaching the body to the arm, and a fastening state of the band part 9204 to the arm are adjusted. The device is composed of an adjustment unit 9205, a display unit 9201, a speaker 9207, and a microphone 9208. It has been completed.

[0403] The main body also has an operation switch 9203, which is used for power input and display switching. In addition to the switch and the switch to start shooting, for example, when you press a button, a program for the Internet Each function can be associated with another function, such as being started.

[0404] Input operations of this mobile phone are performed by touching the display portion 9201 with a finger or an input pen, or by operating the display portion 9201. This is done by operating a switch 9203 or by inputting voice into a microphone 9208. 23(B) shows a display button 9202 displayed on a display unit 9201, and Input can be made by touching the screen.

[0405] The main body also contains an imaging device that converts the subject image formed through the photographic lens into an electronic image signal. It has a camera unit 9206 with a step. Note that it is not necessary to provide a camera unit.

[0406] The mobile phone shown in FIG. 23(B) is configured with a television broadcast receiver and the like. It can receive TV broadcasts and display the images on the display unit 9201, and can also store data in memory etc. It is possible to record television broadcasts in memory by using a storage device. The mobile phone shown in B) may have a function capable of collecting location information such as GPS.

[0407] The display unit 9201 is a light-emitting display panel such as a liquid crystal display panel, an organic light-emitting element, or an inorganic light-emitting element. The mobile phone shown in Figure 23(B) is small and lightweight. Therefore, the battery capacity is limited, and the display device used for the display portion 9201 is a low-power display device. It is preferable to use a force-actuable panel.

[0408] Although FIG. 23B illustrates an electronic device that is worn on the arm, it is not limited to this. It is sufficient that the device has a portable shape.

[0409] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0410] (Embodiment 14) In this embodiment mode, the thin film transistor shown in any of Embodiments 1 to 4 is used as one mode of a semiconductor device. An example of a display device having a display will be described with reference to FIGS. An example of a liquid crystal display device using a liquid crystal element as an element will be described with reference to FIGS. 24 to 37. The TFTs 628 and 629 used in the liquid crystal display devices of FIGS. 24 to 37 are the same as those of the first to third embodiments. The thin film transistor shown in FIG. 4 can be applied to the thin film transistor shown in FIG. The TFT628 is a thin film transistor with excellent electrical properties and high reliability that can be easily fabricated. The TFT 629 has a channel protection layer 611, and the TFT 629 has an oxide semiconductor This is an inverted staggered thin film transistor in which the layer serves as a channel forming region.

[0411] First, we will explain the VA (Vertical Alignment) type liquid crystal display device. VA type is a type of method for controlling the arrangement of liquid crystal molecules in an LCD panel. In a liquid crystal display device, when no voltage is applied, the liquid crystal molecules are oriented perpendicular to the panel surface. In this embodiment, a pixel is divided into several regions (sub-pixels). The liquid crystal molecules are tilted in different directions in each cell. In the following explanation, multi-domain design is considered. A liquid crystal display device that takes this into consideration will now be described.

[0412] 25 and 26 show the pixel electrode and the counter electrode, respectively. 1 is a plan view of a substrate on which electrodes are formed, showing a cross-sectional structure corresponding to a cutting line EF shown in the figure. 24. Also, FIG. 26 is a plan view of the substrate side on which the counter electrode is formed. The following description will be given with reference to these figures.

[0413] FIG. 24 shows a TFT 628, a pixel electrode layer 624 connected thereto, and a storage capacitor 630. The substrate 600 on which the counter electrode layer 640 and the like are formed is superimposed on the counter substrate 601. The figure shows the state in which the liquid crystal is injected.

[0414] A colored film 636 and a counter electrode layer 640 are formed on the counter substrate 601. An alignment film 648 is formed on the pixel electrode layer 624. An alignment film 646 is also formed on the counter electrode layer 640 and the protrusions 644. A liquid crystal layer 650 is formed between opposing substrates 601 .

[0415] On the substrate 600, a TFT 628, a pixel electrode layer 624 connected thereto, and a storage capacitor 6 The pixel electrode layer 624 includes a TFT 628, a wiring 616, and a storage capacitor 6 The insulating film 620 covering the insulating film 620 and the insulating film 622 covering the insulating film 620 are formed by contacts. The TFT 628 is connected to the wiring 618 through a hole 623. The storage capacitor 630 can be formed by using a thin film transistor (TFT) 628. The first capacitor wiring 604 formed at the same time as the gate wiring 602, the gate insulating film 606, and the wiring It is composed of a second capacitance wiring 617 formed at the same time as the wirings 616 and 618 .

[0416] The pixel electrode layer 624, the liquid crystal layer 650, and the counter electrode layer 640 are overlapped to form a liquid crystal element. It has been completed.

[0417] 25 shows a planar structure on a substrate 600. The pixel electrode layer 624 is made of the material shown in Embodiment 1. The pixel electrode layer 624 is formed using a slit 625. The slit 625 is formed by This is to control the crystal orientation.

[0418] The TFT 629 shown in FIG. 25 and the pixel electrode layer 626 and storage capacitor 631 connected thereto are The TFT 628, the pixel electrode layer 624, and the storage capacitor 630 can be formed in the same manner. Both the TFT 628 and the TFT 629 are connected to the wiring 616. The pixel of the panel is composed of pixel electrode layer 624 and pixel electrode layer 626. The pixel electrode layer 624 and the pixel electrode layer 626 are sub-pixels.

[0419] 26 shows the planar structure of the opposing substrate side. An opposing electrode layer 640 is formed on a light-shielding film 632. The counter electrode layer 640 is preferably formed using the same material as the pixel electrode layer 624. On the counter electrode layer 640, protrusions 644 are formed to control the alignment of the liquid crystal.

[0420] The equivalent circuit of this pixel structure is shown in Figure 27. Both TFT628 and TFT629 have gate electrodes. The line 602 is connected to the wiring 616. In this case, the capacitance wiring 604 and the capacitance wiring 605 are connected to each other. By making the positions different, the liquid crystal elements 651 and 652 can be made to operate differently. That is, by individually controlling the potentials of the capacitance wiring 604 and the capacitance wiring 605, the liquid crystal The orientation of the liquid crystal is precisely controlled to widen the viewing angle.

[0421] When a voltage is applied to the pixel electrode layer 624 in which the slit 625 is provided, a The slit 625 and the protrusion on the opposing substrate 601 side cause distortion of the electric field (oblique electric field). By arranging the 644 in an alternating interdigitated pattern, a diagonal electric field is effectively generated, By controlling the orientation, the direction in which the liquid crystal is oriented varies depending on the location. The multi-domain technology widens the viewing angle of the LCD panel.

[0422] Next, a VA type liquid crystal display device different from the above will be described with reference to FIGS. 28 to 31. do.

[0423] 28 and 29 show the pixel structure of a VA type liquid crystal display panel. FIG. 28 shows a cross-sectional structure corresponding to the cutting line YZ shown in the figure. The following description will refer to both figures.

[0424] This pixel structure has multiple pixel electrodes in one pixel, and a TFT is connected to each pixel electrode. Each TFT is configured to be driven by a different gate signal. In other words, in a pixel with a multi-domain design, the signals applied to each pixel electrode are independently The system has a configuration for controlling the temperature.

[0425] The pixel electrode layer 624 is formed by contact holes passing through the insulating film 620 and the insulating film 622. In the filter 623, the wiring 618 is connected to the TFT 628. In the contact hole 627 that penetrates the insulating film 620 and the insulating film 622, , and is connected to the TFT 629 by a wiring 619. The gate wiring 603 of T629 is separated so that different gate signals can be applied. On the other hand, the wiring 616 functioning as a data line is formed by the TFT 628 and the TFT 629. The TFT 628 and the TFT 629 are the thin film transistors shown in the first to fourth embodiments. A transistor can be used as appropriate. In addition, a capacitance wiring 690 is provided. A gate insulating film 606 is formed on the gate wiring 602, the gate wiring 603 and the capacitance wiring 690. It has been completed.

[0426] The pixel electrode layer 624 and the pixel electrode layer 626 have different shapes, and the pixel electrode layer 624 and the pixel electrode layer 626 are V-shaped. A pixel electrode layer 626 is formed so as to surround the outside of the pixel electrode layer 624. The timing of applying a voltage to the electrode layer 626 is varied by the TFT 628 and the TFT 629. The liquid crystal orientation is controlled by changing the pixel structure. The equivalent circuit of this pixel structure is shown in Figure 31. The TFT 628 is connected to the gate wiring 602, and the TFT 629 is connected to the gate wiring 603. In addition, both the TFT 628 and the TFT 629 are connected to the wiring 616. By applying different gate signals to the gate wiring 602 and the gate wiring 603, the liquid crystal element 651 and the liquid crystal element That is, the operation of the TFT 628 and the operation of the TFT 629 can be made different. By individually controlling the operation of the liquid crystals, the liquid crystal orientation of the liquid crystal element 651 and the liquid crystal element 652 can be precisely adjusted. It can be controlled to widen the viewing angle.

[0427] A colored film 636 and a counter electrode layer 640 are formed on the counter substrate 601. A flattening film 637 is formed between the electrode layer 636 and the counter electrode layer 640 to prevent the alignment of the liquid crystal from being disturbed. FIG. 30 shows the planar structure of the opposing substrate side. The opposing electrode layer 640 is common to different pixels. The electrode is made of a metal, and a slit 641 is formed in it. The slits 625 on the element electrode layer 624 and pixel electrode layer 626 sides are arranged so as to interdigitate with each other. By doing so, it is possible to effectively generate an oblique electric field and control the alignment of the liquid crystal. This allows the orientation direction of the liquid crystal to vary depending on the location, thereby widening the viewing angle.

[0428] An alignment film 648 is formed on the pixel electrode layer 624 and the pixel electrode layer 626. An alignment film 646 is also formed on the layer 640. The liquid crystal layer 640 is disposed between the substrate 600 and the counter substrate 601. The pixel electrode layer 624, the liquid crystal layer 650, and the counter electrode layer 640 are formed. The pixel electrode layer 626 and the liquid crystal layer 627 are overlapped with each other to form a first liquid crystal element. The layer 650 and the counter electrode layer 640 overlap each other to form a second liquid crystal element. The pixel structure of the display panel shown in FIGS. 28 to 31 has a first liquid crystal element and a second liquid crystal element in one pixel. It has a multi-domain structure with multiple subdomains.

[0429] Next, we will explain about the in-plane switching type liquid crystal display device. In the in-plane switching type, the liquid crystal molecules in the cell This method applies an electric field in the horizontal direction to drive the liquid crystal and express gradation. If this is done, the viewing angle can be widened to approximately 180 degrees. The liquid crystal display device used will be described below.

[0430] FIG. 32 shows a structure in which an electrode layer 607, a TFT 628, and a pixel electrode layer 624 connected to the TFT 628 are formed. The figure shows a state in which the substrate 600 and the opposing substrate 601 are overlapped and liquid crystal is injected. On the counter substrate 601, a colored film 636, a flattening film 637, etc. are formed. No counter electrode layer is provided on the counter substrate 601 side. A liquid crystal layer 650 is formed between them via an alignment film 646 and an alignment film 648 .

[0431] On the substrate 600, an electrode layer 607, a capacitance wiring 604 connected to the electrode layer 607, and a T The capacitor wiring 604 is formed at the same time as the gate wiring 602 of the TFT 628. The TFT 628 can be formed by using the thin film transistor shown in any of the first to fifth embodiments. The electrode layer 607 can be formed by using the same material as the pixel electrode layer 4 shown in any of Embodiments 1 to 4. The electrode layer 607 can be made of the same material as that of the pixel electrode 27. The gate insulating film 606 is formed on the electrode layer 607 and the capacitor wiring 604. is formed.

[0432] The wiring 616 and wiring 618 of the TFT 628 are formed on the gate insulating film 606. 6 is a data line that carries a video signal in the liquid crystal display panel and is a wiring that extends in one direction. At the same time, the source and drain regions of the TFT 628 are connected. The wiring 618 serves as the other electrode of the source and drain, and the pixel electrode layer This is the wiring that connects to 624.

[0433] An insulating film 620 is formed on the wiring 616 and the wiring 618. A contact hole 623 formed in the insulating film 620 is used to connect a pixel electrode to the wiring 618. The pixel electrode layer 624 is formed in the same manner as the pixel electrode layer 427 described in Embodiment 1. It is formed using the same material.

[0434] In this manner, the TFT 628 and the pixel electrode layer 624 connected thereto are formed on the substrate 600. The storage capacitor is formed between the electrode layer 607 and the pixel electrode layer 624.

[0435] 33 is a plan view showing the configuration of a pixel electrode. The surface structure is shown in Figure 32. A slit 625 is provided in the pixel electrode layer 624. The liquid crystal layer 625 is for controlling the orientation of the liquid crystal. In this case, the electric field is applied to the electrode layer 607. The gate insulating layer 607 is located between the pixel electrode layer 624 and the pixel electrode layer 624. The thickness of the gate insulating film 606 is 50 to 200 nm. Since the thickness is sufficiently small compared to the thickness of the liquid crystal layer, which is about 10 μm, the thickness is substantially parallel to the substrate 600. An electric field is generated in the horizontal direction. This electric field controls the orientation of the liquid crystal. The liquid crystal molecules are rotated horizontally using an electric field in a nearly parallel direction. Since the display is horizontal even in this state, the influence of the viewing angle on contrast is minimal, and the viewing angle is wide. In addition, since both the electrode layer 607 and the pixel electrode layer 624 are light-transmitting electrodes, , the aperture ratio can be improved.

[0436] Next, another example of a liquid crystal display device of the lateral electric field type will be described.

[0437] Figures 34 and 35 show the pixel structure of an IPS type liquid crystal display device. Figure 35 is a plan view. The cross-sectional structure corresponding to the cutting line VW shown in the figure is shown in FIG. The following description will be made with reference to these two figures.

[0438] FIG. 34 shows a substrate 600 on which a TFT 628 and a pixel electrode layer 624 connected thereto are formed, The opposing substrate 601 is overlaid and liquid crystal is injected. A coloring film 636, a flattening film 637, etc. are formed on the opposing substrate 601 side. An alignment film 646 and an alignment film 647 are provided between the substrate 600 and the counter substrate 601. A liquid crystal layer 650 is formed via 48 .

[0439] A common potential line 609 and a TFT 628 are formed on the substrate 600. 9 can be formed simultaneously with the gate wiring 602 of the TFT 628. The thin film transistors described in any of Embodiments 1 to 4 can be applied to this.

[0440] The wiring 616 and wiring 618 of the TFT 628 are formed on the gate insulating film 606. 6 is a data line that carries a video signal in the liquid crystal display panel and is a wiring that extends in one direction. At the same time, the source and drain regions of the TFT 628 are connected. The wiring 618 serves as the other electrode of the source and drain, and the pixel electrode layer This is the wiring that connects to 624.

[0441] An insulating film 620 is formed on the wiring 616 and the wiring 618. A contact hole 623 formed in the insulating film 620 is used to connect a pixel electrode to the wiring 618. The pixel electrode layer 624 is formed in the same manner as the pixel electrodes shown in the first to fourth embodiments. As shown in FIG. 35, the pixel electrode layer 624 is formed of a common potential The wire 609 is formed so as to generate a horizontal electric field together with the comb-shaped electrode formed at the same time. The comb-tooth portion of the electrode layer 624 alternately interdigitates with the comb-shaped electrode formed at the same time as the common potential line 609. formed to fit.

[0442] When an electric field is generated between the potential applied to the pixel electrode layer 624 and the potential of the common potential line 609, The orientation of the liquid crystal is controlled by this electric field. The molecules are rotated horizontally. In this case, the liquid crystal molecules are horizontal in any state, so the viewing angle This has little effect on contrast and results in a wider viewing angle.

[0443] In this manner, the TFT 628 and the pixel electrode layer 624 connected thereto are formed on the substrate 600. The storage capacitor is formed by providing a gate insulating film 606 between a common potential line 609 and a capacitor electrode 615. The capacitor electrode 615 and the pixel electrode layer 624 are formed through the contact hole 63. It is connected via 3.

[0444] Next, the configuration of a TN type liquid crystal display device will be described.

[0445] Figures 36 and 37 show the pixel structure of a TN type liquid crystal display device. Figure 37 is a plan view. The cross-sectional structure corresponding to the cutting line KL shown in the figure is shown in FIG. The following description will be made with reference to these two figures.

[0446] The pixel electrode layer 624 is connected to the TFT 628 through the wiring 618 in the contact hole 623. The wiring 616 functioning as a data line is connected to the TFT 628. Any of the TFTs described in Embodiments 1 to 4 can be used as the TFT 628 .

[0447] The pixel electrode layer 624 is formed using a structure similar to that of the pixel electrode described in any of Embodiments 1 to 4. The wiring 604 can be formed simultaneously with the gate wiring 602 of the TFT 628. A gate insulating film 606 is formed on the gate wiring 602 and the capacitor wiring 604. The capacitance is formed between the capacitance wiring 604 and the capacitance electrode 615 via the gate insulating film 606. The capacitor electrode 615 and the pixel electrode layer 624 are connected via a contact hole 633. .

[0448] A colored film 636 and a counter electrode layer 640 are formed on the counter substrate 601. A flattening film 637 is formed between the electrode layer 636 and the counter electrode layer 640 to prevent the alignment of the liquid crystal from being disturbed. The liquid crystal layer 650 is provided between the pixel electrode layer 624 and the counter electrode layer 640 with an alignment film 648 and an alignment layer 648. It is formed through a membrane 646 .

[0449] The pixel electrode layer 624, the liquid crystal layer 650, and the counter electrode layer 640 are overlapped to form a liquid crystal element. It has been completed.

[0450] The colored film 636 may be formed on the substrate 600 side. A polarizing plate is attached to the surface opposite to the surface on which the transistors are formed, and an opposing substrate 601 A polarizing plate is attached to the surface opposite to the surface on which the counter electrode layer 640 is formed.

[0451] Through the above steps, a liquid crystal display device can be manufactured as a display device. The liquid crystal display device has a high aperture ratio.

[0452] (Embodiment 15) In this embodiment, an example in which an oxide semiconductor layer is surrounded by a nitride insulating film as viewed from the cross section is shown in FIG. 38 is different from that in FIG. 1 in the top surface shape and end position of the oxide insulating layer 466. Since the two are the same except for the difference in the configuration of the edge layer, the same symbols are used for the same parts, and Detailed explanation will be omitted.

[0453] The thin film transistor 460 arranged in the drive circuit is a channel-etch type thin film transistor. On a substrate 450 having an insulating surface, a gate electrode layer 461 and a gate electrode made of a nitride insulating film are formed. The gate insulating layer 402, at least the channel forming region 463, the first high resistance drain region 46 4a, and the oxide semiconductor layer 462 having the second high-resistance drain region 464b; Resistive drain region 408a, second low-resistive drain region 408b, source electrode layer 465a and a drain electrode layer 465b. An oxide insulating layer 466 is provided in contact with the formation region 463 .

[0454] The oxide insulating layer 466 is a channel protection layer 47 of a thin film transistor 470 disposed in the pixel. 6 is formed by a photolithography process, the outer gate insulating film of the thin film transistor 460 is The oxide insulating layer 466 is processed so that the layer 402 is exposed. The upper surface shape may be wider than the upper surface shape of the compound semiconductor layer and may cover the thin film transistor 460. preferable.

[0455] Furthermore, a protective insulating layer made of a nitride insulating film is formed so as to cover the top and side surfaces of the oxide insulating layer 466. Form 453.

[0456] In the thin film transistor 460, the first low-resistance drain region 408a is in contact with the lower surface of the first low-resistance drain region 408a. The first high-resistance drain region 464a is formed in a self-aligned manner. A second high-resistance drain region 464b is formed in a self-aligned manner in contact with the lower surface of the drain region 408b. The channel formation region 463 is in contact with the oxide insulating layer 466 and has a thickness of is thinner than the first high-resistance drain region 464a and the second high-resistance drain region 464b. The first high-resistance drain region 464a and the second high-resistance drain region 464b have a resistance greater than that of the first high-resistance drain region 464a. The region with higher resistance than the region with lower resistance (type I region) is called the region with higher resistance than the region with lower resistance (type I region).

[0457] In addition, the channel forming region 463, the first high-resistance drain region 464a, and the second high-resistance A gate insulating layer 402 made of a nitride insulating film is formed in contact with the lower surface of the drain region 464b. It is being done.

[0458] The protective insulating layer 453 made of a nitride insulating film is a silicon nitride film obtained by a sputtering method, an oxynitride film, or the like. Moisture, hydrogen ions, and O H - The inorganic insulating film does not contain impurities such as Use.

[0459] In this embodiment, the protective insulating layer 453 is formed of a nitride insulating film on the oxide semiconductor layer. A silicon nitride film with a thickness of 100 nm is formed on the front and side surfaces using RF sputtering. The protective insulating layer 453 is in contact with the gate insulating layer 402 made of a nitride insulating film. do.

[0460] By using the structure shown in FIG. 38, the manufacturing process after forming the protective insulating layer 453 made of a nitride insulating film In the process, it is possible to prevent moisture from entering from the outside. For example, even after the device is completed as a liquid crystal display device, it will continue to prevent moisture from entering from the outside for a long period of time. This can improve the reliability of the device.

[0461] Similarly, the thin film transistor 470 also has a protective insulating layer 453 made of a nitride insulating film. , a film thickness formed by RF sputtering so as to surround the top surface and side surfaces of the oxide semiconductor layer 472 A 100 nm silicon nitride film is used. Also, the protective insulating layer 453 is a gate insulating film made of a nitride. The insulating layer 402 is in contact with the insulating layer 402 .

[0462] In addition, in this embodiment, a configuration in which one thin film transistor is surrounded by a nitride insulating film is shown. The present invention is not limited to this, and a configuration in which a plurality of thin film transistors are surrounded by a nitride insulating film may also be used. A plurality of thin film transistors in the region may be surrounded by a nitride insulating film. A protective insulating layer 453 and a gate insulating layer 454 are formed around the periphery of the pixel portion of the active matrix substrate. A region in contact with the layer 402 may be provided.

[0463] This embodiment mode can be freely combined with other embodiment modes. [Explanation of symbols]

[0464] 450 board 451 Gate electrode layer 453 Protective Insulation Layer 454 Planarization insulating layer 456 Pixel electrode layer 460 Thin Film Transistor 461 Gate electrode layer 462 Oxide semiconductor layer 463 Channel formation region 464a High-resistivity drain region 464b High-resistivity drain region 465a Source electrode layer 465b Drain electrode layer 466 Oxide insulating layer 467 Conductive Layer 470 Thin Film Transistors 471 Gate electrode layer 472 Oxide semiconductor layer 473 Channel formation region 474a High-resistivity drain region 474b High-resistivity drain region 475a Source electrode layer 475b Drain electrode layer 476 Oxide insulating layer (channel protection layer) 477 Pixel electrode layer

Claims

[Claim 1] a pixel portion having a first thin film transistor and a driver circuit having a second thin film transistor, both of which are formed on the same substrate; the first thin film transistor includes a gate electrode layer over a substrate, a gate insulating layer over the gate electrode layer, an oxide semiconductor layer having a thin region on a periphery thereof over the gate insulating layer, an oxide insulating layer in contact with a part of the oxide semiconductor layer, a source electrode layer and a drain electrode layer over the oxide insulating layer and the oxide semiconductor layer, and a pixel electrode layer electrically connected to the source electrode layer or the drain electrode layer; the gate electrode layer, the gate insulating layer, the oxide semiconductor layer, the source electrode layer, the drain electrode layer, the oxide insulating layer, and the pixel electrode layer of the first thin film transistor have light-transmitting properties; a source electrode layer and a drain electrode layer of the second thin film transistor are covered with a protective insulating layer, are made of a different material from the source electrode layer and the drain electrode layer of the first thin film transistor, and are made of a conductive material having a lower resistance than the source electrode layer and the drain electrode layer of the first thin film transistor.

Images