Semiconductor Devices

Abstract

To provide a semiconductor device capable of suppressing breakage.SOLUTION: A semiconductor device 1 comprises a semiconductor substrate 50. When seen from a surface 51 side, the semiconductor substrate 50 has: an IGBT region 10 including a plurality of IGBTs 1a; a diode region 20 arranged so as to surround the IGBT region 10, including a plurality of diodes 1b to 1d; and a peripheral region 30 arranged so as to surround the diode region 20. Each IGBT 1a has a drift layer 53, a barrier layer 54, a channel layer 55, an emitter layer 56, a pair of trench electrodes 60, a trench insulating film 65, a field stop layer 57, and a collector layer 58. Each diode 1b has the drift layer 53, a semiconductor layer 53a, the channel layer 55, the pair of trench electrodes 60, the trench insulating film 65, the field stop layer 57, and a cathode layer 66.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices. [Background technology]

[0002] Patent Document 1 describes an RC-IGBT (Reverse Conducting-Insulated Gate Bipolar Transistor) having an IGBT region and a diode region on a single semiconductor substrate. The RC-IGBT, which integrates the IGBT and diode on a single chip, allows for a reduced guard ring area (chip shrink). Furthermore, in the RC-IGBT, heat is dissipated from the diode region when the IGBT is in operation, and from the IGBT region when the diode is in operation. Therefore, the RC-IGBT can reduce chip thermal resistance. Therefore, the RC-IGBT can be made smaller and less susceptible to heat than current IGBTs. Demand for RC-IGBTs is expected to increase in the future. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent No. 6969662 Summary of the Invention [Problem to be solved by the invention]

[0004] In general, an RC-IGBT has IGBT regions and diode regions arranged alternately within a plane. When an IGBT is turned off, accumulated carriers (holes) are discharged from the emitter side. However, an IGBT does not have contacts connected to the emitter electrode in the peripheral region. As a result, carriers with nowhere to go concentrate at the active end of the IGBT region. This can cause destruction due to heat generation and other factors caused by the carriers concentrated at the active end.

[0005] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0006] According to one embodiment, a semiconductor device includes a semiconductor substrate having a first main surface and a second main surface opposite to the first main surface, and when viewed from the first main surface side, the semiconductor substrate has an IGBT region including a plurality of IGBTs formed in the semiconductor substrate, a diode region arranged to surround the IGBT region and including a plurality of diodes formed in the semiconductor substrate, and a peripheral region arranged to surround the diode region, and the IGBT includes a drift layer of a first conductivity type, a barrier layer of the first conductivity type provided on the first main surface side of the drift layer, a channel layer of a second conductivity type provided on the first main surface side of the barrier layer, an emitter layer of the first conductivity type provided on the first main surface side of the channel layer, a pair of trench electrodes provided to sandwich the barrier layer, the channel layer, and the emitter layer from both sides in one direction in a plane parallel to the first main surface, and a trench insulating film provided between the channel layer and the emitter layer, a field stop layer of a first conductivity type provided closer to the second main surface than the drift layer, and a collector layer of a second conductivity type provided closer to the second main surface than the field stop layer, and the diode includes the drift layer of the first conductivity type, a semiconductor layer of the first conductivity type provided closer to the first main surface than the drift layer, the channel layer of the second conductivity type provided closer to the first main surface than the semiconductor layer, a pair of trench electrodes provided to sandwich the semiconductor layer and the channel layer from both sides in the one direction, the trench insulating film provided between the trench electrode, the drift layer, the semiconductor layer, and the channel layer, the field stop layer of the first conductivity type provided closer to the second main surface than the drift layer, and a cathode layer of the first conductivity type provided closer to the second main surface than the field stop layer.

[0007] According to one embodiment, a semiconductor device includes a semiconductor substrate having a first main surface and a second main surface opposite to the first main surface, and when viewed from the first main surface side, the semiconductor substrate has an IGBT region including a plurality of IGBTs formed in the semiconductor substrate, a diode region including a plurality of diodes formed in the semiconductor substrate, and a peripheral region arranged to surround the IGBT region and the diode region, and the IGBT has a drift layer of a first conductivity type, a barrier layer of the first conductivity type provided closer to the first main surface than the drift layer, and a barrier layer of the first conductivity type provided between the drift layer and the barrier a channel layer of a second conductivity type provided closer to the first main surface than the drift layer; an emitter layer of a first conductivity type provided closer to the first main surface than the channel layer; a pair of trench electrodes provided so as to sandwich the barrier layer, the channel layer, and the emitter layer from both sides in one direction in a plane parallel to the first main surface; a trench insulating film provided between the trench electrode, the drift layer, the barrier layer, the channel layer, and the emitter layer; a field stop layer of the first conductivity type provided closer to the second main surface than the drift layer; a collector layer of a second conductivity type provided closer to the second main surface than the field stop layer, and the diode includes the drift layer, a semiconductor layer of the first conductivity type provided closer to the first main surface than the drift layer, the channel layer of the second conductivity type provided closer to the first main surface than the semiconductor layer, a pair of trench electrodes provided to sandwich the semiconductor layer and the channel layer from both sides in the one direction, and the trench insulating film provided between the trench electrode, the drift layer, the semiconductor layer, and the channel layer; the semiconductor substrate in the peripheral region has the drift layer, a floating layer of a second conductivity type provided on the first main surface side of the drift layer, the field stop layer of the first conductivity type provided on the second main surface side of the drift layer, the field stop layer of the first conductivity type provided on the second main surface side of the drift layer, and the cathode layer of the first conductivity type provided on the second main surface side of the field stop layer. [Effects of the Invention]

[0008] According to the embodiment, it is possible to provide a semiconductor device that can suppress breakdown. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 10 is a plan view illustrating the surface of a semiconductor device according to a comparative example. [Figure 2] FIG. 10 is a plan view illustrating the back surface of a semiconductor device according to a comparative example. [Figure 3] FIG. 10 is a cross-sectional view illustrating a peripheral region of a semiconductor device according to a comparative example. [Figure 4] 1 is a plan view illustrating a semiconductor device according to a first embodiment. [Figure 5] 5 is a cross-sectional view illustrating the semiconductor device according to the first embodiment, taken along line VV in FIG. 4. FIG. [Figure 6] 6 is an enlarged plan view illustrating a diode region in the semiconductor device according to the first embodiment, showing the plane taken along line VI-VI in FIG. 4. FIG. [Figure 7] 7 is a plan view illustrating an IGBT region and a diode region in the semiconductor device according to the first embodiment, showing a plane taken along line VII-VII in FIG. 4. FIG. [Figure 8] 8 is a cross-sectional view illustrating an IGBT in the semiconductor device according to the first embodiment, taken along line VIII-VIII in FIG. 7. [Figure 9] 9 is a cross-sectional view illustrating a diode in the semiconductor device according to the first embodiment, taken along line IX-IX in FIG. 6. FIG. [Figure 10] 8 is a cross-sectional view illustrating a diode in the semiconductor device according to the first embodiment, showing a cross section taken along line XX in FIG. 6 and line XX in FIG. 7. [Figure 11] 3A to 3C are cross-sectional views illustrating a method for forming an N++ type cathode layer and a P++ type collector layer on the back surface of the semiconductor device according to the first embodiment. [Figure 12] 3A to 3C are cross-sectional views illustrating a method for forming an N++ type cathode layer and a P++ type collector layer on the back surface of the semiconductor device according to the first embodiment. [Figure 13] 2 is a plan view illustrating the back surface of the semiconductor substrate in the semiconductor device according to the first embodiment. FIG. [Figure 14] 10 is a plan view illustrating the surface of a semiconductor substrate in a semiconductor device according to a second embodiment. FIG. [Figure 15] 10 is a plan view illustrating the back surface of a semiconductor substrate in a semiconductor device according to a second embodiment. FIG. [Figure 16] 5 is a cross-sectional view illustrating a semiconductor device according to a third embodiment, taken along the same line as line VV in FIG. 4. FIG. [Figure 17] 7 is a plan view illustrating a semiconductor device according to a fourth embodiment, showing a plane at a position similar to that of line VII-VII in FIG. [Figure 18] 5 is a cross-sectional view illustrating a semiconductor device according to a fifth embodiment, taken along the same line as line VV in FIG. [Figure 19] FIG. 10 is a circuit diagram illustrating the connection of RC-IGBTs in a semiconductor device according to a fifth embodiment. [Figure 20] 10 is a graph illustrating voltages of a trench electrode of an IGBT and a trench electrode of a diode in a semiconductor device according to Embodiment 5, where the horizontal axis represents time and the vertical axis represents voltage. [Figure 21] 10 is a diagram illustrating the discharge of carriers in the semiconductor device according to the fifth embodiment. FIG. [Figure 22] 10 is a diagram illustrating the discharge of carriers in the semiconductor device according to the fifth embodiment. FIG. [Figure 23] 10 is a diagram illustrating the discharge of carriers in the semiconductor device according to the fifth embodiment. FIG. [Figure 24] 13 is a cross-sectional view illustrating a semiconductor substrate in a peripheral region in a semiconductor device according to a sixth embodiment. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0010] For clarity of explanation, the following description and drawings have been omitted and simplified as appropriate. Furthermore, in the drawings, hatching and the like may be omitted even in cross sections if it would otherwise become too complicated or if the distinction from voids is clear. In each drawing, the same elements are given the same reference numerals, and duplicate explanations are omitted as necessary. Furthermore, reference numerals are omitted as appropriate to avoid cluttering the drawings.

[0011] First, a semiconductor device according to a comparative example and problems discovered by the inventors will be described. Then, a semiconductor device according to an embodiment will be described. Note that the semiconductor device according to the comparative example and its problems are also included within the scope of the technical concept of the embodiment.

[0012] (Comparative Example) FIG. 1 is a plan view illustrating the front surface of a semiconductor device according to a comparative example. FIG. 2 is a plan view illustrating the back surface of the semiconductor device according to the comparative example. As shown in FIGS. 1 and 2, in the semiconductor device 101 of the comparative example, when viewed from the front surface 151 side of the semiconductor substrate 150, the IGBT regions 110 and the diode regions 120 are alternately arranged in one direction. If the direction perpendicular to the front surface of the semiconductor substrate 150 is defined as the Z-axis direction, the IGBT regions 110 and the diode regions 120 extend in the Y-axis direction and are alternately arranged in the X-axis direction. The peripheries of the front surface 151 and the back surface 152 of the semiconductor substrate 150 are called peripheral regions 130 (also called termination regions). In the semiconductor device 101, for example, an emitter electrode is connected to the front surface 151 side and a collector electrode is connected to the back surface 152 side.

[0013] The IGBT in the IGBT region 110 discharges accumulated carriers (e.g., holes) from the emitter electrode side when turned off. However, no contact connected to the emitter potential is formed in the peripheral region 130. As a result, carriers that have nowhere to go end up concentrating at the edge of the active region, such as the IGBT region 110. Therefore, the semiconductor device 101 may suffer from thermal breakdown due to this carrier concentration. As such, the semiconductor device 101 of the comparative example has the problem of thermal breakdown due to carrier concentration.

[0014] Furthermore, the semiconductor device 101 of the comparative example has a problem of leakage current. Fig. 3 is a cross-sectional view illustrating a peripheral region 130 of the semiconductor device 101 of the comparative example. As shown in Fig. 3, the semiconductor device 101 has an N- type drift layer 153, a P-type semiconductor layer 159, an insulating film 164, an emitter electrode 141, an N+ type field-stop layer 157, a P+ type collector layer 158, and a collector electrode 142 in the peripheral region 130 where a depletion layer 169 spreads.

[0015] As described above, the semiconductor device 101 of the comparative example has the P+ type collector layer 158 formed on the back surface 152 of the peripheral region 130. Therefore, in the semiconductor device 101 of the comparative example, a parasitic pnp bipolar is formed by the P+ type collector layer 158, the N+ type field stop layer 157, and the P type semiconductor layer 159. This causes a leakage current to flow through the parasitic pnp bipolar in the semiconductor device 101. The leakage current induces heat breakdown of the semiconductor device 101, causing loss of application.

[0016] For example, a semiconductor device may have a gate pad at one end of one side of the surface 151 of the semiconductor substrate 150. When the IGBT is turned off, gate delay occurs in a region far from the gate pad due to gate wiring resistance, which causes current concentration in the semiconductor device.

[0017] The RC-IGBT has a smaller area than an IGBT connected in parallel with a diode. However, the size of one chip is expected to be larger than that of a single IGBT. Therefore, it is expected that the potential difference between each emitter pad due to gate delay will be large. As a result, current concentration due to gate delay occurs at the end in one direction away from the gate pad.

[0018] (Embodiment 1) Next, a semiconductor device according to the first embodiment will be described. The semiconductor device according to the present embodiment solves at least one of the problems of the semiconductor device 101 of the comparative example described above. FIG. 4 is a plan view illustrating the semiconductor device according to the first embodiment. FIG. 5 is a cross-sectional view illustrating the semiconductor device according to the first embodiment, showing a cross-section along line VV in FIG. 4. FIG. 6 is an enlarged plan view illustrating a diode region in the semiconductor device according to the first embodiment, showing a plane along line VI-VI in FIG. 4. FIG. 7 is a plan view illustrating an IGBT region and a diode region in the semiconductor device according to the first embodiment, showing a plane along line VII-VII in FIG. 4. FIG. 8 is a cross-sectional view illustrating an IGBT in the semiconductor device according to the first embodiment, showing a cross-section along line VIII-VIII in FIG. 7. FIG. 9 is a cross-sectional view illustrating a diode in the semiconductor device according to the first embodiment, showing a cross-section along line IX-IX in FIG. 6. FIG. 10 is a cross-sectional view illustrating a diode in the semiconductor device according to the first embodiment, showing a cross-section along line XX in FIG. 6 and XX in FIG. 7. 6 and 7, a part of the emitter electrode 41 and a part of the insulating film 64 are removed.

[0019] 4 to 10, the semiconductor device 1 includes a semiconductor substrate 50 having a front surface 51 (first main surface) and a back surface 52 (second main surface). The back surface 52 is the surface opposite to the front surface 51. The semiconductor device 1 may include an emitter electrode 41 provided on the front surface 51 via an insulating film 64, a gate electrode 40 provided on the front surface 51 via the insulating film 64, and a collector electrode provided on the back surface 52.

[0020] Here, for the sake of convenience in explaining the semiconductor device 1, an XYZ Cartesian coordinate system is introduced. The direction perpendicular to the front surface 51 is defined as the Z-axis direction, and the two directions perpendicular to the Z-axis direction are defined as the X-axis direction and the Y-axis direction. The direction from the back surface 52 toward the front surface 51 is defined as the +Z-axis direction. For convenience, the +Z-axis direction is defined as upward, and the −Z-axis direction is defined as downward. Note that upward and downward do not indicate the directions when the semiconductor device 1 is actually used.

[0021] When viewed from the front surface 51 side, the semiconductor device 1 has an IGBT region 10, a diode region 20, and a peripheral region 30. The IGBT region 10 includes a plurality of IGBTs 1a formed on a semiconductor substrate 50. The diode region 20 includes a plurality of diodes 1b to 1d formed on the semiconductor substrate 50. The diode region 20 is arranged between the IGBT region 10 and the peripheral region 30. The diode region 20 is arranged to surround the IGBT region 10. The peripheral region 30 is arranged to surround the IGBT region 10 and the diode region 20.

[0022] The IGBT region 10 has, for example, regions 11, 12, and 13 extending in the X-axis direction. Regions 11, 12, and 13 are aligned in the Y-axis direction. Specifically, region 11 is disposed on the +Y-axis direction side of the IGBT region 10, and region 13 is disposed on the −Y-axis direction side of the IGBT region 10. Region 12 is disposed between regions 11 and 13.

[0023] Roughly speaking, the diode region 20 has a rectangular frame shape. When viewed from the front surface 51 side, the diode region 20 has a region 21 (first portion), a region 22a (second portion), a region 22b (second portion), a region 23 (third portion), and a region 24 (fourth portion).

[0024] The region 21 is a portion on the +X-axis direction side of the IGBT region 10. Specifically, the region 21 is a portion on the +X-axis direction side of the regions 11, 12, and 13. The region 21 extends in the Y-axis direction. The region 21 is disposed between one end of the IGBT region 10 on the +X-axis direction side in the X-axis direction and the peripheral region 30. The region 21 separates the IGBT region 10 and the peripheral region 30 in the X-axis direction.

[0025] Region 22a is a portion of the IGBT region 10 that is closer to the -X-axis direction than region 11. Region 22a extends in the Y-axis direction. Region 22b is a portion of the IGBT region 10 that is closer to the -X-axis direction than region 13. Region 22b extends in the Y-axis direction. Regions 22a and 22b are arranged between the other end of the IGBT region 10 on the -X-axis direction side in the X-axis direction and the peripheral region 30. Regions 22a and 22b separate the IGBT region 10 and the peripheral region 30 in the X-axis direction.

[0026] The region 23 is a portion on the +Y-axis direction side of the IGBT region 10. Specifically, the region 23 is a portion on the +Y-axis direction side of the region 11. The region 23 extends in the X-axis direction. The region 23 is disposed between one end of the IGBT region 10 on the +Y-axis direction side in the Y-axis direction and the peripheral region 30. The region 23 separates the IGBT region 10 and the peripheral region 30 in the Y-axis direction.

[0027] The region 24 is a portion on the -Y-axis direction side of the IGBT region 10. Specifically, the region 24 is a portion on the -Y-axis direction side of the region 13. The region 24 extends in the X-axis direction. The region 24 is disposed between the other end of the IGBT region 10 on the -Y-axis direction side in the Y-axis direction and the peripheral region 30. The region 24 separates the IGBT region 10 and the peripheral region 30 in the Y-axis direction.

[0028] In the X-axis direction, the width of the region 21 separating the IGBT region 10 and the peripheral region 30 is greater than the widths of the regions 22a and 22b separating the IGBT region 10 and the peripheral region 30. In addition, in the X-axis direction, the width of the region 21 separating the IGBT region 10 and the peripheral region 30 is greater than the widths of the regions 23 and 24 separating the IGBT region 10 and the peripheral region 30 in the Y-axis direction.

[0029] The peripheral region 30 is in the shape of a rectangular frame. The peripheral region 30 has regions 31, 32, 33, and 34. Region 31 is the part on the +X-axis direction side of region 21. Region 31 extends in the Y-axis direction. Region 32 is the part on the -X-axis direction side of regions 22a and 22b. Region 32 extends in the Y-axis direction. Region 33 is the part on the +Y-axis direction side of region 23. Region 33 extends in the X-axis direction. Region 34 is the part on the -Y-axis direction side of region 24. Region 33 extends in the X-axis direction.

[0030] The gate electrode 40 is arranged on the other end side in the X-axis direction of the IGBT region 10. For example, the gate electrode 40 is arranged on the -X-axis direction side of the IGBT region 10. Specifically, the gate electrode 40 is arranged on the -X-axis direction side of region 12. The gate electrode 40 is surrounded by region 11 arranged on the +Y-axis direction side of the gate electrode 40, region 12 arranged on the +X-axis direction side of the gate electrode 40, and region 13 arranged on the -Y-axis direction side of the gate electrode 40. The gate electrode 40 may be provided on the surface 51 via the insulating film 64.

[0031] In the semiconductor device 1 of the present embodiment, in the region surrounding the IGBT region 10, the diode region 20 is arranged in a form connected to the peripheral region 30. Also, in the semiconductor device 1, the width of the diode region 20 at a position far from the gate electrode 40 is widened.

[0032] <IGBT region> A plurality of IGBTs 1a are formed on the semiconductor substrate 50 of the IGBT region 10. The IGBT 1a has an N-type drift layer 53, an N+ type barrier layer 54, a P-type channel layer 55, an N+ type emitter layer 56, a pair of trench electrodes 60, a trench insulating film 65, an N+ type field stop layer 57, a P++ type collector layer 58, and a P-type floating layer 59. So as not to make the figure complicated, the trench insulating film 65 and the insulating film 64 on the semiconductor substrate 50 are shown by thick lines.

[0033] Note that N++ type and P++ type refer to low-resistance N-conductivity type and P-conductivity type, respectively. N+ type and P+ type refer to N-conductivity type and P-conductivity type, respectively, which have higher resistance than N++ type and P++ type, but lower resistance than N-type and P-type. P- type and N- type refer to N-conductivity type and P-conductivity type, respectively, which have higher resistance than N-type and P-type. Therefore, N-type and P-type refer to N-conductivity type and P-conductivity type, respectively, with resistance between N+ type and P+ type and P- type and N- type. N+ type and P+ type refer to N-conductivity type and P-conductivity type, respectively, with resistance between N++ type and P++ type and P- type and N- type. Hereinafter, the same meaning is used unless otherwise specified. N-conductivity type is sometimes referred to as the first conductivity type, and P-conductivity type is sometimes referred to as the second conductivity type.

[0034] Note that the N conductivity type may be the second conductivity type, and the P conductivity type may be the first conductivity type. Furthermore, semiconductor devices in which the conductivity types of the respective configurations of the present disclosure are reversed are also within the scope of the technical concept of the present disclosure. Furthermore, the resistances of the N++, N+, N, and N- type semiconductor layers are merely examples. The resistances may be greater than or less than the resistances indicated in the present disclosure. Similarly, the resistances of the P++, P+, P, and P- type semiconductor layers are merely examples. The magnitude relationship of the resistances of the respective semiconductor layers may be reversed in some cases.

[0035] The N- type drift layer 53 is provided closer to the surface 51 than the N+ type field stop layer 57. As will be described later, the N- type drift layer 53 is provided across the IGBT region 10, the diode region 20, and the peripheral region 30.

[0036] The N+ type barrier layer 54 is provided closer to the front surface 51 than the N- type drift layer 53. The N+ type barrier layer 54 extends, for example, in the Y-axis direction when viewed from the front surface 51 side. The N+ type barrier layer 54 is sandwiched between a pair of trench electrodes 60 on both sides in the X-axis direction. That is, the N+ type barrier layer 54 is disposed between the pair of trench electrodes 60.

[0037] The P-type channel layer 55 is provided closer to the surface 51 than the N+-type barrier layer 54. The P-type channel layer 55 is disposed between a pair of trench electrodes 60. The P-type channel layer 55 is connected to the emitter electrode 41 filled in a through-hole that penetrates the insulating film 64 and the N+-type emitter layer 56.

[0038] The N+ type emitter layer 56 is provided closer to the surface 51 than the P type channel layer 55. The N+ type emitter layer 56 is disposed between a pair of trench electrodes 60. The N+ type emitter layer 56 is connected to the emitter electrode 41 filled in a through hole that penetrates the insulating film 64.

[0039] The pair of trench electrodes 60 are provided to sandwich the N+ type barrier layer 54, the P-type channel layer 55, and the N+ type emitter layer 56 from both sides in the X-axis direction. Each trench electrode 60 extends, for example, in the Y-axis direction when viewed from the front surface 51 side. For example, of the pair of trench electrodes 60, the trench electrode 60 on the −X-axis direction side is referred to as trench electrode 61, and the trench electrode 60 on the +X-axis direction side is referred to as trench electrode 62. Therefore, the pair of trench electrodes 60 of the IGBT 1a includes a trench electrode 61 (first trench electrode) and a trench electrode 62 (second trench electrode). The trench electrode 61 is connected to the gate electrode 40, for example, via a gate wiring (not shown). The trench electrode 62 is connected to the emitter electrode 41 filled in a through hole penetrating the insulating film 64. Therefore, the N+ type emitter layer 56, the P type channel layer 55, and the trench electrode 62 are connected to the emitter electrode 41. The structure between a pair of trench electrodes 60 is called an inter-trench structure. For example, the inter-trench structure of the IGBT 1a includes an N+ type barrier layer 54, a P type channel layer 55, and an N+ type emitter layer 56. The inter-trench structure of the IGBT 1a may include other members such as a contact layer.

[0040] The P-type floating layer 59 is provided between adjacent IGBTs 1a among the multiple IGBTs 1a. For example, the P-type floating layer 59 is provided between the trench electrode 62 of the IGBT 1a on the −X-axis direction side of the adjacent IGBTs 1a and the trench electrode 61 of the IGBT 1a on the +X-axis direction side. The P-type floating layer 59 is provided on the opposite side of the trench electrode 60 from the N+ type barrier layer 54, the P-type channel layer 55, and the N+ type emitter layer 56.

[0041] The P-type floating layer 59 is provided closer to the surface 51 than the N-type drift layer 53. Therefore, on the N-type drift layer 53, from the -X-axis direction side along the X-axis direction, the P-type floating layer 59, the trench electrode 61 (covered with a trench insulating film 65), the inter-trench structure, the trench electrode 62 (covered with a trench insulating film 65), and the P-type floating layer 59 are arranged. In the IGBT region 10, this configuration is arranged so as to be repeated in the X-axis direction.

[0042] The P-type floating layer 59 between one end of the IGBT region 10 on the +X-axis direction side in the X-axis direction and the other end of the IGBT region 10 on the −X-axis direction side in the X-axis direction is in contact with the trench electrode 61 and the trench electrode 62. In other words, the P-type floating layer 59 is formed between adjacent IGBTs 1a in the IGBT region 10 other than the end portions in the X-axis direction.

[0043] The trench insulating film 65 is provided between the trench electrode 60 and the N− type drift layer 53, the N+ type barrier layer 54, the P type channel layer 55, the N+ type emitter layer 56, and the P type floating layer 59.

[0044] The N+ field stop layer 57 is provided closer to the back surface 52 than the N- drift layer 53. The P++ collector layer 58 is provided closer to the back surface 52 than the N+ field stop layer 57. The P++ collector layer 190 is connected to a collector electrode. The collector electrode is omitted to avoid complication in the drawing.

[0045] <Diode region> A plurality of diodes are formed on the semiconductor substrate 50 in the diode region 20. The plurality of diodes includes a plurality of diodes 1b, a plurality of diodes 1c, and a plurality of diodes 1d. Diodes 1b, 1c, and 1d may be collectively referred to as diodes 1bcd. Diodes 1b, 1c, and 1d differ in the shapes of the semiconductor layers, etc.

[0046] The diode 1b includes an N-type drift layer 53, an N-type semiconductor layer 53a, a P-type channel layer 55, a pair of trench electrodes 60, a trench insulating film 65, an N+ type field stop layer 57, and an N++ type cathode layer 66.

[0047] The N− type drift layer 53 is provided closer to the surface 51 than the N+ type field stop layer 57. The N− type drift layer 53 is provided across the IGBT region 10, the diode region 20, and the peripheral region 30.

[0048] The N-type semiconductor layer 53a is provided closer to the surface 51 than the N-type drift layer 53. When viewed from the surface 51 side, the N-type semiconductor layer 53a extends, for example, in the Y-axis direction. The N-type semiconductor layer 53a may be a part of the N-type drift layer 53 extending between a pair of trench electrodes 60. Therefore, the N-type semiconductor layer 53a may have the same resistance value as the N-type drift layer 53. The N-type semiconductor layer 53a is sandwiched between a pair of trench electrodes 60 on both sides in the X-axis direction. That is, the N-type semiconductor layer 53a is disposed between the pair of trench electrodes 60.

[0049] The P-type channel layer 55 is provided closer to the surface 51 than the N-type semiconductor layer 53a. The P-type channel layer 55 is disposed between a pair of trench electrodes 60. The P-type channel layer 55 is connected to the emitter electrode 41 filled in a through-hole that penetrates the insulating film 64.

[0050] The pair of trench electrodes 60 are provided to sandwich the N-type semiconductor layer 53a and the P-type channel layer 55 from both sides in the X-axis direction. When viewed from the front surface 51 side, each trench electrode 60 extends, for example, in the Y-axis direction. For example, each trench electrode 60 is connected to the emitter electrode 41 via an emitter wiring (not shown). Thus, each trench electrode 60 is connected to the emitter electrode 41, similar to the trench electrode 62 of the IGBT 1a. Therefore, the pair of trench electrodes 60 of the diode 1b includes two trench electrodes 62.

[0051] The structure between a pair of trench electrodes 60 is called an inter-trench structure. For example, the inter-trench structure of diode 1b includes an N-type semiconductor layer 53a and a P-type channel layer 55. The inter-trench structure of diode 1b may include other members such as a contact layer.

[0052] On the N-type drift layer 53, a trench electrode 62 (covered with a trench insulating film 65), an inter-trench structure, and a trench electrode 62 (covered with a trench insulating film 65) are arranged along the X-axis direction from the -X-axis direction side. In the region of the diode region 20 where the plurality of diodes 1b are arranged, such a configuration is arranged so as to be repeated in the X-axis direction.

[0053] The trench insulating film 65 is provided between the trench electrode 60 and the N-type drift layer 53, the N-type semiconductor layer 53a, and the P-type channel layer 55.

[0054] The N+ type field stop layer 57 is provided closer to the back surface 52 than the N- type drift layer 53. The N++ type cathode layer 66 is provided closer to the back surface 52 than the N+ type field stop layer 57. The N++ type cathode layer 66 is connected to the collector electrode.

[0055] The diode region 20 may include a plurality of diodes 1c formed in the semiconductor substrate 50. The diodes 1c include a different configuration from the diodes 1b. Specifically, the diodes 1c include a connecting trench electrode that connects adjacent trench electrodes 60. The trench electrodes 60 and the connecting trench electrode form a rectangular cylindrical trench electrode.

[0056] The diode 1c has an N-type drift layer 53, an N-type semiconductor layer 53a, a P-type channel layer 55, a rectangular cylindrical trench electrode 68, a trench insulating film 65, an N+ type field stop layer 57, an N++ type cathode layer 66, and a P-type floating layer 59. The rectangular cylindrical trench electrode 68 includes a pair of trench electrodes 60 and a pair of connecting trench electrodes 67.

[0057] The N− type drift layer 53 is provided closer to the surface 51 than the N+ type field stop layer 57. The N− type drift layer 53 is provided across the IGBT region 10, the diode region 20, and the peripheral region 30.

[0058] The N-type semiconductor layer 53a is provided closer to the surface 51 than the N-type drift layer 53. The N-type semiconductor layer 53a is disposed inside the area surrounded by the rectangular cylindrical trench electrode 68. That is, the N-type semiconductor layer 53a is sandwiched between a pair of trench electrodes 60 on both sides in the X-axis direction, and between a pair of connecting trench electrodes 67 on both sides in the Y-axis direction. The N-type semiconductor layer 53a may be formed by a portion of the N-type drift layer 53 extending into the area surrounded by the rectangular cylindrical trench electrode 68. Therefore, the N-type semiconductor layer 53a may have the same resistance value as the N-type drift layer 53.

[0059] The P-type channel layer 55 is provided closer to the surface 51 than the N-type semiconductor layer 53a. The P-type channel layer 55 is disposed inside an area surrounded by rectangular cylindrical trench electrodes 68. That is, the P-type channel layer 55 is sandwiched between a pair of trench electrodes 60 on both sides in the X-axis direction, and between a pair of connecting trench electrodes 67 on both sides in the Y-axis direction. The P-type channel layer 55 is connected to the emitter electrode 41 filled in a through-hole that penetrates the insulating film 64.

[0060] The rectangular tube trench electrode 68 has a rectangular tube shape with a central axis extending in the Z-axis direction. The rectangular tube trench electrode 68 is provided so as to sandwich the N-type semiconductor layer 53a and the P-type channel layer 55 from both sides in the X-axis direction and from both sides in the Y-axis direction. A pair of connecting trench electrodes 67 in the rectangular tube trench electrode 68 extend in a direction intersecting the extension direction of the trench electrodes 60 when viewed from the front surface 51 side. Specifically, the pair of connecting trench electrodes 67 extend in the X-axis direction. The pair of connecting trench electrodes 67 are connected to a pair of trench electrodes 60. One connecting trench electrode 67 is connected to one end of each trench electrode 60. The other connecting trench electrode 67 is connected to the other end of each trench electrode 60.

[0061] Specifically, one end of the +Y-axis direction connecting trench electrode 67 on the +X-axis direction is connected to one end of the +X-axis direction trench electrode 60 on the +X-axis direction. The other end of the +Y-axis direction connecting trench electrode 67 on the -X-axis direction is connected to one end of the +Y-axis direction trench electrode 60 on the -X-axis direction. The one end of the +X-axis direction connecting trench electrode 67 on the -Y-axis direction is connected to the other end of the -Y-axis direction trench electrode 60 on the +X-axis direction. The other end of the -X-axis direction connecting trench electrode 67 on the -Y-axis direction is connected to the other end of the -Y-axis direction trench electrode 60 on the -X-axis direction. In this way, the pair of connecting trench electrodes 67 and the pair of trench electrodes 60 form a rectangular cylindrical trench electrode 68.

[0062] The rectangular cylindrical trench electrode 68 is connected to the emitter electrode 41 filled in the through-hole that penetrates the insulating film 64. Therefore, the N+ type emitter layer 56, the P type channel layer 55, the trench electrode 62 (IGBT 1a), and the rectangular cylindrical trench electrode 68 are connected to the emitter electrode 41. The internal structure surrounded by the rectangular cylindrical trench electrode 68 is called an inter-trench structure. For example, the inter-trench structure of the diode 1c includes the N- type semiconductor layer 53a and the P type channel layer 55. The inter-trench structure of the diode 1c may include other members such as a contact layer.

[0063] The P-type floating layer 59 is provided between adjacent diodes 1c among the plurality of diodes 1c. For example, the P-type floating layer 59 is provided between the rectangular cylindrical trench electrode 68 of the diode 1c on the −X-axis direction side and the rectangular cylindrical trench electrode 68 of the diode 1c on the +X-axis direction side among the diodes 1c adjacent in the X-axis direction. The P-type floating layer 59 is also provided between the rectangular cylindrical trench electrode 68 of the diode 1c on the −Y-axis direction side and the rectangular cylindrical trench electrode 68 of the diode 1c on the +Y-axis direction side among the diodes 1c adjacent in the Y-axis direction. The P-type floating layer 59 is provided on the opposite side of the N-type semiconductor layer 53a and the P-type channel layer 55, with the rectangular cylindrical trench electrode 68 sandwiched between them.

[0064] The P-type floating layer 59 is provided closer to the surface 51 than the N-type drift layer 53. Thus, on the N-type drift layer 53, from the -X-axis direction side along the X-axis direction, the P-type floating layer 59, the trench electrode 60 (covered with a trench insulating film 65), the inter-trench structure, the trench electrode 60 (covered with a trench insulating film 65), and the P-type floating layer 59 are arranged. In the region of the diode region 20 where the plurality of diodes 1c are arranged, this configuration is arranged so as to be repeated in the X-axis direction. Furthermore, on the N-type drift layer 53, from the -Y-axis direction side along the Y-axis direction, the P-type floating layer 59, the connecting trench electrode 67 (covered with a trench insulating film 65), the inter-trench structure, the connecting trench electrode 67 (covered with a trench insulating film 65), and the P-type floating layer 59 are arranged. In the region of the diode region 20 where the plurality of diodes 1c are arranged, this configuration is arranged so as to be repeated in the Y-axis direction.

[0065] The trench insulating film 65 is provided between the rectangular cylindrical trench electrode 68 and the N-type drift layer 53, the N-type semiconductor layer 53a, the P-type channel layer 55, and the P-type floating layer 59.

[0066] The N+ type field stop layer 57 is provided closer to the back surface 52 than the N- type drift layer 53. The N++ type cathode layer 66 is provided closer to the back surface 52 than the N+ type field stop layer 57. The N++ type cathode layer 66 is connected to the collector electrode.

[0067] The diode region 20 may include multiple diodes 1d formed in the semiconductor substrate 50. The diodes 1d are formed, for example, in regions 23 and 24. The diodes 1d may use the same trench as the IGBT 1a. In this case, the diodes 1d are formed by removing the N+ type barrier layer 54 and the N+ type emitter layer 56 from the configuration of the IGBT 1a. Thus, the diodes 1d are formed by deactivating the configuration of the IGBT 1a. The diodes 1d can be operated as diodes 1d by forming an N++ type cathode layer 66 on the back surface 52.

[0068] The diode 1d includes an N-type drift layer 53, an N-type semiconductor layer 53a, a P-type channel layer 55, a pair of trench electrodes 60, a trench insulating film 65, an N+ type field stop layer 57, an N++ type cathode layer 66, and a P-type floating layer 59.

[0069] The N− type drift layer 53 is provided closer to the surface 51 than the N+ type field stop layer 57. The N− type drift layer 53 is provided across the IGBT region 10, the diode region 20, and the peripheral region 30.

[0070] The N-type semiconductor layer 53a is provided closer to the surface 51 than the N-type drift layer 53. The N-type semiconductor layer 53a is disposed inside an area surrounded by the trench electrodes 60. The N-type semiconductor layer 53a extends, for example, in the Y-axis direction when viewed from the surface 51 side. The N-type semiconductor layer 53a may be a portion of the N-type drift layer 53 extending between the pair of trench electrodes 60. Therefore, the N-type semiconductor layer 53a may have the same resistance value as the N-type drift layer 53. The N-type semiconductor layer 53a is sandwiched between the pair of trench electrodes 60 on both sides in the X-axis direction. That is, the N-type semiconductor layer 53a is disposed between the pair of trench electrodes 60.

[0071] The P-type channel layer 55 is provided closer to the surface 51 than the N-type semiconductor layer 53a. The P-type channel layer 55 is disposed between a pair of trench electrodes 60. The P-type channel layer 55 is connected to the emitter electrode 41 filled in a through-hole that penetrates the insulating film 64.

[0072] A pair of trench electrodes 60 are provided to sandwich the N-type semiconductor layer 53a and the P-type channel layer 55 from both sides in the X-axis direction. Each trench electrode 60 extends, for example, in the Y-axis direction when viewed from the front surface 51. Like the trench electrode 62 of the IGBT 1a, the trench electrode 60 may be connected to the emitter electrode 41 filled in a through-hole that penetrates the insulating film 64. Therefore, the pair of trench electrodes 60 of the diode 1b includes two trench electrodes 62. The P-type channel layer 55 and the trench electrode 62 are connected to the emitter electrode 41 filled in a through-hole that penetrates the insulating film 64. The structure between the pair of trench electrodes 60 is called an inter-trench structure. For example, the inter-trench structure of the diode 1d includes the N-type semiconductor layer 53a and the P-type channel layer 55. The inter-trench structure of the diode 1d may include other components such as a contact layer.

[0073] The P-type floating layer 59 is provided between adjacent diodes 1d among the plurality of diodes 1d. For example, the P-type floating layer 59 is provided between the trench electrode 60 on the +X-axis direction side of the diode 1d on the −X-axis direction side of adjacent diodes 1d and the trench electrode 60 on the −X-axis direction side of the diode 1d on the +X-axis direction side. The P-type floating layer 59 is provided on the opposite side of the trench electrode 60 from the N-type semiconductor layer 53a and the P-type channel layer 55.

[0074] The P-type floating layer 59 is provided closer to the surface 51 than the N-type drift layer 53. Therefore, on the N-type drift layer 53, from the -X-axis direction side along the X-axis direction, the P-type floating layer 59, the trench electrode 60 (covered with a trench insulating film 65), the inter-trench structure, the trench electrode 60 (covered with a trench insulating film 65), and the P-type floating layer 59 are arranged. In the region of the diode region 20 where the multiple diodes 1d are arranged, this configuration is arranged so as to be repeated in the X-axis direction.

[0075] The trench insulating film 65 is provided between the trench electrode 60 and the N − type drift layer 53 , the N − type semiconductor layer 53 a , the P type channel layer 55 , and the P type floating layer 59 .

[0076] The N+ type field stop layer 57 is provided closer to the back surface 52 than the N- type drift layer 53. The N++ type cathode layer 66 is provided closer to the back surface 52 than the N+ type field stop layer 57. The N++ type cathode layer 66 is connected to the collector electrode.

[0077] <Surrounding Areas> The semiconductor substrate 50 in the peripheral region 30 has an N- type drift layer 53, an N+ type field stop layer 57, an N++ type cathode layer 66, and a P type floating layer 59. The P type floating layer 59 is provided closer to the front surface 51 than the N- type drift layer 53. The N+ type field stop layer 57 is provided closer to the back surface 52 than the N- type drift layer 53. The N++ type cathode layer 66 is provided closer to the back surface 52 than the N+ type field stop layer 57.

[0078] 11 and 12 are cross-sectional views illustrating a method for forming the N++ type cathode layer 66 and the P++ type collector layer 58 on the back surface 52 of the semiconductor device 1 according to the first embodiment. As shown in Fig. 11, an N+ type field stop layer 57 is formed on the back surface 52 side of the semiconductor substrate 50. For example, the N+ type field stop layer 57 is formed by ion implantation.

[0079] 12, an N++ cathode layer 66 is formed on the back surface 52 of the diode region 20 and the back surface 52 of the peripheral region 30 by ion implantation or the like, on the back surface 52 side of the N+ type field stop layer 57. Then, as shown in FIG. 5, a P++ type collector layer 58 is formed on the back surface 52 of the IGBT region 10 by ion implantation or the like, on the back surface 52 side of the N+ type field stop layer 57.

[0080] 13 is a plan view illustrating the back surface 52 of the semiconductor substrate 50 in the semiconductor device 1 according to the first embodiment. As shown in Fig. 13, a P++ type collector layer 58 is formed on the back surface 52 of the IGBT region 10. An N++ cathode layer 66 is formed on the back surface 52 of the diode region 20 and the back surface 52 of the peripheral region 30. When viewed from the back surface 52 side, the N++ cathode layer 66 is formed to surround the P++ type collector layer 58.

[0081] Next, the effects of this embodiment will be described. The semiconductor device 1 of this embodiment has the diode region 20 between the IGBT region 10 and the peripheral region 30. That is, the diode region 20 of the semiconductor device 1 is arranged so as to be connected to the peripheral region 30. Therefore, in the semiconductor device 1, when the IGBT 1a is turned off, the diode 1bcd operates as a parasitic P-MOS. This improves the semiconductor device 1's ability to discharge carriers such as holes accumulated in the peripheral region 30. This reduces local carrier concentration (current concentration) at the active edge. Furthermore, the diode region 20 can suppress conductivity modulation when the IGBT 1a is turned on, thereby reducing the amount of carriers. This improves breakdown resistance.

[0082] Furthermore, the semiconductor device 1 has an N++ cathode layer 66 not only on the back surface 52 of the diode region 20 but also on the back surface 52 of the peripheral region 30. Therefore, the semiconductor device 1 can suppress the formation of a parasitic pnp bipolar in the peripheral region 30. As a result, the semiconductor device 1 can suppress leakage current. This can suppress heat generation and improve breakdown resistance. Meanwhile, when the diode 1bcd is turned on, electrons are also supplied from the peripheral region 30. This allows the semiconductor device 1 to reduce the forward voltage VF.

[0083] Furthermore, in the semiconductor device 1, the width of the portion of the diode region 20 far from the gate electrode 40 is made larger than the width of the portion close to the gate electrode 40. This reduces the gate wiring resistance and gate delay, thereby suppressing the potential difference between the emitter pads.

[0084] The semiconductor device 1 also has an interrupted trench structure with a shear contact at the portion where the diode region 20 and the peripheral region 30 are connected. That is, the diode region 20 has a plurality of rectangular cylindrical trench electrodes 68 arranged separately. This allows carriers to move between the rectangular cylindrical trench electrodes 68, thereby suppressing local carrier concentration (current concentration) at the active end of the IGBT region 10.

[0085] (Embodiment 2) Next, a semiconductor device according to a second embodiment will be described. In the semiconductor device of this embodiment, the semiconductor substrate has an internal diode region arranged inside the IGBT region 10 so as to separate the IGBT region 10 surrounded by the diode region 20. Fig. 14 is a plan view illustrating an example of a front surface of the semiconductor substrate in the semiconductor device according to the second embodiment. Fig. 15 is a plan view illustrating an example of a back surface of the semiconductor substrate in the semiconductor device according to the second embodiment.

[0086] 14 and 15, the semiconductor device 2 further includes an internal diode region 20a. The internal diode region 20a is arranged inside the IGBT region 10 so as to divide the IGBT region 10. A plurality of internal diode regions 20a may be arranged inside the IGBT region 10. The internal diode region 20a extends in the Y-axis direction. The internal diode region 20a is connected to the diode region 20. Specifically, one end of the internal diode region 20a on the +Y-axis direction side is connected to the region 23, and the other end of the internal diode region 20a on the −Y-axis direction side is connected to the region 24.

[0087] The internal diode region 20a is provided with a plurality of diodes 1bcd. The plurality of diodes 1bcd may be at least one of diodes 1b, 1c, and 1d. The diode 1d can use the same trench as the IGBT 1a, thereby reducing manufacturing costs.

[0088] According to this embodiment, when the IGBT 1a is turned on, the internal diode region 20a can suppress the conductivity modulation and the amount of carriers, thereby improving the breakdown voltage. Other configurations and effects are included in the description of the first embodiment.

[0089] (Embodiment 3) Next, a semiconductor device according to a third embodiment will be described. In the semiconductor device of this embodiment, the N++ cathode layer 66 is not provided on the back surface 52 of the peripheral region 30. The N+ type field stop layer 57 is connected to the collector electrode. Figure 16 is a cross-sectional view illustrating the semiconductor device according to the third embodiment, showing a cross section at a position similar to the VV line in Figure 4.

[0090] 16 , in the semiconductor device 3 of this embodiment, the semiconductor substrate 50 in the peripheral region 30 has an N− type drift layer 53, an N+ type field stop layer 57, and a P type floating layer 59. The P type floating layer 59 is provided closer to the front surface 51 than the N− type drift layer 53. The N+ type field stop layer 57 is provided closer to the back surface 52 than the N− type drift layer 53. The N+ type field stop layer is connected to the collector electrode 42.

[0091] According to this embodiment, a Schottky barrier is formed between the semiconductor substrate 50 in the peripheral region 30 and the collector electrode 42. This reduces the leakage current caused by holes from the collector electrode 42 to the emitter electrode 41. By forming a Schottky barrier on the back surface 52 of the peripheral region 30, carrier injection during avalanche can be suppressed. Other configurations and effects are included in the descriptions of the first and second embodiments.

[0092] (Embodiment 4) Next, a semiconductor device according to a fourth embodiment will be described. The semiconductor device 1 according to the first embodiment includes a plurality of diodes 1c at the junction with the peripheral region 30 in a region 21 on the X-axis direction side of the diode region 20. The diodes 1c have a trench intermittent structure with a share contact. The semiconductor device 1 according to the first embodiment also includes a plurality of diodes 1d that use the same trench as the IGBT 1a in regions 23 and 24 on the Y-axis direction side of the diode region 20. In contrast, the semiconductor device according to the present embodiment includes diodes 1c in regions 23 and 24 of the diode region 20. FIG. 17 is a plan view illustrating a semiconductor device according to the fourth embodiment, showing a plane at the same position as line VII-VII in FIG. 4.

[0093] 17, in the semiconductor device 4 of this embodiment, the regions 23 and 24 in the diode region 20 include a plurality of diodes 1c. As described above, this embodiment has a structure in which an intermittent trench structure having a share contact is additionally provided in the regions 23 and 24. The configuration shown in FIG. 7 is arranged in the region surrounded by the dotted line in FIG. 17.

[0094] According to this embodiment, regions 23 and 24 also include multiple diodes 1c with a trench interrupted structure having share contacts, so that carriers can move between the diodes 1c, thereby suppressing local carrier concentration (current concentration) at the active end of the IGBT region 10. Other configurations and effects are included in the descriptions of embodiments 1 to 3.

[0095] (Embodiment 5) Next, a semiconductor device according to a fifth embodiment will be described. In the semiconductor device of this embodiment, the trench electrode 60 of the diode 1b is controlled as a second gate different from the gate of the IGBT 1a. FIG. 18 is a cross-sectional view illustrating the semiconductor device according to the fifth embodiment, showing a cross section at the same position as line VV in FIG. 4. FIG. 19 is a circuit diagram illustrating the connection of an RC-IGBT in the semiconductor device according to the fifth embodiment. FIG. 20 is a graph illustrating the voltages of the trench electrode 61 of the IGBT 1a and the trench electrode 63 of the diode 1b in the semiconductor device according to the fifth embodiment, where the horizontal axis represents time and the vertical axis represents voltage. FIGS. 21 to 23 are diagrams illustrating the discharge of carriers in the semiconductor device according to the fifth embodiment.

[0096] As shown in FIG. 18 , in the semiconductor device 5 of this embodiment, a pair of trench electrodes 60 of the IGBT 1a includes a trench electrode 61 and a trench electrode 62. The trench electrode 61 is connected to the gate electrode 40 via a gate wiring (not shown). The N+ type emitter layer 56, the P type channel layer 55, and the trench electrode 62 are connected to the emitter electrode 41 via an emitter wiring. The diode 1b includes two trench electrodes 60. Each trench electrode 60 is connected to another gate electrode different from the gate electrode 40 via another gate wiring. The trench electrode 60 connected to another gate electrode is called a trench electrode 63. Therefore, a pair of trench electrodes 60 in the plurality of diodes 1b includes two trench electrodes 63.

[0097] 19, the semiconductor device 5 has, for example, an RC-IGBTA and an RC-IGBTB. The RC-IGBTA has an IBGT1a and a diode 1b. The diode 1b of the RC-IGBTA is called DIODEA. The RC-IGBTB has an IBGT1a and a diode 1b. The diode 1b of the RC-IGBTB is called DIODEB.

[0098] As shown in the upper part of FIG. 20, in an RC-IGBT, a negative voltage is applied to a trench electrode 63 (called VG2) of the DIODEA, and then a negative voltage is applied to a trench electrode 61 (called VG1) of the IGBT 1a. Specifically, a negative voltage is applied to the trench electrode 63 immediately before the IGBT 1a is turned off. In this way, applying a negative voltage to the trench electrode 63 immediately before the IGBT 1a is turned off can improve the carrier sweep effect. This can improve the breakdown voltage of the IGBT 1a. In addition, the forward voltage VF can be reduced.

[0099] Furthermore, after applying a positive voltage to trench electrode 63, a positive voltage is applied to trench electrode 61. Specifically, a positive voltage is applied to trench electrode 63 immediately before IGBT 1a turns on. By applying a positive voltage to trench electrode 63 immediately before IGBT 1a turns on in this way, reverse recovery loss Err can be reduced and diode performance can be improved. The RC-IGTB operates in a similar manner to the RC-IGBTTA, although the timing is different.

[0100] The operation of the RC-IGBT A at times T1 to T3 in Fig. 20 will be described with reference to the drawings. As shown in Fig. 20, when a positive voltage is applied to the trench electrode 63 (VG2) at time T1, the parasitic P-MOS of the diode 1b (DIODEA) is off, as shown in Fig. 21. Therefore, carrier emission from the diode 1b (DIODEA) is suppressed.

[0101] As shown in Fig. 20, when a negative voltage is applied to the trench electrode 63 (VG2) at time T2, the parasitic P-MOS of the diode 1b (DIODEA) turns on as shown in Fig. 22. Therefore, the diode 1b (DIODEA) starts discharging carriers.

[0102] As shown in Fig. 20, when the IGBT1a (RC-IGBT1) is turned off at time T3, the carrier injection from the rear surface 52 stops as shown in Fig. 23. The accumulated carriers are discharged through the parasitic P-MOS of the diode 1b (DIODEA).

[0103] According to this embodiment, when the IGBT 1a is turned off, a negative voltage is applied to the trench electrode 63 immediately before the turn-off, thereby improving the carrier sweep-out effect. This improves the breakdown voltage of the IGBT 1a. It also reduces the forward voltage VF. On the other hand, by applying a positive voltage to the trench electrode 63 immediately before the turn-on of the IGBT 1a, it is possible to suppress the carrier discharge effect and reduce the reverse recovery loss Err. Other configurations and effects are included in the descriptions of the first to fourth embodiments.

[0104] (Embodiment 6) Next, a semiconductor device according to embodiment 6 will be described. The semiconductor device according to this embodiment has a planar gate in the peripheral region 30. Fig. 24 is a cross-sectional view illustrating a semiconductor substrate in the peripheral region in the semiconductor device according to embodiment 6.

[0105] As shown in FIG. 24, in the semiconductor device 6 of this embodiment, the semiconductor substrate 50 in the peripheral region 30 has an N-type drift layer 53, multiple P-type floating layers 59, an insulating film 64, a planar gate 69, an N+ type field stop layer 57, and an N++ type cathode layer 66.

[0106] The multiple P-type floating layers 59 are provided on the N-type drift layer 53. The multiple P-type floating layers 59 are provided so as to sandwich a part of the N-type drift layer 53 in the X-axis direction. The insulating film 64 is provided on the N-type drift layer 53 and on adjacent P-type floating layers 59.

[0107] The planar gate 69 is provided on the N- type drift layer 53 and the adjacent P-type floating layer 59 via an insulating film 64. The N+ type field stop layer 57 is provided closer to the back surface 52 than the N- type drift layer 53. The N++ type cathode layer 66 is provided closer to the back surface 52 than the N+ type field stop layer 57.

[0108] In the semiconductor device 6 of this embodiment, when turning off the IGBT 1a, a negative voltage is applied to the planar gate 69. By applying a negative voltage to the planar gate 69, holes also flow through a path via the P-type floating layer 59. This expands the anode region, and the forward voltage VF can be reduced.

[0109] According to this embodiment, when the IGBT 1a is turned off, a negative voltage can be applied to the planar gate 69, so that accumulated carriers can be discharged also from the path via the P-type floating layer 59. This improves the carrier discharge effect. Other configurations and effects are included in the descriptions of the first to fifth embodiments.

[0110] The present invention has been specifically described above based on the embodiments, but it goes without saying that the present invention is not limited to the above embodiments and can be modified in various ways without departing from the spirit of the invention. Furthermore, combinations of the configurations of embodiments 1 to 6 are also within the scope of the technical idea. [Explanation of symbols]

[0111] 1, 2, 3, 4, 5, 6 Semiconductor device 1a IGBT 1b, 1c, 1d, 1bcd diodes 10 IGBT area 11, 12, 13 areas 20 Diode Region 20a Internal diode region 21, 22a, 22b, 23, 24 areas 30 Surrounding Area 31, 32, 33, 34 area 40 gate electrode 41 Emitter electrode 50 Semiconductor substrate 51 Surface 52 Back side 53 N-type drift layer 53a N-type semiconductor layer 54 N+ type barrier layer 55 P-type channel layer 56 N+ type emitter layer 57 N+ type field stop layer 58 P++ type collector layer 59 P-type floating layer 60, 61, 62, 63 Trench electrodes 64 insulating film 65 Trench insulating film 66 N++ type cathode layer 67 Connected trench electrode 68 Square tube trench electrode 69 Planar Gate 101 Semiconductor device 110 IGBT area 120 Diode Region 130 Surrounding Area 141 Emitter electrode 142 Collector electrode 150 Semiconductor substrate 151 Surface 152 Back side 153 N-type drift layer 157 N+ type field stop layer 158 P+ type collector layer 159 P-type semiconductor layer 164 insulating film 169 Depletion Layer

Claims

1. a semiconductor substrate having a first main surface and a second main surface opposite the first main surface; When viewed from the first main surface side, the semiconductor substrate has an IGBT region including a plurality of IGBTs formed on the semiconductor substrate; a diode region that is arranged to surround the IGBT region and includes a plurality of diodes formed on the semiconductor substrate; a peripheral region arranged to surround the diode region; and The IGBT is a drift layer of a first conductivity type; a barrier layer of a first conductivity type provided closer to the first main surface than the drift layer; a second conductivity type channel layer provided on the first main surface side of the barrier layer; an emitter layer of a first conductivity type provided closer to the first main surface than the channel layer; a pair of trench electrodes provided so as to sandwich the barrier layer, the channel layer, and the emitter layer from both sides in one direction in a plane parallel to the first main surface; a trench insulating film provided between the trench electrode and the drift layer, the barrier layer, the channel layer, and the emitter layer; a field stop layer of a first conductivity type provided closer to the second main surface than the drift layer; a collector layer of a second conductivity type provided closer to the second principal surface than the field stop layer; and The diode is the drift layer of a first conductivity type; a semiconductor layer of a first conductivity type provided closer to the first main surface than the drift layer; the channel layer of a second conductivity type provided closer to the first major surface than the semiconductor layer; a pair of trench electrodes provided to sandwich the semiconductor layer and the channel layer from both sides in the one direction; the trench insulating film provided between the trench electrode and the drift layer, the semiconductor layer, and the channel layer; the field stop layer of the first conductivity type provided closer to the second main surface than the drift layer; a cathode layer of a first conductivity type provided closer to the second principal surface than the field stop layer; and the diode region includes a plurality of other diodes formed in the semiconductor substrate; The other diode is the drift layer; the semiconductor layer of a first conductivity type provided closer to the first main surface than the drift layer; the channel layer of a second conductivity type provided closer to the first major surface than the semiconductor layer; a rectangular cylindrical trench electrode provided to sandwich the semiconductor layer and the channel layer from both sides in the one direction and to sandwich the semiconductor layer and the channel layer from both sides in another direction intersecting the one direction; the trench insulating film provided between the rectangular cylindrical trench electrode, the drift layer, the semiconductor layer, and the channel layer; the field stop layer of the first conductivity type provided closer to the second main surface than the drift layer; the cathode layer of the first conductivity type provided on the second principal surface side of the field stop layer; having Semiconductor device.

2. The semiconductor substrate in the peripheral region is the drift layer; a floating layer of a second conductivity type provided closer to the first main surface than the drift layer; the field stop layer of the first conductivity type provided closer to the second main surface than the drift layer; the cathode layer of the first conductivity type provided on the second principal surface side of the field stop layer; having The semiconductor device according to claim 1 .

3. a semiconductor substrate having a first main surface and a second main surface opposite the first main surface; When viewed from the first main surface side, the semiconductor substrate has an IGBT region including a plurality of IGBTs formed on the semiconductor substrate; a diode region that is arranged to surround the IGBT region and includes a plurality of diodes formed on the semiconductor substrate; a peripheral region arranged to surround the diode region; and The IGBT is a drift layer of a first conductivity type; a barrier layer of a first conductivity type provided closer to the first main surface than the drift layer; a second conductivity type channel layer provided on the first main surface side of the barrier layer; an emitter layer of a first conductivity type provided closer to the first main surface than the channel layer; a pair of trench electrodes provided so as to sandwich the barrier layer, the channel layer, and the emitter layer from both sides in one direction in a plane parallel to the first main surface; a trench insulating film provided between the trench electrode and the drift layer, the barrier layer, the channel layer, and the emitter layer; a field stop layer of a first conductivity type provided closer to the second main surface than the drift layer; a collector layer of a second conductivity type provided closer to the second principal surface than the field stop layer; and The diode is the drift layer of a first conductivity type; a semiconductor layer of a first conductivity type provided closer to the first main surface than the drift layer; the channel layer of a second conductivity type provided closer to the first major surface than the semiconductor layer; a pair of trench electrodes provided to sandwich the semiconductor layer and the channel layer from both sides in the one direction; the trench insulating film provided between the trench electrode and the drift layer, the semiconductor layer, and the channel layer; the field stop layer of the first conductivity type provided closer to the second main surface than the drift layer; a cathode layer of a first conductivity type provided closer to the second principal surface than the field stop layer; and When viewed from the first main surface side, The diode region is a first portion disposed between one end of the IGBT region in the one direction and the peripheral region; a second portion disposed between the other end of the IGBT region in the one direction and the peripheral region; a third portion disposed between one end of the IGBT region in another direction intersecting the one direction and the peripheral region; a fourth portion disposed between the other end of the IGBT region in the other direction and the peripheral region; and an emitter electrode provided on the first main surface via an insulating film; a gate electrode provided on the first main surface via the insulating film and arranged closer to the other end in the one direction than the IGBT region; a collector electrode provided on the second main surface; Furthermore, a width of the first portion separating the IGBT region and the peripheral region in the one direction is larger than a width of the second portion separating the IGBT region and the peripheral region in the one direction; Semiconductor device.

4. a width of the first portion separating the IGBT region and the peripheral region in the one direction is larger than a width of the third portion separating the IGBT region and the peripheral region in the other direction; The semiconductor device according to claim 3 .

5. the pair of trench electrodes of the IGBT includes a first trench electrode and a second trench electrode; the pair of trench electrodes of the diode includes two of the second trench electrodes; the first trench electrode is connected to the gate electrode; the emitter layer, the channel layer, and the second trench electrode are connected to the emitter electrode; The semiconductor device according to claim 3 .

6. the diode region includes a plurality of other diodes formed in the semiconductor substrate; The other diode is the drift layer; the semiconductor layer of a first conductivity type provided closer to the first main surface than the drift layer; the channel layer of a second conductivity type provided closer to the first major surface than the semiconductor layer; a rectangular cylindrical trench electrode provided to sandwich the semiconductor layer and the channel layer from both sides in the one direction and to sandwich the semiconductor layer and the channel layer from both sides in another direction intersecting the one direction; the trench insulating film provided between the rectangular cylindrical trench electrode, the drift layer, the semiconductor layer, and the channel layer; the field stop layer of the first conductivity type provided closer to the second main surface than the drift layer; the cathode layer of the first conductivity type provided on the second principal surface side of the field stop layer; and the pair of trench electrodes of the IGBT includes a first trench electrode and a second trench electrode; the first trench electrode is connected to the gate electrode; the emitter layer, the channel layer, the second trench electrode, and the rectangular cylindrical trench electrode are connected to the emitter electrode; The semiconductor device according to claim 3 .

7. The IGBT is a floating layer of a second conductivity type provided on the opposite side of the barrier layer, the channel layer, and the emitter layer with the trench electrode interposed therebetween; The other diode is The floating layer of the second conductivity type is provided on the opposite side of the semiconductor layer and the channel layer with the rectangular cylindrical trench electrode interposed therebetween. The semiconductor device according to claim 6.

8. the floating layer between the floating layer at one end in the one direction of the IGBT region and the floating layer at the other end in the one direction is in contact with the first trench electrode and the second trench electrode; The semiconductor device according to claim 7 .

9. a semiconductor substrate having a first main surface and a second main surface opposite the first main surface; When viewed from the first main surface side, the semiconductor substrate has an IGBT region including a plurality of IGBTs formed on the semiconductor substrate; a diode region that is arranged to surround the IGBT region and includes a plurality of diodes formed on the semiconductor substrate; a peripheral region arranged to surround the diode region; and The IGBT is a drift layer of a first conductivity type; a barrier layer of a first conductivity type provided closer to the first main surface than the drift layer; a second conductivity type channel layer provided on the first main surface side of the barrier layer; an emitter layer of a first conductivity type provided closer to the first main surface than the channel layer; a pair of trench electrodes provided so as to sandwich the barrier layer, the channel layer, and the emitter layer from both sides in one direction in a plane parallel to the first main surface; a trench insulating film provided between the trench electrode and the drift layer, the barrier layer, the channel layer, and the emitter layer; a field stop layer of a first conductivity type provided closer to the second main surface than the drift layer; a collector layer of a second conductivity type provided closer to the second principal surface than the field stop layer; and The diode is the drift layer of a first conductivity type; a semiconductor layer of a first conductivity type provided closer to the first main surface than the drift layer; the channel layer of a second conductivity type provided closer to the first major surface than the semiconductor layer; a pair of trench electrodes provided to sandwich the semiconductor layer and the channel layer from both sides in the one direction; the trench insulating film provided between the trench electrode and the drift layer, the semiconductor layer, and the channel layer; the field stop layer of the first conductivity type provided closer to the second main surface than the drift layer; a cathode layer of a first conductivity type provided closer to the second principal surface than the field stop layer; and the diode region includes a plurality of other diodes formed in the semiconductor substrate; The other diode is the drift layer; the semiconductor layer of a first conductivity type provided closer to the first main surface than the drift layer; the channel layer of a second conductivity type provided closer to the first major surface than the semiconductor layer; a rectangular cylindrical trench electrode provided to sandwich the semiconductor layer and the channel layer from both sides in the one direction and to sandwich the semiconductor layer and the channel layer from both sides in another direction intersecting the one direction; the trench insulating film provided between the rectangular cylindrical trench electrode, the drift layer, the semiconductor layer, and the channel layer; the field stop layer of the first conductivity type provided closer to the second main surface than the drift layer; the cathode layer of the first conductivity type provided on the second principal surface side of the field stop layer; and When viewed from the first main surface side, The diode region is a first portion disposed between one end of the IGBT region in the one direction and the peripheral region; a second portion disposed between the other end of the IGBT region in the one direction and the peripheral region; a third portion disposed between one end of the IGBT region in another direction intersecting the one direction and the peripheral region; a fourth portion disposed between the other end of the IGBT region in the other direction and the peripheral region; and At least one of the third portion and the fourth portion includes the other diode. Semiconductor device.

10. a semiconductor substrate having a first main surface and a second main surface opposite the first main surface; When viewed from the first main surface side, the semiconductor substrate has an IGBT region including a plurality of IGBTs formed on the semiconductor substrate; a diode region that is arranged to surround the IGBT region and includes a plurality of diodes formed on the semiconductor substrate; a peripheral region arranged to surround the diode region; and The IGBT is a drift layer of a first conductivity type; a barrier layer of a first conductivity type provided closer to the first main surface than the drift layer; a second conductivity type channel layer provided on the first main surface side of the barrier layer; an emitter layer of a first conductivity type provided closer to the first main surface than the channel layer; a pair of trench electrodes provided so as to sandwich the barrier layer, the channel layer, and the emitter layer from both sides in one direction in a plane parallel to the first main surface; a trench insulating film provided between the trench electrode and the drift layer, the barrier layer, the channel layer, and the emitter layer; a field stop layer of a first conductivity type provided closer to the second main surface than the drift layer; a collector layer of a second conductivity type provided closer to the second principal surface than the field stop layer; and The diode is the drift layer of a first conductivity type; a semiconductor layer of a first conductivity type provided closer to the first main surface than the drift layer; the channel layer of a second conductivity type provided closer to the first major surface than the semiconductor layer; a pair of trench electrodes provided to sandwich the semiconductor layer and the channel layer from both sides in the one direction; the trench insulating film provided between the trench electrode and the drift layer, the semiconductor layer, and the channel layer; the field stop layer of the first conductivity type provided closer to the second main surface than the drift layer; a cathode layer of a first conductivity type provided closer to the second principal surface than the field stop layer; and an emitter electrode provided on the first main surface via an insulating film; a first gate electrode provided on the first main surface via the insulating film; a second gate electrode provided on the first main surface via the insulating film; a collector electrode provided on the second main surface; Furthermore, the pair of trench electrodes of the IGBT includes a first trench electrode and a second trench electrode; the pair of trench electrodes of the diode includes two third trench electrodes; the first trench electrode is connected to the first gate electrode; the emitter layer, the channel layer, and the second trench electrode are connected to the emitter electrode; the third trench electrode is connected to the second gate electrode; Semiconductor device.

11. applying a negative voltage to the third trench electrode, then applying a negative voltage to the first trench electrode; and applying a positive voltage to the third trench electrode, then applying a positive voltage to the first trench electrode. The semiconductor device according to claim 10.

12. a semiconductor substrate having a first main surface and a second main surface opposite the first main surface; When viewed from the first main surface side, the semiconductor substrate has an IGBT region including a plurality of IGBTs formed on the semiconductor substrate; a diode region that is arranged to surround the IGBT region and includes a plurality of diodes formed on the semiconductor substrate; a peripheral region arranged to surround the diode region; and The IGBT is a drift layer of a first conductivity type; a barrier layer of a first conductivity type provided closer to the first main surface than the drift layer; a second conductivity type channel layer provided on the first main surface side of the barrier layer; an emitter layer of a first conductivity type provided closer to the first main surface than the channel layer; a pair of trench electrodes provided so as to sandwich the barrier layer, the channel layer, and the emitter layer from both sides in one direction in a plane parallel to the first main surface; a trench insulating film provided between the trench electrode and the drift layer, the barrier layer, the channel layer, and the emitter layer; a field stop layer of a first conductivity type provided closer to the second main surface than the drift layer; a collector layer of a second conductivity type provided closer to the second principal surface than the field stop layer; and The diode is the drift layer of a first conductivity type; a semiconductor layer of a first conductivity type provided closer to the first main surface than the drift layer; the channel layer of a second conductivity type provided closer to the first major surface than the semiconductor layer; a pair of trench electrodes provided to sandwich the semiconductor layer and the channel layer from both sides in the one direction; the trench insulating film provided between the trench electrode and the drift layer, the semiconductor layer, and the channel layer; the field stop layer of the first conductivity type provided closer to the second main surface than the drift layer; a cathode layer of a first conductivity type provided closer to the second principal surface than the field stop layer; and The semiconductor substrate in the peripheral region is the drift layer; a plurality of second conductivity type floating layers provided on the drift layer so as to sandwich a portion of the drift layer in the one direction; an insulating film provided on the drift layer and on the adjacent floating layer; a planar gate provided on the drift layer and the adjacent floating layer via the insulating film; the field stop layer of the first conductivity type provided closer to the second main surface than the drift layer; the cathode layer of the first conductivity type provided on the second principal surface side of the field stop layer; having Semiconductor device.

13. applying a negative voltage to the planar gate when turning off the IGBT; The semiconductor device according to claim 12.

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