Semiconductor Devices

Abstract

To adjust a threshold voltage of a MISFET by a simple method without increasing the manufacturing cost of a semiconductor device.SOLUTION: In a p-type substrate region KB of a semiconductor substrate, an n-type source region SR, an n-type drain region DR, a p-type body region PB with a higher impurity concentration than the p-type substrate region KB, a p-type body contact region PR with a higher impurity concentration than the p-type body region PB, and an n-type drift region ND with a lower impurity concentration than the n-type drain region DR are formed. On the semiconductor substrate, a gate electrode GE is formed through a gate insulating film. The semiconductor substrate includes a first region RG1 and a second region RG2 alternately disposed in an extending direction of the gate electrode GE. A width W1 of the p-type body region PB overlapping with the gate electrode GE in the second region RG2 is smaller than a width W1 of the p-type body region PB overlapping with the gate electrode GE in the first region RG1.SELECTED DRAWING: Figure 7

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device, and can be suitably used in, for example, a semiconductor device having an LDMOSFET. [Background technology]

[0002] The laterally diffused metal-oxide-semiconductor field effect transistor (LDMOSFET) is a type of MISFET (Metal Insulator Semiconductor Field Effect Transistor). LDMOSFETs have a high drain breakdown voltage.

[0003] Japanese Patent Application Laid-Open No. 2019-117883 (Patent Document 1) describes a technique related to a semiconductor device having an LDMOSFET. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 2019-117883 Summary of the Invention [Problem to be solved by the invention]

[0005] In MISFETs such as LDMOSFETs, the threshold voltage is an important electrical characteristic, and it is necessary to adjust the threshold voltage of the MISFET according to the application of the semiconductor device, etc. Therefore, it is desirable to adjust the threshold voltage of the MISFET by a simple method without increasing the manufacturing cost of the semiconductor device.

[0006] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0007] According to one embodiment, a semiconductor device includes a semiconductor substrate having a surface, a substrate region of a first conductivity type formed in the semiconductor substrate, a first MISFET formed on the surface of the semiconductor substrate, a first source region and a first drain region of a second conductivity type formed in the substrate region and spaced apart from each other, and a first gate electrode formed on the semiconductor substrate between the first source region and the first drain region with a first gate insulating film interposed therebetween. The semiconductor device further includes a first semiconductor region of the first conductivity type formed in the substrate region so as to partially overlap with the first gate electrode in a planar view and having a higher impurity concentration than the substrate region. The semiconductor device further includes a second semiconductor region of the first conductivity type formed in the substrate region so as not to overlap with the first gate electrode in a planar view and adjacent to the first source region. The semiconductor device further includes a third semiconductor region of the second conductivity type formed in the substrate region so as to partially overlap with the first gate electrode in a planar view and having a lower impurity concentration than the first drain region. The first gate electrode extends in a first direction, and the first semiconductor region extends in the first direction so as to cover a bottom surface of the first source region and a bottom surface of the second semiconductor region. The semiconductor substrate has first regions and second regions arranged alternately in the first direction. A width of the first semiconductor region overlapping with the first gate electrode in the second region is smaller than a width of the first semiconductor region overlapping with the first gate electrode in the first region. [Effects of the Invention]

[0008] According to one embodiment, the threshold voltage of a MISFET can be adjusted by a simple method, and the threshold voltage of a MISFET can be adjusted while suppressing the manufacturing cost of a semiconductor device. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a plan view of a main part of a semiconductor device according to a first embodiment. [Figure 2] 1 is a cross-sectional view of a main part of a semiconductor device according to a first embodiment. [Figure 3] 1 is a cross-sectional view of a main part of a semiconductor device according to a first embodiment. [Figure 4] 1 is a cross-sectional view of a main part of a semiconductor device according to a first embodiment. [Figure 5] 1 is a cross-sectional view of a main part of a semiconductor device according to a first embodiment. [Figure 6] 1 is a cross-sectional view of a main part of a semiconductor device according to a first embodiment. [Figure 7] 1 is a plan view of a main part of a semiconductor device according to a first embodiment. [Figure 8] 1 is a cross-sectional view of a main part of a semiconductor device according to a first embodiment. [Figure 9] 1 is a cross-sectional view of a main part of a semiconductor device according to a first embodiment. [Figure 10] 1 is a cross-sectional view of a main part of a semiconductor device according to a first embodiment. [Figure 11] 1 is a cross-sectional view of a main part of a semiconductor device according to a first embodiment. [Figure 12] 1 is a cross-sectional view of a main part of a semiconductor device according to a first embodiment. [Figure 13] 1 is a cross-sectional view of a main part of a semiconductor device according to a first embodiment. [Figure 14] 1 is a plan view of a main part of a semiconductor device according to a first embodiment. [Figure 15] 1 is a cross-sectional view of a main part of a semiconductor device according to a first embodiment. [Figure 16] 2 is a cross-sectional view of a main part of the semiconductor device in the manufacturing process of the first embodiment. FIG. [Figure 17] FIG. 17 is a cross-sectional view of a main part of the semiconductor device during the same manufacturing process as in FIG. 16 [Figure 18] FIG. 18 is a cross-sectional view of a main part of the semiconductor device during the manufacturing process following FIG. [Figure 19] 19 is a cross-sectional view of a main part of the semiconductor device during the same manufacturing process as in FIG. 18. [Figure 20] FIG. 20 is a cross-sectional view of a main part of the semiconductor device during the manufacturing process following FIG. 19. [Figure 21] 21 is a cross-sectional view of a main part of the semiconductor device during the same manufacturing process as in FIG. 20. [Figure 22] FIG. 10 is a plan view of a main part of a semiconductor device according to a first modified example. [Figure 23] FIG. 10 is a plan view of a main part of a semiconductor device according to a second modified example. [Figure 24] FIG. 11 is a plan view of a main part of a semiconductor device according to a third modified example. [Figure 25] FIG. 10 is a plan view of a main part of a semiconductor device according to a second embodiment. [Figure 26] FIG. 10 is a cross-sectional view of a main part of a semiconductor device according to a second embodiment. [Figure 27] FIG. 10 is a cross-sectional view of a main part of a semiconductor device according to a second embodiment. [Figure 28] FIG. 10 is a cross-sectional view of a main part of a semiconductor device according to a second embodiment. [Figure 29] FIG. 10 is a plan view of a main part of a semiconductor device according to a second embodiment. [Figure 30] FIG. 10 is a cross-sectional view of a main part of a semiconductor device according to a second embodiment. [Figure 31] FIG. 10 is a cross-sectional view of a main part of a semiconductor device according to a second embodiment. [Figure 32] FIG. 10 is a cross-sectional view of a main part of a semiconductor device according to a second embodiment. [Figure 33] FIG. 10 is a plan view of a main part of a semiconductor device according to a second embodiment. [Figure 34] FIG. 10 is a cross-sectional view of a main part of a semiconductor device according to a second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0010] In the following embodiments, the description will be divided into multiple sections or embodiments for convenience, as necessary. However, unless otherwise specified, they are not unrelated to one another, and one is a partial or complete modification, detail, supplementary explanation, etc., of the other. Furthermore, in the following embodiments, when the number of elements (including the number, numerical value, amount, range, etc.) is mentioned, it is not limited to the specific number, and may be more or less than the specific number, unless otherwise specified or clearly limited to a specific number in principle. Furthermore, in the following embodiments, it goes without saying that the components (including element steps, etc.) are not necessarily essential, unless otherwise specified or clearly considered essential in principle. Similarly, in the following embodiments, when the shape, positional relationship, etc. of components, etc. are mentioned, it is intended to include those that are substantially similar to or similar to the shape, etc., unless otherwise specified or clearly considered not to be essential in principle. The same applies to the above numerical values ​​and ranges.

[0011] Hereinafter, embodiments will be described in detail with reference to the drawings. In all drawings for explaining the embodiments, components having the same functions are designated by the same reference numerals, and repeated explanations thereof will be omitted. In the following embodiments, explanations of the same or similar parts will not be repeated unless particularly necessary.

[0012] In the drawings used in the embodiments, hatching may be omitted even in cross-sectional views to make the drawings easier to see, and hatching may be added even in plan views to make the drawings easier to see.

[0013] (Embodiment 1) <About the structure of semiconductor devices> A semiconductor device according to a first embodiment will be described with reference to the drawings. FIGS. 1 and 7 are plan views of a main portion of the semiconductor device according to this embodiment, and FIGS. 2 to 6 and 8 to 13 are cross-sectional views of a main portion of the semiconductor device according to this embodiment. FIGS. 2, 8, and 9 show cross sections substantially perpendicular to the gate width direction (Y direction), and FIGS. 3 to 6 and 10 to 13 show cross sections substantially perpendicular to the gate length direction (X direction). The cross-sectional view taken along line A1-A1 in FIG. 1 corresponds approximately to FIG. 2, the cross-sectional view taken along line A3-A3 in FIG. 1 corresponds approximately to FIG. 3, the cross-sectional view taken along line A4-A4 in FIG. 1 corresponds approximately to FIG. 4, the cross-sectional view taken along line A5-A5 in FIG. 1 corresponds approximately to FIG. 5, and the cross-sectional view taken along line A6-A6 in FIG. 1 corresponds approximately to FIG. 6. 7. The cross-sectional view taken along line B1-B1 in FIG. 7 corresponds approximately to FIG. 8, the cross-sectional view taken along line B2-B2 in FIG. 7 corresponds approximately to FIG. 9, the cross-sectional view taken along line B3-B3 in FIG. 7 corresponds approximately to FIG. 10, the cross-sectional view taken along line B4-B4 in FIG. 7 corresponds approximately to FIG. 11, the cross-sectional view taken along line B5-B5 in FIG. 7 corresponds approximately to FIG. 12, and the cross-sectional view taken along line B6-B6 in FIG. 7 corresponds approximately to FIG. 13. Also, FIGS. 1 and 7 show plan views of the surface of the semiconductor substrate SB, with a view through the structure above the gate insulating film GF, gate electrode GE, interlayer insulating film IL, plug PG, wiring M1, and interlayer insulating film IL, which will be described later. Although FIGS. 1 and 7 are plan views, hatching is used to make each region easily distinguishable, and the position of the gate electrode GE is indicated by a dotted line.

[0014] 1 and 7 are directions perpendicular to each other. The X and Y directions are directions along the front surface (main surface) SBa or rear surface of the semiconductor substrate SB, i.e., horizontal directions. Here, the X direction corresponds to the gate length direction of the gate electrode GE of the LDMOSFET, and the Y direction corresponds to the gate width direction of the gate electrode GE of the LDMOSFET.

[0015] The semiconductor device of this embodiment is a semiconductor device having a MISFET, and in this case, the semiconductor device has an LDMOSFET as the MISFET.

[0016] In this application, the terms MOSFET (Metal Oxide Semiconductor Field Effect Transistor) or LDMOSFET include not only MISFETs that use an oxide film (silicon oxide film) as the gate insulating film, but also MISFETs that use an insulating film other than an oxide film as the gate insulating film. LDMOSFET is a type of MISFET element. LDMOSFET is also sometimes called HV-MOSFET (High Voltage Metal Oxide Semiconductor Field Effect Transistor) or DEMOSFET (Drain Extended Metal Oxide Semiconductor Field Effect Transistor). LDMOSFET is used in power conversion circuits such as inverter circuits, and can function as a power switching element.

[0017] The semiconductor device of this embodiment has an element region 1A, which is a region (planar region) where LDMOSFET 1 is formed, and an element region 2A, which is a region (planar region) where LDMOSFET 2 is formed. The element region 1A and the element region 2A correspond to different planar regions of a semiconductor substrate SB. Each of LDMOSFET 1 and LDMOSFET 2 is formed on a surface SBa of the semiconductor substrate SB. Here, a case will be described where LDMOSFET 1 and LDMOSFET 2 are each an n-channel type LDMOSFET.

[0018] The threshold voltage of the LDMOSFET 1 formed in the element region 1A is different from the threshold voltage of the LDMOSFET 2 formed in the element region 2A. More specifically, the threshold voltage of the LDMOSFET 2 formed in the element region 2A is lower than the threshold breakdown voltage of the LDMOSFET 1 formed in the element region 1A. FIG. 1 shows a plan view of the element region 1A, FIGS. 2 to 6 show cross-sectional views of the element region 1A, FIG. 7 shows a plan view of the element region 2A, and FIGS. 8 to 13 show cross-sectional views of the element region 2A.

[0019] The structure of the semiconductor device of this embodiment will be described below.

[0020] The semiconductor substrate SB is a semiconductor substrate made of single crystal silicon or the like. It is preferable to use a p-type semiconductor substrate as the semiconductor substrate SB, but an n-type semiconductor substrate may also be used. An epitaxial wafer, in which an epitaxial semiconductor layer is formed on a semiconductor substrate, may also be used as the semiconductor substrate SB. When an epitaxial wafer is used as the semiconductor substrate SB, a p-type substrate region KB is formed by the epitaxial semiconductor layer.

[0021] The semiconductor substrate SB has a front surface SBa and a back surface SBb, which are main surfaces located on opposite sides of each other. An STI region (element isolation region) 3 is formed on the front surface SBa of the semiconductor substrate SB using an STI (Shallow Trench Isolation) method. The STI region 3 is made of an insulator (insulating film) embedded in a trench formed in the semiconductor substrate SB.

[0022] Alternatively, a LOCOS (LOCal Oxidation of Silicon) method may be used to form a LOCOS region instead of the STI region 3. Alternatively, there may be a case where neither the STI region 3 nor the LOCOS region is formed.

[0023] <<About the structure of the semiconductor device in the element region 1A>> First, the structure of the semiconductor device in the element region 1A will be specifically described with reference to FIGS.

[0024] The semiconductor substrate SB has a p-type substrate region KB. The p-type substrate region KB is a p-type semiconductor region. The p-type substrate region KB may be a p-type semiconductor region formed in a p-type semiconductor substrate, a p-type semiconductor region formed in an n-type semiconductor substrate, or a region that maintains p-type in a p-type semiconductor substrate. The p-type substrate region KB may also be a p-type epitaxial semiconductor layer formed on a p-type or n-type semiconductor substrate. In the semiconductor substrate SB, an n-type buried layer (not shown) may exist below the p-type substrate region KB.

[0025] The element region 1A is contained within a p-type substrate region KB in a planar view. Note that the planar view corresponds to a view taken along a plane substantially parallel to the surface SBa of the semiconductor substrate SB. Therefore, the n-type source region SR, n-type drain region DR, and channel formation region (a region where a channel is formed) of the LDMOSFET 1 formed in the element region 1A are formed within the p-type substrate region KB in a planar view.

[0026] In the semiconductor substrate SB, an n-type drift region (n-type semiconductor region, n-type well) ND and a p-type body region (p-type semiconductor region, p-type well) PB are formed above (in an upper layer portion of) the p-type substrate region KB. The n-type drift region ND and the p-type body region PB are adjacent to or spaced apart from each other in the gate length direction (X direction) of the LDMOSFET1. The gate length direction of the LDMOSFET1 coincides with the channel length direction of the LDMOSFET1, and the gate width direction of the LDMOSFET1 coincides with the channel width direction of the LDMOSFET1.

[0027] Of the n-type drift region ND and the p-type body region PB, the n-type drift region ND is located on the drain side of the LDMOSFET1, and the p-type body region PB is located on the source side of the LDMOSFET1. The n-type drift region ND and the p-type body region PB each reach the surface SBa of the semiconductor substrate SB. The bottom surfaces of the n-type drift region ND and the p-type body region PB are in contact with the p-type substrate region KB. In other words, the bottom surfaces of the n-type drift region ND and the p-type body region PB are covered with the p-type substrate region KB. A PN junction is formed at the boundary between the n-type drift region ND and the p-type substrate region KB. The impurity concentration (p-type impurity concentration) of the p-type body region PB is higher than the impurity concentration (p-type impurity concentration) of the p-type substrate region KB.

[0028] The p-type body region PB is formed to surround the n-type source region SR and the p-type body contact region PR, which will be described later. The p-type body region PB can function as a back gate. The p-type body region PB can also function as a punch-through stopper that suppresses the extension of a depletion layer from the drain to the source of the LDMOSFET 1.

[0029] In the semiconductor substrate SB, an n-type source region SR and a p-type body contact region (p-type semiconductor region) PR are formed in the p-type body region PB. The n-type source region SR is an n-type semiconductor region that functions as the source region of the LDMOSFET 1. Between the n-type source region SR and the n-type drain region DR, a part of the p-type body region PB is located below the gate electrode GE. Between the n-type source region SR and the n-type drain region DR, an upper part (upper layer part) of the p-type body region PB located below the gate electrode GE and an upper part (upper layer part) of the p-type substrate region KB located below the gate electrode GE form a channel formation region of the LDMOSFET 1.

[0030] The n-type source region SR and the p-type body contact region PR each extend in the gate width direction (Y direction) of the LDMOSFET 1, and are adjacent to each other in the gate length direction (X direction) of the LDMOSFET 1. Of the n-type source region SR and the p-type body contact region PR, the n-type source region SR is located on the side adjacent to the channel formation region of the LDMOSFET 1, and the p-type body contact region PR is located on the side farther from the channel formation region of the LDMOSFET 1. In other words, the n-type source region SR is located between the channel formation region and the p-type body contact region PR. The bottom surfaces of the n-type source region SR and the p-type body contact region PR are in contact with the p-type body region PB. In other words, the bottom surfaces of the n-type source region SR and the p-type body contact region PR are covered with the p-type body region PB. In addition, the side surface of the n-type source region SR opposite to the side adjacent to the p-type body contact region PR is in contact with the p-type body region PB. That is, the side surface of the n-type source region SR opposite to the side adjacent to the p-type body contact region PR is covered with the p-type body region PB. Therefore, the p-type body region PB extends in the Y direction while covering the bottom surface of the n-type source region SR, the bottom surface of the p-type body contact region PR, and the side surface of the n-type source region SR (the side surface opposite to the side adjacent to the p-type body contact region PR). The top surfaces of the n-type source region SR and the p-type body contact region PR reach the surface SBa of the semiconductor substrate SB. Also, an LDD (Lightly Doped Drain) structure can be applied to the n-type source region SR.

[0031] The impurity concentration of the p-type body contact region PR is higher than the impurity concentration of the p-type body region PB, and the p-type body contact region PR can function as a contact portion for the p-type body region PB.

[0032] An n-type drain region (n-type semiconductor region) DR is formed in the n-type drift region ND. The n-type drain region DR is an n-type semiconductor region that functions as the drain region of the LDMOSFET 1. The n-type drain region DR extends in the Y direction, and the upper surface of the n-type drain region DR reaches the surface SBa of the semiconductor substrate SB. The impurity concentration of the n-type drain region DR is higher than the impurity concentration of the n-type drift region ND. The n-type drain region DR and the n-type source region SR are spaced apart from each other in the X direction.

[0033] A gate electrode GE of the LDMOSFET 1 is formed on the surface SBa of the semiconductor substrate SB with a gate insulating film GF interposed therebetween. Specifically, the gate electrode GE is formed on the surface SBa of the semiconductor substrate SB between the n-type source region SR and the n-type drain region DR with the gate insulating film GF interposed therebetween. The gate insulating film GF is made of, for example, a silicon oxide film. The gate electrode GE is made of, for example, a single-layer film of a polycrystalline silicon film (doped polysilicon film) or a stacked film of a polycrystalline silicon film and a metal silicide layer.

[0034] In a plan view, an STI region 3 is disposed between the channel formation region and the n-type drain region DR of the LDMOSFET 1, and a portion (a portion on the drain side) of the gate electrode GE is disposed on this STI region 3. That is, a portion of the gate electrode GE is located on the STI region 3. The STI region 3 interposed between the channel formation region and the n-type drain region DR of the LDMOSFET 1 extends in the Y direction, and an n-type drift region ND is present below the STI region 3 interposed between the channel formation region and the n-type drain region DR of the LDMOSFET 1. A bottom surface of the n-type drain region DR is in contact with the n-type drift region ND, and a side surface of the n-type drain region DR is in contact with the STI region 3. In other words, a bottom surface of the n-type drain region DR is covered with the n-type drift region ND, and a side surface of the n-type drain region DR is covered with the STI region 3. Therefore, the n-type drift region ND below the STI region 3 can also function as a conduction path between the channel of the LDMOSFET 1 and the n-type drain region DR.

[0035] 2 shows a case where a gate insulating film GF is interposed between the gate electrode GE and the underlying STI region 3, but there may be a case where the gate insulating film GF is not interposed between the gate electrode GE and the underlying STI region 3. Also, sidewall spacers (not shown) made of an insulating film (e.g., a silicon oxide film) may be formed on both side surfaces of the gate electrode GE.

[0036] The p-type body region PB and the n-type drift region ND each extend in the Y direction, with a portion of the p-type body region PB located below the gate electrode GE and a portion of the n-type drift region ND located below the gate electrode GE. From another perspective, a portion of the gate electrode GE (a portion on the source side) overlaps with the p-type body region PB in a planar view, and another portion of the gate electrode GE (a portion on the drain side) overlaps with the n-type drift region ND in a planar view. Of the p-type body region PB, the portion located below the gate electrode GE (i.e., the portion overlapping with the gate electrode GE in a planar view) extends in the Y direction with a constant width (width in the X direction). Furthermore, of the n-type drift region ND, the portion located below the gate electrode GE (i.e., the portion overlapping with the gate electrode GE in a planar view) extends in the Y direction with a constant width (width in the X direction).

[0037] 2, the p-type substrate region KB is interposed between the p-type body region PB and the n-type drift region ND in the X direction. In this case, the side surface of the n-type drift region ND (the side surface facing the p-type body region PB) contacts the p-type substrate region KB to form a PN junction, and the side surface of the p-type body region PB (the side surface facing the n-type drift region ND) also contacts the p-type substrate region KB.

[0038] As another example, the p-type body region PB and the n-type drift region ND may be in contact with each other in the X direction. In this case, a PN junction is formed at the boundary between the p-type body region PB and the n-type drift region ND.

[0039] The side surface of the n-type drift region ND (the side surface facing the p-type body region PB) is located midway along the gate electrode GE in the X direction and extends in the Y direction.

[0040] In plan view, the gate electrode GE is disposed between the n-type source region SR and the n-type drain region DR. When a voltage equal to or greater than the threshold voltage is applied to the gate electrode GE, an n-type inversion layer is formed in the upper portion (upper layer) of the p-type body region PB located under the gate electrode GE and in the upper portion (upper layer) of the p-type substrate region KB located under the gate electrode GE. This n-type inversion layer functions as a channel (channel region). The n-type source region SR and the n-type drain region DR are electrically connected via the channel and the n-type drift region ND.

[0041] In the X direction, an n-type drift region ND having a lower impurity concentration (n-type impurity concentration) than the n-type drain region DR is interposed between the p-type body region PB and the n-type drain region DR. Therefore, an n-type drift region ND having a lower impurity concentration than the n-type drain region DR is present between the channel formation region of the LDMOSFET 1 and the n-type drain region DR. Therefore, in the X direction, a channel formation region and the n-type drift region ND are present between the n-type source region SR and the n-type drain region DR, with the channel formation region located on the n-type source region SR side and the n-type drift region ND located on the n-type drain region DR side. In addition, the p-type substrate region KB below the n-type drift region ND and the p-type body region PB can function as a resurf layer (resurf region).

[0042] In addition, a metal silicide layer (not shown) may be formed on the upper portion (surface portion) of each of the n-type drain region DR, the n-type source region SR, and the p-type body contact region PR. This metal silicide layer can be formed by using a salicide (Self Aligned Silicide) technique.

[0043] In this embodiment, the n-type drain region DR is in contact with the n-type drift region ND. As a result, the n-type drain region DR and the n-type drift region ND are electrically connected to each other. As another example, the n-type drain region DR may not be in contact with the n-type drift region ND, and an n-type semiconductor region having a higher impurity concentration than the n-type drift region ND and a lower impurity concentration than the n-type drain region DR may be interposed between the n-type drain region DR and the n-type drift region ND. In this case, the n-type drain region DR and the n-type drift region ND are electrically connected to each other via the n-type semiconductor region interposed therebetween. In either case, the n-type drain region DR and the n-type drift region ND are electrically connected to each other.

[0044] <<About the structure of the semiconductor device in the element region 2A>> Next, the structure of the semiconductor device in the element region 2A will be specifically described with reference to Figures 7 to 13. Note that the following description will focus on the differences between the structure of the semiconductor device in the element region 2A and the structure of the semiconductor device in the element region 1A, and a repeated description of the commonalities between the structure of the semiconductor device in the element region 2A and the structure of the semiconductor device in the element region 1A will be omitted.

[0045] The structure of the semiconductor device in element region 2A differs from the structure of the semiconductor device in element region 1A in the region where the p-type body region PB is formed. Except for the region where the p-type body region PB is formed, the structure of the semiconductor device in element region 2A is basically the same as the structure of the semiconductor device in element region 1A. Therefore, the cross-sectional structure of FIG. 10 is substantially the same as the cross-sectional structure of FIG. 3, the cross-sectional structure of FIG. 11 is substantially the same as the cross-sectional structure of FIG. 4, and the cross-sectional structure of FIG. 13 is substantially the same as the cross-sectional structure of FIG. 6. Hereinafter, the p-type body region PB formed in the semiconductor substrate SB in element region 2A will be referred to as p-type body region PB2, and the p-type body region PB formed in the semiconductor substrate SB in element region 1A will be referred to as p-type body region PB1. Furthermore, while the LDMOSFET formed in element region 1A was previously referred to as LDMOSFET1, the LDMOSFET formed in element region 2A will be referred to as LDMOSFET2.

[0046] In the element region 2A, a region RG1 having the cross-sectional structure shown in Fig. 8 and a region RG2 having the cross-sectional structure shown in Fig. 9 are alternately repeated in the gate width direction (Y direction) of the LDMOSFET 2. That is, in the element region 2A, in the Y direction, a region RG2 having the cross-sectional structure shown in Fig. 9 is located next to a region RG1 having the cross-sectional structure shown in Fig. 8, and a region RG1 having the cross-sectional structure shown in Fig. 8 is located next to a region RG2 having the cross-sectional structure shown in Fig. 9. Fig. 8 is a cross-sectional view of region RG1 (cross-sectional view perpendicular to the Y direction), and Fig. 9 is a cross-sectional view of region RG2 (cross-sectional view perpendicular to the Y direction).

[0047] The cross-sectional structure shown in Fig. 8 is substantially the same as the cross-sectional structure shown in Fig. 2. On the other hand, the cross-sectional structure shown in Fig. 9 differs from the cross-sectional structure shown in Fig. 8 in the formation region of the p-type body region PB2.

[0048] 8 and 9, what is common to the cross-sectional structure of the formation region of the p-type body region PB2 is that the p-type body region PB2 exists below the n-type source region SR and the p-type body contact region PR, and the bottom surfaces of the n-type source region SR and the p-type body contact region PR are in contact with the p-type body region PB2 (and therefore are covered by the p-type body region PB2). Therefore, in the element region 2A in which the region RG1 having the cross-sectional structure shown in Fig. 8 and the region RG2 having the cross-sectional structure shown in Fig. 9 are repeated in the Y direction, the p-type body region PB2 extends in the Y direction while covering the bottom surfaces of the n-type source region SR and the p-type body contact region PR (see Figs. 8 to 11).

[0049] However, the width W1 of the p-type body region PB overlapping with the gate electrode GE differs between the region RG1 having the cross-sectional structure shown in FIG. 8 and the region RG2 having the cross-sectional structure shown in FIG. 9. Here, the width of the p-type body region PB overlapping with the gate electrode GE in a plan view (i.e., the width of the portion of the p-type body region PB located below the gate electrode GE) will be referred to as the width W1 of the p-type body region PB overlapping with the gate electrode GE. Note that the width W1 of the p-type body region PB overlapping with the gate electrode GE corresponds to the width (dimension) in the X direction. The width W1 is shown in FIGS. 1 and 7.

[0050] In this embodiment, as can be seen from FIG. 7, the width W1 of the p-type body region PB (PB2) overlapping with the gate electrode GE in region RG2 is smaller than the width W1 of the p-type body region PB (PB2) overlapping with the gate electrode GE in region RG1.

[0051] In the element region 1A, the width W1 of the p-type body region PB (PB1) overlapping with the gate electrode GE is substantially constant regardless of the position in the Y direction. That is, in the element region 1A, when a cross section perpendicular to the Y direction is viewed, the width W1 is substantially the same (constant) regardless of the position in the cross section in the Y direction. Therefore, in the element region 1A, the p-type body region PB1 extends in the Y direction so as to cover the bottom surfaces of the n-type source region SR and the p-type body contact region PR, and to overlap with the gate electrode GE by a constant width (W1) in plan view.

[0052] 8, the width W1 of the p-type body region PB (PB2) overlapping with the gate electrode GE is substantially constant regardless of the position in the Y direction and is substantially the same as the width W1 of the p-type body region PB1 overlapping with the gate electrode GE in the element region 1A. That is, when a cross section perpendicular to the Y direction is viewed in the region RG1 of the element region 1A, the width W1 is substantially the same (constant) regardless of the position in the Y direction. On the other hand, in the element region 2A, the width W1 of the p-type body region PB (PB2) overlapping with the gate electrode GE in the region RG2 having the cross-sectional structure of FIG. 9 is smaller than the width W1 of the p-type body region PB (PB2) overlapping with the gate electrode GE in the region RG1 having the cross-sectional structure of FIG. From another perspective, compared to region RG1 of element region 2A, in region RG2 of element region 2A, end TB1 of p-type body region PB2 (end facing n-type drift region ND) is set back in the X direction in plan view so that width W1 of p-type body region PB2 overlapping with gate electrode GE is smaller. From yet another perspective, in the X direction, minimum distance L3 between p-type body region PB2 and n-type drift region ND in region RG2 is greater than minimum distance L2 between p-type body region PB2 and n-type drift region ND in region RG1 (i.e., L3>L2).

[0053] The width W1 of the p-type body region PB2 overlapping with the gate electrode GE in the region RG2 may be zero (W1=0). Note that the width W1 of the p-type body region PB2 overlapping with the gate electrode GE in the region RG2 being zero (W1=0) means that the p-type body region PB2 does not overlap with the gate electrode GE in the region RG2 in a planar view. From another perspective, the width W1 of the region RG2 being zero (W1=0) means that the p-type body region PB2 is not located below the gate electrode GE in the region RG2.

[0054] 14 and 15 are a plan view (FIG. 14) and a cross-sectional view (FIG. 15) of the element region 2A when the width W1 of the p-type body region PB2 overlapping with the gate electrode GE in region RG2 is zero (W1=0). On the other hand, FIGS. 7 and 9 are a plan view (FIG. 7) and a cross-sectional view (FIG. 9) of the element region 2A when the width W1 of the p-type body region PB2 overlapping with the gate electrode GE in region RG2 is greater than zero (W1>0).

[0055] Note that Fig. 14 corresponds to Fig. 7, and Fig. 15 is a cross-sectional view taken along line B2-B2 in Fig. 14. The cross-sectional view taken along line B1-B1 in Fig. 14 is similar to Fig. 8, the cross-sectional view taken along line B3-B3 in Fig. 14 is similar to Fig. 10, the cross-sectional view taken along line B4-B4 in Fig. 14 is similar to Fig. 11, the cross-sectional view taken along line B5-B5 in Fig. 14 is similar to Fig. 12, and the cross-sectional view taken along line B6-B6 in Fig. 14 is similar to Fig. 13.

[0056] 14, in region RG1, a portion of the p-type body region PB2 overlaps with the gate electrode GE in a planar view, but in region RG2, the p-type body region PB2 does not overlap with the gate electrode GE in a planar view. In this case, as shown in FIG. 8 above, a portion of the p-type body region PB2 is located below the gate electrode GE in region RG1, whereas as shown in FIG. 15, in region RG2, the p-type body region PB2 is not formed (located) below the gate electrode GE. From another perspective, in the case of FIG. 14, in region RG1 of the element region 2A, the end TB1 (the end facing the n-type drift region ND) of the p-type body region PB2 overlaps with the gate electrode GE in a planar view, but in region RG2 of the element region 2A, the end TB1 (the end facing the n-type drift region ND) of the p-type body region PB2 does not overlap with the gate electrode GE in a planar view and is therefore exposed from the gate electrode GE. That is, in the case of FIG. 14, in the region RG2, the end TB1 of the p-type body region PB2 closest to the n-type drift region ND in the X direction is exposed from the gate electrode GE.

[0057] Comparing FIG. 8 with FIG. 9 (or FIG. 15), in the portion where the p-type body region PB2 is formed in FIG. 8 but the p-type body region PB2 is not formed in FIG. 9 (or FIG. 15), the p-type substrate region KB exists in FIG. 9 (or FIG. 15).

[0058] Therefore, in the cross-sectional structure shown in FIG. 8 (hence region RG1) and the cross-sectional structure shown in FIG. 9 (hence region RG2), the surface portion of the semiconductor substrate SB below the gate electrode GE is composed of the n-type drift region ND, the p-type substrate region KB, and the p-type body region PB. Therefore, in the cross-sectional structure (region RG1) shown in FIG. 8 and the cross-sectional structure (region RG2) shown in FIG. 9, the upper portion (upper layer portion) of the p-type body region PB located below the gate electrode GE and the upper portion (upper layer portion) of the p-type substrate region KB located below the gate electrode GE function as the channel formation region CN of the LDMOSFET 2. That is, in the cross-sectional structure (region RG1) shown in FIG. 8 and the cross-sectional structure (region RG2) shown in FIG. 9, the channel formation region CN of the LDMOSFET 2 is composed of the p-type body region PB and the p-type substrate region KB. Note that in FIGS. 8, 9, and 15, the position of the channel formation region CN is schematically indicated by a dotted line.

[0059] However, as described above, the width W1 in the region RG2 is smaller than the width W1 in the region RG1. Reflecting this, the proportion of the p-type body region PB in the channel formation region CN in the cross-sectional structure shown in FIG. 9 (hence, region RG2) is smaller than the proportion of the p-type body region PB in the channel formation region CN in the cross-sectional structure shown in FIG. 8 (hence, region RG1).

[0060] 15 (hence, region RG2), the surface layer portion of the semiconductor substrate SB below the gate electrode GE is composed of the n-type drift region ND and the p-type substrate region KB, and the upper portion (upper layer portion) of the p-type substrate region KB located below the gate electrode GE functions as the channel formation region CN of the LDMOSFET 2. In other words, in the cross-sectional structure shown in Fig. 9 (hence, region RG2), the channel formation region CN of the LDMOSFET 2 is composed of the p-type substrate region KB, and the p-type body region PB does not function as a channel formation region.

[0061] 8 (hence, region RG1) and the cross-sectional structure shown in FIG. 9 (hence, region RG2), when a voltage equal to or greater than the threshold voltage is applied to the gate electrode GE, an n-type inversion layer (channel) is formed in the upper part (upper layer) of the p-type body region PB located below the gate electrode GE and in the upper part (upper layer) of the p-type substrate region KB located below the gate electrode GE. On the other hand, in the cross-sectional structure shown in FIG. 15 (hence, region RG2), when a voltage equal to or greater than the threshold voltage is applied to the gate electrode GE, an n-type inversion layer (channel) is formed in the upper part (upper layer) of the p-type substrate region KB located below the gate electrode GE. The n-type source region SR and the n-type drain region DR are electrically connected via the n-type inversion layer (channel) and the n-type drift region ND.

[0062] 7 and 14, as an example, four regions RG1 and four regions RG2 are arranged alternately in the Y direction, but the number of regions RG1 and RG2 can be changed as needed. For example, if the gate width of the LDMOSFET is large, the dimension of the element region 2A in the Y direction increases, and therefore the number of regions RG1 and RG2 increases. In any case, there are multiple regions RG1 and multiple regions RG2 in the element region 2A, and the regions RG1 and RG2 are arranged so that they are adjacent to each other in the Y direction.

[0063] <<About the structure on the semiconductor substrate>> Next, the structure on the semiconductor substrate SB will be described.

[0064] As shown in Figures 2 to 6, 8 to 13, and 15, an interlayer insulating film IL is formed on the surface of the semiconductor substrate SB so as to cover the gate electrode GE. The interlayer insulating film IL is made of, for example, a silicon oxide film. The interlayer insulating film IL can also be formed of a stacked film of a relatively thin silicon nitride film and a relatively thick silicon oxide film on the silicon nitride film. The upper surface of the interlayer insulating film IL is flattened.

[0065] Contact holes (through holes) are formed in the interlayer insulating film IL, and conductive plugs (contact plugs) PG made mainly of a tungsten (W) film are formed (embedded) in the contact holes. A plurality of plugs PG are provided, and each plug PG penetrates the interlayer insulating film IL. The plugs PG are formed on the n-type source region SR, the n-type drain region DR, and the p-type body contact region PR, respectively.

[0066] The plug PG can also be disposed on the gate electrode GE, but the cross-sectional views of FIGS. 2 to 6, 8 to 13, and 15 do not show the plug PG on the gate electrode GE.

[0067] The plug PG arranged on the n-type drain region DR is in contact with the n-type drain region DR and is thereby electrically connected to the n-type drain region DR1. The plug PG arranged on the n-type source region SR is in contact with the n-type source region SR and is thereby electrically connected to the n-type source region SR1. The plug PG arranged on the p-type body contact region PR is in contact with the p-type body contact region PR and is further electrically connected to the p-type body region PB via the p-type body contact region PR.

[0068] In addition, when a metal silicide layer (not shown) is formed on the upper part (surface portion) of each of the n-type drain region DR, the n-type source region SR, and the p-type body contact region PR, each plug PG contacts the metal silicide layer and is electrically connected to each region below the metal silicide layer via the metal silicide layer.

[0069] On the interlayer insulating film IL in which the plugs PG are embedded, wiring (first-layer wiring) M1 made of a conductive film mainly made of aluminum (Al) or an aluminum alloy is formed. The wiring M1 is preferably aluminum wiring, but can also be wiring made of other metal materials, such as tungsten wiring or copper wiring. Each plug PG is electrically connected to the wiring M1.

[0070] The wiring M1 has a source wiring M1S electrically connected to the n-type source region SR via a plug PG arranged on the n-type source region SR, and a drain wiring M1D electrically connected to the n-type drain region DR via a plug PG arranged on the n-type drain region DR.

[0071] In the element region 1A, the source wiring M1S is electrically connected to the n-type source region SR through the plug PG arranged on the n-type source region SR, and is also electrically connected to the p-type body contact region PR through the plug PG arranged on the p-type body contact region PR. That is, in the element region 1A, the source wiring M1S is electrically connected to both the plug PG arranged on the n-type source region SR and the plug PG arranged on the p-type body contact region PR. Therefore, in the element region 1A, the potential supplied to the n-type source region SR from the plug PG arranged on the n-type source region SR is the same as the potential supplied to the p-type body contact region PR from the plug PG arranged on the p-type body contact region PR. Therefore, in the element region 1A, the same potential (source potential) as the potential supplied to the n-type source region SR from the source wiring M1S through the plug PG arranged on the n-type source region SR is supplied from the source wiring M1S to the p-type body contact region PR through the plug PG arranged on the p-type body contact region PR, and is further supplied from the p-type body contact region PR to the p-type body region PB.

[0072] Furthermore, in the element region 2A, the source wiring M1S is electrically connected to the n-type source region SR via the plug PG arranged on the n-type source region SR, and is also electrically connected to the p-type body contact region PR via the plug PG arranged on the p-type body contact region PR. That is, in the element region 2A, the source wiring M1S is electrically connected to both the plug PG arranged on the n-type source region SR and the plug PG arranged on the p-type body contact region PR. Therefore, in the element region 2A, the potential supplied to the n-type source region SR from the plug PG arranged on the n-type source region SR is the same as the potential supplied to the p-type body contact region PR from the plug PG arranged on the p-type body contact region PR. Therefore, in the element region 2A, the same potential (source potential) as the potential supplied to the n-type source region SR from the source wiring M1S via the plug PG arranged on the n-type source region SR is supplied from the source wiring M1S to the p-type body contact region PR via the plug PG arranged on the p-type body contact region PR, and is further supplied from the p-type body contact region PR to the p-type body region PB.

[0073] Furthermore, the wiring M1 further includes a gate wiring electrically connected to the gate electrode GE via a plug PG, but the gate wiring is not shown in the cross-sectional views of Figures 2 to 6, 8 to 13, and 15.

[0074] The illustration and description of the structure above the interlayer insulating film IL and the wiring M1 will be omitted here.

[0075] Furthermore, the LDMOSFET 1 formed in the element region 1A may have a configuration in which a plurality of unit LDMOSFETs are connected in parallel, and similarly, the LDMOSFET 2 formed in the element region 2A may have a configuration in which a plurality of unit LDMOSFETs are connected in parallel.

[0076] As described above, when a voltage equal to or greater than the threshold voltage is applied to the gate electrode GE, a channel (n-type inversion layer) is formed. When the channel is formed, the n-type source region SR and the n-type drain region DR are electrically connected via the channel (n-type inversion layer) and the n-type drift region ND. In this state, if a large current flows between the n-type source region SR and the n-type drain region DR, the n-type source region SR may have a higher potential than the p-type body region PB, potentially causing a parasitic bipolar transistor to operate (become ON). However, by supplying the same potential as that supplied to the n-type source region SR from the plug PG disposed on the n-type source region SR to the p-type body region PB via the p-type body contact region PR from the plug PG disposed on the p-type body contact region PR, the n-type source region SR can be prevented from becoming electrically higher than the p-type body region PB when a large current flows between the n-type source region SR and the n-type drain region DR. This prevents the parasitic bipolar transistor from operating. The on-breakdown voltage is the maximum voltage applied between the n-type source region SR and the n-type drain region DR at which the parasitic bipolar transistor does not operate. By providing a p-type body contact region PR and supplying the same potential as that supplied to the source region SR to the p-type body region PB via the p-type body contact region PR, the on-breakdown voltage of the LDMOSFET can be increased.

[0077] <About the manufacturing process of semiconductor devices> Next, the manufacturing process of the semiconductor device of this embodiment will be described with reference to Figures 16 to 21. Figures 16 to 21 are cross-sectional views of a main part during the manufacturing process of the semiconductor device of this embodiment. Figures 16, 18, and 20 are cross-sectional views of element region 1A, and show a cross section corresponding to Figure 2 above. Figures 17, 19, and 21 are cross-sectional views of element region 2A, and show a cross section corresponding to Figure 9 above.

[0078] As shown in Figures 16 and 17, first, a semiconductor substrate SB is prepared. The semiconductor substrate SB may be, for example, a p-type single crystal silicon substrate, or an epitaxial wafer in which a p-type epitaxial semiconductor layer is formed on a p-type single crystal silicon substrate, and may further have an n-type buried layer. In either case, the semiconductor substrate SB has a p-type substrate region KB. At this stage, the p-type body region PB, n-type source region SR, p-type body contact region PR, n-type drift region ND, and n-type drain region DR have not yet been formed in the semiconductor substrate SB, and therefore the regions in which these regions will be formed also consist of the p-type substrate region KB.

[0079] Next, as shown in FIGS. 18 and 19, an STI region (element isolation region) 3 is formed on the surface of the semiconductor substrate SB by using, for example, an STI method.

[0080] Next, an n-type drift region ND is formed in the semiconductor substrate SB (p-type substrate region KB) by ion implantation. At this time, the n-type drift region ND in the element region 1A and the n-type drift region ND in the element region 2A are formed in the same ion implantation step.

[0081] Next, a p-type body region PB is formed in the semiconductor substrate SB (p-type substrate region KB) by ion implantation. At this time, the p-type body region PB of the element region 1A and the p-type body region PB of the element region 2A are formed in the same ion implantation step.

[0082] Next, a gate electrode GE is formed on the semiconductor substrate SB with a gate insulating film GF interposed therebetween. This process includes the steps of forming the gate insulating film GF, forming a conductive film (e.g., a polycrystalline silicon film) for the gate electrode GE, and patterning the conductive film for the gate electrode GE.

[0083] Next, an n-type source region SR is formed in the semiconductor substrate SB (p-type substrate region KB) by ion implantation. At this time, the n-type source region SR in the element region 1A and the n-type source region SR in the element region 2A are formed in the same ion implantation step.

[0084] Next, a p-type body contact region PR is formed in the semiconductor substrate SB (p-type substrate region KB) using the ion implantation method. At this time, the p-type body contact region PR in the element region 1A and the p-type body contact region PR in the element region 2A are formed in the same ion implantation process.

[0085] Next, an n-type drain region DR is formed in the semiconductor substrate SB (p-type substrate region KB) using the ion implantation method. At this time, the n-type drain region DR in the element region 1A and the n-type drain region DR in the element region 2A are formed in the same ion implantation process.

[0086] In this way, the structures shown in FIGS. 18 and 19 are obtained, but the order of the above-mentioned processes can be changed as necessary.

[0087] Next, as shown in FIGS. 20 and 21, an interlayer insulating film IL is formed on the semiconductor substrate SB so as to cover the gate electrode GE. After the formation of the interlayer insulating film IL, the flatness of the interlayer insulating film IL can also be improved by polishing the upper surface of the interlayer insulating film IL by the CMP method or the like.

[0088] Next, after forming a contact hole in the interlayer insulating film IL, a plug PG is formed in the contact hole.

[0089] Next, a wiring M1 is formed on the interlayer insulating film IL. Thereafter, further upper interlayer insulating films and wirings are formed, but the description thereof is omitted here.

[0090] <Regarding the threshold voltage of the LDMOSFET> The threshold voltage of the LDMOSFET2 formed in the element region 2A is different from the threshold voltage of the LDMOSFET1 formed in the element region 1A. More specifically, the threshold voltage of the LDMOSFET2 formed in the element region 2A is lower than the threshold voltage of the LDMOSFET1 formed in the element region 1A. The reason is that the channel formation regions are different due to the difference in the formation regions of the p-type body regions PB. This will be described below.

[0091] In the case of the LDMOSFET 1 formed in the element region 1A, the surface layer portion of the semiconductor substrate SB below the gate electrode GE is composed of an n-type drift region ND, a p-type substrate region KB, and a p-type body region PB. The upper portion (upper layer portion) of the p-type body region PB located below the gate electrode GE and the upper portion (upper layer portion) of the p-type substrate region KB located below the gate electrode GE form the channel formation region CN of the LDMOSFET 1. In the element region 1A, the width W1 of the p-type body region PB (PB1) overlapping with the gate electrode GE is approximately constant regardless of the position in the Y direction. Therefore, in the case of the LDMOSFET 1 formed in the element region 1A, the impurity concentration distribution of the channel formation region is common regardless of the position in the Y direction.

[0092] On the other hand, in the case of the LDMOSFET2 formed in the element region 2A, the width W1 of the p-type body region PB (PB2) overlapping with the gate electrode GE in the region RG2 having the cross-sectional structure of FIG. 9 or FIG. 15 is smaller than the width W1 of the p-type body region PB (PB2) overlapping with the gate electrode GE in the region RG1 having the cross-sectional structure of FIG. 8. Reflecting this, the proportion of the p-type body region PB2 in the channel formation region CN in the cross-sectional structure shown in FIG. 9 or FIG. 15 (hence, region RG2) is smaller than the proportion of the p-type body region PB2 in the channel formation region CN in the cross-sectional structure shown in FIG. 8 (hence, region RG1). Furthermore, the p-type body region PB2 does not contribute to the channel formation region CN in the cross-sectional structure shown in FIG. 15 (hence, region RG2).

[0093] Therefore, in the case of the LDMOSFET 2 formed in the element region 2A, the impurity concentration distribution of the channel formation region CN differs between the regions RG1 and RG2. This results in a difference in the ease of forming a channel (n-type inversion layer) between the regions RG1 and RG2. Specifically, the gate voltage required to form a channel (n-type inversion layer) is lower in the region RG2 than in the region RG1. This is because the higher the p-type impurity concentration of the channel formation region CN, the higher the gate voltage required to form the n-type inversion layer (channel). Furthermore, because the impurity concentration of the p-type body region PB is higher than that of the p-type substrate region KB, the smaller the proportion of the p-type body region PB in the channel formation region CN, the lower the gate voltage required to form the n-type inversion layer (channel). Therefore, reducing the width W1 of the p-type body region PB overlapping with the gate electrode GE acts to lower the gate voltage required to form a channel.

[0094] That is, since the impurity concentration distributions of the channel formation regions of the region RG1 of the element region 2A and the element region 1A are substantially the same, the gate voltage required to form a channel (n-type inversion layer) in the region RG1 of the element region 2A is substantially the same as the gate voltage required to form a channel (n-type inversion layer) in the element region 1A. On the other hand, the impurity concentration distributions of the channel formation regions of the region RG2 of the element region 2A and the region RG1 of the element region 2A are different from each other, and the gate voltage required to form a channel (n-type inversion layer) in the region RG2 of the element region 2A is lower than the gate voltage required to form a channel (n-type inversion layer) in the region RG1 of the element region 2A. Therefore, the threshold voltage of the LDMOSFET2 formed in the element region 2A in which the regions RG1 and RG2 are repeated in the Y direction is lower than that of the LDMOSFET1 formed in the element region 1A in which a structure similar to that of the region RG1 extends in the Y direction.

[0095] If element region 2A did not have the structure of region RG2 and were composed only of the structure of region RG1, the structure of element region 2A would be substantially the same as the structure of element region 1A, and therefore the effective threshold voltage of LDMOSFET2 formed in element region 2A would be the same as the effective threshold voltage of LDMOSFET1 formed in element region 1A. However, element region 2A has, in addition to region RG1 having the cross-sectional structure of Figure 8, region RG2 in which a channel (n-type inversion layer) is more likely to form than in region RG1, and therefore the effective threshold voltage of LDMOSFET2 formed in element region 2A is lower than the effective threshold voltage of LDMOSFET1 formed in element region 1A.

[0096] For this reason, in this embodiment, it is possible to form in element region 2A LDMOSFET2 having a threshold voltage lower than that of LDMOSFET1 in element region 1A. Furthermore, LDMOSFET1 can be a normally-off type (enhancement type) LDMOSFET, and LDMOSFET2 can be a normally-off type (enhancement type) LDMOSFET having a threshold voltage lower than that of LDMOSFET1, but as an alternative, LDMOSFET2 can also be a normally-on type (depletion type) LDMOSFET.

[0097] Here, the cases of FIGS. 7 and 9 are compared with the cases of FIGS. 14 and 15. In the cases of FIGS. 7 and 9, in region RG2, p-type body region PB2 overlaps with gate electrode GE in a planar view. Therefore, a portion of p-type body region PB2 is located below gate electrode GE. On the other hand, in the cases of FIGS. 14 and 15, in region RG2, p-type body region PB2 does not overlap with gate electrode GE in a planar view. Therefore, p-type body region PB2 is not located below gate electrode GE. For this reason, the gate voltage required to form a channel (n-type inversion layer) in region RG2 of element region 2A is lower in the cases of FIGS. 14 and 15 than in the cases of FIGS. 7 and 9. 7 and 9, the channel formation region CN in region RG2 of element region 2A is composed of p-type substrate region KB and p-type body region PB2 having a higher impurity concentration than p-type substrate region KB, whereas in Figures 14 and 15, in region RG2 of element region 2A, the channel formation region CN is composed of p-type substrate region KB, and p-type body region PB2 does not function as channel formation region CN. Therefore, the effective threshold voltage of the LDMOSFET2 formed in element region 2A can be made smaller in the cases of Figures 14 and 15 than in the cases of Figures 7 and 9.

[0098] <Background of the review> The present inventors have been considering forming MISFETs (here, LDMOSFETs) having different threshold voltages on the same semiconductor substrate. Channel doping ion implantation is one method for adjusting the threshold voltage of an LDMOSFET. However, adjusting the threshold voltage using channel doping ion implantation requires a channel doping ion implantation process for each LDMOSFET having different threshold voltages, which increases the number of processes. Furthermore, forming LDMOSFETs having different threshold voltages on the same semiconductor substrate using channel doping ion implantation requires a mask for channel doping ion implantation (a mask that blocks channel doping ion implantation in one of the LDMOSFETs having different threshold voltages). This increases the manufacturing cost of the semiconductor device. Furthermore, performing channel doping ion implantation may affect the impurity concentration distribution in the n-type drift region ND, potentially degrading the electrical characteristics (e.g., breakdown voltage) of the LDMOSFET.

[0099] Therefore, it is desirable to adjust the threshold voltage of a MISFET (here, an LDMOSFET) by a simple method without increasing the manufacturing cost of the semiconductor device.

[0100] <Main features and effects> The semiconductor device of this embodiment includes an n-type source region SR and an n-type drain region DR of the LDMOSFET 2 formed spaced apart in a p-type substrate region KB of a semiconductor substrate SB, and a gate electrode GE of the LDMOSFET 2 formed on the semiconductor substrate SB between the n-type source region SR and the n-type drain region DR with a gate insulating film GF interposed therebetween. The semiconductor device of this embodiment further includes a p-type body region PB formed in the p-type substrate region KB of the semiconductor substrate SB so as to partially overlap with the gate electrode GE in a planar view, and a p-type body contact region PR formed in the p-type substrate region KB of the semiconductor substrate SB so as not to overlap with the gate electrode GE in a planar view and adjacent to the n-type source region SR. The impurity concentration of the p-type body region PB is higher than that of the p-type substrate region KB, and the impurity concentration of the p-type body contact region PR is higher than that of the p-type body region PB. The semiconductor device of this embodiment further includes an n-type drift region ND formed in the p-type substrate region KB of the semiconductor substrate SB so as to partially overlap with the gate electrode GE in a planar view and electrically connected to the n-type drain region DR. The n-type drift region ND has an impurity concentration lower than that of the n-type drain region DR. The gate electrode GE extends in the Y direction, and the p-type body region PB extends in the Y direction so as to cover bottom surfaces of the n-type source region SR and the p-type body contact region PR.

[0101] One of the main features of the semiconductor device of this embodiment is that, in the element region 2A in which the LDMOSFET 2 is formed, regions RG1 having the relatively large width W1 and regions RG2 having the relatively small width W1 are alternately arranged in the Y direction. That is, the semiconductor substrate SB has regions RG1 and RG2 alternately arranged in the Y direction, and the width W1 in region RG2 is smaller than the width W1 in region RG1. Specifically, regions RG1 having the cross-sectional structure of FIG. 8 and regions RG2 having the cross-sectional structure of FIG. 9 or FIG. 15 are alternately arranged in the Y direction. This allows the threshold voltage of the LDMOSFET 2 formed in the element region 2A to be adjusted to a desired threshold voltage, as explained in the above section "Regarding the Threshold Voltage of the LDMOSFET."

[0102] That is, by applying a structure in which regions RG1 and RG2 are alternately arranged in the Y direction in element region 2A, the threshold voltage of LDMOSFET2 formed in element region 2A can be made different from that of LDMOSFET1 formed in element region 1A, and more specifically, can be made lower than that of LDMOSFET1 formed in element region 1A.

[0103] The threshold voltage of the LDMOSFET 2 in the element region 2A can be controlled by adjusting the Y-direction dimensions of the regions RG1 and RG2. For example, the threshold voltage of the LDMOSFET 2 tends to decrease as the Y-direction dimension of the region RG1 decreases and the Y-direction dimension of the region RG2 increases. This is because the contribution of the region RG2 to the effective threshold voltage of the LDMOSFET 2 increases as the Y-direction dimension of the region RG1 decreases and the Y-direction dimension of the region RG2 increases. Therefore, an LDMOSFET 2 having a desired threshold voltage can be formed by adjusting the Y-direction dimensions of the regions RG1 and RG2 in the element region 2A according to the threshold voltage required for the LDMOSFET 2.

[0104] Also, when applying the structures of FIGS. 14 and 15, it is easier to adjust the threshold voltage of the LDMOSFET2 in the element region 2A than when applying the structures of FIGS. 7 and 9. Therefore, the difference between the threshold voltage of the LDMOSFET1 formed in the element region 1A and the threshold voltage of the LDMOSFET2 formed in the element region 2A can be made larger. This is because, compared to the case of applying the structures of FIGS. 7 and 9, the difference between the gate voltage required to form a channel in the region RG1 of the element region 2A and the gate voltage required to form a channel in the region RG2 of the element region 2A becomes larger when applying the structures of FIGS. 14 and 15.

[0105] <First Modified Example> FIG. 22 is a plan view of the main part of a first modified example of the semiconductor device of the present embodiment. FIG. 22 corresponds to FIG. 14 above, and in FIG. 22, a plan view of the element region 1A is shown. In FIGS. 7 and 14, the case where the dimension (length) S1 in the Y direction of the region RG1 and the dimension (length) S2 in the Y direction of the region RG2 are substantially the same (that is, the case where S1≈S2) is shown, but in FIG. 22, the case where the dimension (length) S1 in the Y direction of the region RG1 is smaller than the dimension (length) S2 in the Y direction of the region RG2 (that is, the case where S1<S2) is shown. Compared to the case of FIG. 15, in the case of FIG. 22, the ratio of the region RG2 contributing to the effective threshold voltage of the LDMOSFET2 increases, so the threshold voltage of the LDMOSFET2 can be made lower.

[0106] Furthermore, in this embodiment, an LDMOSFET 2 having a threshold voltage different from that of the LDMOSFET 1 formed in the element region 1A can be formed in the element region 2A. The LDMOSFET 1 in the element region 1A and the LDMOSFET 2 in the element region 2A have different formation regions for the p-type body region PB. This can be achieved by adjusting the photoresist pattern used as an ion implantation mask in the ion implantation step for forming the p-type body region PB. Therefore, the LDMOSFET 1 in the element region 1A and the LDMOSFET 2 in the element region 2A can be formed in the same process. This allows the LDMOSFET 1 in the element region 1A and the LDMOSFET 2 in the element region 2A to be formed together without adding any additional steps to the steps required to form the LDMOSFET 1 in the element region 1A.

[0107] This allows the threshold voltage of the LDMOSFET to be adjusted using a simple method, and also allows the threshold voltage of the LDMOSFET to be adjusted while suppressing the manufacturing cost of the semiconductor device without increasing the manufacturing cost of the semiconductor device.

[0108] Furthermore, if the p-type body region PB does not exist at all in the element region 2A, there is a concern that the breakdown voltage of the LDMOSFET 2 may decrease. However, in this embodiment, the presence of the p-type body region PB in the element region 2A makes it easier to ensure the breakdown voltage of the LDMOSFET 2.

[0109] <Second Modification> Next, a further modification of the semiconductor device of this embodiment will be described.

[0110] Fig. 23 is a plan view of a main part of a semiconductor device according to the second modification, which corresponds to Fig. 14 and shows a plan view of an element region 2A.

[0111] 7 and 14, in the region RG1 of the element region 2A, the dimension L1 in the Y direction of the portion of the p-type body region PB (PB2) overlapping with the gate electrode GE in plan view is approximately constant regardless of the position in the X direction.

[0112] 23, in region RG1 of element region 2A, the dimension L1 in the Y direction of the portion of p-type body region PB (PB2) that overlaps with gate electrode GE in plan view is smallest at the end facing n-type drift region ND and gradually increases with increasing distance from n-type drift region ND. Compared to the case of Fig. 14, in the case of Fig. 23, the portion of p-type body region PB (PB2) that overlaps with gate electrode GE in plan view is smaller, making it easier for on-current to flow in LDMOSFET2, and therefore the threshold voltage of LDMOSFET2 can be reduced.

[0113] <Third Modification> Fig. 24 is a plan view of a main part of a semiconductor device according to the third modification, which corresponds to Fig. 14 and shows a plan view of an element region 2A.

[0114] In any of the cases of FIG. 7, FIG. 14, and FIG. 24, in the element region 2A, the position (position in the X direction) of the end TB1 of the p-type body region PB facing the n-type drift region ND in plan view is set back in region RG2 compared to region RG1.

[0115] In addition, in the case of Figure 7 and Figure 14, in the element region 2A, the positions (positions in the X direction) of the end TB1 of the n-type drift region ND on the side facing the p-type body region PB in plan view are the same in the regions RG1 and RG2.

[0116] On the other hand, in the case of FIG. 24, in the element region 2A, in region RG2, the position (position in the X direction) of the end TB2 of the n-type drift region ND facing the p-type body region PB in plan view is set back toward the side away from the p-type body region PB compared to region RG1.

[0117] In region RG2 of element region 2A, the p-type body region PB is not formed below the gate electrode GE, and therefore there is a concern about a decrease in the breakdown voltage due to the extension of the depletion layer from the drain to the source. In contrast, in the case of Fig. 24, in region RG2, the position (position in the X direction) of end TB2 of n-type drift region ND facing the p-type body region PB in plan view is set back to the side away from the p-type body region PB, compared to region RG1, which makes it easier to suppress or prevent a decrease in the breakdown voltage due to the extension of the depletion layer from the drain to the source.

[0118] (Embodiment 2) 25 and 29 are plan views of a main portion of the semiconductor device of the second embodiment, and FIGS. 26 to 28 and 30 to 32 are cross-sectional views of a main portion of the semiconductor device of the second embodiment. FIG. 25 corresponds to FIG. 1 of the first embodiment, and shows a plan view of an element region 1A. FIG. 29 corresponds to FIG. 7 of the first embodiment, and shows a plan view of an element region 2A. The cross-sectional view taken along line C1-C1 in FIG. 25 corresponds approximately to FIG. 26, the cross-sectional view taken along line C2-C2 in FIG. 25 corresponds approximately to FIG. 27, and the cross-sectional view taken along line C4-C4 in FIG. 25 corresponds approximately to FIG. 28. The cross-sectional view taken along line C5-C5 in FIG. 25 is similar to FIG. 5, and the cross-sectional view taken along line C6-C6 in FIG. 25 is similar to FIG. 6. Also, the cross-sectional view taken along line D1-D1 in Fig. 29 roughly corresponds to Fig. 30, the cross-sectional view taken along line D2-D2 in Fig. 29 roughly corresponds to Fig. 31, and the cross-sectional view taken along line D4-D4 in Fig. 29 roughly corresponds to Fig. 32. The cross-sectional view taken along line D5-D5 in Fig. 29 is similar to Fig. 12 above, and the cross-sectional view taken along line D6-D6 in Fig. 29 is similar to Fig. 13 above.

[0119] In the second embodiment as well, the structure of the semiconductor device in the element region 2A differs from the structure of the semiconductor device in the element region 1A in the region where the p-type body region PB is formed, and the structure of the semiconductor device in the element region 2A is basically the same as the structure of the semiconductor device in the element region 1A except for the region where the p-type body region PB is formed. Moreover, the semiconductor device of the second embodiment differs mainly from the semiconductor device of the first embodiment above in the n-type source region SR and the p-type body contact region PR, and the rest are basically the same.

[0120] The differences between the semiconductor device of the second embodiment and the semiconductor device of the first embodiment will be described below.

[0121] 1, 3, 4, 7, 10, and 11, in each of the element regions 1A and 2A, the n-type source region SR and the p-type body contact region PR extend in the Y direction and are adjacent to each other in the X direction. Of the n-type source region SR and the p-type body contact region PR, the n-type source region SR is disposed closer to the channel formation region, and the p-type body contact region PR is disposed farther from the channel formation region.

[0122] 25, 28, 29, and 32, in the semiconductor device of the second embodiment, the n-type source regions SR and the p-type body contact regions PR are alternately arranged in the Y direction in each of the element regions 1A and 2A. The p-type body region PB extends in the Y direction so as to cover the bottom surfaces of the n-type source regions SR and the p-type body contact regions PR alternately arranged in the Y direction.

[0123] The region RG1 of the element region 2A has the cross-sectional structure of Figure 30, but the above-mentioned first embodiment and the second embodiment have in common that a portion of the p-type body region PB2 is located below the gate electrode GE (and therefore a portion of the p-type body region PB2 overlaps with the gate electrode GE in a planar view).

[0124] Furthermore, the width W1 of the p-type body region PB2 overlapping with the gate electrode GE in the region RG2 of the element region 2A is smaller than the width W1 of the p-type body region PB2 overlapping with the gate electrode GE in the region RG1 of the element region 2A, which is common to the above-mentioned first embodiment and the second embodiment.

[0125] As in the first embodiment, in the second embodiment, the width W1 of the p-type body region PB2 overlapping with the gate electrode GE in the region RG2 of the element region 2A may be zero (W1=0). FIGS. 33 and 34 are a plan view (FIG. 33) and a cross-sectional view (FIG. 34) of the element region 2A when the width W1 of the p-type body region PB2 overlapping with the gate electrode GE in the region RG2 is zero (W1=0). FIG. 34 is a cross-sectional view taken along the line D2-D2 in FIG. 33. The cross-sectional view taken along the line D1-D1 in FIG. 33 is similar to FIG. 30, the cross-sectional view taken along the line D4-D4 in FIG. 33 is similar to FIG. 32, the cross-sectional view taken along the line D5-D5 in FIG. 33 is similar to FIG. 12, and the cross-sectional view taken along the line D6-D6 in FIG. 33 is similar to FIG. 13. 29 and 31 are a plan view (FIG. 29) and a cross-sectional view (FIG. 31) of the element region 2A when the width W1 of the p-type body region PB2 overlapping with the gate electrode GE in the region RG2 is greater than zero (W1>0).

[0126] In the case of Fig. 29, a portion of the p-type body region PB2 in region RG2 overlaps with the gate electrode GE in a planar view. Therefore, as shown in Fig. 31, a portion of the p-type body region PB2 is located below the gate electrode GE in region RG2. In contrast, in the case of Fig. 33, the p-type body region PB2 in region RG2 does not overlap with the gate electrode GE in a planar view. Therefore, as shown in Fig. 34, the p-type body region PB2 is not formed (located) below the gate electrode GE in region RG2.

[0127] In the second embodiment, in the element region 2A, regions RG1 and RG2 are alternately arranged in the Y direction, and n-type source regions SR and p-type body contact regions PR are alternately arranged in the Y direction. The p-type body contact regions PR are formed in the region RG1, and the n-type source regions SR are formed in the region RG2.

[0128] Other configurations of the semiconductor device of the present second embodiment are almost the same as those of the semiconductor device of the above-mentioned first embodiment, so a repeated description thereof will be omitted here. Also, a manufacturing process of the semiconductor device of the present second embodiment is almost the same as that of the semiconductor device of the above-mentioned first embodiment, so a repeated description thereof will be omitted here.

[0129] In the semiconductor device of the second embodiment, too, in the element region 2A in which the LDMOSFET 2 is formed, regions RG1 having the relatively large width W1 and regions RG2 having the relatively small width W1 are alternately arranged in the Y direction. Specifically, regions RG1 having the cross-sectional structure of FIG. 30 and regions RG2 having the cross-sectional structure of FIG. 31 or 34 are alternately arranged in the Y direction. As explained in the section "Regarding the Threshold Voltage of the LDMOSFET," a channel (n-type inversion layer) is more likely to form in region RG2 than in region RG1. Therefore, in the second embodiment as well, the threshold voltage of the LDMOSFET 2 formed in the element region 2A can be adjusted to a desired threshold voltage.

[0130] Also in the second embodiment, it is possible to form in the element region 2A an LDMOSFET 2 having a threshold voltage different from that of the LDMOSFET 1 formed in the element region 1A. The LDMOSFET 1 in the element region 1A and the LDMOSFET 2 in the element region 2A can be formed in the same process, and therefore the LDMOSFET 1 in the element region 1A and the LDMOSFET 2 in the element region 2A can be formed together without adding any additional process steps to those required to form the LDMOSFET 1 in the element region 1A. This makes it possible to adjust the threshold voltage of the LDMOSFET by a simple method without increasing the manufacturing cost of the semiconductor device.

[0131] Furthermore, in the second embodiment, a p-type body contact region PR is formed in the region RG1, and an n-type source region SR is formed in the region RG2. In this case, a current flowing between the n-type source region SR and the n-type drain region DR can be efficiently passed through a channel (n-type inversion layer) formed in the region RG2 in which the source region SR is formed. Therefore, when the regions RG1 and RG2 are alternately arranged in the Y direction in the element region 2A, and the n-type source regions SR and the p-type body contact regions PR are alternately arranged in the Y direction, forming the p-type body contact region PR in the region RG1 and the n-type source region SR in the region RG2 makes it possible to efficiently adjust the threshold voltage of the LDMOSFET2.

[0132] Moreover, the second embodiment can be combined with each of the modifications of the first embodiment.

[0133] Furthermore, in the above-described first and second embodiments, the case where the LDMOSFET is an n-channel type has been described. However, by reversing all the conductivity types, the above-described first and second embodiments and their modifications can also be applied to a p-channel type LDMOSFET.

[0134] The invention made by the inventor has been specifically described above based on the embodiments thereof, but it goes without saying that the present invention is not limited to the above-described embodiments and can be modified in various ways without departing from the spirit of the invention. [Explanation of symbols]

[0135] 1,2 LDMOSFET 1A, 2A element area 3 STI area DR n-type drain region GE gate electrode GF gate insulating film IL Interlayer insulating film KB p-type substrate area M1 wiring M1D drain wiring M1S source wiring ND n-type drift region PB,PB1,PB2 p-type body region PG plug PR p-type body contact region RG1,RG2 area SB semiconductor substrate SR n-type source region TB1,TB2 end

Claims

1. a semiconductor substrate having a surface; a substrate region of a first conductivity type formed on the semiconductor substrate; a first MISFET formed on the surface of the semiconductor substrate; a first source region of a second conductivity type opposite to the first conductivity type of the first MISFET and a first drain region of the second conductivity type of the first MISFET, the first source region and the first drain region being formed in the substrate region and spaced apart from each other; a first gate electrode of the first MISFET formed on the semiconductor substrate between the first source region and the first drain region via a first gate insulating film; a first semiconductor region of the first conductivity type having a higher impurity concentration than the substrate region, the first semiconductor region being formed in the substrate region so as to partially overlap the first gate electrode in a plan view; a second semiconductor region of the first conductivity type having a higher impurity concentration than the first semiconductor region, the second semiconductor region being formed in the substrate region so as not to overlap the first gate electrode in a plan view and so as to be adjacent to the first source region; a third semiconductor region of the second conductivity type, which is formed in the substrate region so as to partially overlap the first gate electrode in a plan view and is electrically connected to the first drain region and has a lower impurity concentration than the first drain region; and the first gate electrode extends in a first direction along the surface of the semiconductor substrate; the first semiconductor region extends in the first direction so as to cover a bottom surface of the first source region and a bottom surface of the second semiconductor region; the semiconductor substrate has first regions and second regions alternately arranged in the first direction; a width in the second direction of the first semiconductor region overlapping with the first gate electrode in the second region is smaller than a width in the second direction of the first semiconductor region overlapping with the first gate electrode in the first region; the second direction is perpendicular to the first direction and extends along the surface of the semiconductor substrate; In a planar view, a position of an end of the first semiconductor region in the second region facing the third semiconductor region is set back away from the third semiconductor region from a position of an end of the first semiconductor region in the first region facing the third semiconductor region.

2. 2. The semiconductor device according to claim 1, A semiconductor device, wherein in the first region, a portion of the first semiconductor region is located below the first gate electrode in a cross-sectional view perpendicular to the first direction, while in the second region, the first semiconductor region is not located below the first gate electrode in a cross-sectional view perpendicular to the first direction.

3. 2. The semiconductor device according to claim 1, an interlayer insulating film formed on the semiconductor substrate so as to cover the first gate electrode; a plurality of contact plugs embedded in the interlayer insulating film; and a first contact plug of the plurality of contact plugs is disposed on the first source region and is electrically connected to the first source region; a second contact plug of the plurality of contact plugs is disposed on the second semiconductor region and is electrically connected to the second semiconductor region;

4. 4. The semiconductor device according to claim 3, a first wiring formed on the interlayer insulating film; and The first contact plug and the second contact plug are electrically connected to the first wiring.

5. 4. The semiconductor device according to claim 3, a potential supplied from the first contact plug to the first source region and a potential supplied from the second contact plug to the second semiconductor region are the same.

6. 2. The semiconductor device according to claim 1, in the first region, an upper portion of the substrate region located below the first gate electrode and an upper portion of the first semiconductor region located below the first gate electrode constitute a channel formation region of the first MISFET, In the second region, an upper portion of the substrate region located below the first gate electrode is a channel formation region of the first MISFET.

7. 2. The semiconductor device according to claim 1, The first source region and the second semiconductor region each extend in the first direction and are adjacent to each other in the second direction.

8. 2. The semiconductor device according to claim 1, The semiconductor device, wherein the first source regions and the second semiconductor regions are alternately arranged in the first direction.

9. 9. The semiconductor device according to claim 8, the first region overlaps with the second semiconductor region in a plan view; The second region overlaps with the first source region in a plan view.

10. 2. The semiconductor device according to claim 1, A semiconductor device, wherein the dimension of the first region in the first direction is smaller than the dimension of the second region in the first direction.

11. 2. The semiconductor device according to claim 1, a semiconductor device, wherein in the first region, a dimension of a portion where the first semiconductor region overlaps with the first gate electrode in the first direction in a planar view is smallest at an end facing the third semiconductor region and gradually increases with increasing distance from the third semiconductor region.

12. 2. The semiconductor device according to claim 1, In a planar view, a position of an end of the third semiconductor region in the second region facing the first semiconductor region is set back away from the first semiconductor region from a position of an end of the third semiconductor region in the first region facing the first semiconductor region.

13. 2. The semiconductor device according to claim 1, The semiconductor device, wherein the first MISFET is an LDMOSFET.

14. 2. The semiconductor device according to claim 1, further comprising a second MISFET formed on the surface of the semiconductor substrate; A semiconductor device, wherein a threshold voltage of the first MISFET and a threshold voltage of the second MISFET are different from each other.

15. 15. The semiconductor device according to claim 14, a second source region of the second conductivity type of the second MISFET and a second drain region of the second conductivity type of the second MISFET formed in the substrate region and spaced apart from each other; a second gate electrode of the second MISFET formed on the semiconductor substrate between the second source region and the second drain region via a second gate insulating film; a fourth semiconductor region of the first conductivity type having a higher impurity concentration than the substrate region, the fourth semiconductor region being formed in the substrate region so as to partially overlap the second gate electrode in a plan view; a fifth semiconductor region of the first conductivity type having a higher impurity concentration than the fourth semiconductor region, the fifth semiconductor region being formed in the substrate region so as not to overlap the second gate electrode in a plan view and so as to be adjacent to the second source region; a sixth semiconductor region of the second conductivity type formed in the substrate region so as to partially overlap the second gate electrode in a plan view, electrically connected to the second drain region, and having a lower impurity concentration than the second drain region; and the second gate electrode extends in the first direction; the fourth semiconductor region extends in the first direction so as to cover a bottom surface of the second source region and a bottom surface of the fifth semiconductor region, and while overlapping with the second gate electrode by a certain width in a planar view.

16. 16. The semiconductor device according to claim 15, the first conductivity type is p-type, the second conductivity type is n-type, A semiconductor device, wherein a threshold voltage of the second MISFET is lower than a threshold voltage of the first MISFET.

17. 2. The semiconductor device according to claim 1, The semiconductor substrate is A substrate; an epitaxial semiconductor layer formed on the substrate; and The epitaxial semiconductor layer is the substrate region.

18. 2. The semiconductor device according to claim 1, A semiconductor device, wherein in the second direction, a minimum distance between the first semiconductor region and the third semiconductor region in the second region is greater than a minimum distance between the first semiconductor region and the third semiconductor region in the first region.

19. 2. The semiconductor device according to claim 1, an end of the first semiconductor region in the second region that is closest to the third semiconductor region in the second direction is exposed from the first gate electrode.

Images