Systems and methods for accelerating physical simulation models during microelectronic device manufacturing

Abstract

A method for accelerating a physical simulation model during microelectronic device manufacturing may include, but is not limited to, executing the physical simulation model at a first grid size having a first resolution, generating output from the physical simulation model at the first grid size having the first resolution, inputting the output from the physical simulation model at the first grid size having the first resolution into a resolution enhanced model (REM), and generating output via the REM at a second grid size having a second resolution, thereby reducing at least one of computational time costs or computational resource costs of a controller running the physical simulation model. The physical simulation model can simulate on-wafer performance of at least one microelectronic manufacturing process. The second grid size may be smaller than the first grid size. The second resolution may be higher than the first resolution.

Description

[Technical Field]

[0001] The present invention relates generally to the field of plasma processing, and more particularly to a system and method for accelerating physical simulation models during microelectronic device manufacturing. [Background technology]

[0002] REFERENCE TO RELATED APPLICATIONS This application claims the benefit of U.S. Provisional Patent Application No. 63 / 075,223 (September 7, 2020), the entire contents of which are incorporated herein by reference.

[0003] The fabrication of microelectronic devices involves various lithography and / or plasma process steps. For example, a specimen may be exposed to tens of thousands of lithography and / or plasma processes during fabrication. As critical dimensions in microelectronic devices continue to decrease, physical models utilized for simulation of processes such as lithography and / or plasma processes typically utilize methods to reduce grid size (characteristic length of the model), or mesh refinement, to account for the effects of device dimensions and on-wafer process(es). However, mesh refinement can require significant computational resources and can significantly slow time-to-solution. Additionally, the large number of simulations that physical models may require can slow development cycles. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] U.S. Patent Application Publication No. 2020 / 0278604 Summary of the Invention [Problem to be solved by the invention]

[0005] It would therefore be desirable to provide a system and method that addresses the above-identified shortcomings of previous approaches. [Means for solving the problem]

[0006] According to one or more exemplary embodiments, a system is disclosed in which a controller includes one or more processors and a memory. In another exemplary embodiment, the memory is configured to store program instructions. In another exemplary embodiment, the one or more processors are configured to execute program instructions that cause the one or more processors to run a physical simulation model at a first grid size having a first resolution. In another exemplary embodiment, the physical simulation model simulates on-wafer performance of at least one microelectronic device manufacturing process. In another exemplary embodiment, the one or more processors are configured to execute program instructions that cause the one or more processors to generate output from the physical simulation model at the first grid size having the first resolution. In another exemplary embodiment, the one or more processors are configured to execute program instructions that cause the one or more processors to input output from the physical simulation model at the first grid size having the first resolution into a resolution enhanced model (REM). In another exemplary embodiment, the one or more processors are configured to execute program instructions that cause the one or more processors to generate output via the REM at a second grid size having a second resolution. In another exemplary embodiment, the second grid size is smaller than the first grid size. In another exemplary embodiment, the second resolution is higher than the first resolution. In another exemplary embodiment, generating output at a second grid size having a second resolution via REM based on output at a first grid size having a first resolution from the physical simulation model reduces at least one of a computational time cost or a computational resource cost of the controller for executing the physical simulation model.

[0007] A method is disclosed according to one or more embodiments of the present disclosure. In one exemplary embodiment, the method may include, but is not limited to, running a physical simulation model at a first grid size having a first resolution. In another exemplary embodiment, the physical simulation model simulates on-wafer performance of at least one microelectronic device manufacturing process. In another exemplary embodiment, the method may include, but is not limited to, generating output from the physical simulation model at the first grid size having the first resolution. In another exemplary embodiment, the method may include, but is not limited to, inputting the output from the physical simulation model at the first grid size having the first resolution into a resolution enhanced model (REM). In another exemplary embodiment, the method may include, but is not limited to, generating output via the REM at a second grid size having a second resolution. In another exemplary embodiment, the second grid size is smaller than the first grid size. In another exemplary embodiment, the second resolution is higher than the first resolution. In another exemplary embodiment, generating an output of a second grid size having a second resolution via REM based on an output of a first grid size having a first resolution from a physical simulation model reduces at least one of a computational time cost or a computational resource cost of a controller executing the physical simulation model.

[0008] A system is disclosed according to one or more embodiments of the present disclosure. In one exemplary embodiment, the system includes a metrology subsystem configured to obtain one or more measurements of a portion of a specimen. In another exemplary embodiment, the system includes a controller. In another exemplary embodiment, the controller includes one or more processors and a memory. In another exemplary embodiment, the memory is configured to store program instructions. In another exemplary embodiment, the one or more processors are configured to execute program instructions that cause the one or more processors to obtain one or more inputs from the metrology subsystem, the one or more inputs including an image having a first resolution. In another exemplary embodiment, the one or more processors are configured to execute program instructions that cause the one or more processors to run a physical simulation model at a first grid size having the first resolution. In another exemplary embodiment, the physical simulation model simulates on-wafer performance of at least one microelectronic device manufacturing process. In another exemplary embodiment, the one or more processors are configured to execute program instructions that cause the one or more processors to generate output at the first grid size having the first resolution from the physical simulation model. In another exemplary embodiment, the one or more processors are configured to execute program instructions that cause the one or more processors to input output from the physical simulation model at a first grid size having a first resolution into an enhanced resolution model (REM). In another exemplary embodiment, the one or more processors are configured to execute program instructions that cause the one or more processors to generate output via the REM at a second grid size having a second resolution. In another exemplary embodiment, the second grid size is smaller than the first grid size. In another exemplary embodiment, the second resolution is higher than the first resolution.In another exemplary embodiment, generating an output at a second grid size having a second resolution via REM based on an output at a first grid size having a first resolution from the physical simulation model reduces at least one of a computational time cost or a computational resource cost of the controller for executing the physical simulation model.

[0009] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not necessarily restrictive of the invention as claimed. The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the invention and, together with the general description, serve to explain the principles of the invention. [Brief explanation of the drawings]

[0010] The many advantages of the present disclosure may be better understood by those skilled in the art by reference to the accompanying drawings: [Figure 1A] FIG. 1 illustrates a simplified block diagram of a system for accelerating physical simulation models during microelectronic device manufacturing, in accordance with one or more embodiments of the present disclosure. [Figure 1B] FIG. 1 shows a simplified schematic diagram of a system for accelerating physical simulation models during microelectronic device manufacturing, in accordance with one or more embodiments of the present disclosure. [Figure 2] 1 is a flow chart illustrating steps performed in a method for accelerating physical simulation models during microelectronic device manufacturing in accordance with one or more embodiments of the present disclosure. [Figure 3] FIG. 1 illustrates a block diagram of a method for accelerating physical simulation models during microelectronic device manufacturing in accordance with one or more embodiments of the present disclosure. [Figure 4] 1 is a flow chart illustrating steps performed in a method for accelerating physical simulation models during microelectronic device manufacturing in accordance with one or more embodiments of the present disclosure. [Figure 5]FIG. 1 illustrates a block diagram of a method for accelerating physical simulation models during microelectronic device manufacturing in accordance with one or more embodiments of the present disclosure. [Figure 6] 1 is a flow chart illustrating steps performed in a method for accelerating physical simulation models during microelectronic device manufacturing in accordance with one or more embodiments of the present disclosure. [Figure 7] 1 illustrates a block diagram and block diagram of a method for accelerating physical simulation models during microelectronic device manufacturing in accordance with one or more embodiments of the present disclosure. [Figure 8] 1 is a flow chart illustrating steps performed in a method for accelerating physical simulation models during microelectronic device manufacturing in accordance with one or more embodiments of the present disclosure. [Figure 9] FIG. 1 illustrates a block diagram of a method for accelerating physical simulation models during microelectronic device manufacturing in accordance with one or more embodiments of the present disclosure. [Figure 10] 1 is a flow chart illustrating steps performed in a method for accelerating physical simulation models during microelectronic device manufacturing in accordance with one or more embodiments of the present disclosure. [Figure 11A] FIG. 1 illustrates a simplified block diagram of a training stage for accelerating physical simulation models during microelectronic device manufacturing, in accordance with one or more embodiments of the present disclosure. [Figure 11B] FIG. 1 illustrates a simplified block diagram of a test / production stage for accelerating physical simulation models during microelectronic device manufacturing, in accordance with one or more embodiments of the present disclosure. [Figure 12] 1 shows a graph comparing validation loss and training loss when training a resolution enhancement model (REM), in accordance with one or more embodiments of the present disclosure. [Figure 13] 10 shows a set comparing a coarse resolution image and an REM-generated version of the coarse resolution image for comparison with a fine resolution image of two patterns, in accordance with one or more embodiments of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0011] The present disclosure has been particularly shown and described with reference to certain embodiments and certain features thereof. The embodiments described herein are to be construed as illustrative and not restrictive. It will be readily apparent to those skilled in the art that various changes and modifications in form and detail can be made therein without departing from the spirit and scope of the present disclosure.

[0012] Reference will now be made in detail to the disclosed subject matter, which is illustrated in the accompanying drawings.

[0013] The fabrication of microelectronic devices involves various lithography and / or plasma process steps. For example, a specimen may be exposed to tens of thousands or more lithography and / or plasma processes (e.g., etching, deposition, ion implantation, etc.) during fabrication. As critical dimensions in microelectronic devices continue to decrease, physical models utilized in the simulation of processes such as lithography and / or plasma processes typically utilize methods to reduce grid size (characteristic length of the model) or refine meshes to describe the dimensions of the device and the effect of the process(es) on the wafer.

[0014] However, mesh refinement can require a large amount of computational resources, which can significantly delay the time to solution. For example, mesh refinement can require computational resources such as logic cores, memory, and disk space. The computational time cost and / or computational resource cost for mesh refinement can range from O(n 3-4 For example, if the grid size is reduced by a factor of 5, the memory footprint increases by a factor of 125, and the time to solution increases by at least a factor of 125, which may result in the need for at least 125 logical cores for the same time to solution.

[0015] Additionally, the large number of simulations that physical models may require can delay development cycles. To meet time-to-market demands for next-generation microelectronic devices, physical simulation models are often utilized to describe various aspects of on-wafer processes. Physical simulation models use a grid of cells to establish spatial locations and perform calculations to estimate characteristics (e.g., patterns) of interest to the model. To capture a higher level of detail in the model, smaller grid cell sizes may be utilized. However, this higher level of detail comes at the expense of longer computation times, which reduces the model's effectiveness in accelerating process development cycles. For example, physical models may be utilized for process development and / or process window optimization, requiring hundreds to tens of thousands of simulations to be completed in a short time (e.g., compared to the actual cost of performing physical experiments). As such, long simulation times are inefficient for development cycles (e.g., customer development cycles).

[0016] Furthermore, as the critical dimensions of features in microelectronic device manufacturing continue to decrease, the challenges of developing processes that enable the continued shrinking of features in microelectronic manufacturing increase, for example, the time to develop a process that can be manufactured on a large scale and the research and development costs associated with developing the process increase.

[0017] Accordingly, embodiments of the present disclosure are directed to systems and methods for accelerating physical simulation models during microelectronic device manufacturing, having advantages over conventional systems and methods. For example, embodiments of the present disclosure are directed to using physical simulation models to enable accelerated time-to-solution while retaining the benefits (or requirements) of higher levels of detail afforded by smaller grid sizes, allowing for reduced research and development time and costs. As another example, embodiments of the present disclosure are directed to enabling mesh refinement to be independent of physical simulation. As another example, embodiments of the present disclosure are directed to using dummy process conditions to pre-train deep learning (DL) models. As another example, embodiments of the present disclosure are directed to improving simulation accuracy and visualization while maintaining desired fast computation times.

[0018] 1A-13 generally illustrate systems and methods for accelerating physical simulation models during microelectronic device manufacturing in accordance with one or more embodiments of the present disclosure.

[0019] 1A shows a simplified block diagram of a system for accelerating physical simulation models during microelectronic device manufacturing in accordance with one or more embodiments of the present disclosure. In one embodiment, system 100 includes a metrology subsystem 102. In another embodiment, system 100 includes a controller 104 including one or more processors 106 and a memory 108. Controller 104 may include or be communicatively coupled to a user interface 110.

[0020] It is noted herein that the metrology subsystem 102 may include any metrology subsystem 102 known in the art, including, but not limited to, an optical metrology system, a charged particle based metrology system, etc. For example, the metrology subsystem may include, but is not limited to, an optical critical dimension (OCD) tool, a critical dimension scanning electron microscope (CD-SEM) tool, a transmission electron microscope (TEM) tool, a cross-sectional scanning electron microscope (X-SEM) tool, etc.

[0021] In another embodiment, the controller 104 is communicatively coupled to the metrology subsystem 102. In this regard, the one or more processors 106 of the controller 104 may be configured to receive one or more measurement signals from the metrology subsystem 102. This collected data may be used to generate and / or adjust a physical simulation model, as discussed further herein. Additionally, the one or more processors 106 of the controller 104 may be configured to generate one or more control signals for adjusting one or more characteristics / parameters of the metrology subsystem 102.

[0022] In another embodiment, the system 100 may further include one or more process tools communicatively coupled to the controller 104. The one or more process tools may include any process tools known in the art for microelectronic manufacturing, including, but not limited to, lithography tools and / or plasma process tools (e.g., etching tools, deposition tools, polishing tools, scanners, etc.). For example, the controller 104 may be configured to generate one or more control signals configured to adjust one or more characteristics of the one or more process tools in a feedforward or feedback loop based on a physical simulation model. For example, the one or more processors 106 of the controller 104 may be configured to generate one or more control signals to a downstream process tool. In another example, the one or more processors 106 of the controller 104 may be configured to generate one or more control signals to an upstream process tool.

[0023] FIG. 1B shows a simplified schematic diagram of a metrology subsystem 102 arranged in a reflectometry and / or ellipsometry configuration, in accordance with one or more embodiments of the present disclosure.

[0024] In one embodiment, the metrology subsystem 102 includes an illumination source 112, an illumination arm 114, a collection arm 116, and a detector assembly 118. Illumination 101 from the illumination source 112 can be directed to the sample 120 via the illumination arm 114.

[0025] The metrology subsystem 102 can be configured to collect illumination emanating from the sample via a collection arm 116. The path of the illumination arm 114 can include one or more optical elements 122 suitable for modifying and / or conditioning the illumination 101. For example, the one or more optical elements 122 can include, but are not limited to, one or more polarizers, one or more filters, one or more beam splitters, one or more diffusers, one or more homogenizers, one or more apodizers, one or more beam shapers, one or more lenses, or any combination thereof.

[0026] The illumination arm 114 can utilize a first focusing element 124 to focus and / or direct the illumination 101 (e.g., a beam) onto the sample 120. In some embodiments, the sample 120 is disposed on a stage assembly 126 to facilitate movement of the sample 120. In some embodiments, the stage assembly 126 is an actuatable stage. For example, the stage assembly 126 can include, but is not limited to, one or more translation stages suitable for selectively translating the sample 120 along one or more linear directions (e.g., x-direction, y-direction, and / or z-direction). As another example, the stage assembly 126 can include, but is not limited to, one or more rotation stages suitable for selectively rotating the sample 120 along a rotational direction. As another example, the stage assembly 126 can include, but is not limited to, a rotational stage and a translation stage suitable for selectively translating the sample 120 along a linear direction and / or rotating the sample 120 along a rotational direction. It is noted herein that the system 100 can operate in any scanning mode known in the art.

[0027] The collection arm 116 may include a second focusing element 128 for collecting illumination from the sample 120. In another embodiment, the detector assembly 118 is configured to capture illumination emanating from the sample 120 through the collection arm 116. For example, the detector assembly 118 may receive illumination reflected or scattered from the sample 120 (e.g., via specular reflection, diffuse reflection, etc.). As another example, the detector assembly 118 may receive illumination generated by the sample 120 (e.g., luminescence associated with absorption of the illumination 101, etc.). It should be noted that the detector assembly 118 may include any sensor and detector assembly known in the art. The sensor may include, but is not limited to, a charge-coupled device (CCD detector), a complementary metal-oxide semiconductor (CMOS) detector, a time-delay integration (TDI) detector, a photomultiplier tube (PMT), an avalanche photodiode (APD), etc.

[0028] In another embodiment, the controller 104 may obtain one or more measurements of the sample 120. For example, the controller 104 may be configured to collect metrology measurements of the sample 120.

[0029] The collection arm 116 may further include collection optics 130 for directing and / or modifying the illumination collected by the second focusing element 128, including, but not limited to, one or more lenses, one or more filters, one or more polarizers, or one or more phase plates.

[0030] As used throughout this disclosure, the term "sample" generally refers to a substrate formed from a semiconductor or non-semiconductor material (e.g., a wafer, a reticle, etc.). For example, the semiconductor or non-semiconductor material may include, but is not limited to, monocrystalline silicon, gallium arsenide, and indium phosphide. A sample may include one or more layers. For example, such layers may include, but are not limited to, resist, dielectric material, conductive material, and semiconductor material. Many different types of such layers are known in the art, and the term sample, as used herein, is intended to encompass samples on which all types of such layers may be formed. One or more layers formed on a sample may be patterned or unpatterned. For example, a sample may include multiple dies, each die having repeatable patterned features. The formation and processing of such layers of material may ultimately result in a completed device. Many different types of devices can be formed on a sample, and the term sample, as used herein, is intended to encompass samples on which any type of device known in the art is fabricated. Furthermore, for purposes of this disclosure, the terms sample and wafer should be interpreted as interchangeable.

[0031] It is noted herein that one or more components of system 100 may be communicatively coupled to various other components of system 100 in any manner known in the art. For example, one or more processors 106 may be communicatively coupled to each other and the other components via wireline (e.g., copper wire, fiber optic cable, etc.) or wireless connection (e.g., RF coupling, IR coupling, WiMax, Bluetooth, 3G, 4G, 4G LTE, 5G, etc.). As another example, controller 104 may be communicatively coupled to one or more components of metrology subsystem 102 via any wired or wireless connection known in the art.

[0032] In one embodiment, the one or more processors 106 may include any one or more processing elements known in the art. In this sense, the one or more processors 106 may include any microprocessor-type device configured to execute software algorithms and / or instructions. In one embodiment, the one or more processors 106 may be comprised of a desktop computer, a mainframe computer system, a workstation, an image computer, a parallel processor, or other computer system (e.g., a networked computer) configured to execute programs configured to operate the system 100 as described throughout this disclosure. It should be appreciated that the steps described throughout this disclosure may be performed by a single computer system or, alternatively, by multiple computer systems. Furthermore, it should be appreciated that the steps described throughout this disclosure may be performed in any one or more of the one or more processors 106. In general, the term “processor” may be broadly defined to encompass any device having one or more processing elements that execute program instructions from memory 108. Additionally, different subsystems of system 100 (e.g., illumination source 112, detector assembly 118, controller 104, user interface 110, etc.) may include processors or logic elements suitable for performing at least some of the steps described throughout this disclosure. Accordingly, the above description should not be construed as a limitation on the present disclosure, but merely as an example.

[0033] The memory 108 may include any storage medium known in the art suitable for storing program instructions executable by the associated one or more processors 106 and data received from the metrology subsystem 102. For example, the memory 108 may include a non-transitory storage medium. For example, the memory 108 may include, but is not limited to, read-only memory (ROM), random access memory (RAM), magnetic or optical memory devices (e.g., disks), magnetic tape, solid-state drives, etc. It should further be noted that the memory 108 may be housed within a common controller housing along with one or more processors 106. In alternative embodiments, the memory 108 may be located remotely relative to the physical locations of the processors 106, the controller 104, etc. In another embodiment, the memory 108 holds program instructions for causing one or more processors 106 to perform various steps described throughout this disclosure.

[0034] In one embodiment, the user interface 110 is communicatively coupled to the controller 104. In one embodiment, the user interface 110 may include, but is not limited to, one or more desktops, tablets, smartphones, smartwatches, etc. In another embodiment, the user interface 110 includes a display used to display data of the system 100 to a user. The display of the user interface 110 may include any display known in the art. For example, the display may include, but is not limited to, a liquid crystal display (LCD), an organic light-emitting diode (OLED)-based display, or a CRT display. Those skilled in the art will recognize that any display device that can be integrated with the user interface 110 is suitable for implementation in the present disclosure. In another embodiment, a user may input selections and / or commands in response to data displayed to the user via a user input device of the user interface 110.

[0035] In at least one set of embodiments, as shown in Figures 2-5, resolution enhancement can help reduce the computational time and / or resource costs of a physical simulation model by using the output of the physical simulation model at a first grid size as input and generating a refined output based on a second grid size.

[0036] It is noted herein that the physical simulation model may be a simulation of on-wafer performance of applying lithography and / or plasma processes (e.g., etching, deposition, ion implantation, etc.) during microelectronic device fabrication, as described throughout this disclosure.

[0037] FIG. 2 shows a flow diagram illustrating a method or process 200 for developing a resolution enhancement model (REM) in accordance with one or more embodiments of the present disclosure. FIG. 3 shows a block diagram 300 of the method or process 200 for developing a REM in accordance with one or more embodiments of the present disclosure. The method or process 200 may utilize information such as one or more measurements from a metrology tool (e.g., the metrology subsystem 102 shown in FIGS. 1A and 1B). In this regard, the method or process 200 may include steps performed by / in one or more processors 106 of the controller 104.

[0038] In step 202, a physical simulation model may be run at a first grid size. The physical simulation model 302 may include a grid size Δ, where “Δ” is a computationally efficient degree of mesh refinement or grid resolution that enables faster solution times. Output 304 at grid size Δ may be generated by the physical simulation model 302.

[0039] In step 204, the physical simulation model may be run at a second grid size. The physical simulation model 306 may include a grid size fΔ, where f is a degree of mesh refinement or grid resolution utilized to capture a selected or desired level of detail in the simulation output. For example, f may be less than 1.0. Output 308 at grid size fΔ may be generated by the physical simulation model 306.

[0040] It is noted herein that the physical simulation models 302, 306 used in steps 202 and 204, respectively, may be the same or different physical simulation models. Additionally, it is noted herein that steps 202 and 204 may be performed in any order or simultaneously.

[0041] In step 206, a REM may be developed based on outputs from the physical simulation model run at the first grid size and the physical simulation model run at the second grid size. Developing the REM 310 may include generating the REM, adjusting the REM, refining the REM, etc.

[0042] The output of a physical simulation model running at a Δ grid size may be mapped to the output of a physical simulation model running at an fΔ grid size. In one non-limiting example, the output of the physical simulation model may be processed to achieve a desired uniformity of results. For example, if the output of the physical simulation model is an image, the image may be optionally manipulated for image sharpness, color depth, color range, or the like. In another non-limiting example, the output of the physical simulation model may be scaled up (or down) for REM utilization and / or development.

[0043] REMs may be developed using several techniques. For example, REMs may be developed using machine learning models that utilize any technique known in the art, including, but not limited to, supervised learning, unsupervised learning, etc. For example, machine learning models may include learning-based processes, including, but not limited to, linear regression, neural networks or deep neural networks, heuristic-based models, etc. For example, heuristic-based models may utilize physical information about the process being modeled (e.g., pressure, temperature, gas mixture flow rate, gas mixture concentration, etc.).

[0044] The REM may be developed through tuning or refinement (e.g., for optimization of a selected quantity) to achieve a desired degree of similarity in the output from the REM model. For example, the metric describing the similarity may depend on the type of data. For example, the metric may be based on other statistical tests, including, but not limited to, the standardized sum of squared deviations, goodness of fit, and / or the sum of least squared deviations, signal-to-noise ratio (e.g., peak, geometric, etc.), structural similarity index measures (and variations thereof), or any other statistical metric known in the art.

[0045] FIG. 4 shows a flow diagram illustrating a method or process 400 for accelerating a physical simulation model during microelectronic device manufacturing in accordance with one or more embodiments of the present disclosure. FIG. 5 shows a block diagram 500 of the method or process 400 for accelerating a physical simulation model during microelectronic device manufacturing in accordance with one or more embodiments of the present disclosure. The method or process 400 may utilize information such as one or more measurements from a metrology tool (e.g., the metrology subsystem 102 shown in FIGS. 1A and 1B). In this regard, the method or process 400 may include steps performed by / in one or more processors 106 of the controller 104.

[0046] In step 402, one or more physical simulation models may be run at a first grid size. The one or more physical simulation models 502 may include a grid size Δ, where “Δ” is a computationally efficient degree of mesh refinement or grid resolution that enables faster time-to-solution. However, it is noted herein that the one or more physical simulation models 502 may be run at a grid size different from Δ (e.g., a δ grid size). It is further noted herein that the one or more physical simulation models 502 may be the same as or different from the physical simulation models 302, 306. An output 504 at grid size Δ may be generated by the physical simulation model 502.

[0047] In step 404, the output from the physical simulation model may be run through a REM. For example, the REM 506 may be developed using one or more steps of the method or process 200.

[0048] In step 406, a second grid size output can be generated via REM. REM 506 can generate output at a grid size fΔ, where f is a degree of mesh refinement or grid resolution utilized to capture a selected or desired level of detail in the simulation output. For example, f may be less than 1.0.

[0049] If the output from step 402 with grid size Δ is passed through REM 506 once, the output from REM 506 will have a grid size fΔ based on the development of REM 506 (e.g., as shown in FIGS. 2 and 3). However, it is noted herein that REM 506 may be utilized multiple times to generate an output with a degree of refinement less than f. For example, "p" passes through REM 506 may be used to generate "f" p For example, two passes through the REM 506 may produce outputs corresponding to a grid size of "f 2Δ” grid size.

[0050] While Figures 2-5 show that the output of a physical simulation model is input to the REM, it should be noted that in this specification, the REM is not limited to the output of a physical simulation model being input after the REM is developed.

[0051] In another set of embodiments, as shown at least in FIGS. 6 and 7, an iterative optimization algorithm can be utilized in combination with method or process 200 and / or 400 to adjust or refine parameters of a physical simulation model (e.g., for a selected amount of optimization) so that the output resembles 50-100 percent of a reference data set. For example, the reference data may be collected experimentally by system 100 (e.g., as images, probe measurements, optical measurements, scattering patterns, etc.) and / or may be the output of another physical simulation model. For purposes of this embodiment, an output similar to or near 100 percent may indicate perfect agreement with the reference data, while an output similar to or near 50 percent may indicate the output is ±0.5 times the reference data.

[0052] FIG. 6 illustrates a method or process 600 for accelerating a physical simulation model during microelectronic device manufacturing in accordance with one or more embodiments of the present disclosure. FIG. 7 illustrates a block diagram 700 of the method or process 600 for accelerating a physical simulation model during microelectronic device manufacturing in accordance with one or more embodiments of the present disclosure. The method or process 600 may utilize information such as one or more measurements from a metrology tool (e.g., the metrology subsystem 102 shown in FIGS. 1A and 1B ). In this regard, the method or process 600 may include steps performed by / in one or more processors 106 of the controller 104.

[0053] In step 602, one or more physical simulation models may be run at a first grid size based on one or more parameters. The one or more physical simulation models 702 may include a grid size Δ, where “Δ” is a computationally efficient degree of mesh refinement or grid resolution that enables faster solution times. Further, it is noted herein that the one or more physical simulation models 702 may be the same as or different from the physical simulation models 302, 306, 502.

[0054] One or more physical simulation models 702 may be configured to calculate one or more parameters 704 (e.g., p j ), where j ranges between 1, 2, and n. For example, the method may be performed based on one or more parameters 704 (e.g., p1, p2, p n ) may be the parameters selected to be optimized. n Note that the initial value of ) can be estimated or received from a third party.

[0055] The output 706 at grid size Δ may be generated by the physical simulation model 702. The output 706 (e.g., q j,i ) may include a list of outputs j generated through a physical simulation model for different conditions i or combinations of different conditions, where i ranges between 1, 2, ..., m. For example, outputs 706 (e.g., q 1,i ,q 2i ,....q n.i ) may be output with a grid size of Δ. Note that herein, n (e.g., for j) and m (e.g., for i) may be the same or different.

[0056] In step 604, the output from the physical simulation model may be run through a REM. For example, the REM 708 may be developed using one or more steps of the method or process 200.

[0057] In step 606, an output of a second grid size can be generated via REM. j.i ) may be input to REM 708, which outputs 706 (e.g., q j.i ), where f is the degree of mesh refinement or grid resolution utilized to capture a selected or desired level of detail in the simulation output. For example, f may be less than 1.0.

[0058] In step 608, the output from the REM at the second grid size may be compared to the reference data. The output 706 at the increased resolution grid size fΔ (e.g., q j.i ) is the output 706 (e.g., q j.i ) may be compared with the reference data 710 until it is within a desired mismatch tolerance or threshold of the corresponding reference data 710. For example, the mismatch tolerance or threshold may vary between 0 (e.g., an output that is at or near 100 percent similar may indicate a perfect match with the reference data) and 50 percent (e.g., the output is 50 percent or nearly 50 percent similar to the reference data).

[0059] In step 610, one or more parameters may be iteratively adjusted. The output 706 (e.g., q j,iIf the model parameters 704 (e.g., pj) are outside (e.g., not inside) a desired mismatch tolerance or threshold, the model parameters 704 (e.g., pj) may be iteratively adjusted and the output 706 from the physical simulation model 702 may be re-run through REM. In contrast, if the output 706 at an increased resolution grid size fΔ (e.g., q i,i ) is within a desired mismatch tolerance or threshold, then the method or process 600 is complete.

[0060] In another set of embodiments, as shown in at least Figures 8 and 9, post-processing procedures may be utilized in conjunction with methods or processes 200, 400, and / or 600 and applied to the output of a physical simulation model. For example, post-processing procedures may include, but are not limited to, Monte Carlo simulations that utilize randomness to solve problems that are otherwise deterministic but may produce results that have a probabilistic interpretation.

[0061] FIG. 8 illustrates a method or process 800 for accelerating a physical simulation model during microelectronic device manufacturing in accordance with one or more embodiments of the present disclosure. FIG. 9 illustrates a block diagram 900 of the method or process 800 for accelerating a physical simulation model during microelectronic device manufacturing in accordance with one or more embodiments of the present disclosure. The method or process 800 may utilize information such as one or more measurements from a metrology tool (e.g., the metrology subsystem 102 shown in FIGS. 1A and 1B ). In this regard, the method or process 800 may include steps performed by / in one or more processors 106 of the controller 104.

[0062] In step 802, multiple trials of one or more physical simulation models at a first grid size may be performed. The one or more physical simulation models 902 may include a grid size Δ, where “Δ” is a computationally efficient degree of mesh refinement or grid resolution that enables faster time-to-solution. Further, it is noted herein that the one or more physical simulation models 902 may be the same as or different from the physical simulation models 302, 306, 502, 702.

[0063] To consider all possible scenarios, multiple trials can be performed using the physical simulation model 902 at grid size Δ (e.g., for the same or similar conditions or inputs). One or more outputs 904 at grid size Δ of the physical simulation model 902 can be generated.

[0064] At step 804, outputs from multiple runs of one or more physical simulation models may be run through one or more post-processing models. The outputs 904 of the multiple runs may be run through one or more post-processing models 906. For example, the one or more post-processing models 906 may manipulate the outputs 904 of the multiple runs for image clarity, color depth, color range, etc. As another example, the one or more post-processing models 906 may include a Monte Carlo simulation. The one or more post-processing models 906 may generate one or more probabilistic outputs 908 for the multiple runs. This may determine a probabilistic distribution of the outputs 904 across a grid size Δ of the one or more physical simulation models 902. It is noted herein that the outputs of the multiple physical simulation models may be run through the post-processing models together or in one or more batches (e.g., up to the entire set of outputs).

[0065] In step 806, the output from the one or more post-processing models may be run through a REM. The stochastic output 908 at grid size Δ from the one or more post-processing models 906 may be run through a REM 910. For example, the REM 910 may be developed using one or more steps of the method or process 200.

[0066] In step 808, outputs of a second grid size can be generated via REM. REM 910 can generate outputs 912 at a grid size fΔ, where f is a degree of mesh refinement or grid resolution utilized to capture a selected or desired level of detail in the simulation output. For example, f may be less than 1.0. Note herein that the probabilistic outputs 908 can be run through REM 910 together or in one or more (e.g., up to the entire set of outputs) batches. In this regard, the outputs 912 at grid size fΔ can include distributions corresponding to the outputs 908 generated by one or more post-processing models 906, where the one or more post-processing models receive the outputs 904 of the multiple trials.

[0067] In another set of embodiments, as illustrated in at least FIGS. 10-11B, the REM may be trained in a machine learning model, which may be utilized in combination with methods or processes 200, 400, 600, and / or 800.

[0068] FIG. 10 illustrates a method or process 1000 for accelerating a physical simulation model during microelectronic device manufacturing in accordance with one or more embodiments of the present disclosure. FIGS. 11A and 11B illustrate schematic diagrams 1100 and 1110 of a method or process 1000 for accelerating a physical simulation model during microelectronic device manufacturing in accordance with one or more embodiments of the present disclosure. The method or process 1000 may utilize information such as one or more measurements from a metrology tool (e.g., the metrology subsystem 102 shown in FIGS. 1A and 1B). In this regard, the method or process 1000 may include steps performed by / in one or more processors 106 of the controller 104.

[0069] During the training phase 1100 shown in FIG. 11A , a trained REM is generated at step 1002. One or more physical simulation models 1102 that generate output at a first grid size and one or more physical simulation models 1104 that generate output at a second grid size may be input to a training algorithm 1106. The physical simulation models 1102 may include a grid size Δ, where “Δ” is a computationally efficient degree of mesh refinement or grid resolution that enables faster time-to-solution. The physical simulation models 1104 may include a grid size fΔ, where f is a degree of mesh refinement or grid resolution utilized to capture a selected or desired level of detail in the simulation output. For example, f may be less than 1.0. Note that the output of the grid size Δ may be input information, and the output of the grid size Δ may be target information.

[0070] The learning algorithm 1106 may implement a machine learning model utilizing any technique known in the art, including but not limited to supervised learning, unsupervised learning, etc. For example, the machine learning model may include a learning-based process (e.g., linear regression, neural or deep neural networks, heuristic-based models, etc.) configured to generate a trained REM 1108. For example, a heuristic-based model may leverage physical information about the process being modeled.

[0071] During the test / production phase 1110 illustrated in FIG. 11B , data from one or more physical simulation models at a first grid size is input in step 1004. Data from one or more physical simulation models 1112 that generate outputs at the first grid size for n trials can be input to a trained REM 1108. In step 1006, outputs at a second grid size are generated via the trained REM, which can generate outputs 1114 having a grid size fΔ for m trials. Note that, herein, “n” can range between 4 and 1 trillion (e.g., at low resolution), while “m” can range between 1 and 10,000 (e.g., at high resolution). Additionally, note that, herein, a subset of “n” trials can equal a single output via the REM. In one non-limiting example, it is noted herein that four images (or n=4) of low resolution Δ can be equal to one image (or m=1) of high resolution fΔ.

[0072] A description of the learning-based process can be found in D.C. Montgomery et al., Introduction to Linear Regression Analysis, New York: Wiley, 2001, which is incorporated by reference in its entirety. Additionally, a description of the learning-based process can be found in I. Goodfellow, et al., Deep Learning, The MIT Press, 2016, which is incorporated by reference in its entirety.

[0073] It should be noted that the embodiments and enabling techniques described herein above in the context of system 100 should be construed as extending to methods or processes 200, 400, 600, 800, 1000, and 1000. In this regard, the steps of methods or processes 200, 400, 600, 800, and 1000 may be performed by system 100, and methods or processes 200, 400, 600, 800, and 1000 may further include one or more steps required or implied by the architecture of system 100. However, it will be recognized that methods or processes 200, 400, 600, 800, and 1000 are not limited to the architecture of system 100, and one or more steps of methods or processes 200, 400, 600, 800, and 1000, or portions thereof, may be performed using alternative system components and / or architectures. Furthermore, the steps of the methods or processes 200, 400, 600, 800, 1000 may be performed in any order unless otherwise specified herein.

[0074] In one non-limiting example, in an optional step for any of the methods or processes, one or more control signals are configured to selectively adjust one or more characteristics of one or more process tools based on the REM. System 100 may further include one or more process tools communicatively coupled to controller 104. For example, the one or more process tools may include any process tools known in the art for microelectronic manufacturing, including, but not limited to, lithography tools and / or plasma process tools (e.g., etch tools, deposition tools, polishing tools, scanners, etc.). Controller 104 may be configured to generate one or more control signals configured to adjust one or more characteristics of the one or more process tools in a feedforward or feedback loop based on the REM.

[0075] In another non-limiting example, in an optional step, one or more control signals are configured to selectively adjust one or more characteristics of the metrology subsystem 102 of the system 100 based on the REM.

[0076] It should be noted herein that the methods or processes 200, 400, 600, 800, 1000 are not limited to the steps and / or sub-steps provided. The methods or processes 200, 400, 600, 800, 1000 may include more or fewer steps and / or sub-steps. The methods or processes 200, 400, 600, 800, 1000 may perform steps and / or sub-steps simultaneously. The methods or processes 200, 400, 600, 800, 1000 may perform steps and / or sub-steps sequentially, including in the order provided or in an order other than that provided. Therefore, the above description should not be construed as a limitation on the scope of the present disclosure, but should be interpreted merely as an example.

[0077] In one non-limiting example, an output from a physical simulation model at a high-resolution grid size fΔ and an output from a physical simulation model at a low-resolution grid size Δ may be received or generated. In this example, the output may be in the form of an image of the etch process. However, the output need not be a raw image, but instead may be preprocessed and / or represented by a list of parameters (e.g., pj) that allow faithful reconstruction of a typical output of the physical model. Additionally, it should be noted that the physical models used herein may similarly be utilized for alternative on-wafer processes, including, but not limited to, deposition and / or lithography or any other physical model.

[0078] The REM may be generated by any combination of methods or processes 200, 400, 600, 800, 1000. For example, the REM may be generated by mapping output from a physical simulation model at a high-resolution grid size fΔ to output from a physical simulation model at a low-resolution grid size Δ. For example, the mapping may require training the REM with a learning algorithm such as described with respect to method or process 1000.

[0079] FIG. 12 shows a graph 1200 comparing the validation loss 1202 and the training loss 1204. As shown in the graph 1200, both the validation loss 1202 and the training loss 1204 decrease with an increasing number of training epochs. When the validation loss 1202 reaches or saturates a selection threshold, the training of the REM can be considered complete. Note that the selection threshold may vary. Furthermore, it is noted herein that the range of the selection threshold may depend on one or more requirements of the training model and / or loss function applied during the training of the REM. For example, the range of the selection threshold may be between 10e -5 and 10e 5 It can be between.

[0080] Following training of the REM, the image output from the physical simulation model at a grid size Δ can be utilized in the REM to generate an output that corresponds to the output of the physical simulation model at a grid size fΔ. For example, if the grid size Δ is 2 nanometers (nm) and f is 0.25, the output of the REM is a grid size of 0.5 nm.

[0081] 13 illustrates a set of images 1300, including a coarse resolution image of 2 nm and a fine resolution image of 0.5 nm, acquired from system 100 (e.g., from metrology subsystem 102) for two different patterns 1302, 1304. Set of images 1300 compares an actual physical model at 2 nm, an actual physical model at 0.5 nm, and an image generated by REM with a 4x resolution increase from the actual physical model at 2 nm for each of the two different patterns 1302, 1304. As can be seen from the comparison, the 4x resolution increase image generated by REM of the actual physical model at 2 nm accurately captures the attributes of the actual physical model at 0.5 nm, while the ability to utilize REM may significantly reduce the computational time and / or cost that would otherwise be required if the images were taken at 0.5 nm resolution. It is noted herein that both the Peak Signal-to-Noise Ratio (PSNR) and Structural Similarity Index Measure (SSIM) metrics are provided to describe the degree of similarity of the REM output at 0.5 nm and the actual physical model at 4x resolution increase.

[0082] In this regard, the present disclosure has several advantages over conventional systems and methods. Embodiments of the present disclosure are directed to combining physical modeling with acceleration techniques to enable higher levels of detail. Embodiments of the present disclosure are directed to combining physical modeling with image-based techniques. Embodiments of the present disclosure are directed to combining physical modeling with learning algorithms. Embodiments of the present disclosure are directed to accelerating demo cycles by utilizing data generated a priori from physical simulation models. Embodiments of the present disclosure are directed to generating probability distributions (e.g., Monte Carlo methods) at finer grid resolution without increasing computational load.

[0083] Those skilled in the art will recognize that the components (e.g., operations), devices, objects, and accompanying discussion described herein are used as examples for conceptual clarity, and that various configuration modifications are contemplated. Thus, as used herein, the specific examples described and accompanying discussion are intended to be representative of their more general classes. In general, the use of any specific example is intended to represent its class, and non-inclusion of specific components (e.g., operations), devices, and objects should not be construed as limiting.

[0084] As will be appreciated by those skilled in the art, these may be accomplished using various processes and / or systems and / or other techniques (wherein, once the vehicle has been transformed into a (e.g., hardware, software, and / or firmware) vehicle, contextual processes and / or systems and / or other techniques are provided. For example, if the implementer determines that speed and accuracy are paramount, the implementer may select a primarily hardware and / or firmware vehicle; alternatively, if flexibility is paramount, the implementer may opt for a primarily software implementation; or, again alternatively, the implementer may select some combination of hardware, software, and / or firmware. Thus, there are several possible vehicles by which the processes and / or devices and / or other techniques described herein may be accomplished, none of which is inherently superior to another, in that any vehicle utilized is a choice that depends on the context in which the vehicle is deployed and the implementer's specific concerns (e.g., speed, flexibility, or predictability), and is subject to variation.

[0085] The preceding description is presented to enable one skilled in the art to make and use the invention as provided in the context of a particular application and its requirements. As used herein, directional terms such as "up," "down," "upper," "lower," "upper," "upper," "lower," and the like are intended to provide relative positions for descriptive purposes and are not intended to indicate an absolute frame of reference. Various modifications to the described embodiments will be apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments. Therefore, the present invention is not limited to the particular embodiments shown and described, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0086] With respect to the use of virtually any plural and / or singular term herein, those skilled in the art will be able to convert from the plural to the singular and / or from the singular to the plural as appropriate to the context and / or application. The various singular / plural permutations are not expressly set forth herein for ease of understanding.

[0087] All of the methods described herein may include storing results of one or more steps of a method embodiment in memory. The results may include any of the results described herein and may be stored in any manner known in the art. The memory may include any memory described herein or any other suitable storage medium known in the art. After the results are stored, they can be accessed in memory, used by any of the method or system embodiments described herein, formatted for display to a user, used by another software module, method, or system, etc. Furthermore, the results may be stored “permanently,” “semi-permanently,” “temporarily,” or for a period of time. For example, the memory may be random access memory (RAM), and the results may not necessarily persist in memory indefinitely.

[0088] It is further contemplated that each of the above-described method embodiments may include any other step(s) of any other method(s) described herein. In addition, each of the above-described method embodiments may be performed by any of the systems described herein.

[0089] The subject matter described herein illustrates different components that are, in some cases, included within or connected to other components. It should be understood that such depicted architectures are merely exemplary, and that in fact many other architectures that achieve the same functionality may be implemented. In a conceptual sense, any arrangement of components to achieve the same functionality is effectively “associated” such that the desired functionality is achieved. Thus, any two components herein that combine to achieve a particular function can be considered to be “associated” with each other such that the desired functionality is achieved, regardless of the architecture or intermediate components. Similarly, any two components so associated can also be considered to be “connected” or “coupled” to each other to achieve the desired functionality, and any two components that can be so associated can also be considered to be “couplable” with each other to achieve the desired functionality. Specific examples of what can be coupled include, but are not limited to, physically coupleable and / or physically interacting components and / or wirelessly interacting and / or wirelessly interacting components and / or logically interacting and / or logically interacting components.

[0090] It should further be understood that the present invention is defined by the appended claims. In general, those skilled in the art will understand that the terms used in this specification, and particularly in the appended claims (e.g., the body of the appended claims), are generally intended as "open" terms (e.g., the term "including" should be interpreted as "including but not limited to," the term "having" should be interpreted as "having at least," the term "includes" should be interpreted as "includes but not limited to," etc.). Those skilled in the art will further understand that if a specific number of introduced claim recitations is intended, such intention will be expressly recited in the claim; in the absence of such recitation, no such intention exists. For example, as an aid to understanding, the following appended claims may include the use of the introductory phrases "at least one" and "one or more" to introduce claim recitations. However, the use of such phrases should not be interpreted as meaning that the introduction of a claim recitation with the indefinite article "a" or "an" limits any particular claim containing such an introduced claim recitation to an invention containing only one such recitation. The same applies to the use of express articles used to introduce claim recitations, even when the same claim includes the introductory phrase "one or more" or "at least one" and an indefinite article such as "a" or "an" (e.g., "a" and / or "an" should typically be interpreted to mean "at least one" or "one or more"). Those skilled in the art will also recognize that even when a specific number of introduced claim recitations is explicitly recited, such a recitation should typically be interpreted to mean at least the recited number (e.g., a bare recitation of "two recitations" without other modifiers typically means at least two recitations, or two or more recitations).Furthermore, in instances where a conventional expression similar to "such as at least one of A, B, and C" is used, such configuration is generally intended in the sense that one of ordinary skill in the art would understand the conventional expression (e.g., "a system having at least one of A, B, and C" includes, but is not limited to, a system having only A, a system having only B, a system having only C, a system having both A and B, a system having both A and C, a system having both B and C, and / or a system having both A, B, and C, etc.). In instances where a conventional expression similar to "such as at least one of A, B, or C" is used, such configuration is generally intended in the sense that one of ordinary skill in the art would understand the conventional expression (e.g., "a system having at least one of A, B, or C" includes, but is not limited to, a system having only A, a system having only B, a system having only C, a system having both A and B, a system having both A and C, a system having both B and C, and / or a system having both A, B, and C, etc.). Those of ordinary skill in the art will further understand that virtually any disjunctive word and / or phrase presenting two or more alternative terms, wherever it appears in the description, claims, or drawings, should be understood to contemplate the possibility of including one of the terms, either of the terms, or both terms. For example, the phrase "A or B" would be understood to include the possibilities of "A" or "B" or "A and B."

[0091] It is believed that the present disclosure and many of its attendant advantages will be understood from the foregoing description, and it will be apparent that various changes can be made in the form, construction, and arrangement of the elements without departing from the disclosed subject matter or sacrificing all of its material advantages. The described forms are merely illustrative, and it is the intent of the following claims to embrace and include such modifications. It is further understood that the invention is defined by the appended claims.

Claims

1. 1. A system comprising: a controller including one or more processors and a memory, the memory configured to store program instructions, the one or more processors being configured to execute the program instructions causing the one or more processors to: running a physical simulation model at a first grid size having a first resolution, the physical simulation model simulating on-wafer performance of at least one microelectronic device manufacturing process; generating output from the physical simulation model at a first grid size having the first resolution; inputting output from the physical simulation model at a first grid size with the first resolution into an enhanced resolution model (REM); generating an output at a second grid size having a second resolution via the REM, the second grid size being smaller than the first grid size and the second resolution being greater than the first resolution; adjusting the REM to achieve a desired degree of similarity in the output of the REM; Run A system in which generating an output at a second grid size having the second resolution via the REM based on an output at a first grid size having the first resolution from the physical simulation model reduces at least one of the computational time cost or computational resource cost of the controller for executing the physical simulation model.

2. 2. The system of claim 1, wherein output from the physical simulation model at a first grid size and having the first resolution includes one or more images having the first resolution, and output from the physical simulation model at a second grid size and having the second resolution generated via the REM includes one or more images having the second resolution.

3. The system of claim 1 , wherein the first grid size is Δ and the second grid size is fΔ, where f is less than 1.

0.

4. The controller running the physical simulation model at a first grid size having the first resolution; running the physical simulation model at a second grid size having the second resolution; developing the REM based on output from the physical simulation model run on a first grid size having the first resolution and the physical simulation model run on a second grid size having the second resolution; The system of claim 1 , further configured to:

5. The controller developing the REM through a learning process of at least one of a deep learning model, a machine learning model, or a heuristics-based model; The system of claim 4 , further configured to:

6. The controller running the physical simulation model at a first grid size with the first resolution for n trials; generating m outputs at a second grid size having the second resolution from the REM, where m is less than n; The system of claim 5 , further configured to:

7. 7. The system of claim 6, wherein the subset of n trials is equal to a single output through the REM.

8. The controller comparing the output at the second grid size and the second resolution produced by the REM with a set of reference data to determine whether the output at the second grid size and the second resolution is within a selected mismatch tolerance; iteratively adjusting one or more parameters of the physical simulation model if the output of the second grid size with the second resolution is outside a selected mismatch tolerance; The system of claim 1 , further configured to:

9. The controller obtaining a set of reference data from the metrology subsystem; The system of claim 8 , further configured to:

10. The controller running a plurality of trials of the physical simulation model at a first grid size having the first resolution to generate a probability distribution for the plurality of trials; generating a plurality of outputs from the plurality of runs of the physical simulation model at a first grid size having the first resolution; running a plurality of outputs at a first grid size having said first resolution through a post-processing model; generating, via a post-processing model, a plurality of post-processing model outputs at a first grid size having the first resolution; running a plurality of post-processed model outputs at a first grid size with the first resolution through the REM; generating a plurality of outputs from the REM at a second grid size having the second resolution; The system of claim 1 , further configured to:

11. The system of claim 10 , wherein the post-processing model comprises a Monte Carlo simulation.

12. 1. A method comprising: running a physical simulation model at a first grid size having a first resolution, the physical simulation model simulating on-wafer performance of at least one microelectronic device manufacturing process; generating output from the physical simulation model at a first grid size having the first resolution; inputting output from the physical simulation model at a first grid size having the first resolution into an enhanced resolution model (REM); generating an output at a second grid size having a second resolution via the REM, the second grid size being smaller than the first grid size and the second resolution being greater than the first resolution; adjusting the REM to achieve a desired degree of similarity in the output of the REM; Equipped with The method, wherein generating an output at a second grid size having a second resolution via the REM based on an output at a first grid size having the first resolution from the physical simulation model reduces at least one of a computational time cost or a computational resource cost of a controller executing the physical simulation model.

13. 13. The method of claim 12, wherein output from the physical simulation model at a first grid size and having the first resolution includes one or more images having the first resolution, and output from the physical simulation model at a second grid size and having the second resolution generated via the REM includes one or more images having the second resolution.

14. 13. The method of claim 12, wherein the first grid size is Δ and the second grid size is fΔ, where f is less than 1.

0.

15. running the physical simulation model at a first grid size having the first resolution; running the physical simulation model at a second grid size having the second resolution; developing the REM based on output from the physical simulation model run on a first grid size having the first resolution and the physical simulation model run on a second grid size having the second resolution; The method of claim 12 further comprising:

16. developing the REM through a learning process of at least one of a deep learning model, a machine learning model, or a heuristics-based model; 16. The method of claim 15 further comprising:

17. running the physical simulation model at a first grid size with the first resolution for n trials; generating m outputs at a second grid size having the second resolution from the REM, where m is less than n; 17. The method of claim 16 further comprising:

18. 18. The method of claim 17, wherein the subset of n trials is equal to a single output through the REM.

19. comparing the output at the second grid size and the second resolution produced by the REM with a set of reference data to determine whether the output at the second grid size and the second resolution is within a selected mismatch tolerance; iteratively adjusting one or more parameters of the physical simulation model if the output of the second grid size with the second resolution is outside a selected mismatch tolerance; The method of claim 12 further comprising:

20. obtaining a set of reference data from the metrology subsystem; 20. The method of claim 19 further comprising:

21. running a plurality of trials of the physical simulation model at a first grid size having the first resolution to generate a probability distribution for the plurality of trials; generating a plurality of outputs from the plurality of runs of the physical simulation model at a first grid size having the first resolution; running a plurality of outputs at a first grid size having said first resolution through a post-processing model; generating, via a post-processing model, a plurality of post-processing model outputs at a first grid size having the first resolution; running the plurality of post-processed model outputs through the REM at a first grid size having the first resolution; generating a plurality of outputs from the REM at a second grid size having the second resolution; The method of claim 12 further comprising:

22. The method of claim 21 , wherein the post-processing model comprises a Monte Carlo simulation.

23. 1. A system comprising: a metrology subsystem configured to obtain one or more measurements of a portion of the sample; a communicatively coupled controller, the controller including one or more processors and a memory, the memory configured to store program instructions, the one or more processors configured to execute the program instructions, the one or more processors: acquiring one or more inputs from the metrology subsystem, the one or more inputs including an image having a first resolution; running a physical simulation model at a first grid size having a first resolution, the physical simulation model simulating on-wafer performance of at least one microelectronic device manufacturing process; generating output from the physical simulation model at a first grid size having the first resolution; inputting output from the physical simulation model at a first grid size with the first resolution into an enhanced resolution model (REM); generating an output at a second grid size having a second resolution via the REM, the second grid size being smaller than the first grid size and the second resolution being greater than the first resolution; adjusting the REM to achieve a desired degree of similarity in the output of the REM; Run A system in which generating an output at a second grid size having the second resolution via the REM based on an output at a first grid size having the first resolution from the physical simulation model reduces at least one of the computational time cost or computational resource cost of the controller for executing the physical simulation model.

24. 24. The system of claim 23, wherein output from the physical simulation model at a first grid size and having the first resolution includes one or more images having the first resolution, and output from the physical simulation model at a second grid size and having the second resolution generated via the REM includes one or more images having the second resolution.

25. 24. The system of claim 23, wherein the first grid size is Δ and the second grid size is fΔ, where f is less than 1.

0.

26. The controller running the physical simulation model at a first grid size having the first resolution; running the physical simulation model at a second grid size having the second resolution; developing the REM based on outputs from the physical simulation model run at a first grid size with the first resolution and the physical simulation model run at a second grid size with the second resolution.

24. The system of claim 23, further configured to:

27. The controller developing the REM through a learning process of at least one of a deep learning model, a machine learning model, or a heuristics-based model; 27. The system of claim 26, further configured to:

28. The controller running the physical simulation model at a first grid size with the first resolution for n trials; generating m outputs at a second grid size having the second resolution from the REM, where m is less than n; 28. The system of claim 27, further configured to:

29. 30. The system of claim 28, wherein the subset of n trials is equal to a single output through the REM.

30. The controller comparing the output at the second grid size and the second resolution produced by the REM with a set of reference data to determine whether the output at the second grid size and the second resolution is within a selected mismatch tolerance; iteratively adjusting one or more parameters of the physical simulation model if the output of the second grid size with the second resolution is outside a selected mismatch tolerance; 24. The system of claim 23, further configured to:

31. The controller obtaining a set of reference data from the metrology subsystem; 31. The system of claim 30, further configured to:

32. The controller running a plurality of trials of the physical simulation model at a first grid size having the first resolution to generate a probability distribution for the plurality of trials; generating a plurality of outputs at a first grid size having the first resolution from a plurality of runs of the physical simulation model; running a plurality of outputs at a first grid size having said first resolution through a post-processing model; generating, via a post-processing model, a plurality of post-processing model outputs at a first grid size having the first resolution; running a plurality of post-processed model outputs at a first grid size with the first resolution through the REM; generating a plurality of outputs from the REM at a second grid size having the second resolution; 24. The system of claim 23, further configured to:

33. 33. The system of claim 32, wherein the post-processing model comprises a Monte Carlo simulation.

Images