Semiconductor Devices

Abstract

To provide a semiconductor device having less variation of transistor characteristic.SOLUTION: In a semiconductor device, a transistor 200 includes: an insulator 214 on an insulator 216; a conductor 205 arranged so as to be embedded in the insulator 216; an insulator 222 on the insulator 216 and the conductor 205; an insulator 224 there on; an oxide 230 further thereon; conductors 242a and b and insulator 250 on the oxide 230; a conductor 260 positioned on the insulator 250 and overlaps the oxide 230; and an insulator 254 being brought into contact with a part of an upper surface of the insulator 224, a part of a side face of the oxide 230, side faces of the conductors 242a and b, and upper faces of the conductors 242a and b. An upper surface of the oxide 230 in a region overlapping the conductor 260 is lower than an upper surface of the oxide 230 in a region overlapping the conductors 242a and b. The oxide 230 has a curved surface in a region overlapping the conductor 260. A curvature radius of the curved surface is 1 nm or more and 15 nm or more.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] 1. Field of the Invention

[0003] One embodiment of the present invention relates to a transistor, a semiconductor device, and an electronic device. Another embodiment of the present invention relates to a method for manufacturing a semiconductor device. Another embodiment of the present invention relates to a semiconductor wafer and a module.

[0002] In this specification and the like, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. Semiconductor elements such as transistors, semiconductor circuits, arithmetic devices, and memory devices are all embodiments of semiconductor devices. Display devices (liquid crystal display devices, light-emitting display devices, etc.), projection devices, lighting devices, electro-optical devices, power storage devices, memory devices, semiconductor circuits, imaging devices, electronic devices, and the like may be considered to include semiconductor devices.

[0003] Note that one aspect of the present invention is not limited to the above technical fields. One aspect of the invention disclosed in this specification relates to an object, a method, or a manufacturing method. Another aspect of the present invention relates to a process, a machine, a manufacture, or a composition of matter. [Background technology]

[0004] Technology that constructs transistors using semiconductor thin films formed on substrates with insulating surfaces is attracting attention. Such transistors are widely used in electronic devices such as integrated circuits (ICs) and image display devices (also simply referred to as display devices). Silicon-based semiconductor materials are widely known as semiconductor thin films that can be used in transistors, but oxide semiconductors are also attracting attention as other materials.

[0005] In oxide semiconductors, c-axis aligned crystalline (CAAC) structures and nanocrystalline (nc) structures, which are neither single crystal nor amorphous, have been found (see Non-Patent Documents 1 and 2).

[0006] Non-Patent Documents 1 and 2 disclose techniques for manufacturing a transistor using an oxide semiconductor having a CAAC structure. [Prior art documents] [Non-patent literature]

[0007] [Non-Patent Document 1] S. Yamazaki et al., “SID Symposium Digest of Technical Papers”, 2012, volume 43, issue 1, p.183-186 [Non-patent document 2] S. Yamazaki et al., “Japanese Journal of Applied Physics”, 2014, volume 53, Number 4S, p.04ED18-1-04ED18-10 Summary of the Invention [Problem to be solved by the invention]

[0008] An object of one embodiment of the present invention is to provide a semiconductor device with little variation in transistor characteristics. Another object of one embodiment of the present invention is to provide a semiconductor device with large on-state current. Another object of one embodiment of the present invention is to provide a semiconductor device with favorable electrical characteristics. Another object of one embodiment of the present invention is to provide a semiconductor device that can be miniaturized or highly integrated. Another object of one embodiment of the present invention is to provide a semiconductor device with high reliability. Another object of one embodiment of the present invention is to provide a semiconductor device with low power consumption.

[0009] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these will become apparent from the description of the specification, drawings, claims, etc., and it is possible to extract other problems from the description of the specification, drawings, claims, etc. [Means for solving the problem]

[0010] One embodiment of the present invention is a semiconductor device including a transistor. The transistor includes a first insulator, a first oxide on the first insulator, a first conductor, a second conductor, and a second oxide disposed between the first conductor and the second conductor on the first oxide, a second insulator on the second oxide, and a third conductor on the second insulator. An upper surface of the first oxide in a region overlapping with the third conductor is lower than an upper surface of the first oxide in a region overlapping with the first conductor. The first oxide has a curved surface between its side surface and its upper surface in the region overlapping with the third conductor, and the radius of curvature of the curved surface is 1 nm to 15 nm.

[0011] In the above semiconductor device, it is preferable that, when the lower surface of the first insulator is used as a reference, the difference in height between the upper surface of the first oxide in the region overlapping with the third conductor and the upper surface of the first oxide in the region overlapping with the first conductor is 1 nm or more and 5 nm or less.

[0012] In addition, in the above semiconductor device, it is preferable that half the difference in the channel width direction of the transistor between the length of the underside of the first oxide in the region overlapping with the first conductor and the length of the underside of the first oxide in the region overlapping with the third conductor is 2 nm or more and 10 nm or less.

[0013] Furthermore, in the above semiconductor device, it is preferable that the transistor has a third oxide and a fourth oxide, the third oxide is arranged between the first oxide and the first conductor, the fourth oxide is arranged between the first oxide and the second conductor, and the bottom surface of the second oxide is lower than the bottom surfaces of the third oxide and the fourth oxide in the channel length direction of the transistor.

[0014] Another embodiment of the present invention is a semiconductor device having a plurality of transistors, the plurality of transistors having a first insulator, a first oxide on the first insulator, a first conductor, a second conductor, and a second oxide disposed between the first conductor and the second conductor on the first oxide, a second insulator on the second oxide, and a third conductor on the second insulator, wherein an upper surface of the first oxide in a region overlapping with the third conductor is lower than an upper surface of the first oxide in a region overlapping with the first conductor, and the first oxide has a curved surface between its side surface and its upper surface in the region overlapping with the third conductor, and the Id-Vg characteristics of the plurality of transistors have a standard deviation σ of Vsh of less than 60 mV.

[0015] In the semiconductor device, the plurality of transistors preferably have channel lengths of 40 nm to 80 nm, and channel widths of 40 nm to 80 nm.

[0016] In the semiconductor device, the radius of curvature of the curved surface is preferably 1 nm or more and 15 nm or less.

[0017] Another embodiment of the present invention is a semiconductor device including a transistor. The transistor includes a first insulator, a first oxide on the first insulator, a first conductor, a second conductor, and a second oxide disposed between the first conductor and the second conductor on the first oxide, a second insulator on the second oxide, a third conductor on the second insulator, and a third insulator disposed in contact with a top surface of the first conductor, a top surface of the second conductor, and a part of a side surface of the first oxide. The first oxide overlaps with the first conductor in a channel width direction of the transistor. The length of the bottom surface of the first oxide is greater than the length of the bottom surface of the first oxide in the region overlapping with the third conductor, the first oxide has a curved surface between the side surface and the top surface in the region overlapping with the third conductor, the first oxide contains indium, element M (M is gallium, yttrium, or tin), and zinc, the third insulator contains an element that becomes an impurity of the first oxide, and the concentration ratio of the element to element M in the side surface of the first oxide in the region overlapping with the third conductor is smaller than the concentration ratio of the element to element M in the side surface of the first oxide in the region overlapping with the first conductor.

[0018] In the above semiconductor device, the element contained in the third insulator is preferably aluminum.

[0019] In the semiconductor device, the radius of curvature of the curved surface is preferably 1 nm or more and 15 nm or less. [Effects of the Invention]

[0020] According to one embodiment of the present invention, a semiconductor device with little variation in transistor characteristics can be provided. According to another embodiment of the present invention, a semiconductor device with large on-state current can be provided. According to another embodiment of the present invention, a semiconductor device with favorable electrical characteristics can be provided. According to another embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. According to another embodiment of the present invention, a semiconductor device with favorable reliability can be provided. According to another embodiment of the present invention, a semiconductor device with low power consumption can be provided.

[0021] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. Note that effects other than these will become apparent from the description in the specification, drawings, claims, etc., and it is possible to extract other effects from the description in the specification, drawings, claims, etc. [Brief explanation of the drawings]

[0022] [Figure 1] 1A is a top view of a semiconductor device according to one embodiment of the present invention, and FIGS. 1B to 1D are cross-sectional views of the semiconductor device according to one embodiment of the present invention. [Figure 2] FIG. 2 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 3] 3A and 3B are perspective views of a semiconductor device according to one embodiment of the present invention. [Figure 4] 4A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 4B to 4D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 5] 5A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 5B to 5D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 6] 6A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 6B to 6D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 7] 7A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 7B to 7D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 8] 8A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 8B to 8D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 9]9A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 9B to 9D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 10] 10A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 10B to 10D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 11] 11A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 11B to 11D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 12] 12A is a top view of a semiconductor device according to one embodiment of the present invention, and FIGS. 12B to 12D are cross-sectional views of the semiconductor device according to one embodiment of the present invention. [Figure 13] 13A and 13B are cross-sectional views of a semiconductor device according to one embodiment of the present invention. [Figure 14] FIG. 14 is a cross-sectional view illustrating a configuration of a memory device according to one embodiment of the present invention. [Figure 15] FIG. 15 is a cross-sectional view illustrating a configuration of a memory device according to one embodiment of the present invention. [Figure 16] 16A and 16B are block diagrams illustrating configuration examples of a memory device according to one embodiment of the present invention. [Figure 17] 17A to 17H are circuit diagrams illustrating configuration examples of a memory device according to one embodiment of the present invention. [Figure 18] 18A and 18B are schematic diagrams of a semiconductor device according to one embodiment of the present invention. [Figure 19] 19A to 19E are schematic diagrams of a memory device according to one embodiment of the present invention. [Figure 20] 20A to 20H are diagrams illustrating electronic devices according to one embodiment of the present invention. [Figure 21] FIG. 21 is a diagram showing a normal probability plot of the Shift values ​​of the samples according to the example. [Figure 22] FIG. 22 is a diagram showing the stress time dependency of ΔVsh in the +GBT stress test according to the example. [Figure 23] Fig. 23A is a diagram showing the stress time dependence of Ion in a +GBT stress test according to an example, Fig. 23B is a diagram showing the stress time dependence of S value in a +GBT stress test according to an example, and Fig. 23C is a diagram showing the stress time dependence of μFE in a +GBT stress test according to an example. [Figure 24] FIG. 24 is a diagram showing the Id-Vg characteristics of the transistor according to the example. [Figure 25] Figure 25A shows a normal probability plot of Vsh according to an example, Figure 25B shows a normal probability plot of Ion according to an example, and Figure 25C shows the Vbg dependence of Vsh according to an example. [Figure 26] Fig. 26A shows ΔVsh in a +GBT stress test according to the example, and Fig. 26B shows the stress time dependency of the S value according to the example. DETAILED DESCRIPTION OF THE INVENTION

[0023] Hereinafter, embodiments will be described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways and that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the following embodiments.

[0024] In addition, in the drawings, sizes, layer thicknesses, or regions may be exaggerated for clarity. Therefore, the drawings are not necessarily limited to the scale. The drawings are schematic representations of ideal examples and are not limited to the shapes or values ​​shown in the drawings. For example, in actual manufacturing processes, layers, resist masks, etc. may be unintentionally thinned by processes such as etching, but this may not be reflected in the drawings to facilitate understanding. In addition, in the drawings, the same symbols are used for identical parts or parts having similar functions across different drawings, and repeated explanations may be omitted. When referring to similar functions, the same hatch pattern may be used and no particular symbols may be assigned.

[0025] In order to make the invention easier to understand, particularly in top views (also called "plan views") and perspective views, some components may be omitted from the drawings. Also, some hidden lines may be omitted from the drawings.

[0026] In addition, in this specification, ordinal numbers such as first, second, etc. are used for convenience and do not indicate the order of processes or stacking. Therefore, for example, "first" can be appropriately replaced with "second" or "third," etc. in the description. Furthermore, the ordinal numbers used to identify one embodiment of the present invention may not match the ordinal numbers used in this specification.

[0027] Furthermore, in this specification, terms indicating arrangement such as "above" and "below" are used for convenience in describing the positional relationship between components with reference to the drawings. Furthermore, the positional relationship between components changes as appropriate depending on the direction in which each component is depicted. Therefore, the terms are not limited to those described in the specification, and can be rephrased appropriately depending on the situation.

[0028] For example, if it is explicitly stated in this specification that X and Y are connected, it is assumed that the specification also discloses cases in which X and Y are electrically connected, cases in which X and Y are functionally connected, and cases in which X and Y are directly connected. Therefore, it is not limited to a specific connection relationship, for example, a connection relationship shown in a figure or text, and it is assumed that connections other than those shown in a figure or text are also disclosed in a figure or text. Here, X and Y are assumed to be objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.).

[0029] In this specification and the like, a transistor is an element having at least three terminals including a gate, a drain, and a source. A transistor has a region (hereinafter also referred to as a channel formation region) where a channel is formed between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode), and a current can flow between the source and the drain through the channel formation region. In this specification and the like, the channel formation region refers to a region through which a current mainly flows.

[0030] Furthermore, the functions of the source and drain may be interchanged when transistors of different polarities are used, when the direction of current flow changes during circuit operation, etc. For this reason, in this specification and the like, the terms source and drain may be used interchangeably.

[0031] Note that the channel length refers to, for example, a region where the semiconductor (or a portion in the semiconductor through which current flows when the transistor is on) and the gate electrode overlap in a top view of a transistor, or the distance between the source (source region or source electrode) and the drain (drain region or drain electrode) in the channel formation region. Note that the channel length of one transistor does not necessarily have the same value in all regions. That is, the channel length of one transistor may not be fixed to a single value. Therefore, in this specification, the channel length is defined as any one value, maximum value, minimum value, or average value in the channel formation region.

[0032] The channel width refers to, for example, the length of a channel formation region in a region where a semiconductor (or a portion of the semiconductor through which current flows when the transistor is on) and a gate electrode overlap in a top view of a transistor, or the length of the channel formation region in a direction perpendicular to the channel length direction in the channel formation region. Note that the channel width of a single transistor does not necessarily have the same value in all regions. That is, the channel width of a single transistor may not be determined to a single value. Therefore, in this specification, the channel width refers to any one value, maximum value, minimum value, or average value in the channel formation region.

[0033] In this specification and the like, depending on the structure of a transistor, the channel width in a region where a channel is actually formed (hereinafter also referred to as an "effective channel width") may differ from the channel width shown in a top view of the transistor (hereinafter also referred to as an "apparent channel width"). For example, when a gate electrode covers the side surface of a semiconductor, the effective channel width may be larger than the apparent channel width, and the influence thereof may not be negligible. For example, in a fine transistor in which a gate electrode covers the side surface of a semiconductor, the proportion of the channel formation region formed on the side surface of the semiconductor may be large. In such a case, the effective channel width is larger than the apparent channel width.

[0034] In such cases, it may be difficult to estimate the effective channel width by actual measurement. For example, in order to estimate the effective channel width from the design value, it is necessary to assume that the shape of the semiconductor is known. Therefore, if the shape of the semiconductor is not accurately known, it is difficult to accurately measure the effective channel width.

[0035] In this specification, when simply referred to as a channel width, it may refer to an apparent channel width. Alternatively, when simply referred to as a channel width, it may refer to an effective channel width. Note that values ​​of the channel length, channel width, effective channel width, apparent channel width, etc. can be determined by analyzing a cross-sectional TEM image, etc.

[0036] Note that impurities in semiconductors refer to, for example, elements other than the main components constituting the semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity. The presence of impurities can, for example, increase the defect state density of the semiconductor or reduce the crystallinity. When the semiconductor is an oxide semiconductor, impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components of the oxide semiconductor, such as hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Note that water can also function as an impurity. For example, the inclusion of impurities can cause oxygen deficiency (V) in the oxide semiconductor. O :oxygen vacancy) may be formed.

[0037] In this specification and the like, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, and silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0038] In this specification and the like, the term "insulator" can be replaced with an insulating film or an insulating layer, the term "conductor" can be replaced with a conductive film or a conductive layer, and the term "semiconductor" can be replaced with a semiconductor film or a semiconductor layer.

[0039] Furthermore, in this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, it also includes cases in which the angle is -5 degrees or more and 5 degrees or less. Furthermore, "substantially parallel" refers to a state in which two straight lines are arranged at an angle of -30 degrees or more and 30 degrees or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it also includes cases in which the angle is 85 degrees or more and 95 degrees or less. Furthermore, "substantially perpendicular" refers to a state in which two straight lines are arranged at an angle of 60 degrees or more and 120 degrees or less.

[0040] In this specification and the like, the term "metal oxide" refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as "oxide semiconductors" or simply as "OSs"). For example, when a metal oxide is used in a semiconductor layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. In other words, an OS transistor can be rephrased as a transistor including a metal oxide or an oxide semiconductor.

[0041] Furthermore, in this specification and the like, normally off means that when no potential is applied to the gate or when a ground potential is applied to the gate, the drain current flowing through the transistor per 1 μm of channel width is 1×10 -20 A or less, 1 x 10 at 85°C -18 A or less, or 1 x 10 at 125°C -16 This means that it is A or below.

[0042] (Embodiment 1) In this embodiment, an example of a semiconductor device including a transistor 200 according to one embodiment of the present invention will be described.

[0043] <Configuration example of semiconductor device> 1A to 1D are top views and cross-sectional views of a semiconductor device including a transistor 200. FIG. 1A is a top view of the semiconductor device. FIGS. 1B to 1D are cross-sectional views of the semiconductor device. FIG. 1B is a cross-sectional view of a portion indicated by a dashed dotted line A1-A2 in FIG. 1A, and is also a cross-sectional view of the transistor 200 in the channel length direction. FIG. 1C is a cross-sectional view of a portion indicated by a dashed dotted line A3-A4 in FIG. 1A, and is also a cross-sectional view of the transistor 200 in the channel width direction. FIG. 1D is a cross-sectional view of a portion indicated by a dashed dotted line A5-A6 in FIG. 1A. Note that some elements are omitted from the top view of FIG. 1A for clarity.

[0044] A semiconductor device of one embodiment of the present invention includes an insulator 212 over a substrate (not shown), an insulator 214 over the insulator 212, a transistor 200 over the insulator 214, an insulator 280 over the transistor 200, an insulator 282 over the insulator 280, an insulator 283 over the insulator 282, an insulator 274 over the insulator 283, and an insulator 281 over the insulator 274. The insulators 212, 214, 280, 282, 283, 274, and 281 function as interlayer films. The semiconductor device also includes a conductor 240 (conductor 240a and conductor 240b) electrically connected to the transistor 200 and functioning as a plug. Note that an insulator 241 (insulator 241a and insulator 241b) is provided in contact with a side surface of the conductor 240 functioning as a plug. In addition, on the insulator 281 and the conductor 240, a conductor 246 (conductor 246a and conductor 246b) is provided, which is electrically connected to the conductor 240 and functions as wiring.

[0045] Furthermore, insulator 241a is provided in contact with the inner walls of the openings of insulators 254, 280, 282, 283, 274, and 281, a first conductor of conductor 240a is provided in contact with the side surface of insulator 241a, and a second conductor of conductor 240a is provided further inward. Furthermore, insulator 241b is provided in contact with the inner walls of the openings of insulators 254, 280, 282, 283, 274, and 281, a first conductor of conductor 240b is provided in contact with the side surface of insulator 241b, and a second conductor of conductor 240b is provided further inward. Here, the height of the upper surface of conductor 240 and the height of the upper surface of insulator 281 can be made approximately the same. Note that, although the transistor 200 has a structure in which the first conductor of the conductor 240 and the second conductor of the conductor 240 are stacked, the present invention is not limited to this. For example, the conductor 240 may be configured as a single layer or a stacked structure of three or more layers. When the structure has a stacked structure, the structures may be distinguished by assigning ordinal numbers to indicate the order of formation.

[0046] [Transistor 200] As shown in FIGS. 1A to 1D, the transistor 200 includes an insulator 216 on an insulator 214, a conductor 205 (conductor 205a and conductor 205b) disposed so as to be embedded in the insulator 216, an insulator 222 on the insulator 216 and on the conductor 205, an insulator 224 on the insulator 222, an oxide 230a on the insulator 224, an oxide 230b on the oxide 230a, a conductor 242a on the oxide 230b, and a conductor 242b and oxide 230c, insulator 250 on oxide 230c, conductor 260 (conductor 260a and conductor 260b) located on insulator 250 and overlapping oxide 230c, and insulator 254 in contact with a portion of the top surface of insulator 224, a portion of the side surface of oxide 230a, a portion of the side surface of oxide 230b, the side surface of conductor 242a, the top surface of conductor 242a, the side surface of conductor 242b, and the top surface of conductor 242b. Furthermore, oxide 230c is in contact with the side surface of insulator 254, the side surface of conductor 242a, and the side surface of conductor 242b. Here, as shown in FIG. 1B, the top surface of conductor 260 is positioned so as to be substantially coincident with the top surface of insulator 250 and the top surface of oxide 230c. Additionally, insulator 282 contacts the top surfaces of conductor 260, insulator 250, oxide 230c, and insulator 280.

[0047] The insulator 280 and the insulator 254 have openings that reach the oxide 230b. The oxide 230c, the insulator 250, and the conductor 260 are disposed in the openings. The conductor 260, the insulator 250, and the oxide 230c are disposed between the conductor 242a and the conductor 242b in the channel length direction of the transistor 200. The insulator 250 has a region that overlaps with a side surface of the conductor 260 and a region that overlaps with a bottom surface of the conductor 260. In the region that overlaps with the oxide 230b, the oxide 230c has a region in contact with the oxide 230b, a region that overlaps with a side surface of the conductor 260 with the insulator 250 interposed therebetween, and a region that overlaps with the bottom surface of the conductor 260 with the insulator 250 interposed therebetween.

[0048] In the transistor 200, it is preferable to use a metal oxide that functions as a semiconductor (hereinafter also referred to as an oxide semiconductor) for the oxide 230 (the oxide 230a, the oxide 230b, and the oxide 230c) including the channel formation region.

[0049] The metal oxide functioning as a semiconductor preferably has a band gap of 2 eV or more, preferably 2.5 eV or more. By using such a metal oxide with a wide band gap, the off-state current of the transistor can be reduced.

[0050] A transistor using a metal oxide for a channel formation region has an extremely small leakage current in a non-conducting state, and therefore can provide a semiconductor device with low power consumption. Furthermore, since a metal oxide film can be formed by a sputtering method or the like, it can be used for a transistor that constitutes a highly integrated semiconductor device.

[0051] For example, a metal oxide such as In-M-Zn oxide containing indium, element M, and zinc (element M is one or more elements selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc.) may be used as oxide 230. Alternatively, In-Ga oxide or In-Zn oxide may be used as oxide 230.

[0052] The oxide 230 preferably includes an oxide 230a disposed on the insulator 224, an oxide 230b disposed on the oxide 230a, and an oxide 230c disposed on the oxide 230b, at least a portion of which is in contact with the upper surface of the oxide 230b. By providing the oxide 230a below the oxide 230b, it is possible to suppress the diffusion of impurities from structures formed below the oxide 230a to the oxide 230b. Furthermore, by providing the oxide 230c on the oxide 230b, it is possible to suppress the diffusion of impurities from structures formed above the oxide 230c to the oxide 230b.

[0053] Note that, in the transistor 200, the oxide 230 has a three-layer structure of the oxide 230a, the oxide 230b, and the oxide 230c, but the present invention is not limited to this. For example, the oxide 230 may have a single layer of the oxide 230b, a two-layer structure of the oxide 230a and the oxide 230b, a two-layer structure of the oxide 230b and the oxide 230c, or a stacked structure of four or more layers. Alternatively, each of the oxide 230a, the oxide 230b, and the oxide 230c may have a stacked structure.

[0054] Furthermore, it is preferable that the oxides 230a and 230b, and the oxides 230b and 230c contain a common element other than oxygen as a main component. This reduces the defect state density at the interface between the oxides 230a and 230b and at the interface between the oxides 230b and 230c. This reduces the effect of interface scattering on carrier conduction, allowing the transistor 200 to achieve a large on-state current and high frequency characteristics.

[0055] The conductor 242 (conductor 242a and conductor 242b) is provided on the oxide 230b. The conductor 242a and the conductor 242b function as a source electrode and a drain electrode of the transistor 200, respectively.

[0056] The conductor 260 includes a conductor 260a and a conductor 260b, and the conductor 260a is disposed so as to surround the bottom and side surfaces of the conductor 260b. The conductor 260 functions as a first gate (also referred to as a top gate) electrode of the transistor 200.

[0057] FIG. 2 shows an enlarged cross-sectional view of a portion of the transistor 200 shown in FIG. 1B. As shown in FIG. 2, the oxide 230 has a region 234 that functions as a channel formation region of the transistor 200 and a region 231 (region 231a and region 231b) that functions as a source region or drain region. The region 231 is a low-resistance region with a high carrier concentration. The region 231 may also include a portion of the low-resistance region. The region 234 is a region with a lower carrier concentration than the region 231. At least a portion of the region 231a and at least a portion of the region 231b have regions in contact with the conductor 242a and the conductor 242b, respectively.

[0058] Note that while Figure 2 shows a configuration in which regions 231 and 234 are formed in oxide 230b, this is not limited to this. For example, regions 231 or 234 may be formed in oxide 230a and oxide 230b, or in oxide 230b and oxide 230c, or in oxide 230a, oxide 230b, and oxide 230c.

[0059] 2, the boundary between the region 231 and the region 234 is shown as being substantially perpendicular to the bottom surface of the oxide 230b, but this is not limited to this. For example, the region 234 may widen toward the conductor 240 near the surface of the oxide 230b and narrow near the bottom surface of the oxide 230b.

[0060] In a transistor using an oxide semiconductor for its channel formation region, if a low-resistance region is formed in the channel formation region, a leakage current (parasitic channel) between the source and drain electrodes of the transistor is likely to occur in the low-resistance region. Furthermore, the parasitic channel is likely to cause defects in transistor characteristics, such as normally-on transistors, increased leakage current, and threshold voltage shift due to stress application. Furthermore, if the processing precision of a transistor is low, the parasitic channel varies from transistor to transistor, resulting in variations in transistor characteristics.

[0061] Furthermore, in a transistor using an oxide semiconductor, if impurities and oxygen vacancies exist in the channel formation region of the oxide semiconductor, the resistance of the oxide semiconductor may be reduced. Furthermore, the electrical characteristics may be easily changed, and reliability may be reduced. Examples of such impurities include aluminum (Al) and silicon (Si). The inclusion of such impurities in the channel formation region may result in the formation of defect states or oxygen vacancies.

[0062] Aluminum and silicon have a higher bond energy with oxygen than indium and zinc. For example, when an In-M-Zn oxide is used as an oxide semiconductor, if aluminum is mixed into the oxide semiconductor, oxygen contained in the oxide semiconductor may be taken by the aluminum, resulting in oxygen vacancies being formed near the indium or zinc.

[0063] If oxygen vacancies exist in the channel formation region of a metal oxide, the transistor may exhibit normally-on characteristics. Furthermore, if hydrogen enters the oxygen vacancies in the metal oxide, the oxygen vacancies and hydrogen combine to form a V O H may be formed. A defect where hydrogen enters an oxygen vacancy (V O Hydrogen atoms (H) function as donors, generating electrons as carriers. Some hydrogen atoms may also bond with oxygen atoms that bond with metal atoms, generating electrons as carriers. Therefore, transistors using metal oxides containing a large amount of hydrogen tend to exhibit normally-on characteristics. Furthermore, since hydrogen atoms in metal oxides are easily moved by stresses such as heat and electric fields, the presence of a large amount of hydrogen in metal oxides can reduce the reliability of transistors.

[0064] Therefore, it is preferable to reduce the impurities and oxygen vacancies as much as possible in the channel formation region of the oxide semiconductor and its vicinity.

[0065] Therefore, it is preferable to form the channel formation region of a transistor and the structures in its vicinity into the shape described below. By forming the structures constituting the transistor into the shape described below, it is possible to reduce the low-resistance region formed in the channel formation region and suppress the occurrence of a parasitic channel. Therefore, it is possible to suppress variations in transistor characteristics due to the parasitic channel. Here, the transistor characteristics include the current value in the on state (on current value), the current value in the off state (off current value), the threshold voltage, the subthreshold swing value (S value), and the field-effect mobility. In addition, it is possible to reduce the impurity concentration in the channel formation region of the oxide semiconductor and its vicinity, thereby improving the reliability of the transistor.

[0066] <Preferred shapes of the channel formation region and structures in its vicinity> The following describes preferred shapes of the channel formation region and the structures in its vicinity. For ease of explanation, it is assumed that the region that functions as the channel formation region of the transistor 200 is formed in the oxide 230b.

[0067] 3A is a perspective view of the transistor 200 and its vicinity shown in FIGS. 1A to 1D. FIG. 3B is an enlarged perspective view of a portion of the transistor 200 shown in FIG. 3A. Note that some elements are omitted from the perspective views of FIGS. 3A and 3B for clarity.

[0068] The oxide 230b has a region 231a (not shown in FIGS. 3A and 3B) that is in contact with at least a portion of the conductor 242a, a region 231b (not shown in FIGS. 3A and 3B) that is in contact with at least a portion of the conductor 242b, and a region 234 that functions as a channel formation region of the transistor 200 between the region 231a and the region 231b. The region 234 includes a region of the oxide 230b where the oxide 230b overlaps with the conductor 260. Hereinafter, the region of the oxide 230b where the oxide 230b overlaps with the conductor 242a may be referred to as the region 231a, and the region where the oxide 230b overlaps with the conductor 242b may be referred to as the region 231b.

[0069] 1C and 3B, in a cross-sectional view of the transistor 200 in the channel width direction, the oxide 230b preferably has a curved surface between the side surface and the top surface of the oxide 230b in the region 234. In other words, the end of the side surface and the end of the top surface are preferably curved (hereinafter also referred to as rounded).

[0070] 2 and 3B, in a cross-sectional view of the transistor 200 in the channel length direction, the distance between the side end of the conductor 242a and the side end of the conductor 242b facing each other is defined as L. Note that L can also be considered as the length of the top surface of the oxide 230b in the region that does not overlap with the conductor 242 in a cross-sectional view of the transistor 200 in the channel length direction.

[0071] Also, as shown in Figure 3B, in a cross-sectional view of the transistor 200 in the channel width direction, the length of the region of the top surface of the oxide 230b that does not have a curved surface in the region where the oxide 230b overlaps with the conductor 260 is defined as W.

[0072] 3B, the radius of curvature of the curved surface is denoted by La. Note that La may be considered to be the difference in height between the upper surface of the oxide 230b and the lower end of the curved region of the side surface of the oxide 230b in the region where the oxide 230b overlaps with the conductor 260, relative to the lower surface of the insulator 224, in a cross-sectional view of the transistor 200 in the channel width direction.

[0073] La is preferably greater than 0 nm and smaller than the film thickness of the oxide 230b in the region overlapping with the conductor 242, or smaller than half of the above-mentioned W. Specifically, La is greater than 0 nm and less than 20 nm, preferably 1 nm to 15 nm, and more preferably 2 nm to 10 nm. This shape can suppress the concentration of an electric field between the side surface and the top surface, thereby suppressing fluctuations in the transistor characteristics. It can also prevent a decrease in W and suppress a decrease in the on-current and mobility of the transistor 200. Therefore, a semiconductor device with excellent electrical characteristics can be provided.

[0074] Furthermore, by adopting the above-described shape, the effective channel length of the side surface of the oxide 230b in the region 234 becomes longer than the effective channel length of the top surface of the oxide 230b, thereby reducing the current flowing through the side surface. This suppresses the influence of the parasitic channel formed on the side surface, thereby reducing the S value of the transistor 200. Furthermore, since the influence of the parasitic channel formed on the side surface due to variations between transistors is reduced, a semiconductor device with reduced variations in transistor characteristics can be provided.

[0075] In a cross-sectional view of the transistor 200 in the channel width direction, the length of the non-curved region of the side surface of the oxide 230b in the region where the oxide 230b and the conductor 260 overlap is defined as Lb. Note that if the side surface of the oxide 230b in the region where the oxide 230b and the conductor 260 overlap has a tapered shape, Lb can also be considered as the length of the tapered portion of the oxide 230b. Furthermore, Lb may be considered as the difference in height between the upper end of the non-curved region and the lower end of the non-curved region, relative to the lower surface of the insulator 224. Lb depends on La, the film thickness of the oxide 230b, the taper angle of the oxide 230b, and other factors. The taper angle here refers to the angle between the side surface of a tapered film and the bottom surface of the film.

[0076] Furthermore, let Lc be the amount of film reduction on the top surface of the oxide 230b in the region where the oxide 230b overlaps with the conductor 260. Lc can be calculated, for example, as the difference in height between the top surface of the oxide 230b in the region where it overlaps with the conductor 242 and the top surface of the oxide 230b in the region where it overlaps with the conductor 260, when the bottom surface of the insulator 222 is used as the reference, in a cross-sectional view of the transistor 200 in the channel width direction.

[0077] As will be described later, when an element contained in the conductive layer 242B provided on and in contact with the oxide 230b has the function of absorbing oxygen from the oxide 230b, a low-resistance region may be partially formed between the oxide 230b and the conductive layer 242B or near the surface of the oxide 230b. Furthermore, when an element contained in the insulating film 254A provided on and in contact with the side surface of the channel formation region of the oxide 230b has the function of absorbing oxygen from the oxide 230b, a low-resistance region may be partially formed between the oxide 230b and the insulating film 254A or near the side surface of the channel formation region of the oxide 230b. In other words, these elements may act as impurities in the oxide semiconductor. In this case, impurities or impurities (such as hydrogen, nitrogen, or metal elements) that have entered oxygen vacancies may function as donors in the low-resistance region, increasing the carrier concentration.

[0078] Furthermore, when impurities are mixed into an oxide semiconductor, defect states or oxygen vacancies may be formed. Therefore, when impurities are mixed into the channel formation region of the oxide semiconductor, the electrical characteristics of a transistor using the oxide semiconductor are likely to fluctuate, and the reliability may be reduced. Furthermore, when oxygen vacancies are present in the channel formation region, the transistor is likely to have normally-on characteristics (a channel exists even when no voltage is applied to the gate electrode, and current flows through the transistor).

[0079] Therefore, it is preferable that the upper surface of the oxide 230b in the region 234 is lower than the upper surface of the oxide 230b in the region overlapping with the conductor 242. For example, it is preferable that Lc is greater than 0 nm and smaller than the film thickness of the oxide 230b in the region overlapping with the conductor 242. Specifically, Lc is greater than 0 nm and less than or equal to 15 nm, preferably 0.5 nm to 10 nm, and more preferably 1 nm to 5 nm. By adopting such a shape, the above-mentioned impurities can be removed, the low-resistance region formed near the upper surface of the region 234 can be reduced, and the occurrence of a parasitic channel can be suppressed. Note that the effective channel length at the upper surface of the region 234 is L + 2 × Lc. Therefore, by reducing Lc, it is possible to suppress a decrease in the on-current of the transistor.

[0080] We denotes the thickness loss of the oxide 230b in the region where the oxide 230b overlaps with the conductor 260. We can be calculated, for example, as the difference between the length of the side surface of the oxide 230b in the region where the oxide 230b overlaps with the conductor 242 and the length of the side surface of the oxide 230b in the region where the oxide 230b does not have the curved surface, in a cross-sectional view of the transistor 200 in the channel width direction. We can also be calculated, for example, as half the difference between the length of the bottom surface of the oxide 230b in the region where the oxide 230b overlaps with the conductor 242 and the length of the bottom surface of the oxide 230b in the region where the oxide 230b does not overlap with the conductor 242, in a cross-sectional view of the transistor 200 in the channel width direction.

[0081] We is preferably greater than 0 nm and equal to or less than the film thickness of the oxide 230b in the region overlapping with the conductor 242. Specifically, We is greater than 0 nm and equal to or less than 20 nm, preferably 1 nm to 15 nm, and more preferably 2 nm to 10 nm. By making We greater than 0 nm, impurities near the side surfaces of the region 234 can be removed, the low-resistance region can be reduced, and the occurrence of a parasitic channel can be suppressed.

[0082] As a result, the low-resistance region formed in the channel formation region can be reduced, and the occurrence of a parasitic channel can be suppressed. Therefore, variations in transistor characteristics due to the parasitic channel can be suppressed. Furthermore, the impurity concentration in the channel formation region of the oxide semiconductor and its vicinity can be reduced, thereby improving the reliability of the transistor.

[0083] By forming the channel formation region of the transistor 200 and the structures in its vicinity into the above-described shape, it is possible to reduce variations in transistor characteristics. For example, it is possible to reduce variations in Vsh. In this specification, Vsh is defined as the drain current Id=1.0×10 in the Id-Vg curve of the transistor. -12 It is defined as the gate voltage Vg at A. The variation in Vsh can be evaluated using, for example, the standard deviation σ. The standard deviation σ of Vsh for n transistors (n is an integer of 3 or more) is expressed by the following formula:

[0084]

number

[0085] In the above equation, x i is the Vsh value of the i-th transistor (i is an integer between 1 and n), and μ is the average Vsh value of n transistors.

[0086] In the Id-Vg characteristics of the transistor 200, the standard deviation σ of Vsh is specifically 60 mV or less, preferably 40 mV or less, and more preferably 20 mV or less.

[0087] Furthermore, by forming the channel formation region and the structure in the vicinity of the channel formation region of the transistor 200 into the above-described shape, the impurity concentration in the channel formation region of the oxide semiconductor and the vicinity thereof can be reduced. Specifically, the impurity concentration in the channel formation region of the oxide semiconductor and the vicinity thereof measured by secondary ion mass spectrometry (SIMS) can be reduced to 1×10 18atoms / cm 3 Less than or equal to 2 x 10 16 atoms / cm 3 or less. Alternatively, the impurity concentration in the channel formation region of the oxide semiconductor and its vicinity, which is obtained by elemental analysis using energy dispersive X-ray spectroscopy (EDX), is set to 1.0 atomic % or less. Note that when an oxide containing element M is used as the oxide semiconductor, the concentration ratio of the impurity to element M in the channel formation region of the oxide semiconductor and its vicinity is set to less than 0.10, preferably less than 0.05. Here, the concentration of element M used in calculating the concentration ratio may be the concentration in the same region as the region where the impurity concentration is calculated, or may be the concentration in the oxide semiconductor.

[0088] Furthermore, the impurity concentration on the side surface of the oxide 230b in the channel formation region is made lower than the impurity concentration on the side surface of the oxide 230b in the region overlapping with the conductor 242. Alternatively, the concentration ratio of the impurity to the element M on the side surface of the oxide 230b in the channel formation region is made lower than the concentration ratio of the impurity to the element M on the side surface of the oxide 230b in the region overlapping with the conductor 242. Furthermore, the concentration ratio of the impurity to the element M on the top surface of the oxide 230b in the channel formation region is made lower than the concentration ratio of the impurity to the element M on the top surface of the oxide 230b in the region overlapping with the conductor 242.

[0089] <Detailed configuration of semiconductor device> Below, the detailed structures of a semiconductor device according to one embodiment of the present invention and a transistor 200 included in the semiconductor device will be described.

[0090] The insulators 212, 214, 254, 282, 283, and 281 preferably function as barrier insulating films that suppress the diffusion of impurities such as water and hydrogen from the substrate side or from above the transistor 200 into the transistor 200. Therefore, the insulators 212, 214, 254, 282, 283, and 281 are preferably made of an insulating material that suppresses the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (such as NO, NO, and NO), and copper atoms (i.e., through which the above impurities are less likely to permeate). Alternatively, the insulators 212, 214, 254, 282, 283, and 281 are preferably made of an insulating material that suppresses the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, and the like).

[0091] For example, it is preferable to use silicon nitride or the like for the insulators 212, 283, and 281, and aluminum oxide or the like for the insulators 214, 254, and 282. This can prevent impurities such as water and hydrogen from diffusing from the substrate side to the transistor 200 through the insulators 212 and 214. Alternatively, it can prevent oxygen contained in the insulator 224 or the like from diffusing to the substrate side through the insulators 212 and 214. It can also prevent impurities such as water and hydrogen from diffusing from the insulator 280, the conductor 246, and the like, which are arranged above the insulator 254, to the inside of the transistor 200 through the insulator 254. In this way, it is preferable to have a structure in which the transistor 200 is surrounded by the insulators 212, 214, 254, 282, and 283, which have the function of preventing the diffusion of impurities such as water and hydrogen, and oxygen.

[0092] It may also be preferable to reduce the resistivity of the insulators 212, 283, and 281. For example, it may be preferable to reduce the resistivity of the insulators 212, 283, and 281 to approximately 1×10 13By setting the resistivity at Ωcm, the insulator 212, the insulator 283, and the insulator 281 may be able to reduce charge-up of the conductor 205, the conductor 242, or the conductor 260 during treatment using plasma or the like in the semiconductor device manufacturing process. The resistivity of the insulator 212, the insulator 283, and the insulator 281 is preferably 1×10 10 Ωcm or more 1×10 15 Ωcm or less.

[0093] Furthermore, the insulators 216, 280, and 274 preferably have a lower dielectric constant than the insulator 214. Using a material with a low dielectric constant as an interlayer film can reduce parasitic capacitance between wirings. For example, the insulators 216, 280, and 274 may be made of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen have been added, silicon oxide having vacancies, or the like, as appropriate.

[0094] The conductor 205 is disposed so as to overlap the oxide 230 and the conductor 260. The conductor 205 is preferably embedded in the insulator 214 or the insulator 216.

[0095] The conductor 260 may function as a first gate electrode. The conductor 205 may function as a second gate electrode. In this case, the threshold voltage (Vth) of the transistor 200 can be controlled by changing the potential applied to the conductor 205 independently of the potential applied to the conductor 260. In particular, applying a negative potential to the conductor 205 can increase the Vth of the transistor 200 and reduce the off-state current. Therefore, applying a negative potential to the conductor 205 can reduce the drain current when the potential applied to the conductor 260 is 0 V compared to not applying a negative potential to the conductor 205.

[0096] As shown in FIG. 1A, the conductor 205 is preferably larger than the area of ​​the oxide 230 that does not overlap with the conductors 242a and 242b. In particular, as shown in FIG. 1C, the conductor 205 preferably extends to an area outside the end of the oxide 230 that intersects with the channel width direction. That is, outside the side surface of the oxide 230 in the channel width direction, the conductor 205 and the conductor 260 preferably overlap with each other via an insulator. This structure allows the channel formation region of the oxide 230 to be electrically surrounded by the electric field of the conductor 260, which functions as the first gate electrode, and the electric field of the conductor 205, which functions as the second gate electrode. In this specification, a transistor structure in which the channel formation region is electrically surrounded by the electric fields of the first and second gates is referred to as a surrounded channel (S-channel) structure.

[0097] In this specification, an S-channel transistor refers to a transistor structure in which a channel formation region is electrically surrounded by the electric fields of one and the other of a pair of gate electrodes. In this specification, the S-channel structure is characterized in that the side and periphery of the oxide 230 in contact with the conductors 242a and 242b, which function as source and drain electrodes, are I-type, just like the channel formation region. Furthermore, the side and periphery of the oxide 230 in contact with the conductors 242a and 242b can be I-type, just like the channel formation region, because they are in contact with the insulator 280. In this specification, I-type can be treated as the same as the high-purity intrinsic oxide described later. The S-channel structure disclosed in this specification differs from the fin structure and planar structure. The S-channel structure enhances resistance to the short-channel effect, in other words, makes the transistor less susceptible to the short-channel effect.

[0098] 1C, the conductor 205 is extended to function as wiring. However, the present invention is not limited to this, and a conductor functioning as wiring may be provided below the conductor 205. Furthermore, it is not necessary to provide one conductor 205 for each transistor. For example, the conductor 205 may be shared by multiple transistors.

[0099] Note that, in the transistor 200, the conductor 205 has a stacked structure of the conductor 205a and the conductor 205b, but the present invention is not limited to this. For example, the conductor 205 may have a single layer or a stacked structure of three or more layers. When the structure has a stacked structure, it may be distinguished by assigning an ordinal number to the order of formation.

[0100] Here, the conductor 205a is preferably made of a conductive material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (NO, NO, NO, etc.), copper atoms, etc. Alternatively, it is preferably made of a conductive material that has the function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0101] By using a conductive material capable of suppressing oxygen diffusion for the conductor 205a, it is possible to prevent the conductor 205b from being oxidized and its conductivity from decreasing. Examples of conductive materials capable of suppressing oxygen diffusion include tantalum, tantalum nitride, ruthenium, and ruthenium oxide. Therefore, the conductor 205a may be a single layer or a multilayer of the above conductive materials. For example, the conductor 205a may be a multilayer of tantalum, tantalum nitride, ruthenium, or ruthenium oxide with titanium or titanium nitride.

[0102] The conductor 205b is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. Although the conductor 205b is illustrated as a single layer, it may have a multilayer structure, for example, a multilayer structure of titanium or titanium nitride and the conductive material.

[0103] Insulator 222 and insulator 224 function as gate insulators.

[0104] The insulator 222 preferably has a function of suppressing the diffusion of hydrogen (e.g., at least one of hydrogen atoms, hydrogen molecules, etc.). The insulator 222 also preferably has a function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.). For example, the insulator 222 preferably has a function of suppressing the diffusion of one or both of hydrogen and oxygen more than the insulator 224.

[0105] The insulator 222 may be an insulator containing an oxide of one or both of aluminum and hafnium, which are insulating materials. Aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate) is preferably used as the insulator. When the insulator 222 is formed using such a material, the insulator 222 functions as a layer that suppresses oxygen release from the oxide 230 to the substrate side and the diffusion of impurities such as hydrogen from the periphery of the transistor 200 to the oxide 230. Therefore, the insulator 222 can suppress the diffusion of impurities such as hydrogen into the inside of the transistor 200 and the generation of oxygen vacancies in the oxide 230. Furthermore, the conductor 205 can be prevented from reacting with the insulator 224 or the oxygen contained in the oxide 230.

[0106] Alternatively, the insulator may contain, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide. Alternatively, these insulators may be nitrided. Furthermore, the insulator 222 may be formed by stacking silicon oxide, silicon oxynitride, or silicon nitride on these insulators.

[0107] The insulator 222 may be a single layer or a multilayer of an insulator containing a so-called high-k material, such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3 (BST). As transistors become smaller and more highly integrated, thinning the gate insulator can cause problems such as leakage current. Using a high-k material for the insulator that functions as the gate insulator allows for a reduction in the gate potential during transistor operation while maintaining the physical film thickness.

[0108] The insulator 224 in contact with the oxide 230 preferably releases oxygen by heating. For example, the insulator 224 may be made of silicon oxide, silicon oxynitride, or the like as appropriate. By providing an insulator containing oxygen in contact with the oxide 230, oxygen vacancies in the oxide 230 can be reduced and the reliability of the transistor 200 can be improved.

[0109] Specifically, it is preferable to use an oxide material from which a portion of oxygen is released by heating, in other words, an insulator material having an excess oxygen region, as the insulator 224. The oxide film from which oxygen is released by heating is an oxide film from which the amount of released oxygen molecules is 1.0×10 18 molecules / cm 3 or more, preferably 1.0 × 10 19 molecules / cm 3 More preferably, 2.0 × 10 19 molecules / cm 3 or more, or 3.0 x 10 20 molecules / cm 3 The oxide film is one having the above-mentioned properties. The surface temperature of the film during the TDS analysis is preferably in the range of 100°C or higher and 700°C or lower, or 100°C or higher and 400°C or lower.

[0110] Furthermore, the oxide 230 may be brought into contact with an insulator having the excess oxygen region and subjected to one or more of heat treatment, microwave treatment, and RF treatment. By performing such treatment, water or hydrogen in the oxide 230 can be removed. For example, in the oxide 230, defects (V) in which hydrogen has entered an oxygen vacancy can be removed. O A reaction occurs in which the bond of V O H→V O +H" reaction occurs, resulting in dehydrogenation. Some of the hydrogen generated at this time may combine with oxygen to form HO, which may be removed from the oxide 230 or an insulator near the oxide 230. Some of the hydrogen may also diffuse or be captured (also called gettering) by the conductor 242.

[0111] The microwave treatment is preferably performed using, for example, an apparatus having a power source for generating high-density plasma or an apparatus having a power source for applying RF to the substrate side. For example, high-density oxygen radicals can be generated by using an oxygen-containing gas and high-density plasma, and the oxygen radicals generated by the high-density plasma can be efficiently introduced into the oxide 230 or an insulator near the oxide 230 by applying RF to the substrate side. The microwave treatment may be performed at a pressure of 133 Pa or higher, preferably 200 Pa or higher, and more preferably 400 Pa or higher. The gases introduced into the microwave treatment apparatus may be, for example, oxygen and argon, with an oxygen flow ratio (O2 / (O2+Ar)) of 50% or less, preferably 10% to 30%.

[0112] During the manufacturing process of the transistor 200, heat treatment is preferably performed while the surface of the oxide 230 is exposed. The heat treatment may be performed, for example, at a temperature of 100°C to 450°C, more preferably 350°C to 400°C. Note that the heat treatment is performed in a nitrogen gas or inert gas atmosphere, or in an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. For example, the heat treatment is preferably performed in an oxygen atmosphere. This allows oxygen to be supplied to the oxide 230, thereby reducing oxygen vacancies. The heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed in a nitrogen gas or inert gas atmosphere, followed by an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more to replenish desorbed oxygen. Alternatively, the heat treatment may be performed in an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more, followed by another heat treatment in a nitrogen gas or inert gas atmosphere.

[0113] By subjecting the oxide 230 to oxygen addition treatment, oxygen vacancies in the oxide 230 are repaired by the supplied oxygen. In other words, O Furthermore, the reaction of the hydrogen remaining in the oxide 230 with the supplied oxygen can be removed as H2O (dehydration). As a result, the hydrogen remaining in the oxide 230 recombines with the oxygen vacancies to form V O The formation of H can be suppressed.

[0114] The insulator 222 and the insulator 224 may have a laminated structure of two or more layers. In this case, the laminated structures are not limited to those made of the same material, and may be those made of different materials.

[0115] The oxide 230 preferably has a layered structure made up of oxides with different chemical compositions. Specifically, in the metal oxide used for the oxide 230a, the atomic ratio of the element M to the main metal element is preferably greater than the atomic ratio of the element M to the main metal element in the metal oxide used for the oxide 230b. In addition, in the metal oxide used for the oxide 230a, the atomic ratio of the element M to In is preferably greater than the atomic ratio of the element M to In in the metal oxide used for the oxide 230b. In addition, in the metal oxide used for the oxide 230b, the atomic ratio of In to M is preferably greater than the atomic ratio of In to M in the metal oxide used for the oxide 230a. In addition, the oxide 230c can be made from the same metal oxide that can be used for the oxide 230a or the oxide 230b.

[0116] Note that, when it is desired to increase the on-state current of the transistor 200, it is preferable to use an In-Zn oxide for the oxide 230. When an In-Zn oxide is used for the oxide 230, examples of the structure include a stacked structure in which an In-Zn oxide is used for the oxide 230a and an In-M-Zn oxide is used for the oxide 230b and the oxide 230c, or a stacked structure in which an In-M-Zn oxide is used for the oxide 230a and an In-Zn oxide is used for either the oxide 230b or the oxide 230c.

[0117] Furthermore, the oxide 230b and the oxide 230c preferably have crystallinity. For example, it is preferable to use a c-axis aligned crystalline oxide semiconductor (CAAC-OS) described later. Crystalline oxides such as CAAC-OS have few impurities and defects (such as oxygen vacancies), a highly crystalline, and a dense structure. This can prevent the source electrode or drain electrode from extracting oxygen from the oxide 230b. This can reduce the extraction of oxygen from the oxide 230b even during heat treatment, making the transistor 200 stable against high temperatures (so-called thermal budget) during the manufacturing process.

[0118] The oxide 230c is preferably a CAAC-OS, and the c-axis of the crystal of the oxide 230c is preferably oriented in a direction substantially perpendicular to the surface on which the oxide 230c is formed or the top surface of the oxide 230c. The CAAC-OS has the property of easily transferring oxygen in a direction perpendicular to the c-axis. Therefore, oxygen contained in the oxide 230c can be efficiently supplied to the oxide 230b.

[0119] Furthermore, the conduction band minimums of the oxides 230a and 230c are preferably closer to the vacuum level than the conduction band minimum of the oxide 230b. In other words, the electron affinity of the oxides 230a and 230c is preferably smaller than that of the oxide 230b. In this case, the oxide 230c is preferably made of a metal oxide that can be used for the oxide 230a. In this case, the main carrier path is the oxide 230b.

[0120] Here, the conduction band minimum changes smoothly at the junctions of the oxides 230a, 230b, and 230c. In other words, the conduction band minimum at the junctions of the oxides 230a, 230b, and 230c changes continuously or forms a continuous junction. To achieve this, it is advisable to reduce the defect level density of the mixed layers formed at the interfaces between the oxides 230a and 230b and between the oxides 230b and 230c.

[0121] Specifically, when the oxide 230a and the oxide 230b, and the oxide 230b and the oxide 230c have a common element other than oxygen as a main component, a mixed layer with a low density of defect states can be formed. For example, when the oxide 230b is an In-Ga-Zn oxide, the oxide 230a and the oxide 230c may be made of an In-Ga-Zn oxide, a Ga-Zn oxide, a gallium oxide, or the like.

[0122] Specifically, the oxide 230a may be a metal oxide having an atomic ratio of In:Ga:Zn=1:3:4 or In:Ga:Zn=1:1:0.5. The oxide 230b may be a metal oxide having an atomic ratio of In:Ga:Zn=1:1:1 or In:Ga:Zn=4:2:3. The oxide 230c may be a metal oxide having an atomic ratio of In:Ga:Zn=1:3:4, In:Ga:Zn=4:2:3, Ga:Zn=2:1, or Ga:Zn=2:5.

[0123] When a metal oxide film is formed by sputtering, the atomic ratio is not limited to the atomic ratio of the formed metal oxide film, but may be the atomic ratio of a sputtering target used to form the metal oxide film.

[0124] By configuring the oxide 230a and the oxide 230c as described above, the defect state density at the interface between the oxide 230a and the oxide 230b and at the interface between the oxide 230b and the oxide 230c can be reduced, which reduces the influence of interface scattering on carrier conduction, and the transistor 200 can achieve a large on-state current and high frequency characteristics.

[0125] As the conductor 242 (conductor 242a and conductor 242b), it is preferable to use, for example, a nitride containing tantalum, a nitride containing titanium, a nitride containing molybdenum, a nitride containing tungsten, a nitride containing tantalum and aluminum, or a nitride containing titanium and aluminum. In one embodiment of the present invention, a nitride containing tantalum is particularly preferable. Also, for example, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel may be used. These materials are preferable because they are conductive materials that are resistant to oxidation or that maintain conductivity even when they absorb oxygen.

[0126] When the conductor 242 and the oxide 230b come into contact with each other, oxygen in the oxide 230b may diffuse into the conductor 242, resulting in the oxidation of the conductor 242. The oxidation of the conductor 242 is likely to result in a decrease in the conductivity of the conductor 242. The diffusion of oxygen in the oxide 230b into the conductor 242 can be rephrased as the conductor 242 absorbing the oxygen in the oxide 230b.

[0127] Furthermore, oxygen in the oxide 230b may diffuse into the conductor 242a and the conductor 242b, forming layers between the conductor 242a and the oxide 230b, and between the conductor 242b and the oxide 230b. Since these layers contain more oxygen than the conductor 242a or the conductor 242b, they are presumed to have insulating properties. In this case, the three-layer structure of the conductor 242a or the conductor 242b, the layer, and the oxide 230b can be regarded as a three-layer structure consisting of a metal, an insulator, and a semiconductor, and can be regarded as a metal-insulator-semiconductor (MIS) structure or a diode junction structure primarily based on the MIS structure.

[0128] Note that hydrogen contained in the oxide 230b and the like may diffuse into the conductor 242a or the conductor 242b. In particular, by using a nitride containing tantalum for the conductor 242a and the conductor 242b, hydrogen contained in the oxide 230b and the like is likely to diffuse into the conductor 242a or the conductor 242b, and the diffused hydrogen may bond with nitrogen contained in the conductor 242a or the conductor 242b. In other words, hydrogen contained in the oxide 230b and the like may be absorbed by the conductor 242a or the conductor 242b.

[0129] Furthermore, there may be a curved surface between the side surface of the conductor 242 and the top surface of the conductor 242. In other words, the end of the side surface and the end of the top surface may be curved. The curved surface has a radius of curvature of, for example, 3 nm or more and 10 nm or less, preferably 5 nm or more and 6 nm or less, at the end of the conductor 242. The lack of corners at the end improves film coverage in the subsequent film formation process.

[0130] 1B, the insulator 254 preferably contacts the upper and side surfaces of the conductor 242a, the upper and side surfaces of the conductor 242b, the side surfaces of the oxide 230a, the side surfaces of the oxide 230b, and part of the upper surface of the insulator 224. With this configuration, the insulator 280 is separated from the insulator 224, the oxide 230a, and the oxide 230b by the insulator 254.

[0131] Similarly to the insulator 222, the insulator 254 preferably has a function of suppressing the diffusion of one or both of hydrogen and oxygen. For example, the insulator 254 preferably has a function of suppressing the diffusion of one or both of hydrogen and oxygen more than the insulators 224 and 280. This can suppress the diffusion of hydrogen contained in the insulator 280 into the oxide 230a and the oxide 230b. Furthermore, by surrounding the insulator 224, the oxide 230, etc. with the insulators 222 and 254, it can suppress the diffusion of impurities such as water and hydrogen from the outside into the insulator 224 and the oxide 230. Therefore, the transistor 200 can have good electrical characteristics and reliability.

[0132] The insulator 254 is preferably formed by sputtering. By forming the insulator 254 by sputtering in an oxygen-containing atmosphere, oxygen can be added to the insulator 224 near the region where the insulator 254 is in contact with the insulator 254. This allows oxygen to be supplied from this region to the oxide 230 through the insulator 224. The insulator 254 has a function of suppressing upward oxygen diffusion, thereby preventing oxygen from diffusing from the oxide 230 to the insulator 280. The insulator 222 has a function of suppressing downward oxygen diffusion, thereby preventing oxygen from diffusing from the oxide 230 toward the substrate. In this way, oxygen is supplied to the channel formation region of the oxide 230. This reduces oxygen vacancies in the oxide 230 and suppresses the transistor from becoming normally on.

[0133] The insulator 254 may be formed, for example, as an insulator containing an oxide of one or both of aluminum and hafnium. In this case, the insulator 254 is preferably formed by atomic layer deposition (ALD). The ALD method is a film formation method with good coverage, so that it is possible to prevent the formation of discontinuities due to unevenness of the insulator 254.

[0134] The insulator 254 can be, for example, an insulator containing aluminum nitride. This provides a film with excellent insulating properties and thermal conductivity, thereby improving the heat dissipation properties of heat generated when the transistor 200 is driven. Silicon nitride, silicon nitride oxide, or the like can also be used.

[0135] Alternatively, the insulator 254 may be, for example, an oxide containing gallium. An oxide containing gallium is preferable because it may have the function of suppressing the diffusion of one or both of hydrogen and oxygen. Note that examples of oxides containing gallium include gallium oxide, gallium zinc oxide, and indium gallium zinc oxide. Note that when indium gallium zinc oxide is used as the insulator 254, it is preferable that the atomic ratio of gallium to indium is large. Increasing this atomic ratio can improve the insulating properties of the oxide.

[0136] Furthermore, the insulator 254 can have a multi-layer structure of two or more layers. When the insulator 254 has a two-layer stacked structure, the lower and upper layers of the insulator 254 can be formed using the above-mentioned method, and the lower and upper layers of the insulator 254 can be formed using the same method or different methods. For example, the lower layer of the insulator 254 can be formed using a sputtering method in an oxygen-containing atmosphere, and then the upper layer of the insulator 254 can be formed using an ALD method. The ALD method is a film formation method with good coverage, so it can prevent discontinuities and the like caused by unevenness in the first layer.

[0137] The above-mentioned materials can be used for the lower and upper layers of the insulator 254, and the lower and upper layers of the insulator 254 may be the same material or different materials. For example, a stacked structure of silicon oxide, silicon oxynitride, silicon nitride oxide, or silicon nitride and an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen may be used. Furthermore, as the insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen, for example, an insulator containing an oxide of one or both of aluminum and hafnium can be used.

[0138] The insulator 250 functions as a gate insulator. The insulator 250 is preferably disposed in contact with at least a portion of the oxide 230c. The insulator 250 can be made of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, silicon oxide having vacancies, or the like. Silicon oxide and silicon oxynitride are particularly preferred because they are stable against heat.

[0139] The insulator 250 is preferably formed using an insulator that releases oxygen upon heating, similar to the insulator 224. By providing the insulator that releases oxygen upon heating as the insulator 250 in contact with at least a portion of the oxide 230c, oxygen can be effectively supplied to the channel formation region of the oxide 230b, thereby reducing oxygen vacancies in the channel formation region of the oxide 230b. Therefore, a transistor with reduced fluctuations in electrical characteristics, stable electrical characteristics, and improved reliability can be provided. Furthermore, similar to the insulator 224, the concentrations of impurities such as water and hydrogen in the insulator 250 are preferably reduced. The thickness of the insulator 250 is preferably 1 nm or more and 20 nm or less.

[0140] Although the insulator 250 is illustrated as a single layer in FIGS. 1A to 1C, it may have a stacked structure of two or more layers. When the insulator 250 has a stacked structure of two layers, it is preferable that the lower layer of the insulator 250 is formed using an insulator that releases oxygen when heated, and the upper layer of the insulator 250 is formed using an insulator that has a function of suppressing oxygen diffusion. This configuration can suppress the diffusion of oxygen contained in the lower layer of the insulator 250 into the conductor 260. In other words, it can suppress a decrease in the amount of oxygen supplied to the oxide 230. It can also suppress oxidation of the conductor 260 due to oxygen contained in the lower layer of the insulator 250. For example, the lower layer of the insulator 250 can be formed using a material that can be used for the insulator 250 described above, and the upper layer of the insulator 250 can be formed using a material similar to that of the insulator 222.

[0141] When silicon oxide or silicon oxynitride is used for the lower layer of the insulator 250, the upper layer of the insulator 250 may be made of an insulating material, which is a high-k material with a high dielectric constant. By forming the gate insulator into a laminated structure consisting of the lower layer of the insulator 250 and the upper layer of the insulator 250, a laminated structure that is stable against heat and has a high dielectric constant can be achieved. This makes it possible to reduce the gate potential applied during transistor operation while maintaining the physical thickness of the gate insulator. It also makes it possible to reduce the equivalent oxide thickness (EOT) of the insulator that functions as the gate insulator.

[0142] Specifically, the upper layer of the insulator 250 can be made of a metal oxide containing one or more elements selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, etc., or a metal oxide that can be used as the oxide 230. In particular, it is preferable to use an insulator containing an oxide of one or both of aluminum and hafnium.

[0143] Furthermore, a metal oxide may be provided between the insulator 250 and the conductor 260. The metal oxide preferably suppresses the diffusion of oxygen from the insulator 250 to the conductor 260. By providing a metal oxide that suppresses the diffusion of oxygen, the diffusion of oxygen from the insulator 250 to the conductor 260 is suppressed. In other words, a decrease in the amount of oxygen supplied to the oxide 230 can be suppressed. Furthermore, oxidation of the conductor 260 by oxygen from the insulator 250 can be suppressed.

[0144] It is preferable that the metal oxide functions as part of the first gate electrode. For example, a metal oxide that can be used as the oxide 230 can be used as the metal oxide. In this case, by forming the conductor 260a by a sputtering method, the electrical resistance value of the metal oxide can be reduced to make it a conductor. This can be called an OC (Oxide Conductor) electrode. For example, by reducing the resistance of an oxide semiconductor that can be used as the oxide 230, it can be used as the metal oxide.

[0145] By including an upper layer of the insulator 250 and / or the metal oxide, the on-state current of the transistor 200 can be improved without weakening the influence of the electric field from the conductor 260. Furthermore, the physical thickness of the insulator 250 and the metal oxide maintains a distance between the conductor 260 and the oxide 230, thereby suppressing leakage current between the conductor 260 and the oxide 230. Furthermore, by providing a stacked structure of the insulator 250 and the metal oxide, the physical distance between the conductor 260 and the oxide 230 and the electric field strength applied from the conductor 260 to the oxide 230 can be easily and appropriately adjusted.

[0146] The conductor 260 preferably includes a conductor 260a and a conductor 260b disposed on the conductor 260a. For example, the conductor 260a is preferably disposed so as to surround the bottom and side surfaces of the conductor 260b. Note that although the conductor 260 is shown in Figures 1A to 1C as having a two-layer structure of the conductor 260a and the conductor 260b, it may have a single-layer structure or a laminated structure of three or more layers.

[0147] The conductor 260a is preferably made of a conductive material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, copper atoms, etc. Alternatively, it is preferably made of a conductive material that has the function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0148] Furthermore, since the conductor 260a has the function of suppressing oxygen diffusion, it is possible to suppress a decrease in conductivity due to oxidation of the conductor 260b caused by oxygen contained in the insulator 250. As a conductive material having the function of suppressing oxygen diffusion, it is preferable to use, for example, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like.

[0149] Furthermore, since the conductor 260 also functions as wiring, it is preferable to use a conductor with high conductivity. For example, the conductor 260b can be made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductor 260b may also have a layered structure, such as a layered structure of titanium or titanium nitride and the above-mentioned conductive material.

[0150] Furthermore, in the transistor 200, the conductor 260 is formed in a self-aligned manner so as to fill an opening formed in the insulator 280 or the like. By forming the conductor 260 in this manner, the conductor 260 can be reliably placed in the region between the conductor 242a and the conductor 242b without alignment.

[0151] 1C , in the channel width direction of the transistor 200, the height of the bottom surface of the conductor 260 in a region where the conductor 260 and the oxide 230b do not overlap is preferably lower than the height of the bottom surface of the oxide 230b, relative to the bottom surface of the insulator 222. The conductor 260, which functions as a gate electrode, covers the side and top surfaces of the channel formation region of the oxide 230b via the insulator 250 or the like, making it easier for the electric field of the conductor 260 to act on the entire channel formation region of the oxide 230b. This increases the on-state current of the transistor 200 and improves its frequency characteristics. The difference between the height of the bottom surface of the conductor 260 and the height of the bottom surface of the oxide 230b in a region where the oxides 230a and 230b do not overlap with the conductor 260, relative to the bottom surface of the insulator 222, is 0 nm or more and 100 nm or less, preferably 3 nm or more and 50 nm or less, and more preferably 5 nm or more and 20 nm or less.

[0152] The insulator 280 is provided on the insulator 224, the oxide 230a, the oxide 230b, the conductor 242, and the insulator 254. The top surface of the insulator 280 may be planarized.

[0153] The insulator 280, which functions as an interlayer film, preferably has a low dielectric constant. Using a material with a low dielectric constant as the interlayer film can reduce the parasitic capacitance that occurs between wirings. The insulator 280 is preferably formed using, for example, the same material as the insulator 216. In particular, silicon oxide and silicon oxynitride are preferred because they are thermally stable. In particular, materials such as silicon oxide, silicon oxynitride, and silicon oxide with vacancies are preferred because they can easily form regions containing oxygen that is released by heating.

[0154] The concentration of impurities such as water and hydrogen in the insulator 280 is preferably reduced. The insulator 280 preferably has a low hydrogen concentration and an excess oxygen region or excess oxygen, and may be formed using, for example, the same material as the insulator 216. The insulator 280 may also have a stacked structure of the above materials, such as a stacked structure of silicon oxide formed by sputtering and silicon oxynitride formed thereon by chemical vapor deposition (CVD). Silicon nitride may also be stacked on top of this.

[0155] The insulator 282 or the insulator 283 preferably functions as a barrier insulating film that suppresses diffusion of impurities such as water and hydrogen from above into the insulator 280. The insulator 282 or the insulator 283 preferably functions as a barrier insulating film that suppresses oxygen permeation. The insulator 282 and the insulator 283 may be made of, for example, aluminum oxide, silicon nitride, or silicon nitride oxide. For example, the insulator 282 may be made of aluminum oxide, which has a high blocking property against oxygen, and the insulator 283 may be made of silicon nitride, which has a high blocking property against hydrogen.

[0156] It is also preferable to provide an insulator 274 functioning as an interlayer film over the insulator 282. Like the insulator 224, the insulator 274 preferably has a reduced concentration of impurities such as water and hydrogen.

[0157] The conductors 240a and 240b are preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductors 240a and 240b may have a layered structure.

[0158] Furthermore, when the conductors 240a and 240b have a layered structure, it is preferable to use a conductive material that has the function of suppressing the permeation of impurities such as water and hydrogen for the conductors in contact with the insulators 281, 274, 283, 282, 280, and 254. For example, it is preferable to use tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, or the like. Furthermore, the conductive material that has the function of suppressing the permeation of impurities such as water and hydrogen may be used in a single layer or a layered structure. Using such a conductive material can prevent oxygen added to the insulator 280 from being absorbed by the conductors 240a and 240b. Furthermore, it is possible to prevent impurities such as water and hydrogen contained in layers above the insulator 281 from being mixed into the oxide 230 through the conductors 240a and 240b.

[0159] The insulators 241a and 241b may be made of, for example, silicon nitride, aluminum oxide, or silicon nitride oxide. The insulators 241a and 241b are provided in contact with the insulator 254, and therefore can prevent impurities such as water and hydrogen contained in the insulator 280 from entering the oxide 230 through the conductors 240a and 240b. Silicon nitride is particularly suitable because it has a high blocking property against hydrogen. Furthermore, it can prevent oxygen contained in the insulator 280 from being absorbed by the conductors 240a and 240b.

[0160] Conductors 246 (conductors 246a and 246b) may be disposed in contact with the upper surfaces of the conductors 240a and 240b, functioning as wiring. Conductor 246 is preferably made of a conductive material containing tungsten, copper, or aluminum as its main component. The conductor may have a layered structure, for example, a layered structure of titanium or titanium nitride and the above-mentioned conductive material. The conductor may be formed so as to be embedded in an opening provided in an insulator.

[0161] <Materials for semiconductor devices> The following describes constituent materials that can be used in semiconductor devices.

[0162] <<Substrate>> The substrate on which the transistor 200 is formed may be, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (e.g., yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide. Examples of semiconductor substrates include those having an insulating region within the semiconductor substrate, such as an SOI (Silicon-On-Insulator) substrate. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Other examples include substrates having a metal nitride and a metal oxide. Examples of other substrates include a substrate in which a conductor or semiconductor is provided on an insulating substrate, a substrate in which a conductor or insulator is provided on a semiconductor substrate, and a substrate in which a semiconductor or insulator is provided on a conductive substrate. Alternatively, a substrate provided with elements may be used, such as a capacitor element, a resistor element, a switch element, a light-emitting element, a memory element, or the like.

[0163] <<Insulators>> Examples of the insulator include oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides, all of which have insulating properties.

[0164] For example, as transistors become more miniaturized and highly integrated, thinner gate insulators can cause problems such as leakage current. Using a high-k material for the gate insulator allows for lower voltage operation of the transistor while maintaining the physical film thickness. On the other hand, using a material with a low dielectric constant for the interlayer insulator can reduce the parasitic capacitance between wiring. Therefore, it is best to select materials based on the insulator's function.

[0165] Furthermore, examples of insulators with a high relative dielectric constant include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0166] Examples of insulators with a low dielectric constant include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, silicon oxide with voids, and resin.

[0167] Furthermore, a transistor using a metal oxide can have stable electrical characteristics by being surrounded by an insulator that has a function of suppressing the permeation of impurities such as hydrogen and oxygen. Examples of insulators that have a function of suppressing the permeation of impurities such as hydrogen and oxygen include insulators containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum, and can be used in a single layer or a stacked layer. Specifically, examples of insulators that have a function of suppressing the permeation of impurities such as hydrogen and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and metal nitrides such as aluminum nitride, silicon nitride oxide, and silicon nitride.

[0168] The insulator functioning as the gate insulator is preferably an insulator having a region containing oxygen that is released by heating. For example, by using a structure in which silicon oxide or silicon oxynitride having a region containing oxygen that is released by heating is in contact with the oxide 230, oxygen vacancies in the oxide 230 can be compensated for.

[0169] <<Conductors>> The conductor is preferably a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above metal elements as a component, or an alloy combining the above metal elements. For example, tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. Furthermore, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are resistant to oxidation or maintain conductivity even when absorbing oxygen. Furthermore, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide may also be used.

[0170] Furthermore, a plurality of conductive layers formed from the above materials may be stacked. For example, a stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing oxygen. A stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing nitrogen. A stacked structure may be formed by combining the above-described material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0171] When an oxide is used for the channel formation region of a transistor, a conductor functioning as a gate electrode preferably has a stacked structure in which a material containing the metal element and a conductive material containing oxygen are combined. In this case, the conductive material containing oxygen is preferably provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen released from the conductive material is easily supplied to the channel formation region.

[0172] In particular, as a conductor functioning as a gate electrode, it is preferable to use a conductive material containing oxygen and a metal element contained in the metal oxide in which the channel is formed. Alternatively, a conductive material containing the aforementioned metal element and nitrogen may be used. For example, a conductive material containing nitrogen, such as titanium nitride or tantalum nitride, may be used. Alternatively, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide doped with silicon may be used. Furthermore, indium gallium zinc oxide containing nitrogen may be used. Using such a material may allow hydrogen contained in the metal oxide in which the channel is formed to be captured. Alternatively, hydrogen introduced from an external insulator or the like may be captured.

[0173] <<Metal oxides>> A metal oxide that functions as a semiconductor (oxide semiconductor) is preferably used as the oxide 230. Metal oxides that can be used as the oxide 230 of one embodiment of the present invention are described below.

[0174] The metal oxide preferably contains at least indium or zinc. It is particularly preferable that it contains indium and zinc. It is also preferable that it contains aluminum, gallium, yttrium, tin, or the like in addition to these. It may also contain one or more elements selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and the like.

[0175] Here, we consider a case where the metal oxide is an In-M-Zn oxide containing indium, element M, and zinc. The element M is aluminum, gallium, yttrium, or tin. Other elements that can be used for element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium. However, there are cases where a combination of the aforementioned elements can be used as element M.

[0176] In this specification and the like, nitrogen-containing metal oxides may also be collectively referred to as metal oxides. Nitrogen-containing metal oxides may also be referred to as metal oxynitrides.

[0177] [Metal oxide structures] Oxide semiconductors (metal oxides) are classified into single-crystal oxide semiconductors and non-single-crystal oxide semiconductors, such as CAAC-OS, polycrystalline oxide semiconductors, nanocrystalline oxide semiconductors (nc-OS), amorphous-like oxide semiconductors (a-like OS), and amorphous oxide semiconductors.

[0178] CAAC-OS has a c-axis orientation and a distorted crystal structure in which multiple nanocrystals are connected in the ab-plane direction. The distorted crystal structure refers to the change in the lattice orientation between regions with a uniform lattice arrangement and regions with a different uniform lattice arrangement in the regions where multiple nanocrystals are connected.

[0179] Nanocrystals are basically hexagonal, but not necessarily regular hexagons; they can also have non-regular hexagonal shapes. Furthermore, distortion can result in pentagonal, heptagonal, or other lattice arrangements. It is difficult to identify clear grain boundaries in CAAC-OS, even near the distortion. This indicates that the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is because CAAC-OS can tolerate distortion due to the lack of close-packed oxygen atom arrangement in the ab-plane direction and the change in interatomic bond distance caused by substitution with metal elements.

[0180] CAAC-OS also tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium and oxygen (hereinafter referred to as an In layer) and a layer containing the element M, zinc, and oxygen (hereinafter referred to as an (M,Zn) layer) are stacked. Note that indium and the element M are mutually substituted, and when the element M in an (M,Zn) layer is substituted with indium, it can also be expressed as an (In,M,Zn) layer. When the indium in an In layer is substituted with the element M, it can also be expressed as an (In,M) layer.

[0181] CAAC-OS is a metal oxide with high crystallinity. Because it is difficult to identify clear grain boundaries in CAAC-OS, it is unlikely that the electron mobility will decrease due to grain boundaries. Furthermore, because the crystallinity of metal oxides can be reduced by the incorporation of impurities or the generation of defects, CAAC-OS can be considered a metal oxide with few impurities or defects (such as oxygen vacancies). Therefore, metal oxides with CAAC-OS have stable physical properties. Therefore, metal oxides with CAAC-OS are heat-resistant and highly reliable.

[0182] The nc-OS has periodic atomic arrangement in a small region (for example, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). Furthermore, the nc-OS exhibits no regularity in the crystal orientation between different nanocrystals. Therefore, no orientation is observed throughout the film. Therefore, depending on the analytical method, the nc-OS may be indistinguishable from an a-like OS or an amorphous oxide semiconductor.

[0183] In-Ga-Zn oxide (hereinafter referred to as IGZO), a type of metal oxide containing indium, gallium, and zinc, can sometimes have a stable structure when made into the above-mentioned nanocrystals. In particular, since IGZO tends to have difficulty growing crystals in the atmosphere, it may be structurally more stable to make it into smaller crystals (for example, the above-mentioned nanocrystals) than larger crystals (here, crystals of a few millimeters or a few centimeters).

[0184] The a-like OS is a metal oxide having a structure between the nc-OS and the amorphous oxide semiconductor. The a-like OS has pores or low-density regions. That is, the a-like OS has lower crystallinity than the nc-OS and CAAC-OS.

[0185] Oxide semiconductors (metal oxides) have a variety of structures, each with different characteristics. The oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, an nc-OS, and a CAAC-OS.

[0186] [impurities] Here, the influence of each impurity in the metal oxide will be described.

[0187] When impurities are mixed into an oxide semiconductor, defect states or oxygen vacancies may be formed. Therefore, when impurities are mixed into a channel formation region of an oxide semiconductor, the electrical characteristics of a transistor using the oxide semiconductor are likely to fluctuate, and the reliability may be reduced. Furthermore, when oxygen vacancies are present in the channel formation region, the transistor is likely to have normally-on characteristics.

[0188] A transistor using a metal oxide tends to have a normally-on characteristic (a characteristic in which a channel exists and a current flows through the transistor even when no voltage is applied to the gate electrode) due to impurities and oxygen vacancies in the metal oxide. Furthermore, when the transistor is operated in a state in which the metal oxide contains excess oxygen exceeding the appropriate amount, the valence of the excess oxygen atoms changes, which changes the electrical characteristics of the transistor, and may result in a decrease in reliability.

[0189] Therefore, it is preferable to use a metal oxide with a low carrier concentration in the channel formation region of a transistor. When the carrier concentration of a metal oxide is to be low, the impurity concentration in the metal oxide is reduced to reduce the density of defect states. In this specification and the like, a low impurity concentration and a low density of defect states are referred to as high-purity intrinsic or substantially high-purity intrinsic. Note that in this specification and the like, a metal oxide with a carrier concentration of 1×10 16 cm -3 The following cases are defined as substantially high purity and authentic:

[0190] The carrier concentration of the metal oxide in the channel formation region is 1×10 18 cm -3 Preferably, it is 1×10 or less. 17 cm -3 More preferably, it is 1×10 or less. 16 cm -3 More preferably, it is 1×10 or less. 13 cm -3 More preferably, it is less than 1×10 12 cm -3 The lower limit of the carrier concentration of the metal oxide in the channel formation region is not particularly limited, but is preferably, for example, 1×10 -9 cm -3 It can be said that:

[0191] Impurities in metal oxides include, for example, hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon. In particular, hydrogen contained in metal oxides reacts with oxygen that bonds with metal atoms to form water, which can cause oxygen vacancies in the metal oxide. If oxygen vacancies are present in the channel formation region of the metal oxide, the transistor may exhibit normally-on characteristics. Furthermore, if hydrogen enters an oxygen vacancy in the metal oxide, the oxygen vacancy and hydrogen bond to form a V O H may be formed. A defect where hydrogen enters an oxygen vacancy (V O Hydrogen atoms (H) function as donors, generating electrons as carriers. Some hydrogen atoms may also bond with oxygen atoms that bond with metal atoms, generating electrons as carriers. Therefore, transistors using metal oxides containing a large amount of hydrogen tend to exhibit normally-on characteristics. Furthermore, since hydrogen atoms in metal oxides are easily moved by stresses such as heat and electric fields, the presence of a large amount of hydrogen in metal oxides can reduce the reliability of transistors.

[0192] In one embodiment of the present invention, V in the oxide 230 O It is preferable to reduce H as much as possible to obtain high-purity intrinsic or substantially high-purity intrinsic V. O To obtain metal oxides with sufficiently reduced H, it is important to remove impurities such as water and hydrogen from the metal oxide (sometimes referred to as dehydration or dehydrogenation treatment), and to supply oxygen to the metal oxide to compensate for oxygen deficiencies (sometimes referred to as oxygen addition treatment). O By using a metal oxide in which impurities such as H are sufficiently reduced for the channel formation region of a transistor, stable electrical characteristics can be achieved.

[0193] A defect where hydrogen enters an oxygen vacancy (V OH) can function as a donor in metal oxides. However, it is difficult to quantitatively evaluate such defects. Therefore, metal oxides are sometimes evaluated by carrier concentration rather than donor concentration. Therefore, in this specification and the like, as a parameter of metal oxides, carrier concentration assuming a state in which no electric field is applied may be used rather than donor concentration. In other words, the "carrier concentration" described in this specification and the like can sometimes be rephrased as "donor concentration." Furthermore, the "carrier concentration" described in this specification and the like can sometimes be rephrased as "carrier density."

[0194] Therefore, it is preferable that the hydrogen content in the metal oxide is reduced as much as possible. Specifically, the hydrogen concentration in the metal oxide obtained by SIMS is reduced to 1×10 20 atoms / cm 3 Less than 1 x 10 19 atoms / cm 3 less than 5 × 10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 By using a metal oxide in which impurities such as hydrogen are sufficiently reduced for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0195] The defect levels may include trap levels. Charges trapped in the trap levels of metal oxides take a long time to disappear and may behave like fixed charges. Therefore, a transistor having a channel formation region made of a metal oxide with a high density of trap levels may have unstable electrical characteristics.

[0196] Furthermore, the presence of impurities in the channel formation region of the oxide semiconductor may reduce the crystallinity of the channel formation region or the crystallinity of an oxide provided in contact with the channel formation region. The low crystallinity of the channel formation region tends to reduce the stability or reliability of the transistor. Furthermore, the low crystallinity of the oxide provided in contact with the channel formation region may form an interface state, which may reduce the stability or reliability of the transistor.

[0197] Therefore, in order to improve the stability or reliability of a transistor, it is effective to reduce the impurity concentration in the channel formation region of the oxide semiconductor and its vicinity. The impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, etc. Metal oxides with reduced impurity concentrations have a low density of defect states, and therefore may also have a low density of trap states.

[0198] <<Other semiconductor materials>> The semiconductor material that can be used for the oxide 230 is not limited to the metal oxides described above. A semiconductor material having a band gap (a semiconductor material that is not a zero-gap semiconductor) may also be used for the oxide 230. For example, it is preferable to use a semiconductor of a simple element such as silicon, a compound semiconductor such as gallium arsenide, or a layered material that functions as a semiconductor (also called an atomic layer material or a two-dimensional material). In particular, it is preferable to use a layered material that functions as a semiconductor.

[0199] In this specification and the like, a layered material is a general term for a group of materials having a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent bonds or ionic bonds are stacked via bonds weaker than covalent bonds or ionic bonds, such as van der Waals forces. A layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-current can be provided.

[0200] Layered materials include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogen. Chalcogen is a general term for elements in Group 16, including oxygen, sulfur, selenium, tellurium, polonium, and livermorium. Chalcogenides also include transition metal chalcogenides and Group 13 chalcogenides.

[0201] It is preferable to use, for example, a transition metal chalcogenide that functions as a semiconductor as the oxide 230. Specific examples of transition metal chalcogenides that can be used as the oxide 230 include molybdenum sulfide (typically MoS2), molybdenum selenide (typically MoSe2), molybdenum tellurium (typically MoTe2), tungsten sulfide (typically WS2), tungsten selenide (typically WSe2), tungsten tellurium (typically WTe2), hafnium sulfide (typically HfS2), hafnium selenide (typically HfSe2), zirconium sulfide (typically ZrS2), and zirconium selenide (typically ZrSe2).

[0202] <Method for manufacturing semiconductor device> Next, a manufacturing method of the semiconductor device illustrated in FIGS. 1A to 1D, which is one embodiment of the present invention, will be described with reference to FIGS. 4A to 11D.

[0203] Figures 4A, 5A, 6A, 7A, 8A, 9A, 10A, and 11A are top views, while Figures 4B, 5B, 6B, 7B, 8B, 9B, 10B, and 11B are cross-sectional views corresponding to the portions indicated by the dashed dotted lines A1-A2 in Figures 4A, 5A, 6A, 7A, 8A, 9A, 10A, and 11A, respectively, and are also cross-sectional views in the channel length direction of transistor 200. 4C, 5C, 6C, 7C, 8C, 9C, 10C, and 11C are cross-sectional views corresponding to the portions indicated by the dashed dotted lines A3-A4 in FIGS. 4A, 5A, 6A, 7A, 8A, 9A, 10A, and 11A, respectively, and are also cross-sectional views in the channel width direction of transistor 200. 4D, 5D, 6D, 7D, 8D, 9D, 10D, and 11D are cross-sectional views corresponding to the portions indicated by the dashed dotted lines A5-A6 in FIGS. 4A, 5A, 6A, 7A, 8A, 9A, 10A, and 11A, respectively. Note that some elements are omitted from the top views of FIGS. 4A, 5A, 6A, 7A, 8A, 9A, 10A, and 11A for clarity.

[0204] First, a substrate (not shown) is prepared, and then a film of the insulator 212 is formed on the substrate. The insulator 212 can be formed by a sputtering method, a CVD method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, an ALD method, or the like.

[0205] CVD methods can be classified into plasma-enhanced CVD (PECVD), which uses plasma, thermal CVD (TCVD), which uses heat, and photo-CVD (Photo-CVD), which uses light. They can also be further divided into metal CVD (MCVD) and metal-organic CVD (MOCVD), depending on the source gas used.

[0206] The plasma CVD method can produce high-quality films at relatively low temperatures. Furthermore, because the thermal CVD method does not use plasma, it is a film formation method that can minimize plasma damage to the workpiece. For example, wiring, electrodes, elements (transistors, capacitors, etc.) included in a semiconductor device may become charged up by receiving electric charge from the plasma. In this case, the accumulated electric charge may destroy the wiring, electrodes, elements, etc. included in the semiconductor device. On the other hand, the thermal CVD method, which does not use plasma, does not cause such plasma damage, and therefore can increase the yield of semiconductor devices. Furthermore, because the thermal CVD method does not cause plasma damage during film formation, it can produce films with fewer defects.

[0207] Furthermore, ALD utilizes the self-regulating properties of atoms to deposit atoms layer by layer, enabling the formation of ultrathin films, films with high aspect ratios, films with fewer defects such as pinholes, films with excellent coverage, and films formed at low temperatures. ALD also includes plasma-enhanced ALD (PEALD), which utilizes plasma. Using plasma can sometimes be preferable because it enables film formation at lower temperatures. Note that some precursors used in ALD contain impurities such as carbon. Therefore, films formed by ALD may contain higher amounts of impurities such as carbon than films formed by other film formation methods. Quantitative determination of impurities can be performed using X-ray photoelectron spectroscopy (XPS).

[0208] Unlike film formation methods in which particles emitted from a target or the like are deposited, CVD and ALD are film formation methods in which a film is formed by a reaction on the surface of the workpiece. Therefore, these film formation methods are less affected by the shape of the workpiece and have good step coverage. In particular, ALD has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surface of openings with high aspect ratios. However, because ALD has a relatively slow film formation rate, it may be preferable to use it in combination with other film formation methods, such as CVD, which has a faster film formation rate.

[0209] The CVD method and the ALD method can control the composition of the resulting film by adjusting the flow rate ratio of the source gases. For example, the CVD method and the ALD method can form a film of any composition by adjusting the flow rate ratio of the source gases. Furthermore, for example, the CVD method and the ALD method can form a film with a continuously changing composition by changing the flow rate ratio of the source gases while forming the film. When forming a film while changing the flow rate ratio of the source gases, the time required for film formation can be shortened compared to when forming a film using multiple film formation chambers because no time is required for transportation and pressure adjustment. Therefore, the productivity of semiconductor devices can be improved in some cases.

[0210] In this embodiment, a silicon nitride film is formed by a CVD method as the insulator 212. By using an insulator such as silicon nitride that is impermeable to copper as the insulator 212 in this manner, even if a metal that easily diffuses, such as copper, is used in a conductor below the insulator 212 (not shown), the metal can be prevented from diffusing upward through the insulator 212. Furthermore, by using an insulator such as silicon nitride that is impermeable to impurities such as water and hydrogen, the diffusion of impurities such as water and hydrogen contained in the layer below the insulator 212 can be prevented.

[0211] Next, the insulator 214 is deposited over the insulator 212. The insulator 214 can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, aluminum oxide is used as the insulator 214.

[0212] Next, the insulator 216 is deposited on the insulator 214. The insulator 216 can be deposited by sputtering, CVD, MBE, PLD, ALD, or the like.

[0213] Next, an opening is formed in the insulator 216, reaching the insulator 214. The opening may be, for example, a groove or a slit. The region where the opening is formed may also be referred to as an opening. The opening may be formed by wet etching, but dry etching is preferable for fine processing. For the insulator 214, it is preferable to select an insulator that functions as an etching stopper film when etching the insulator 216 to form the groove. For example, if silicon oxide is used for the insulator 216 that forms the groove, it is preferable to use silicon nitride, aluminum oxide, or hafnium oxide for the insulator 214.

[0214] The dry etching apparatus may be a capacitively coupled plasma (CCP) etching apparatus having parallel-plate electrodes. The capacitively coupled plasma etching apparatus having parallel-plate electrodes may be configured to apply a high-frequency voltage to one of the parallel-plate electrodes. Alternatively, it may be configured to apply a plurality of different high-frequency voltages to one of the parallel-plate electrodes. Alternatively, it may be configured to apply a high-frequency voltage of the same frequency to each of the parallel-plate electrodes. Alternatively, it may be configured to apply high-frequency voltages of different frequencies to each of the parallel-plate electrodes. Alternatively, a dry etching apparatus having a high-density plasma source may be used. For example, an inductively coupled plasma (ICP) etching apparatus may be used as the dry etching apparatus having a high-density plasma source.

[0215] After the opening is formed, a conductive film that will become the conductor 205a is formed. The conductive film preferably contains a conductor that has a function of suppressing oxygen permeation. For example, tantalum nitride, tungsten nitride, titanium nitride, or the like can be used. Alternatively, the conductive film can be a stacked film of a conductor that has a function of suppressing oxygen permeation and tantalum, tungsten, titanium, molybdenum, aluminum, copper, or a molybdenum-tungsten alloy. The conductive film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0216] In this embodiment, the conductive film that becomes the conductor 205a has a multilayer structure. First, a tantalum nitride film is formed by sputtering, and then titanium nitride is laminated on the tantalum nitride. By using such a metal nitride as the lower layer of the conductor 205b, even if a metal that easily diffuses, such as copper, is used in the conductive film that becomes the conductor 205b (described later), the metal can be prevented from diffusing out of the conductor 205a.

[0217] Next, a conductive film that will become the conductor 205b is formed. The conductive film can be formed by plating, sputtering, CVD, MBE, PLD, ALD, or the like. In this embodiment, a low-resistance conductive material such as copper is deposited as the conductive film.

[0218] Next, CMP processing is performed to remove the conductive film that will become the conductor 205a and a portion of the conductive film that will become the conductor 205b, thereby exposing the insulator 216. As a result, the conductors 205a and 205b remain only in the openings. This allows the formation of a conductor 205 with a flat upper surface (see FIGS. 4B to 4D). Note that the CMP processing may remove a portion of the insulator 216.

[0219] In the above description, the conductor 205 is formed so as to be embedded in the opening of the insulator 216, but this embodiment is not limited to this. For example, the conductor 205 may be formed on the insulator 214, the insulator 216 may be formed on the conductor 205, and a part of the insulator 216 may be removed by performing CMP treatment on the insulator 216, thereby exposing the surface of the conductor 205.

[0220] Next, the insulator 222 is formed over the insulator 216 and the conductor 205. The insulator 222 may be an insulator containing one or both of an oxide of aluminum and hafnium. The insulator containing one or both of an oxide of aluminum and hafnium has barrier properties against oxygen, hydrogen, and water. The insulator 222 having barrier properties against hydrogen and water prevents hydrogen and water contained in structures provided around the transistor 200 from diffusing into the inside of the transistor 200 through the insulator 222, thereby preventing the generation of oxygen vacancies in the oxide 230.

[0221] The insulator 222 can be formed by sputtering, CVD, MBE, PLD, ALD, or the like.

[0222] Subsequently, heat treatment is preferably performed. The heat treatment may be performed at a temperature of 250°C to 650°C, preferably 300°C to 500°C, and more preferably 320°C to 450°C. The heat treatment may be performed in a nitrogen gas or inert gas atmosphere, or in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. The heat treatment may also be performed under reduced pressure. Alternatively, the heat treatment may be performed in a nitrogen gas or inert gas atmosphere, followed by another heat treatment in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to compensate for the desorbed oxygen.

[0223] In this embodiment, heat treatment is performed in a nitrogen atmosphere at 400° C. for 1 hour after the formation of the insulator 222, followed by heat treatment in an oxygen atmosphere at 400° C. for 1 hour. This heat treatment can remove impurities such as water and hydrogen contained in the insulator 222. The heat treatment can also be performed at the timing after the formation of the insulator 224.

[0224] Next, the insulator 224 is deposited over the insulator 222. The insulator 224 can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, a silicon oxynitride film is deposited as the insulator 224 by a CVD method.

[0225] Here, to form an excess oxygen region in the insulator 224, a plasma treatment containing oxygen may be performed under reduced pressure. For the plasma treatment containing oxygen, it is preferable to use an apparatus having a power source that generates high-density plasma using, for example, microwaves. Alternatively, a power source that applies RF (radio frequency) to the substrate side may be provided. By using high-density plasma, high-density oxygen radicals can be generated, and by applying RF to the substrate side, the oxygen radicals generated by the high-density plasma can be efficiently guided into the insulator 224. Alternatively, after performing a plasma treatment containing an inert gas using this apparatus, a plasma treatment containing oxygen may be performed to replenish the desorbed oxygen. Note that impurities such as water and hydrogen contained in the insulator 224 can be removed by appropriately selecting the conditions for the plasma treatment. In this case, heat treatment is not required.

[0226] Here, after forming an aluminum oxide film on the insulator 224 by, for example, a sputtering method, CMP processing may be performed until the aluminum oxide reaches the insulator 224. This CMP processing can planarize and smooth the surface of the insulator 224. By placing the aluminum oxide on the insulator 224 and performing the CMP processing, it becomes easier to detect the end point of the CMP processing. Furthermore, the CMP processing may polish a portion of the insulator 224, resulting in a thinner film of the insulator 224. However, the film thickness can be adjusted during the formation of the insulator 224. Planarizing and smoothing the surface of the insulator 224 may prevent a deterioration in the coverage of the oxide film to be formed later and may prevent a decrease in the yield of the semiconductor device. Furthermore, forming an aluminum oxide film on the insulator 224 by a sputtering method is preferable because it allows oxygen to be added to the insulator 224.

[0227] Next, oxide films 230A and 230B are sequentially formed on insulator 224 (see FIGS. 4B to 4D). Preferably, oxide films 230A and 230B are successively formed without being exposed to the atmosphere. By forming the films without being exposed to the atmosphere, impurities or moisture from the atmosphere can be prevented from adhering to oxide films 230A and 230B, and the vicinity of the interface between oxide films 230A and 230B can be kept clean.

[0228] The oxide film 230A and the oxide film 230B can be formed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0229] For example, when the oxide film 230A and the oxide film 230B are formed by sputtering, oxygen or a mixed gas of oxygen and a rare gas is used as the sputtering gas. By increasing the proportion of oxygen contained in the sputtering gas, the amount of excess oxygen in the formed oxide film can be increased. Furthermore, when the oxide film is formed by sputtering, the above-mentioned In-M-Zn oxide target can be used.

[0230] In particular, during the deposition of the oxide film 230A, some of the oxygen contained in the sputtering gas may be supplied to the insulator 224. Therefore, the proportion of oxygen contained in the sputtering gas should be 70% or more, preferably 80% or more, and more preferably 100%.

[0231] When the oxide film 230B is formed by a sputtering method, an oxygen-excessive oxide semiconductor is formed when the proportion of oxygen contained in the sputtering gas is set to more than 30% and less than or equal to 100%, preferably 70% to 100%. A transistor using an oxygen-excessive oxide semiconductor for a channel formation region can have relatively high reliability. However, one embodiment of the present invention is not limited thereto. When the oxide film 230B is formed by a sputtering method, an oxygen-deficient oxide semiconductor is formed when the proportion of oxygen contained in the sputtering gas is set to 1% to 30%, preferably 5% to 20%. A transistor using an oxygen-deficient oxide semiconductor for a channel formation region can have relatively high field-effect mobility. Furthermore, the crystallinity of the oxide film can be improved by forming the oxide film while heating the substrate.

[0232] In this embodiment, oxide film 230A is formed by sputtering using an oxide target with an atomic ratio of In:Ga:Zn=1:3:4. Oxide film 230B is formed by sputtering using an oxide target with an atomic ratio of In:Ga:Zn=4:2:4.1. Each oxide film can be formed according to the desired characteristics of oxide 230a and oxide 230b by appropriately selecting the film formation conditions and atomic ratio.

[0233] It is preferable to form the insulator 222, the insulator 224, the oxide film 230A, and the oxide film 230B without exposing them to the atmosphere, for example, by using a multi-chamber film forming apparatus.

[0234] Next, a heat treatment may be performed. The heat treatment conditions described above can be used for the heat treatment. The heat treatment can remove impurities such as water and hydrogen from the oxide film 230A and the oxide film 230B. In this embodiment, the heat treatment is performed in a nitrogen atmosphere at 400°C for one hour, followed by another heat treatment in an oxygen atmosphere at 400°C for one hour.

[0235] Next, a conductive film 242A is formed on the oxide film 230B (see FIGS. 4B to 4D). The conductive film 242A can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. Note that heat treatment may be performed before the formation of the conductive film 242A. The heat treatment may be performed under reduced pressure, and the conductive film 242A may be formed successively without exposure to the air. By performing such treatment, moisture and hydrogen adsorbed on the surface of the oxide film 230B can be removed, and the moisture and hydrogen concentrations in the oxide film 230A and the oxide film 230B can be further reduced. The temperature of the heat treatment is preferably 100° C. or higher and 400° C. or lower. In this embodiment, the temperature of the heat treatment is 200° C.

[0236] Next, the oxide film 230A, the oxide film 230B, and the conductive film 242A are processed into island shapes using lithography to form the oxide 230a, the oxide 230b, and the conductive layer 242B (see FIGS. 5A to 5D). This processing can be performed using dry etching or wet etching. Dry etching is suitable for fine processing. The oxide film 230A, the oxide film 230B, and the conductive film 242A may be processed under different conditions. During this process, the thickness of the insulator 224 in the region not overlapping with the oxide 230a may become thinner.

[0237] In lithography, a resist is first exposed through a mask. The exposed area is then removed or left using a developer to form a resist mask. Then, etching is performed through the resist mask to process conductors, semiconductors, insulators, and the like into desired shapes. For example, a resist mask can be formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, EUV (Extreme Ultraviolet) light, or the like. An immersion technique may also be used, in which a liquid (e.g., water) is filled between the substrate and the projection lens for exposure. An electron beam or an ion beam may also be used instead of the light described above. When an electron beam or an ion beam is used, a mask is not required. The resist mask can be removed by dry etching such as ashing, wet etching, dry etching followed by wet etching, or wet etching followed by dry etching.

[0238] Alternatively, a hard mask made of an insulator or a conductor may be used instead of a resist mask. When using a hard mask, an insulating film or a conductive film that serves as a hard mask material is formed on the conductive film 242A, a resist mask is formed thereon, and the hard mask material is etched to form a hard mask with a desired shape. The conductive film 242A may be etched after removing the resist mask or with the resist mask left in place. In the latter case, the resist mask may be lost during etching. The hard mask may be removed by etching after etching the conductive film 242A. On the other hand, if the hard mask material does not affect subsequent processes or can be used in subsequent processes, it is not necessarily necessary to remove the hard mask.

[0239] Here, the oxide 230a, the oxide 230b, and the conductive layer 242B are formed so that at least a portion thereof overlaps with the conductor 205. Furthermore, the side surfaces of the oxide 230a, the oxide 230b, and the conductive layer 242B are preferably approximately perpendicular to the top surface of the insulator 222. By making the side surfaces of the oxide 230a, the oxide 230b, and the conductive layer 242B approximately perpendicular to the top surface of the insulator 222, a smaller area and higher density can be achieved when providing multiple transistors 200. Furthermore, the side surfaces of the oxide 230a, the oxide 230b, and the conductive layer 242B may be configured so that the angles formed between the side surfaces and the top surface of the insulator 222 are small. In this case, the angles formed between the side surfaces of the oxide 230a, the oxide 230b, and the conductive layer 242B and the top surface of the insulator 222 are preferably greater than or equal to 60 degrees and less than 70 degrees. By forming the insulating layer 254 in this shape, the covering property of the insulating layer 254 can be improved in the subsequent steps, and defects such as voids can be reduced.

[0240] Furthermore, a curved surface is present between the side surface of the conductive layer 242B and the top surface of the conductive layer 242B. In other words, it is preferable that the end of the side surface and the end of the top surface are curved. For example, the curved surface has a radius of curvature of 3 nm to 10 nm, preferably 5 nm to 6 nm, at the end of the conductive layer 242B. The lack of corners at the end improves film coverage in the subsequent film formation process.

[0241] Next, an insulating film 254A is formed on the insulator 224, the oxide 230a, the oxide 230b, and the conductive layer 242B (see FIGS. 6B to 6D).

[0242] The insulating film 254A can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. It is preferable that the insulating film 254A be an insulating film that has a function of suppressing oxygen permeation. For example, aluminum oxide, silicon nitride, silicon oxide, or gallium oxide is formed by sputtering or ALD. Alternatively, aluminum oxide may be formed by sputtering, and then another aluminum oxide may be formed on the aluminum oxide by ALD.

[0243] Next, an insulating film to be the insulator 280 is formed on the insulating film 254A. The insulating film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, a silicon oxide film is formed as the insulating film by a CVD method or a sputtering method. Note that a heat treatment may be performed before the insulating film is formed. The heat treatment may be performed under reduced pressure, and the insulating film may be formed continuously without exposure to the atmosphere. By performing such a treatment, moisture and hydrogen adsorbed on the surface of the insulating film 254A can be removed, and the moisture and hydrogen concentrations in the oxide 230a, the oxide 230b, and the insulator 224 can be further reduced. The heat treatment conditions described above can be used.

[0244] The insulating film may have a multi-layer structure, for example, a silicon oxide film formed by sputtering, and another silicon oxide film formed on the silicon oxide film by CVD.

[0245] Next, the insulating film is subjected to CMP processing to form an insulator 280 with a flat upper surface (see FIGS. 6B to 6D).

[0246] Here, microwave treatment may be performed. The microwave treatment is preferably performed in an oxygen-containing atmosphere under reduced pressure. By performing the microwave treatment, an electric field due to microwaves is applied to the insulator 280, the oxide 230b, the oxide 230a, etc., and V in the oxide 230b and the oxide 230a is increased. O H is oxygen vacancy (V O ) and hydrogen (H). At this time, some of the separated hydrogen may combine with oxygen contained in the insulator 280 and be removed as water molecules. Also, some of the hydrogen may be gettered to the conductive layer 242B via the insulating film 254A.

[0247] Alternatively, a heat treatment may be performed while maintaining the reduced pressure after the microwave treatment. By performing such a treatment, hydrogen in the insulator 280, the oxide 230b, and the oxide 230a can be efficiently removed. The heat treatment temperature is preferably 300° C. or higher and 500° C. or lower.

[0248] Furthermore, microwave treatment can modify the film quality of the insulator 280, thereby suppressing the diffusion of hydrogen, water, impurities, etc. Therefore, it is possible to suppress the diffusion of hydrogen, water, impurities, etc. into the oxide 230 via the insulator 280 in post-processing steps after the formation of the insulator 280 or by heat treatment, etc.

[0249] Next, a part of the insulator 280, a part of the insulating film 254A, and a part of the conductive layer 242B are processed to form an opening that reaches the oxide 230b. The opening is preferably formed so as to overlap the conductor 205. By forming the opening, the insulator 254, the conductor 242a, and the conductor 242b are formed (see FIGS. 7A to 7D).

[0250] At this time, it is preferable to thin the oxide 230b in the region overlapping the opening. The amount of film reduction in this region corresponds to Lc shown in FIG. 3B. By thinning the oxide 230b in this region, it is possible to prevent the formation of a low-resistance region near the top surface of the channel formation region and suppress the occurrence of a parasitic channel. Therefore, it is possible to suppress variations in transistor characteristics due to the parasitic channel.

[0251] It is also preferable to remove a portion of the side surface of the oxide 230b in the region overlapping the opening. The amount of film reduction in this region corresponds to We shown in FIG. 3B. This prevents the formation of a low-resistance region near the side surface of the channel formation region and suppresses the occurrence of a parasitic channel. This reduces variations in transistor characteristics due to the parasitic channel.

[0252] Furthermore, a portion of the insulator 280, a portion of the insulating film 254A, and a portion of the conductive layer 242B may be processed under different conditions. For example, a portion of the insulator 280 may be processed by dry etching, a portion of the insulating film 254A may be processed by wet etching, and a portion of the conductive layer 242B may be processed by dry etching.

[0253] Here, it is preferable to remove impurities attached to the surface of or diffused into the oxide 230a, the oxide 230b, etc. Examples of such impurities include those originating from components contained in the insulator 280, the insulating film 254A, and the conductive layer 242B, components contained in the materials used in the device used to form the openings, and components contained in the gas or liquid used in etching. Examples of such impurities include aluminum, silicon, tantalum, fluorine, and chlorine.

[0254] A cleaning treatment may be carried out to remove the above-mentioned impurities, etc. Cleaning methods include wet cleaning using a cleaning solution, plasma treatment using plasma, and cleaning by heat treatment, and the above cleaning methods may be combined as appropriate.

[0255] Wet cleaning may be performed using an aqueous solution of ammonia water, oxalic acid, phosphoric acid, hydrofluoric acid, or the like diluted with carbonated water or pure water, or pure water, or carbonated water. Ultrasonic cleaning may also be performed using these aqueous solutions, pure water, or carbonated water. These cleaning methods may also be used in combination.

[0256] Next, a heat treatment may be performed. The heat treatment is preferably performed in an oxygen-containing atmosphere. Alternatively, the heat treatment may be performed under reduced pressure to continuously form the oxide film 230C without exposure to the atmosphere (see FIGS. 8A to 8D). By performing such a treatment, moisture and hydrogen adsorbed on the surface of the oxide 230b can be removed, and the moisture and hydrogen concentrations in the oxides 230a and 230b can be further reduced. The temperature of the heat treatment is preferably 100°C or higher and 400°C or lower. In this embodiment, the temperature of the heat treatment is set to 200°C.

[0257] The oxide film 230C can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. The oxide film 230C may be formed by the same film formation method as that for the oxide film 230A or 230B, depending on the desired characteristics of the oxide film 230C. In this embodiment, the oxide film 230C is formed by sputtering using an oxide target with an atomic ratio of In:Ga:Zn=4:2:4.1.

[0258] The oxide film 230C may be a laminated film. For example, a film may be formed by sputtering using an oxide target with an atomic ratio of In:Ga:Zn=4:2:4.1, followed by another film formed by sputtering using an oxide target with an atomic ratio of In:Ga:Zn=1:3:4.

[0259] During the formation of the oxide film 230C, some of the oxygen contained in the sputtering gas may be supplied to the oxide 230a and the oxide 230b. Alternatively, during the formation of the oxide film 230C, some of the oxygen contained in the sputtering gas may be supplied to the insulator 280. Therefore, the proportion of oxygen contained in the sputtering gas for the oxide film 230C should be 70% or more, preferably 80% or more, and more preferably 100%.

[0260] Next, a heat treatment may be performed. The heat treatment may be performed under reduced pressure, and the insulating film 250A may be continuously formed without exposure to the atmosphere (see FIGS. 8A to 8D). By performing such a treatment, moisture and hydrogen adsorbed on the surface of the oxide film 230C can be removed, and the moisture and hydrogen concentrations in the oxide 230a, the oxide 230b, and the oxide film 230C can be further reduced. The temperature of the heat treatment is preferably 100°C or higher and 400°C or lower.

[0261] The insulating film 250A can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. In this embodiment, silicon oxynitride is formed as the insulating film 250A by CVD. The film formation temperature for forming the insulating film 250A is preferably 350°C or higher and lower than 450°C, particularly around 400°C. By forming the insulating film 250A at 400°C, an insulating film with few impurities can be formed.

[0262] When the insulator 250 has a two-layer laminated structure, it is preferable to successively deposit the insulating film that will be the lower layer of the insulator 250 and the insulating film that will be the upper layer of the insulator 250 without exposing them to the atmospheric environment. Depositing the films without exposing them to the atmospheric environment can prevent impurities or moisture from the atmospheric environment from adhering to the insulating film that will be the lower layer of the insulator 250 and the insulating film that will be the upper layer of the insulator 250, and can keep the vicinity of the interface between the insulating film that will be the lower layer of the insulator 250 and the insulating film that will be the upper layer of the insulator 250 clean.

[0263] Here, after the insulating film 250A is formed, a microwave treatment may be performed in an oxygen-containing atmosphere under reduced pressure. By performing the microwave treatment, an electric field due to microwaves is applied to the insulating film 250A, the oxide film 230C, the oxide 230b, the oxide 230a, etc., and V in the oxide film 230C, the oxide 230b, and the oxide 230a is increased. O H to V Oand hydrogen. At this time, some of the hydrogen separated may combine with oxygen to form H2O, which may be removed from the insulating film 250A, the oxide film 230C, the oxide 230b, and the oxide 230a. Also, some of the hydrogen may be gettered to the conductor 242 (the conductor 242a and the conductor 242b). In this way, by performing microwave treatment, the hydrogen concentrations in the insulating film 250A, the oxide film 230C, the oxide 230b, and the oxide 230a can be reduced. Also, V in the oxide 230a, the oxide 230b, and the oxide film 230C can be reduced. O H to V O V that can exist after splitting into and hydrogen O Oxygen is supplied to V O can be repaired or compensated for.

[0264] Alternatively, a heat treatment may be performed while maintaining the reduced pressure after the microwave treatment. By performing such a treatment, hydrogen can be efficiently removed from the insulating film 250A, the oxide film 230C, the oxide 230b, and the oxide 230a. Some of the hydrogen may be gettered to the conductor 242 (the conductor 242a and the conductor 242b). Alternatively, a heat treatment step may be repeated multiple times while maintaining the reduced pressure after the microwave treatment. Repeated heat treatments can more efficiently remove hydrogen from the insulating film 250A, the oxide film 230C, the oxide 230b, and the oxide 230a. The heat treatment temperature is preferably 300°C or higher and 500°C or lower.

[0265] Furthermore, microwave treatment can modify the film quality of the insulating film 250A, thereby suppressing the diffusion of hydrogen, water, impurities, etc. Therefore, it is possible to suppress the diffusion of hydrogen, water, impurities, etc. into the oxide 230b, the oxide 230a, etc. via the insulator 250 in a post-process such as film formation of a conductive film that becomes the conductor 260, or in a post-treatment such as heat treatment.

[0266] Next, a conductive film 260A and a conductive film 260B are formed in this order (see FIGS. 9A to 9D). The conductive film 260A and the conductive film 260B can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, the conductive film 260A is formed by an ALD method, and the conductive film 260B is formed by a CVD method.

[0267] Next, the oxide film 230C, the insulating film 250A, the conductive film 260A, and the conductive film 260B are polished by CMP until the insulator 280 is exposed, thereby forming the oxide 230c, the insulator 250, and the conductor 260 (the conductor 260a and the conductor 260b) (see FIGS. 10A to 10C). As a result, the oxide 230c is arranged to cover the inner wall (side wall and bottom surface) of the opening that reaches the oxide 230b. The insulator 250 is arranged to cover the inner wall of the opening via the oxide 230c. The conductor 260 is arranged to fill the opening via the oxide 230c and the insulator 250.

[0268] Next, heat treatment may be performed. In this embodiment, the treatment is performed in a nitrogen atmosphere at a temperature of 400° C. for 1 hour. The heat treatment can reduce the moisture and hydrogen concentrations in the insulators 250 and 280.

[0269] Next, the insulator 282 is formed over the oxide 230c, the insulator 250, the conductor 260, and the insulator 280 (see FIGS. 11B to 11D). The insulator 282 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. For example, it is preferable to form an aluminum oxide film by a sputtering method as the insulator 282. By forming the insulator 282 in an oxygen-containing atmosphere using a sputtering method, oxygen can be added to the insulator 280 during film formation. At this time, it is preferable to form the insulator 282 while heating the substrate. Furthermore, it is preferable to form the insulator 282 in contact with the top surface of the conductor 260, because this can prevent oxygen contained in the insulator 280 from being absorbed by the conductor 260 during subsequent heat treatment.

[0270] Next, the insulator 283 is deposited on the insulator 282 (see FIGS. 11B to 11D). The insulator 283 can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. It is preferable to deposit a silicon nitride film or a silicon nitride oxide film as the insulator 283.

[0271] Next, heat treatment may be performed. In this embodiment, the treatment is performed in a nitrogen atmosphere at 400° C. for 1 hour. This heat treatment allows oxygen added by the formation of the insulator 282 to diffuse into the insulator 280 and to be further supplied to the oxide 230a and the oxide 230b via the oxide 230c. Note that this heat treatment may be performed not only after the formation of the insulator 283 but also after the formation of the insulator 282.

[0272] Next, the insulator 274 may be deposited on the insulator 283. The insulator 274 can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0273] Next, an insulator 281 may be formed on the insulator 274. The insulator 281 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. As the insulator 281, it is preferable to form a film of silicon nitride by a sputtering method, for example.

[0274] Next, openings reaching the conductors 242a and 242b are formed in the insulators 254, 280, 282, 283, 274, and 281. The openings may be formed by lithography.

[0275] Next, an insulating film that will become the insulator 241 (insulator 241a and insulator 241b) is formed, and the insulating film is anisotropically etched to form the insulator 241. The insulating film can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. It is preferable to use an insulating film that has the function of suppressing oxygen permeation as the insulating film. For example, it is preferable to form a silicon nitride film using the PEALD method. Silicon nitride is preferable because it has a high blocking property against hydrogen.

[0276] Furthermore, dry etching, for example, may be used for anisotropic etching of the insulating film that will become the insulator 241. By providing the insulator 241 on the sidewall of the opening, it is possible to suppress the permeation of oxygen from the outside and prevent oxidation of the conductors 240a and 240b that will be formed next. It is also possible to prevent impurities such as water and hydrogen from diffusing to the outside from the conductors 240a and 240b.

[0277] Next, a conductive film that will become the conductors 240a and 240b is formed. The conductive film preferably has a layered structure including a conductor that has the function of suppressing the permeation of impurities such as water and hydrogen. For example, it can be a layered structure of tantalum nitride, titanium nitride, or the like, and tungsten, molybdenum, copper, or the like. The conductive film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0278] Next, CMP processing is performed to remove portions of the conductive film that will become the conductors 240a and 240b, thereby exposing the insulator 281. As a result, the conductive film remains only in the openings, thereby forming the conductors 240a and 240b with flat upper surfaces (see FIGS. 1A to 1D). Note that the CMP processing may remove portions of the insulator 281.

[0279] Next, a conductive film is formed to become the conductor 246. The conductive film can be formed by sputtering, CVD, MBE, PLD, ALD, or the like.

[0280] Next, the conductive film that will become the conductor 246 is processed by lithography to form the conductor 246a that contacts the top surface of the conductor 240a and the conductor 246b that contacts the top surface of the conductor 240b (see Figures 1A to 1D).

[0281] 1A to 1D can be manufactured. As shown in FIGS. 4A to 11D, the transistor 200 can be manufactured by the manufacturing method of a semiconductor device described in this embodiment.

[0282] <Modification of Semiconductor Device> An example of a semiconductor device according to one embodiment of the present invention will be described below with reference to FIGS. 12A to 12D and FIGS. 13A and 13B.

[0283] [Semiconductor Device Variation 1] Fig. 12A shows a top view of the semiconductor device. Fig. 12B is a cross-sectional view corresponding to the portion indicated by the dashed line A1-A2 in Fig. 12A. Fig. 12C is a cross-sectional view corresponding to the portion indicated by the dashed line A3-A4 in Fig. 12A. Fig. 12D is a cross-sectional view corresponding to the portion indicated by the dashed line A5-A6 in Fig. 12A. Some elements have been omitted from the top view of Fig. 12A for clarity.

[0284] 12A to 12D, the same reference numerals are used to designate structures having the same functions as those constituting the semiconductor device shown in <Configuration Example of Semiconductor Device>. Note that, in this section as well, the materials described in detail in <Configuration Example of Semiconductor Device> can be used as the materials constituting the semiconductor device.

[0285] 1A to 1D. The semiconductor device shown in FIGS. 12A to 12D is a modified example of the semiconductor device shown in FIGS. 1A to 1D. The semiconductor device shown in FIGS. 12A to 12D differs from the semiconductor device shown in FIGS. 1A to 1D in the shape of the insulator 283. Also, the semiconductor device shown in FIGS. 12A to 12D differs in that it includes an oxide 243 (oxide 243a and oxide 243b). Also shown is a configuration in which the oxide 230c and the insulator 254 each have a two-layer stacked structure.

[0286] 12A to 12D , the insulators 214, 216, 222, 224, 254 (insulators 254a and 254b), 280, and 282 are patterned, and the insulator 283 covers them. That is, the insulator 283 contacts the top surface and side surfaces of the insulator 282, the side surfaces of the insulator 280, the side surfaces of the insulator 254, the side surfaces of the insulator 224, the side surfaces of the insulator 222, the side surfaces of the insulator 216, the side surfaces of the insulator 214, and the top surface of the insulator 212. As a result, the insulators 214, 216, 222, 224, 254, 280, and 282, including the oxide 230, are isolated from the outside by the insulators 283 and 212. In other words, the transistor 200 is disposed within an area sealed by the insulator 283 and the insulator 212 .

[0287] The insulators 212 and 283 preferably have a high function of suppressing the diffusion of hydrogen (e.g., at least one of hydrogen atoms, hydrogen molecules, etc.) or water molecules. For example, the insulators 212 and 283 are preferably made of silicon nitride or silicon nitride oxide, which have a higher hydrogen barrier property.

[0288] With this configuration, it is possible to prevent hydrogen contained outside the sealed region from being mixed into the sealed region.

[0289] 12A to 12D, the transistor 200 has a structure in which the insulators 212, 214, and 283 are provided as a single layer, but the present invention is not limited to this. For example, the insulators 212, 214, and 283 may have a stacked structure of two or more layers.

[0290] 12A to 12D includes an oxide 243 (oxide 243a and oxide 243b) having a function of suppressing oxygen permeation between the conductor 242 (conductor 242a and conductor 242b) and the oxide 230. By disposing the oxide 243 having a function of suppressing oxygen permeation between the conductor 242 functioning as a source electrode or a drain electrode and the oxide 230b, the electrical resistance between the conductor 242 and the oxide 230b can be reduced, which is preferable. With such a structure, the electrical characteristics and reliability of the transistor 200 can be improved.

[0291] A metal oxide containing element M may be used as oxide 243. In particular, element M may be aluminum, gallium, yttrium, or tin. Preferably, oxide 243 has a higher concentration of element M than oxide 230b. Alternatively, oxide 243 may be gallium oxide. Alternatively, oxide 243 may be a metal oxide such as In-M-Zn oxide. Specifically, the atomic ratio of element M to In in the metal oxide used for oxide 243 is preferably greater than the atomic ratio of element M to In in the metal oxide used for oxide 230b. Furthermore, the film thickness of oxide 243 is preferably 0.5 nm to 5 nm, more preferably 1 nm to 3 nm, and even more preferably 1 nm to 2 nm. Furthermore, oxide 243 preferably has crystallinity. When oxide 243 has crystallinity, oxygen release from oxide 230 can be effectively suppressed. For example, oxide 243 with a hexagonal or other crystal structure may be able to suppress oxygen release from oxide 230.

[0292] In a cross-sectional view of the transistor 200 in the channel length direction, the bottom surface of the oxide 230c in the region overlapping with the conductor 260 is preferably at the same level as or lower than the bottom surface of the oxide 243 (oxide 243a and oxide 243b). This shape can remove impurities near the interface between the oxide 230b and the oxide 230c, thereby reducing the formation of a low-resistance region near the top surface of the region 234. For example, in a cross-sectional view of the transistor 200 in the channel length direction, the difference in height between the bottom surface of the oxide 243 and the bottom surface of the oxide 230c in the region overlapping with the conductor 260, relative to the bottom surface of the insulator 224, is 0 nm or more and 10 nm or less, preferably 0 nm or more and 5 nm or less, and more preferably 0 nm or more and 3 nm or less.

[0293] In the transistor 200 illustrated in FIGS. 12A to 12D, the oxide 230c has a stacked structure of an oxide 230c1 and an oxide 230c2.

[0294] The oxide 230c2 preferably contains at least one of the metal elements constituting the metal oxide used in the oxide 230c1, and more preferably contains all of the metal elements. For example, the oxide 230c1 may be an In-Ga-Zn oxide or an In-Zn oxide, and the oxide 230c2 may be an In-Ga-Zn oxide, a Ga-Zn oxide, or a gallium oxide. This reduces the defect state density at the interface between the oxide 230c1 and the oxide 230c2.

[0295] Furthermore, the conduction band minimums of the oxides 230a and 230c2 are preferably closer to the vacuum level than the conduction band minimums of the oxides 230b and 230c1. In other words, the electron affinity of the oxides 230a and 230c2 is preferably smaller than that of the oxides 230b and 230c1. In this case, it is preferable that the oxide 230c2 be a metal oxide that can be used for the oxide 230a, and the oxide 230c1 be a metal oxide that can be used for the oxide 230b. In this case, the main carrier path may not only be the oxide 230b, but also the oxide 230c1. Using a metal oxide that can be used for the oxide 230b for the oxide 230c1 can prevent the effective channel length at the top surface of the channel formation region from increasing, thereby suppressing a decrease in the on-current of the transistor 200.

[0296] Specifically, a metal oxide having an atomic ratio of In:Ga:Zn=4:2:3 or In:Ga:Zn=5:1:6, or an In-Zn oxide, can be used as oxide 230c1, and a metal oxide having an atomic ratio of In:Ga:Zn=1:3:4, Ga:Zn=2:1, Ga:Zn=2:5, or gallium oxide can be used as oxide 230c2.

[0297] Furthermore, the oxide 230c2 is preferably a metal oxide that suppresses the diffusion or permeation of oxygen more than the oxide 230c1. By providing the oxide 230c2 between the insulator 250 and the oxide 230c1, it is possible to suppress the diffusion of oxygen contained in the insulator 280 into the insulator 250. Therefore, the oxygen can be efficiently supplied to the oxide 230b via the oxide 230c1.

[0298] Furthermore, by making the atomic ratio of In to the main component metal element in the metal oxide used for oxide 230c2 smaller than the atomic ratio of In to the main component metal element in the metal oxide used for oxide 230c1, it is possible to suppress diffusion of In toward insulator 250. Since insulator 250 functions as a gate insulator, if In gets mixed into insulator 250 or the like, it will cause poor transistor characteristics. Therefore, by providing oxide 230c2 between oxide 230c1 and insulator 250, it is possible to provide a highly reliable semiconductor device.

[0299] The oxide 230c1 may be provided for each transistor 200. That is, the oxide 230c1 of one transistor 200 and the oxide 230c1 of another transistor 200 adjacent to the transistor 200 may not be in contact with each other. Alternatively, the oxide 230c1 of one transistor 200 and the oxide 230c1 of another transistor 200 adjacent to the transistor 200 may be separated from each other. In other words, the oxide 230c1 may not be disposed between the transistor 200 and the transistor 200 adjacent to the transistor 200.

[0300] In a semiconductor device in which multiple transistors 200 are arranged in the channel width direction, the above structure allows the oxide 230c to be independently provided in each transistor 200. This prevents a parasitic transistor from being formed between a transistor 200 and a transistor 200 adjacent to the transistor 200, thereby preventing the leakage path from being formed. This makes it possible to provide a semiconductor device that has favorable electrical characteristics and can be miniaturized or highly integrated.

[0301] For example, if the distance between the side edge of the oxide 230c1 of one transistor 200 and the side edge of the oxide 230c1 of another transistor 200 adjacent to the transistor 200, which face each other in the channel width direction of the transistor 200, is represented as L1, L1 is set to be greater than 0 nm. Furthermore, if the distance between the side edge of the oxide 230a of one transistor 200 and the side edge of the oxide 230a of another transistor 200 adjacent to the transistor 200, which face each other in the channel width direction of the transistor 200, is represented as L2, the ratio of L1 to L2 (L1 / L2) is preferably greater than 0 and less than 1, more preferably 0.1 to 0.9, and even more preferably 0.2 to 0.8. Note that L2 may also be the distance between the side edge of the oxide 230b of one transistor 200 and the side edge of the oxide 230b of another transistor 200 adjacent to the transistor 200, which face each other.

[0302] By reducing the ratio of L1 to L2 (L1 / L2), even if a misalignment occurs in the region where oxide 230c1 is not located between transistor 200 and the transistor 200 adjacent to said transistor 200, oxide 230c1 of transistor 200 can be separated from oxide 230c1 of the transistor 200 adjacent to said transistor 200.

[0303] Furthermore, by increasing the ratio of L1 to L2 (L1 / L2), even if the distance between a transistor 200 and an adjacent transistor 200 is narrowed, the width of the minimum processing dimension can be ensured, thereby enabling further miniaturization or high integration of semiconductor devices.

[0304] Note that the conductor 260, the insulator 250, and the oxide 230c2 may be shared between adjacent transistors 200. That is, the conductor 260 of one transistor 200 has a region that is continuous with the conductor 260 of another transistor 200 adjacent to the transistor 200. The insulator 250 of one transistor 200 has a region that is continuous with the insulator 250 of another transistor 200 adjacent to the transistor 200. The oxide 230c2 of one transistor 200 has a region that is continuous with the oxide 230c2 of another transistor 200 adjacent to the transistor 200.

[0305] Furthermore, with the above structure, the oxide 230c2 has a region in contact with the insulator 224 between the transistor 200 and the transistor 200 adjacent to the transistor 200.

[0306] As with the oxide 230c1, the oxide 230c2 of one transistor 200 may be separated from the oxide 230c2 of another transistor 200 adjacent to the transistor 200. In this case, the insulator 250 has a region in contact with the insulator 224 between the transistor 200 and the transistor 200 adjacent to the transistor 200.

[0307] 12A to 12D, the insulator 254 has a stacked structure of an insulator 254a and an insulator 254b. Note that for descriptions of materials, film formation methods, and the like of the insulators 254a and 254b, the descriptions of the lower layer of the insulator 254 and the upper layer of the insulator 254 in <Detailed Structure of Semiconductor Device> can be referred to.

[0308] Alternatively, instead of providing the insulator 254, an insulator functioning as a barrier layer may be provided between the top surface of the conductor 242 and the insulator 280. This structure can prevent the conductor 242 from absorbing excess oxygen contained in the insulator 280. Furthermore, by suppressing oxidation of the conductor 242, an increase in contact resistance between the transistor 200 and the wiring can be suppressed. Therefore, the transistor 200 can have good electrical characteristics and reliability.

[0309] Therefore, it is preferable that the insulator has a function of suppressing the diffusion of oxygen. For example, it is preferable that the insulator has a function of suppressing the diffusion of oxygen more than the insulator 280.

[0310] As the insulator, for example, an insulator containing oxide of one or both of aluminum and hafnium may be formed. In particular, aluminum oxide may be formed by the ALD method. By forming the insulator using the ALD method, a dense film with reduced defects such as cracks and pinholes or with a uniform thickness may be formed. Furthermore, as the insulator, for example, an insulator containing aluminum nitride may be used.

[0311] [Variation 2 of the semiconductor device] 13A and 13B show a structure in which multiple transistors (transistors 200_1 to 200_n) are encapsulated with an insulator 283 and an insulator 212. Note that although the transistors 200_1 to 200_n appear to be aligned in the channel length direction in FIGS. 13A and 13B, this is not a limitation. The transistors 200_1 to 200_n may be aligned in the channel width direction, arranged in a matrix, or arranged irregularly.

[0312] As shown in FIG. 13A, a portion where the insulator 283 and the insulator 212 are in contact with each other (hereinafter, this portion may be referred to as a sealing portion 265) is formed outside a plurality of transistors (transistors 200_1 to 200_n). The sealing portion 265 is formed to surround the plurality of transistors (also referred to as a transistor group). With this structure, the plurality of transistors can be surrounded by the insulator 283 and the insulator 212. That is, the four side surfaces and the upper portion of the plurality of transistors can be surrounded by the insulator 283 and the insulator 281, and the lower portion can be surrounded by the insulator 212. In this way, a plurality of transistor groups surrounded by the sealing portion 265 are provided on the substrate.

[0313] Here, it is preferable that the distance between the sealing portion 265 and the oxide 230 closest to the sealing portion 265 is short. For example, the distance between the sealing portion 265 and the oxide 230 closest to the sealing portion 265 is preferably 1 μm or less, and more preferably 500 nm or less. With this configuration, the volume of the insulator 280 sealed in the insulator 283 or the like can be reduced, and therefore the amount of hydrogen contained in the insulator 280 can be reduced.

[0314] Also, dicing lines (sometimes called scribe lines, division lines, or cutting lines) may be provided overlapping the sealing portion 265. The substrate is divided along the dicing lines, so that a group of transistors surrounded by the sealing portion 265 is extracted as one chip.

[0315] 13A shows an example in which multiple transistors (transistors 200_1 to 200_n) are surrounded by one sealing portion 265, but the present invention is not limited to this. As shown in FIG. 13B, multiple transistors (transistors 200_1 to 200_n) may be surrounded by multiple sealing portions. In FIG. 13B, the multiple transistors are surrounded by a sealing portion 265a and further surrounded by an outer sealing portion 265b.

[0316] In this manner, by using a configuration in which a plurality of transistors (transistors 200_1 to 200_n) are surrounded by a plurality of sealing portions, the contact area between the insulator 283 and the insulator 212 increases, thereby further improving the adhesion between the insulator 283 and the insulator 212. This makes it possible to more reliably seal the plurality of transistors.

[0317] In this case, a dicing line may be provided overlapping the sealing portion 265a or the sealing portion 265b, or may be provided between the sealing portion 265a and the sealing portion 265b.

[0318] 13A and 13B show a configuration in which the insulator 212 has a lower layer and an upper layer stacked together. For example, a silicon nitride film is formed as the lower layer of the insulator 212 by PECVD, and a silicon nitride film is formed as the upper layer of the insulator 212 by sputtering. This allows the lower layer of the insulator 212 to be formed at a faster rate than the upper layer of the insulator 212, thereby improving productivity. Furthermore, the hydrogen concentration in the upper layer of the insulator 212, which is located closer to the oxide 230 than the lower layer of the insulator 212, can be reduced compared to the lower layer of the insulator 212. Thus, by using an insulator that is impermeable to impurities such as water and hydrogen, such as silicon nitride, as the insulator 212, it is possible to suppress the diffusion of impurities such as water and hydrogen from the layer below the insulator 212 (not shown). Furthermore, by using an insulator that is difficult for copper to penetrate, such as silicon nitride, as the insulator 212, even if a metal that easily diffuses, such as copper, is used in a conductor layer below the insulator 212, the metal can be prevented from diffusing upward through the insulator 212.

[0319] The present invention is not limited to the above configuration, and may have a single-layer structure in which either a lower layer of the insulator 212 or an upper layer of the insulator 212 is provided. In addition, in Figures 13A and 13B, etc., the structure is one in which the insulator 214 is provided, but the present invention is not limited to this, and may have a structure in which the insulator 214 is not provided.

[0320] According to one embodiment of the present invention, a semiconductor device with little variation in transistor characteristics can be provided. According to another embodiment of the present invention, a semiconductor device with large on-state current can be provided. According to another embodiment of the present invention, a semiconductor device with favorable electrical characteristics can be provided. According to another embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. According to another embodiment of the present invention, a semiconductor device with favorable reliability can be provided. According to another embodiment of the present invention, a semiconductor device with low power consumption can be provided.

[0321] The structures, methods, and the like described in this embodiment mode can be used in appropriate combination with structures, methods, and the like described in other embodiment modes, examples, and the like.

[0322] (Embodiment 2) In this embodiment, one mode of a semiconductor device will be described with reference to FIGS.

[0323] [Storage device 1] 14 illustrates an example of a semiconductor device (memory device) using the semiconductor device of one embodiment of the present invention. In the semiconductor device of one embodiment of the present invention, the transistor 200 is provided above the transistor 300, and the capacitor 100 is provided above the transistor 300 and the transistor 200. Note that the transistor 200 described in the above embodiment can be used as the transistor 200. Therefore, the description of the above embodiment can be referred to for the transistor 200 and a layer including the transistor 200.

[0324] The transistor 200 is a transistor in which a channel is formed in a semiconductor layer containing an oxide semiconductor. The transistor 200 has a low off-state current; therefore, when used in a memory device, the stored data can be retained for a long time. That is, a refresh operation is not required or the frequency of the refresh operation is extremely low; therefore, the power consumption of the memory device can be sufficiently reduced.

[0325] 14 , a wiring 1001 is electrically connected to the source of a transistor 300, and a wiring 1002 is electrically connected to the drain of the transistor 300. A wiring 1003 is electrically connected to one of the source and drain of a transistor 200, a wiring 1004 is electrically connected to the first gate of the transistor 200, and a wiring 1006 is electrically connected to the second gate of the transistor 200. The gate of the transistor 300 and the other of the source and drain of the transistor 200 are electrically connected to one electrode of a capacitor 100, and a wiring 1005 is electrically connected to the other electrode of the capacitor 100.

[0326] Moreover, the memory device shown in FIG. 14 can be arranged in a matrix to form a memory cell array.

[0327] <Transistor 300> The transistor 300 is provided on a substrate 311 and includes a conductor 316 functioning as a gate, an insulator 315 functioning as a gate insulator, a semiconductor region 313 formed of part of the substrate 311, and low-resistance regions 314a and 314b functioning as source and drain regions. The transistor 300 may be either a p-channel type or an n-channel type.

[0328] Here, in the transistor 300 shown in FIG. 14, a semiconductor region 313 (a part of a substrate 311) where a channel is formed has a convex shape. In addition, a conductor 316 is provided to cover the side and top surfaces of the semiconductor region 313 with an insulator 315 interposed therebetween. Note that the conductor 316 may be made of a material that adjusts the work function. Such a transistor 300 is also called a FIN-type transistor because it utilizes the convex portion of the semiconductor substrate. Note that an insulator may be provided in contact with the top of the convex portion and function as a mask for forming the convex portion. In addition, although the case where the convex portion is formed by processing a part of the semiconductor substrate has been shown, a semiconductor film having a convex shape may also be formed by processing an SOI substrate.

[0329] Note that the transistor 300 shown in FIG. 14 is just an example, and the structure is not limited to this, and an appropriate transistor may be used depending on the circuit configuration and driving method.

[0330] <Capacitor element 100> The capacitor 100 is provided above the transistor 200. The capacitor 100 includes a conductor 110 functioning as a first electrode, a conductor 120 functioning as a second electrode, and an insulator 130 functioning as a dielectric.

[0331] For example, the conductor 112 over the conductor 240 and the conductor 110 can be formed simultaneously. Note that the conductor 112 functions as a plug or a wiring electrically connected to the capacitor 100, the transistor 200, or the transistor 300.

[0332] 14, the conductor 112 and the conductor 110 are shown as having a single layer structure, but are not limited to this configuration and may have a laminated structure of two or more layers. For example, a conductor having barrier properties and a conductor having high adhesion to the conductor having high conductivity may be formed between a conductor having barrier properties and a conductor having high conductivity.

[0333] The insulator 130 can be made of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, hafnium nitride, or the like, and can be formed as a stacked layer or a single layer.

[0334] For example, it is preferable to use a layered structure of a material with high dielectric strength, such as silicon oxynitride, and a high dielectric constant (high-k) material for the insulator 130. With this configuration, the capacitor 100 can ensure sufficient capacitance by having an insulator with high dielectric constant (high-k), and the capacitor 100 can improve its dielectric strength by having an insulator with high dielectric strength, thereby preventing electrostatic breakdown of the capacitor 100.

[0335] Examples of high-dielectric-constant (high-k) materials (materials with a high relative dielectric constant) insulators include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0336] On the other hand, materials with high dielectric strength (materials with low dielectric constant) include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, silicon oxide with voids, and resin.

[0337] <Wiring layer> Between each structure, a wiring layer provided with an interlayer film, wiring, plugs, etc. may be provided. Furthermore, multiple wiring layers may be provided depending on the design. Here, for a conductor functioning as a plug or wiring, the same reference numeral may be used to refer to multiple structures. Furthermore, in this specification and the like, the wiring and the plug electrically connected to the wiring may be integrated. That is, there are cases where a part of the conductor functions as the wiring, and cases where a part of the conductor functions as the plug.

[0338] For example, an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are stacked in this order as an interlayer film over the transistor 300. Conductors 328, 330, and the like that are electrically connected to the capacitor 100 or the transistor 200 are embedded in the insulators 320, 322, 324, and 326. The conductors 328 and 330 function as plugs or wirings.

[0339] The insulator functioning as an interlayer film may also function as a planarizing film that covers the underlying unevenness. For example, the top surface of the insulator 322 may be planarized by a planarization process using a chemical mechanical polishing (CMP) method or the like to enhance flatness.

[0340] A wiring layer may be provided on the insulator 326 and the conductor 330. For example, in Fig. 14, an insulator 350, an insulator 352, and an insulator 354 are stacked in this order. A conductor 356 is formed on the insulator 350, the insulator 352, and the insulator 354. The conductor 356 functions as a plug or a wiring.

[0341] Similarly, a conductor 218, a conductor constituting the transistor 200 (the conductor 205), and the like are embedded in the insulators 210, 212, 214, and 216. Note that the conductor 218 functions as a plug or wiring electrically connected to the capacitor 100 or the transistor 300. Furthermore, an insulator 150 is provided over the conductor 120 and the insulator 130.

[0342] Here, similar to the insulator 241 described in the above embodiment, the insulator 217 is provided in contact with the side surface of the conductor 218 that functions as a plug. The insulator 217 is provided in contact with the inner wall of the opening formed in the insulators 210, 212, 214, and 216. In other words, the insulator 217 is provided between the conductor 218 and the insulators 210, 212, 214, and 216. Note that the conductor 205 can be formed in parallel with the conductor 218, and therefore the insulator 217 may be formed in contact with the side surface of the conductor 205.

[0343] The insulator 217 may be, for example, an insulator such as silicon nitride, aluminum oxide, or silicon nitride oxide. The insulator 217 is provided in contact with the insulators 210, 212, 214, 216, and 222, and therefore can prevent impurities such as water and hydrogen contained in the insulators 210 and 216 from mixing into the oxide 230 through the conductor 218. Silicon nitride is particularly suitable because it has a high blocking property against hydrogen. In addition, the insulator 217 can prevent oxygen contained in the insulator 210 or the insulator 216 from being absorbed by the conductor 218.

[0344] The insulator 217 can be formed by a method similar to that of the insulator 241. For example, a silicon nitride film is formed by a PEALD method, and an opening reaching the conductor 356 is formed by anisotropic etching.

[0345] Examples of insulators that can be used as the interlayer film include insulating oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides.

[0346] For example, by using a material with a low dielectric constant for the insulator that functions as an interlayer film, the parasitic capacitance that occurs between wirings can be reduced. Therefore, it is advisable to select a material depending on the function of the insulator.

[0347] For example, insulators 150, 210, 352, and 354 preferably have an insulator with a low dielectric constant. For example, the insulator preferably includes silicon nitride oxide, silicon nitride, fluorine-doped silicon oxide, carbon-doped silicon oxide, carbon- and nitrogen-doped silicon oxide, pore-containing silicon oxide, or resin. Alternatively, the insulator preferably has a layered structure of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, fluorine-doped silicon oxide, carbon-doped silicon oxide, carbon- and nitrogen-doped silicon oxide, or pore-containing silicon oxide, and resin. Silicon oxide and silicon oxynitride are thermally stable, and therefore can be combined with resin to form a thermally stable layered structure with a low dielectric constant. Examples of suitable resins include polyester, polyolefin, polyamide (e.g., nylon, aramid), polyimide, polycarbonate, and acrylic.

[0348] Furthermore, the electrical characteristics of a transistor including an oxide semiconductor can be stabilized by surrounding the transistor with an insulator that has a function of suppressing the permeation of impurities such as hydrogen and oxygen. Therefore, the insulators 214, 212, 350, and the like can be insulators that have a function of suppressing the permeation of impurities such as hydrogen and oxygen.

[0349] Examples of insulators that can suppress the permeation of impurities such as hydrogen and oxygen include insulators containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum, and can be used in a single layer or a stacked layer. Specifically, examples of insulators that can suppress the permeation of impurities such as hydrogen and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, silicon nitride oxide, and silicon nitride.

[0350] Conductors that can be used for wiring and plugs include materials containing one or more metal elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, etc. Also usable are semiconductors with high electrical conductivity, typified by polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide.

[0351] For example, the conductors 328, 330, 356, conductor 218, conductor 112, etc. can be formed of a single layer or a stack of conductive materials such as metal materials, alloy materials, metal nitride materials, and metal oxide materials formed from the above materials. High-melting-point materials such as tungsten and molybdenum that have both heat resistance and conductivity are preferably used, and tungsten is preferred. Alternatively, they are preferably formed of low-resistance conductive materials such as aluminum and copper. The use of low-resistance conductive materials can reduce wiring resistance.

[0352] <Wiring or plug in layer provided with oxide semiconductor> When an oxide semiconductor is used for the transistor 200, an insulator having an excess oxygen region may be provided near the oxide semiconductor. In that case, an insulator having a barrier property is preferably provided between the insulator having the excess oxygen region and a conductor provided in the insulator having the excess oxygen region.

[0353] 14, for example, an insulator 241 may be provided between the conductor 240 and the insulators 224 and 280 containing excess oxygen. By providing the insulator 241 in contact with the insulators 222 and 254, the insulator 224 and the transistor 200 can be sealed with an insulator having barrier properties. Furthermore, the insulator 241 is preferably also in contact with a portion of the insulator 280. By extending the insulator 241 to the insulator 274, the diffusion of oxygen and impurities can be further suppressed.

[0354] That is, the insulator 241 can prevent excess oxygen contained in the insulator 224 and the insulator 280 from being absorbed by the conductor 240. Furthermore, the insulator 241 can prevent hydrogen, which is an impurity, from diffusing into the transistor 200 through the conductor 240.

[0355] The insulator 241 may be made of an insulating material that has the function of suppressing the diffusion of impurities such as water and hydrogen, as well as oxygen. For example, it is preferable to use silicon nitride, silicon nitride oxide, aluminum oxide, hafnium oxide, or the like. Silicon nitride is particularly preferable because of its high blocking properties against hydrogen. Other examples that can be used include metal oxides such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, and tantalum oxide.

[0356] The above is a description of the configuration example. By using this configuration, in a semiconductor device using a transistor including an oxide semiconductor, fluctuations in electrical characteristics can be suppressed and reliability can be improved. Furthermore, a transistor including an oxide semiconductor with high on-state current can be provided. Furthermore, a transistor including an oxide semiconductor with low off-state current can be provided. Furthermore, a semiconductor device with reduced power consumption can be provided.

[0357] [Storage device 2] An example of a memory device using a semiconductor device according to one embodiment of the present invention is illustrated in Fig. 15. The memory device illustrated in Fig. 15 includes a transistor 400 in addition to the semiconductor device including the transistor 200, the transistor 300, and the capacitor 100 shown in Fig. 14.

[0358] The transistor 400 can control the second gate voltage of the transistor 200. For example, the first gate and the second gate of the transistor 400 are diode-connected to the source, and the source of the transistor 400 is connected to the second gate of the transistor 200. In this configuration, when a negative potential is maintained at the second gate of the transistor 200, the voltage between the first gate and the source of the transistor 400 and the voltage between the second gate and the source of the transistor 400 are 0 V. Because the drain current of the transistor 400 is very small when the second gate voltage and the first gate voltage are 0 V, the negative potential of the second gate of the transistor 200 can be maintained for a long time even without power supply to the transistors 200 and 400. This allows a memory device including the transistor 200 and the transistor 400 to retain stored content for a long time.

[0359] 15 , the wiring 1001 is electrically connected to the source of the transistor 300, and the wiring 1002 is electrically connected to the drain of the transistor 300. The wiring 1003 is electrically connected to one of the source and drain of the transistor 200, the wiring 1004 is electrically connected to the gate of the transistor 200, and the wiring 1006 is electrically connected to the second gate of the transistor 200. The gate of the transistor 300 and the other of the source and drain of the transistor 200 are electrically connected to one electrode of the capacitor 100, and the wiring 1005 is electrically connected to the other electrode of the capacitor 100. The wiring 1007 is electrically connected to the source of the transistor 400, the wiring 1008 is electrically connected to the gate of the transistor 400, the wiring 1009 is electrically connected to the second gate of the transistor 400, and the wiring 1010 is electrically connected to the drain of the transistor 400. Here, the wiring 1006, the wiring 1007, the wiring 1008, and the wiring 1009 are electrically connected.

[0360] 15 can be arranged in a matrix to form a memory cell array, similar to the memory device shown in FIG. 14. Note that one transistor 400 can control the second gate voltages of multiple transistors 200. Therefore, it is preferable to provide fewer transistors 400 than transistors 200.

[0361] <Transistor 400> The transistor 400 is formed in the same layer as the transistor 200 and can be fabricated in parallel with the transistor 200. The transistor 400 includes a conductor 460 (conductor 460a and conductor 460b) functioning as a first gate, a conductor 405 functioning as a second gate, an insulator 222, an insulator 224, and an insulator 450 functioning as gate insulating layers, an oxide 430c having a channel formation region, a conductor 442a, an oxide 431a, and an oxide 431b functioning as a source, a conductor 442b, an oxide 432a, and an oxide 432b functioning as a drain, a conductor 440 (conductor 440a and conductor 440b) functioning as a plug, and an insulator 441 (insulator 441a and insulator 441b) functioning as a barrier insulating film of the conductor 440.

[0362] The conductor 405 and the conductor 205 are formed in the same layer. The oxide 431a, the oxide 432a, and the oxide 230a are formed in the same layer, and the oxide 431b, the oxide 432b, and the oxide 230b are formed in the same layer. The conductor 442a, the conductor 442b, and the conductor 242 are formed in the same layer. The oxide 430c and the oxide 230c are formed in the same layer. The insulator 450 and the insulator 250 are formed in the same layer. The conductor 460 and the conductor 260 are formed in the same layer. The conductor 440 and the conductor 240 are formed in the same layer. The insulator 441 and the insulator 241 are formed in the same layer.

[0363] Note that structures formed in the same layer can be formed simultaneously. For example, oxide 430c can be formed by processing the oxide film that will become oxide 230c.

[0364] The oxide 430c functioning as an active layer of the transistor 400 has reduced oxygen vacancies and reduced impurities such as hydrogen and water, similar to the oxide 230. As a result, the threshold voltage of the transistor 400 can be increased, the off-state current can be reduced, and the drain current when the second gate voltage and the first gate voltage are 0 V can be made very small.

[0365] <Dicing line> The following describes dicing lines (sometimes called scribe lines, dividing lines, or cutting lines) that are provided when dividing a large-area substrate into individual semiconductor elements to extract multiple semiconductor devices in chip form. As a dividing method, for example, first, grooves (dicing lines) for dividing the semiconductor elements are formed in the substrate, and then the substrate is cut along the dicing lines to divide (divide) the multiple semiconductor devices.

[0366] 15, for example, it is preferable to design the area where the insulator 254 and the insulator 222 contact each other to be a dicing line. That is, openings are provided in the insulator 224 near areas that will become dicing lines provided on the outer edges of the memory cell having multiple transistors 200 and the transistor 400. Furthermore, the insulator 254 is provided so as to cover the side surfaces of the insulator 224.

[0367] That is, the insulator 222 and the insulator 254 contact each other through the opening formed in the insulator 224. For example, the insulator 222 and the insulator 254 may be formed using the same material and the same method. By forming the insulator 222 and the insulator 254 using the same material and the same method, adhesion can be improved. For example, it is preferable to use aluminum oxide.

[0368] With this structure, the insulator 224, the transistor 200, and the transistor 400 can be enclosed by the insulator 222 and the insulator 254. The insulator 222 and the insulator 254 have a function of suppressing diffusion of oxygen, hydrogen, and water. Therefore, even when the substrate is divided into multiple chips by dividing the substrate into each circuit region in which the semiconductor element described in this embodiment is formed, impurities such as hydrogen and water can be prevented from entering from the side surface of the divided substrate and diffusing into the transistor 200 and the transistor 400.

[0369] Furthermore, this structure can prevent excess oxygen in the insulator 224 from diffusing to the outside through the insulator 254 and the insulator 222. Therefore, the excess oxygen in the insulator 224 is efficiently supplied to the oxide in which a channel is formed in the transistor 200 or the transistor 400. The oxygen can reduce oxygen vacancies in the oxide in which a channel is formed in the transistor 200 or the transistor 400. This allows the oxide in which a channel is formed in the transistor 200 or the transistor 400 to be an oxide semiconductor with a low density of defect states and stable characteristics. That is, fluctuations in the electrical characteristics of the transistor 200 or the transistor 400 can be suppressed and reliability can be improved.

[0370] The structures, methods, and the like described in this embodiment mode can be used in appropriate combination with structures, methods, and the like described in other embodiment modes, examples, and the like.

[0371] (Embodiment 3) 16A and 16B and 17A to 17H , a transistor including an oxide as a semiconductor (hereinafter also referred to as an OS transistor) and a memory device including a capacitor (hereinafter also referred to as an OS memory device) according to one embodiment of the present invention will be described. The OS memory device is a memory device including at least a capacitor and an OS transistor that controls charging and discharging of the capacitor. Because the off-state current of the OS transistor is extremely small, the OS memory device has excellent retention characteristics and can function as a nonvolatile memory.

[0372] <Storage device configuration example> 16A shows an example of the configuration of an OS memory device. The memory device 1400 includes a peripheral circuit 1411 and a memory cell array 1470. The peripheral circuit 1411 includes a row circuit 1420, a column circuit 1430, an output circuit 1440, and a control logic circuit 1460.

[0373] The column circuit 1430 includes, for example, a column decoder, a precharge circuit, a sense amplifier, a write circuit, etc. The precharge circuit has a function of precharging the wiring. The sense amplifier has a function of amplifying a data signal read from a memory cell. Note that the above wiring is connected to a memory cell in the memory cell array 1470, and will be described in detail later. The amplified data signal is output to the outside of the memory device 1400 as a data signal RDATA via the output circuit 1440. The row circuit 1420 also includes, for example, a row decoder, a word line driver circuit, etc., and can select a row to access.

[0374] The memory device 1400 is supplied with a low power supply voltage (VSS) from the outside as power supply voltages, a high power supply voltage (VDD) for the peripheral circuit 1411, and a high power supply voltage (VIL) for the memory cell array 1470. Control signals (CE, WE, RE), an address signal ADDR, and a data signal WDATA are also input from the outside to the memory device 1400. The address signal ADDR is input to a row decoder and a column decoder, and the data signal WDATA is input to a write circuit.

[0375] The control logic circuit 1460 processes control signals (CE, WE, RE) input from the outside to generate control signals for the row decoder and column decoder. The control signal CE is a chip enable signal, the control signal WE is a write enable signal, and the control signal RE is a read enable signal. The signals processed by the control logic circuit 1460 are not limited to these, and other control signals may be input as needed.

[0376] The memory cell array 1470 has a plurality of memory cells MC arranged in a matrix and a plurality of wirings. The number of wirings connecting the memory cell array 1470 and the row circuit 1420 is determined by the configuration of the memory cells MC, the number of memory cells MC in one column, etc. The number of wirings connecting the memory cell array 1470 and the column circuit 1430 is determined by the configuration of the memory cells MC, the number of memory cells MC in one row, etc.

[0377] 16A shows an example in which the peripheral circuit 1411 and the memory cell array 1470 are formed on the same plane, but the present embodiment is not limited to this. For example, as shown in FIG. 16B, the memory cell array 1470 may be provided so as to overlap a part of the peripheral circuit 1411. For example, a sense amplifier may be provided so as to overlap the memory cell array 1470 below.

[0378] 17A to 17H will be used to explain examples of the configuration of a memory cell that can be applied to the above-described memory cell MC.

[0379] [DOSRAM] 17A to 17C show circuit configuration examples of a DRAM memory cell. In this specification and the like, a DRAM using a memory cell with one OS transistor and one capacitor may be referred to as a DOSRAM (Dynamic Oxide Semiconductor Random Access Memory). The memory cell 1471 shown in FIG. 17A includes a transistor M1 and a capacitor CA. The transistor M1 includes a gate (sometimes referred to as a top gate) and a back gate.

[0380] The first terminal of the transistor M1 is connected to the first terminal of the capacitance element CA, the second terminal of the transistor M1 is connected to the wiring BIL, the gate of the transistor M1 is connected to the wiring WOL, the back gate of the transistor M1 is connected to the wiring BGL, and the second terminal of the capacitance element CA is connected to the wiring CAL.

[0381] The wiring BIL functions as a bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitor CA. When writing and reading data, it is preferable to apply a low-level potential to the wiring CAL. The wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M1. The threshold voltage of the transistor M1 can be increased or decreased by applying an arbitrary potential to the wiring BGL.

[0382] 17A corresponds to the memory device shown in FIG. 14. That is, the transistor M1 corresponds to the transistor 200, the capacitor CA corresponds to the capacitor 100, the wiring BIL corresponds to the wiring 1003, the wiring WOL corresponds to the wiring 1004, the wiring BGL corresponds to the wiring 1006, and the wiring CAL corresponds to the wiring 1005. Note that the transistor 300 shown in FIG. 14 corresponds to a transistor provided in the peripheral circuit 1411 of the memory device 1400 shown in FIG. 16B.

[0383] The memory cell MC is not limited to the memory cell 1471, and the circuit configuration can be changed. For example, the memory cell MC may be configured such that the back gate of the transistor M1 is connected to the wiring WOL instead of the wiring BGL, as in the memory cell 1472 shown in FIG. 17B. Furthermore, for example, the memory cell MC may be configured as a memory cell including a single-gate transistor, i.e., a transistor M1 without a back gate, as in the memory cell 1473 shown in FIG. 17C.

[0384] When the semiconductor device described in the above embodiment is used for the memory cell 1471 or the like, the transistor 200 can be used as the transistor M1 and the capacitor 100 can be used as the capacitor CA. By using an OS transistor as the transistor M1, the leakage current of the transistor M1 can be made very small. That is, written data can be held by the transistor M1 for a long time, so that the frequency of refreshing the memory cell can be reduced. Alternatively, the refresh operation of the memory cell can be made unnecessary. Furthermore, because the leakage current is very small, multilevel data or analog data can be held in the memory cell 1471, the memory cell 1472, and the memory cell 1473.

[0385] Furthermore, in the DOSRAM, if the sense amplifier is configured to overlap under the memory cell array 1470 as described above, the bit line can be shortened, which reduces the bit line capacitance and the storage capacitance of the memory cell.

[0386] [NOSRAM] 17D to 17G show circuit configuration examples of a gain cell type memory cell with two transistors and one capacitor. The memory cell 1474 shown in FIG. 17D includes a transistor M2, a transistor M3, and a capacitor CB. The transistor M2 has a top gate (sometimes simply referred to as a gate) and a back gate. In this specification and the like, a memory device having a gain cell type memory cell using an OS transistor as the transistor M2 may be referred to as a nonvolatile oxide semiconductor RAM (NOSRAM).

[0387] The first terminal of transistor M2 is connected to the first terminal of capacitor CB, the second terminal of transistor M2 is connected to wiring WBL, the gate of transistor M2 is connected to wiring WOL, and the back gate of transistor M2 is connected to wiring BGL. The second terminal of capacitor CB is connected to wiring CAL. The first terminal of transistor M3 is connected to wiring RBL, the second terminal of transistor M3 is connected to wiring SL, and the gate of transistor M3 is connected to the first terminal of capacitor CB.

[0388] The wiring WBL functions as a write bit line, the wiring RBL functions as a read bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitance element CB. When writing data, while retaining data, and when reading data, it is preferable to apply a low-level potential to the wiring CAL. The wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M2. By applying an arbitrary potential to the wiring BGL, the threshold voltage of the transistor M2 can be increased or decreased.

[0389] 17D corresponds to the memory device shown in Fig. 14. That is, the transistor M2 corresponds to the transistor 200, the capacitor CB corresponds to the capacitor 100, the transistor M3 corresponds to the transistor 300, the wiring WBL corresponds to the wiring 1003, the wiring WOL corresponds to the wiring 1004, the wiring BGL corresponds to the wiring 1006, the wiring CAL corresponds to the wiring 1005, the wiring RBL corresponds to the wiring 1002, and the wiring SL corresponds to the wiring 1001.

[0390] Furthermore, the memory cell MC is not limited to the memory cell 1474, and the circuit configuration can be changed as appropriate. For example, the memory cell MC may be configured such that the back gate of the transistor M2 is connected to the wiring WOL instead of the wiring BGL, as in the memory cell 1475 shown in FIG. 17E. Furthermore, for example, the memory cell MC may be configured as a memory cell including a transistor with a single gate structure, that is, a transistor M2 without a back gate, as in the memory cell 1476 shown in FIG. 17F. Furthermore, for example, the memory cell MC may be configured such that the wiring WBL and the wiring RBL are combined into a single wiring BIL, as in the memory cell 1477 shown in FIG. 17G.

[0391] When the semiconductor device described in the above embodiment is used for the memory cell 1474 or the like, the transistor 200 can be used as the transistor M2, the transistor 300 can be used as the transistor M3, and the capacitor CB can be used as the capacitor CB. By using an OS transistor as the transistor M2, the leakage current of the transistor M2 can be significantly reduced. This allows written data to be held by the transistor M2 for a long time, thereby reducing the frequency of refreshing the memory cell. Alternatively, the refresh operation of the memory cell can be eliminated. Furthermore, since the leakage current is extremely small, multilevel data or analog data can be held in the memory cell 1474. The same applies to the memory cells 1475 to 1477.

[0392] Note that the transistor M3 may be a transistor having silicon in a channel formation region (hereinafter, may be referred to as a Si transistor). The conductivity type of the Si transistor may be either an n-channel type or a p-channel type. The Si transistor may have higher field-effect mobility than an OS transistor. Therefore, a Si transistor may be used as the transistor M3 functioning as a read transistor. Furthermore, by using a Si transistor as the transistor M3, the transistor M2 can be stacked on top of the transistor M3, thereby reducing the area occupied by the memory cell and achieving higher integration of the memory device.

[0393] Furthermore, the transistor M3 may be an OS transistor. When OS transistors are used for the transistors M2 and M3, the memory cell array 1470 can be configured as a circuit using only n-type transistors.

[0394] 17H shows an example of a gain cell type memory cell with three transistors and one capacitor. The memory cell 1478 shown in FIG. 17H includes transistors M4 to M6 and a capacitor CC. The capacitor CC is provided as appropriate. The memory cell 1478 is electrically connected to wirings BIL, RWL, WWL, BGL, and GNDL. The GNDL wiring is a wiring that applies a low-level potential. Note that the memory cell 1478 may be electrically connected to wirings RBL and WBL instead of wiring BIL.

[0395] The transistor M4 is an OS transistor having a back gate, and the back gate is electrically connected to the wiring BGL. Note that the back gate and the gate of the transistor M4 may be electrically connected to each other. Alternatively, the transistor M4 does not necessarily have a back gate.

[0396] Note that the transistors M5 and M6 may be n-channel Si transistors or p-channel Si transistors, or the transistors M4 to M6 may be OS transistors. In this case, the memory cell array 1470 can be configured as a circuit using only n-channel transistors.

[0397] When the semiconductor device described in the above embodiment is used in the memory cell 1478, the transistor 200 can be used as the transistor M4, the transistors M5 and M6 can be used as the transistors M5 and M6, and the capacitor 100 can be used as the capacitor CC. By using an OS transistor as the transistor M4, the leakage current of the transistor M4 can be made extremely small.

[0398] Note that the configurations of the peripheral circuit 1411, the memory cell array 1470, and the like shown in this embodiment are not limited to those described above. The arrangement or functions of these circuits, and wirings, circuit elements, and the like connected to the circuits may be changed, deleted, or added as necessary.

[0399] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiment modes, examples, and the like.

[0400] (Fourth embodiment) 18A and 18B, an example of a chip 1200 on which a semiconductor device of the present invention is mounted is shown. A plurality of circuits (systems) are mounted on the chip 1200. A technology for integrating a plurality of circuits (systems) on a single chip in this manner is sometimes called a system on chip (SoC).

[0401] As shown in FIG. 18A, a chip 1200 includes a CPU 1211, a GPU 1212, one or more analog arithmetic units 1213, one or more memory controllers 1214, one or more interfaces 1215, one or more network circuits 1216, and the like.

[0402] 18B, the chip 1200 is provided with bumps (not shown), which are connected to a first surface of a printed circuit board (PCB) 1201. In addition, a plurality of bumps 1202 are provided on the backside of the first surface of the PCB 1201, which is connected to a motherboard 1203.

[0403] The motherboard 1203 may be provided with storage devices such as a DRAM 1221 and a flash memory 1222. For example, the DOSRAM described in the previous embodiment may be used as the DRAM 1221. Also, for example, the NOSRAM described in the previous embodiment may be used as the flash memory 1222.

[0404] The CPU 1211 preferably has multiple CPU cores. The GPU 1212 preferably has multiple GPU cores. The CPU 1211 and the GPU 1212 may each have a memory for temporarily storing data. Alternatively, a memory common to the CPU 1211 and the GPU 1212 may be provided on the chip 1200. The memory may be the NOSRAM or DOSRAM described above. The GPU 1212 is suitable for parallel calculation of a large amount of data and can be used for image processing and multiply-and-accumulate operations. By providing the GPU 1212 with an image processing circuit or a multiply-and-accumulate circuit using the oxide semiconductor of the present invention, it becomes possible to perform image processing and multiply-and-accumulate operations with low power consumption.

[0405] Furthermore, by providing the CPU 1211 and GPU 1212 on the same chip, the wiring between the CPU 1211 and GPU 1212 can be shortened, enabling high-speed data transfer from the CPU 1211 to the GPU 1212, data transfer between the memories of the CPU 1211 and GPU 1212, and transfer of the calculation results from the GPU 1212 to the CPU 1211 after calculation in the GPU 1212.

[0406] The analog calculation unit 1213 has one or both of an A / D (analog / digital) conversion circuit and a D / A (digital / analog) conversion circuit. The analog calculation unit 1213 may also be provided with the above-mentioned product-sum calculation circuit.

[0407] The memory controller 1214 has a circuit that functions as a controller for the DRAM 1221 and a circuit that functions as an interface for the flash memory 1222 .

[0408] The interface 1215 has an interface circuit with externally connected devices such as a display device, speaker, microphone, camera, and controller. Controllers include a mouse, keyboard, game controller, etc. As such an interface, a USB (Universal Serial Bus), HDMI (registered trademark) (High-Definition Multimedia Interface), etc. can be used.

[0409] The network circuit 1216 includes a circuit for a network such as a LAN (Local Area Network), and may also include a circuit for network security.

[0410] The above circuits (systems) can be formed in the same manufacturing process on the chip 1200. Therefore, even if the number of circuits required for the chip 1200 increases, there is no need to increase the manufacturing process, and the chip 1200 can be manufactured at low cost.

[0411] A PCB 1201 on which a chip 1200 having a GPU 1212 is provided, a motherboard 1203 on which a DRAM 1221 and a flash memory 1222 are provided can be called a GPU module 1204.

[0412] The GPU module 1204 includes the chip 1200 using SoC technology, allowing for a small size. Furthermore, due to its superior image processing capabilities, it is suitable for use in portable electronic devices such as smartphones, tablet devices, laptop PCs, and portable (portable) game consoles. Furthermore, a multiply-and-accumulate circuit using the GPU 1212 can execute techniques such as deep neural networks (DNNs), convolutional neural networks (CNNs), recurrent neural networks (RNNs), autoencoders, deep Boltzmann machines (DBMs), and deep belief networks (DBNs). Therefore, the chip 1200 can be used as an AI chip, and the GPU module 1204 can be used as an AI system module.

[0413] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiment modes, examples, and the like.

[0414] (Embodiment 5) In this embodiment, an application example of a storage device using the semiconductor device described in the previous embodiment will be described. The semiconductor device described in the previous embodiment can be applied to storage devices of various electronic devices (e.g., information terminals, computers, smartphones, e-book readers, digital cameras (including video cameras), recording / playback devices, navigation systems, etc.). Note that the term "computer" here refers to a tablet computer, a notebook computer, a desktop computer, and a large-scale computer such as a server system. Alternatively, the semiconductor device described in the previous embodiment can be applied to various removable storage devices such as memory cards (e.g., SD cards), USB memories, and SSDs (solid-state drives). FIGS. 19A to 19E schematically show several configuration examples of removable storage devices. For example, the semiconductor device described in the previous embodiment can be processed into a packaged memory chip and used in various storage devices and removable memories.

[0415] 19A is a schematic diagram of a USB memory. The USB memory 1100 has a housing 1101, a cap 1102, a USB connector 1103, and a board 1104. The board 1104 is housed in the housing 1101. For example, a memory chip 1105 and a controller chip 1106 are attached to the board 1104. The semiconductor device described in the above embodiment can be incorporated into the memory chip 1105 or the like.

[0416] FIG. 19B is a schematic diagram of the appearance of an SD card, and FIG. 19C is a schematic diagram of the internal structure of the SD card. The SD card 1110 has a housing 1111, a connector 1112, and a substrate 1113. The substrate 1113 is housed in the housing 1111. For example, a memory chip 1114 and a controller chip 1115 are attached to the substrate 1113. The capacity of the SD card 1110 can be increased by providing a memory chip 1114 on the back side of the substrate 1113. Furthermore, a wireless chip with a wireless communication function may be provided on the substrate 1113. This enables reading and writing of data from and to the memory chip 1114 through wireless communication between a host device and the SD card 1110. The semiconductor device described in the above embodiment can be incorporated into the memory chip 1114 or the like.

[0417] FIG. 19D is a schematic diagram of the appearance of an SSD, and FIG. 19E is a schematic diagram of the internal structure of the SSD. SSD 1150 has a housing 1151, a connector 1152, and a board 1153. Board 1153 is housed in housing 1151. For example, memory chips 1154, 1155, and a controller chip 1156 are attached to board 1153. Memory chip 1155 is a work memory for controller chip 1156, and may be a DOSRAM chip, for example. By providing a memory chip 1154 on the back side of board 1153, the capacity of SSD 1150 can be increased. The semiconductor device described in the previous embodiment can be incorporated into memory chip 1154 or the like.

[0418] This embodiment mode can be implemented in appropriate combination with structures described in other embodiment modes, examples, and the like.

[0419] (Sixth embodiment) A semiconductor device according to one embodiment of the present invention can be used in a processor such as a CPU or a GPU, or a chip. Specific examples of electronic devices including a processor such as a CPU or a GPU, or a chip according to one embodiment of the present invention are shown in FIGS.

[0420] <Electronic devices and systems> A GPU or chip according to one embodiment of the present invention can be mounted in various electronic devices. Examples of such electronic devices include electronic devices with relatively large screens, such as televisions, monitors for desktop or notebook information terminals, digital signage, and large game machines such as pachinko machines, as well as digital cameras, digital video cameras, digital photo frames, e-book readers, mobile phones, portable game machines, personal digital assistants, and audio playback devices. Furthermore, by providing an electronic device with a GPU or chip according to one embodiment of the present invention, it is possible to equip the electronic device with artificial intelligence.

[0421] The electronic device of one embodiment of the present invention may include an antenna. By receiving a signal through the antenna, images, information, and the like can be displayed on a display portion. When the electronic device includes an antenna and a secondary battery, the antenna may be used for contactless power transmission.

[0422] An electronic device according to one embodiment of the present invention may have a sensor (including a function for measuring force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared rays).

[0423] An electronic device of one embodiment of the present invention can have various functions. For example, it can have a function of displaying various information (still images, videos, text images, etc.) on a display unit, a touch panel function, a function of displaying a calendar, date, time, etc., a function of executing various software (programs), a wireless communication function, a function of reading programs or data recorded on a recording medium, etc. Examples of electronic devices are shown in FIGS. 20A to 20H.

[0424] [Information terminal] 20A shows a mobile phone (smartphone), which is one type of information terminal. The information terminal 5100 has a housing 5101 and a display unit 5102. As input interfaces, a touch panel is provided on the display unit 5102 and buttons are provided on the housing 5101.

[0425] By applying the chip of one embodiment of the present invention, the information terminal 5100 can execute applications using artificial intelligence. Examples of applications using artificial intelligence include an application that recognizes a conversation and displays the conversation content on the display portion 5102, an application that recognizes characters, figures, and the like input by a user to a touch panel provided in the display portion 5102 and displays them on the display portion 5102, and an application that performs biometric authentication such as fingerprint or voiceprint authentication.

[0426] 20B illustrates a notebook information terminal 5200. The notebook information terminal 5200 includes a main body 5201 of the information terminal, a display unit 5202, and a keyboard 5203.

[0427] The notebook information terminal 5200 can execute applications using artificial intelligence by applying a chip of one embodiment of the present invention, similar to the information terminal 5100 described above. Examples of applications using artificial intelligence include design support software, text correction software, and automatic menu generation software. Furthermore, new artificial intelligence can be developed by using the notebook information terminal 5200.

[0428] 20A and 20B, a smartphone and a notebook type information terminal are used as examples of electronic devices, but information terminals other than smartphones and notebook type information terminals can also be used. Examples of information terminals other than smartphones and notebook type information terminals include PDAs (Personal Digital Assistants), desktop type information terminals, and workstations.

[0429] [Game consoles] FIG. 20C illustrates a portable game console 5300, which is an example of a game console. The portable game console 5300 includes a housing 5301, a housing 5302, a housing 5303, a display unit 5304, a connection unit 5305, operation keys 5306, and the like. The housing 5302 and the housing 5303 can be detached from the housing 5301. By attaching the connection unit 5305 of the housing 5301 to another housing (not shown), the video displayed on the display unit 5304 can be output to another video device (not shown). In this case, the housing 5302 and the housing 5303 can each function as an operation unit. This allows multiple players to play a game at the same time. The chips described in the above embodiments can be incorporated into the substrates of the housings 5301, 5302, and 5303.

[0430] 20D shows an example of a game machine, a stationary game machine 5400. A controller 5402 is connected to the stationary game machine 5400 wirelessly or via a wire.

[0431] A game machine with low power consumption can be realized by applying a GPU or a chip of one embodiment of the present invention to a game machine such as a portable game machine 5300 or a stationary game machine 5400. Furthermore, low power consumption can reduce heat generation from a circuit, thereby reducing the influence of heat on the circuit itself, peripheral circuits, and modules.

[0432] Furthermore, by applying the GPU or chip of one embodiment of the present invention to the portable game console 5300, the portable game console 5300 can have artificial intelligence.

[0433] Originally, the expression of the progress of a game, the behavior of creatures appearing in the game, and phenomena occurring in the game are determined by the program of the game, but by applying artificial intelligence to the portable game console 5300, it becomes possible to express things that are not limited to the game program. For example, it becomes possible to express things such as changes in the questions asked by the player, the progress of the game, the time, and the behavior of people appearing in the game.

[0434] Furthermore, when playing a game requiring multiple players on the portable game console 5300, the game players can be personified using artificial intelligence, so that the game can be played by one person by making the opponent a game player based on artificial intelligence.

[0435] 20C and 20D illustrate a portable game machine and a stationary game machine as examples of game machines, but game machines to which the GPU or chip of one embodiment of the present invention is applied are not limited to these. Examples of game machines to which the GPU or chip of one embodiment of the present invention is applied include arcade game machines installed in entertainment facilities (game centers, amusement parks, etc.) and pitching machines for batting practice installed in sports facilities.

[0436] [Mainframe Computer] The GPU or chip according to one embodiment of the present invention can be applied to a mainframe computer.

[0437] 20E is a diagram showing a supercomputer 5500, which is an example of a mainframe computer. FIG. 20F is a diagram showing a rack-mounted computer 5502 included in the supercomputer 5500.

[0438] The supercomputer 5500 includes a rack 5501 and a plurality of rack-mounted computers 5502. The plurality of computers 5502 are stored in the rack 5501. The computer 5502 is provided with a plurality of boards 5504, and the GPU or chip described in the above embodiment can be mounted on the boards.

[0439] The supercomputer 5500 is a large-scale computer primarily used for scientific and technological calculations. Scientific and technological calculations require high-speed processing of enormous amounts of calculations, resulting in high power consumption and large amounts of heat generated by the chip. By applying a GPU or chip according to one embodiment of the present invention to the supercomputer 5500, a supercomputer with low power consumption can be realized. Furthermore, low power consumption can reduce heat generation from circuits, thereby reducing the impact of heat generation on the circuits themselves, peripheral circuits, and modules.

[0440] 20E and 20F illustrate a supercomputer as an example of a mainframe computer, but the mainframe computer to which the GPU or chip of one embodiment of the present invention is applied is not limited to this. Examples of the mainframe computer to which the GPU or chip of one embodiment of the present invention is applied include a computer (server) that provides services, a large general-purpose computer (mainframe), etc.

[0441] [Moving object] The GPU or chip according to one embodiment of the present invention can be applied to automobiles, which are moving objects, and to the area around the driver's seat of an automobile.

[0442] Fig. 20G is a diagram showing the area around the windshield inside the interior of an automobile, which is an example of a moving body, showing display panel 5701, display panel 5702, and display panel 5703 attached to the dashboard, as well as display panel 5704 attached to a pillar.

[0443] The display panels 5701 to 5703 can provide various information by displaying a speedometer, a tachometer, a mileage, a fuel gauge, a gear state, air conditioning settings, etc. The display items and layouts displayed on the display panels can be changed as appropriate to suit the user's preferences, allowing for improved design. The display panels 5701 to 5703 can also be used as lighting devices.

[0444] The display panel 5704 can complement the view (blind spot) blocked by the pillar by displaying an image from an imaging device (not shown) installed in the vehicle. That is, by displaying an image from an imaging device installed outside the vehicle, blind spots can be complemented and safety can be improved. Furthermore, by displaying an image that complements the invisible part, safety can be confirmed more naturally and without discomfort. The display panel 5704 can also be used as a lighting device.

[0445] Since the GPU or chip of one embodiment of the present invention can be used as a component of artificial intelligence, the chip can be used, for example, in an automatic driving system for automobiles. The chip can also be used in a system that provides road guidance, hazard prediction, etc. The display panels 5701 to 5704 may be configured to display information such as road guidance and hazard prediction.

[0446] Although an automobile is described above as an example of a moving body, the moving body is not limited to an automobile. For example, moving bodies can include trains, monorails, ships, and flying bodies (helicopters, unmanned aerial vehicles (drones), airplanes, and rockets), and the chip of one embodiment of the present invention can be applied to these moving bodies to provide a system using artificial intelligence.

[0447] [electric appliances] 20H shows an example of an electric appliance, an electric refrigerator-freezer 5800. The electric refrigerator-freezer 5800 includes a housing 5801, a refrigerator door 5802, a freezer door 5803, and the like.

[0448] The electric refrigerator-freezer 5800 having artificial intelligence can be realized by applying the chip of one embodiment of the present invention to the electric refrigerator-freezer 5800. By using artificial intelligence, the electric refrigerator-freezer 5800 can have a function of automatically generating a menu based on ingredients stored in the electric refrigerator-freezer 5800 and their expiration dates, a function of automatically adjusting the temperature to match the ingredients stored in the electric refrigerator-freezer 5800, and the like.

[0449] Although electric refrigerator-freezers have been described as an example of electrical appliances, other electrical appliances include, for example, vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, induction cookers, water dispensers, heating and cooling appliances including air conditioners, washing machines, dryers, and audio-visual equipment.

[0450] The electronic devices, functions of the electronic devices, application examples of artificial intelligence, and effects thereof described in this embodiment can be appropriately combined with descriptions of other electronic devices.

[0451] This embodiment mode can be implemented in appropriate combination with structures described in other embodiment modes, examples, and the like. [Example]

[0452] In this example, a plurality of transistors 200 including an oxide semiconductor shown in FIGS. 1A to 1D were fabricated in the same process, and the transistor characteristics were measured and the variations in the transistor characteristics were evaluated.

[0453] 1A to 1D is a semiconductor device including the transistor 200. The semiconductor device fabricated as the sample includes 161 transistors fabricated through the same process. In Sample 1A, the design values ​​of the channel length and the channel width were each 60 nm.

[0454] Sample 1A will be described below.

[0455] In sample 1A, oxide 230a was formed by sputtering an In-Ga-Zn oxide film using an oxide target with an atomic ratio of In:Ga:Zn=1:3:4. Oxide 230b was formed by sputtering an In-Ga-Zn oxide film using an oxide target with an atomic ratio of In:Ga:Zn=4:2:4.1. The films that became oxide 230a and oxide 230b were formed by successive deposition.

[0456] In addition, oxide 230c was formed by a laminated structure of an In-Ga-Zn oxide film formed by sputtering using an oxide target with an atomic ratio of In:Ga:Zn=4:2:4.1, and an In-Ga-Zn oxide film formed by sputtering using an oxide target with an atomic ratio of In:Ga:Zn=1:3:4.

[0457] The conductor 242 was formed using a tantalum nitride film, and the insulator 250 was formed using a silicon oxynitride film.

[0458] The conductor 260a was formed using a titanium nitride film, and the conductor 260b was formed using a tungsten film. The film that became the conductor 260a and the film that became the conductor 260b were formed by successive film formation.

[0459] <Electrical characteristics of the transistor of Sample 1A> First, Sample 1A was subjected to heat treatment at 400°C for 4 hours in a nitrogen atmosphere. Then, the electrical characteristics of 161 transistors included in Sample 1A were measured. Note that the Id-Vg characteristics were measured by setting the drain voltage Vd to 1.2 V and varying the gate voltage Vg from -4 V to +4 V.

[0460] Here, in the Id-Vg transistor characteristics, the drain current Id = 1.0 × 10 -12 The value of the gate voltage Vg at time A was taken as the Shift value (Vsh).

[0461] 21 shows a normal probability plot of the electrical characteristics of 161 transistors in Sample 1 A. In Fig. 21, the horizontal axis represents the Shift value (Vsh) [V], and the vertical axis represents the estimated cumulative probability [%].

[0462] The estimated cumulative probability (also called cumulative relative frequency) can be calculated using the median rank method, the mean rank method, the symmetric sample cumulative distribution method, and the Kaplan-Meier method. In this example, the estimated cumulative probability was calculated using the median rank method.

[0463] As can be seen from FIG. 21, the average value of the Shift value for Sample 1A was −0.231 V and the standard deviation σ was 0.056 V.

[0464] From the above, it was found that the transistor 200 using the present invention has small variations in the electrical characteristics of the transistor.

[0465] At least a part of the configurations, methods, and the like shown in this embodiment can be implemented in appropriate combination with other embodiment modes described in this specification. [Example]

[0466] In this example, the semiconductor device shown in FIGS. 12A to 12D was fabricated, and reliability evaluation of the transistor 200 was performed. The results of investigating the stress-time dependency are described below. The reliability evaluation was performed on four transistors, Samples A to D, from one substrate. For the substrates containing Samples A to D, a 2-nm-thick oxide 243 was formed by sputtering using a target with an In:Ga:Zn=1:3:4 atomic ratio at a substrate temperature of 200°C. The substrates were subjected to heat treatment at 400°C for 8 hours in a nitrogen atmosphere. The reliability was evaluated by a +GBT (Gate Bias Temperature) stress test at a stress temperature of 150°C. The set temperature was 150°C, the drain potential Vd, the source potential Vs, and the bottom gate potential Vbg were set to 0 V, and the top gate potential Vg was set to +3.63 V. The transistor sizes of Samples A to D were all designed to have a channel length of 60 nm and a channel width of 60 nm. In this stress test, the stress time when ΔVsh exceeds ±100 mV is defined as the transistor's lifespan. Fluctuations in Ion, S value, and μFE due to stress time were also evaluated.

[0467] The results of the +GBT stress test are shown in Figure 22. In Figure 22, the horizontal axis represents the stress time (hr) and the vertical axis represents ΔVsh (mV). As shown in Figure 22, sample A had a lifespan of 1230 hours, sample B had a lifespan of 1410 hours, sample C had a lifespan of 1240 hours, and sample D had a lifespan of 1230 hours. All four samples achieved good results, with lifespans of 1200 hours or more.

[0468] It is estimated that the +GBT stress test set temperature of 150°C evaluated in this example accelerates deterioration by approximately 24 times compared to the +GBT stress test set temperature of 125°C. Therefore, the lifespan at a stress temperature of 125°C can be estimated to be 28,000 hours or more.

[0469] Fig. 23A shows the variation of Ion with stress time for samples A to D. Fig. 23B shows the variation of S value with stress time for samples A to D. Fig. 23C shows the variation of μFE with stress time for samples A to D.

[0470] Ion (A) is the Id value when Vd = +1.2V and Vg = +3.3V. The S value (mV / dec) is the Vg value required for Id to change by one digit in the subthreshold region when Vd = +1.2V. μFE (cm 2 / Vs) is a value calculated from the equation for the linear region of the gradual channel approximation.

[0471] As shown in FIGS. 23A to 23C, it was confirmed that in Samples A to D, the Ion, S value, and μFE all showed small variations due to stress time.

[0472] The above results confirm that the transistor 200 of one embodiment of the present invention has high reliability.

[0473] This embodiment can be used in appropriate combination with the configurations, structures, methods, and the like shown in other embodiment modes and embodiments. [Example]

[0474] In this example, a semiconductor device having a transistor 200 shown in FIGS. 12A to 12D was fabricated, and the transistor characteristics were measured to evaluate variations in the transistor characteristics.

[0475] The semiconductor device including the fabricated transistor 200 includes 215 transistors fabricated in the same process. The design values ​​of the channel length and the channel width were each 60 nm.

[0476] <Transistor electrical characteristics> First, the fabricated semiconductor device was subjected to heat treatment at 400°C for 8 hours in a nitrogen atmosphere. Then, the electrical characteristics of 215 transistors included in the semiconductor device were measured. For the electrical characteristics, Id-Vg characteristics were measured by setting Vd to 0.1V or 1.2V and varying Vg from -4V to +4V.

[0477] A graph of the Id-Vg characteristics of 215 transistors included in the semiconductor device is shown in Fig. 24. In Fig. 24, the horizontal axis represents Vg (V) and the vertical axis represents Id (A).

[0478] FIG. 25A shows a normal probability plot of Vsh. In FIG. 25A, the horizontal axis is Vsh (V) and the vertical axis is estimated cumulative probability (%). FIG. 25B shows a normal probability plot of Ion. In FIG. 25B, the horizontal axis is Ion (μA) and the vertical axis is estimated cumulative probability (%). FIG. 25C shows a graph of Vsh dependence on Vbg for nine transistors.

[0479] The estimated cumulative probability (also called cumulative relative frequency) can be calculated using the median rank method, the mean rank method, the symmetric sample cumulative distribution method, or the Kaplan-Meier method. In this example, the estimated cumulative probability was calculated using the median rank method.

[0480] FIG. 24 shows the Id-Vg characteristics of each of the 215 transistors superimposed on one another.

[0481] From FIG. 25A, the standard deviation σ of Vsh of the 215 transistors was about 64 mV.

[0482] From FIG. 25B, the average value of Ion for 215 transistors was approximately 7.78 μA, and the standard deviation σ was approximately 6.71 μA.

[0483] From the above, it was confirmed that the transistor 200 using one embodiment of the present invention has good electrical characteristics with small variations in the electrical characteristics. It was also confirmed that Vsh can be controlled by Vbg.

[0484] At least a part of the configurations, methods, and the like shown in this embodiment can be implemented in appropriate combination with other embodiment modes and other embodiments described in this specification. [Example]

[0485] In this example, reliability was evaluated for two transistors (element A and element B) of the semiconductor device having the transistor 200 used in Example 2.

[0486] <Transistor reliability> The reliability was evaluated by a +GBT stress test. In the +GBT stress test according to this example, the set temperature was 150° C., Vd=Vs=Vbg=0 V, and Vg=+3.63 V. Vs is the drain potential, and Vbg is the bottom gate potential.

[0487] Id-Vg measurements were taken at regular intervals during the +GBT stress test. The Id-Vg measurements were performed by sweeping Vg from -3.3V to +3.3V with the transistor's Vd = 1.2V, Vs = 0V, and Vbg = 0V. A Keysight Technologies semiconductor parameter analyzer was used for the Id-Vg measurements. In the +GBT stress test, ΔVsh, which represents the change in Vsh from the start of the measurement, was used as an indicator of the amount of change in the transistor's electrical characteristics. The change in the S value due to stress time was also evaluated.

[0488] Figure 26A shows the results of the +GBT stress test on Device A and Device B. In Figure 26A, the horizontal axis represents stress time (hr) and the vertical axis represents ΔVsh (mV).

[0489] 26A, the change in shift voltage ΔVsh was less than 100 mV even after 490 hours under the stress conditions for both Device A and Device B. Specifically, for Device A, ΔVsh after 490 hours was −16 mV, and for Device B, ΔVsh after 490 hours was −23 mV.

[0490] 26B shows the changes in the S value during the +GBT stress test for Device A and Device B. In Fig. 26B, the horizontal axis represents stress time (hr) and the vertical axis represents the S value (mV / dec).

[0491] As shown in FIG. 26B, even after 490 hours of application of the above stress to Device A and Device B, the fluctuation in the S value did not exceed the range of 100 mV / dec to 140 mV / dec.

[0492] The above results confirm that the transistor 200 using one embodiment of the present invention has high reliability.

[0493] At least a part of the configurations, methods, and the like shown in this embodiment can be implemented in appropriate combination with other embodiment modes and other embodiments described in this specification. [Explanation of symbols]

[0494] :100: Capacitor, 110: Conductor, 112: Conductor, 120: Conductor, 130: Insulator, 150: Insulator, 200: Transistor, 200_1: Transistor, 200_2: Transistor, 200_n: Transistor, 205: Conductor, 205a: Conductor, 205b: Conductor, 210: Insulator, 212: Insulator, 214: Insulator, 216: Insulator, 217: Insulator, 218: Conductor, 222: Insulator, 224: Insulator, 230: Oxide, 230a: Oxide, 230A: Oxide film, 230b: Oxide, 230B: Oxide film, 230c: Oxide, 230c1: Oxide, 230c2: oxide, 230C: oxide film, 231: region, 231a: region, 231b: region, 234: region, 240: conductor, 240a: conductor, 240b: conductor, 241: insulator, 241a: insulator, 241b: insulator, 242: conductor, 242a: conductor, 242A: conductive film, 242b: conductor, 242B: conductive layer, 243: oxide, 243a: oxide, 243b: oxide, 246: conductor, 246a: conductor, 246b: conductor, 250: insulator, 250A: insulating film, 254: insulator, 254a: insulator, 254A: insulating film, 254b: insulator Edge, 260: conductor, 260a: conductor, 260A: conductive film, 260b: conductor, 260B: conductive film, 265: sealing portion, 265a: sealing portion, 265b: sealing portion, 274: insulator, 280: insulator, 281: insulator, 282: insulator, 283: insulator, 300: transistor, 311: substrate, 313: semiconductor region, 314a: low resistance region, 314b: low resistance region, 315: insulator, 316: conductor, 320: insulator, 322: insulator, 324: insulator, 326: insulator, 328: conductor, 330: conductor, 350: insulator, 352: insulator, 354: insulator body, 356: conductor, 400: transistor, 405: conductor, 430c: oxide, 431a: oxide, 431b: oxide, 432a: oxide, 432b: oxide, 440: conductor, 440a: conductor, 440b: conductor, 441: insulator, 441a: insulator, 441b: insulator, 442a: conductor, 442b: conductor, 450: insulator, 460: conductor, 460a: conductor, 460b: conductor, 1001: wiring, 1002: wiring, 1003: wiring, 1004: wiring, 1005: wiring, 1006: wiring, 1007: wiring, 1008: wiring, 1009: wiring,1010: Wiring, 1100: USB memory, 1101: Housing, 1102: Cap, 1103: USB connector, 1104: Board, 1105: Memory chip, 1106: Controller chip, 1110: SD card, 1111: Housing, 1112: Connector, 1113: Board, 1114: Memory chip, 1115: Controller chip, 1150: SSD, 1151: Housing, 1152: Connector, 1153: Board, 1154: Memory chip, 1155: Memory chip ,1156: Controller chip, 1200: Chip, 1201: PCB, 1202: Bump, 1203: Motherboard, 1204: GPU module, 1211: CPU, 1212: GPU, 1213: Analogue calculation unit, 1214: Memory controller, 1215: Interface, 1216: Network circuit, 1221: DRAM, 1222: Flash memory, 1400: Storage device, 1411: Peripheral circuit, 1420: Row circuit, 1430: Column circuit, 144 0: output circuit, 1460: control logic circuit, 1470: memory cell array, 1471: memory cell, 1472: memory cell, 1473: memory cell, 1474: memory cell, 1475: memory cell, 1476: memory cell, 1477: memory cell, 1478: memory cell, 5100: information terminal, 5101: housing, 5102: display unit, 5200: notebook information terminal, 5201: main body, 5202: display unit, 5203: keyboard, 5300: portable game console, 5301: housing, 5302: housing, 5303: housing, 5304: display unit, 5305: connection unit, 5306: operation keys, 5400: stationary game machine, 5402: controller, 5500: supercomputer, 5501: rack, 5502: calculator, 5504: circuit board, 5701: display panel, 5702: display panel, 5703: display panel, 5704: display panel, 5800: electric refrigerator-freezer, 5801: housing, 5802: refrigerator compartment door, 5803: freezer compartment door,

Claims

1. A semiconductor device having a plurality of transistors, Each of the plurality of transistors a first conductor; a first insulator; and a first metal oxide on the first insulator; a second conductor and a third conductor provided on the first metal oxide; a second metal oxide disposed on the first metal oxide and having a portion disposed between the second conductor and the third conductor; a second insulator on the second metal oxide; and a fourth conductor on the second insulator; the first metal oxide has a first portion overlapping with the first conductor and the fourth conductor, a second portion overlapping with the second conductor, and a third portion overlapping with the third conductor; a thickness of the first portion is smaller than a thickness of the second portion and a thickness of the third portion; the first metal oxide has a curved surface between a side surface and an upper surface at a portion overlapping the fourth conductor; each of the first metal oxide and the second metal oxide comprises indium; In the Id-Vg characteristics of each of the plurality of transistors, the standard deviation σ of Vsh is less than 60 mV.

2. A semiconductor device having a plurality of transistors, Each of the plurality of transistors a first conductor; a first insulator; and a first metal oxide on the first insulator; a second conductor and a third conductor provided on the first metal oxide; a second insulator on the second conductor and on the third conductor; a third insulator on the second insulator; and a second metal oxide having a portion located in an opening formed in the second insulator and the third insulator, a portion located on the first metal oxide, and a portion located between the second conductor and the third conductor; a fourth insulator on the second metal oxide; and a fourth conductor on the fourth insulator; the first metal oxide has a first portion overlapping with the first conductor and the fourth conductor, a second portion overlapping with the second conductor, and a third portion overlapping with the third conductor; a thickness of the first portion is smaller than a thickness of the second portion and a thickness of the third portion; the first metal oxide has a curved surface between a side surface and an upper surface in the first portion; The semiconductor device, wherein the first metal oxide and the second metal oxide each contain indium.

3. In claim 1 or 2, each of the plurality of transistors has a channel length of 40 nm or more and 80 nm or less; The semiconductor device, wherein each of the plurality of transistors has a channel width of 40 nm or more and 80 nm or less.

Images