Semiconductor Devices

Abstract

To provide a semiconductor device capable of realizing a capacitive element of high breakdown voltage in a small chip area.SOLUTION: A semiconductor device includes: a lower layer electrode 2; first dielectric layers (31, 32) provided on the lower layer electrode 2; a first upper layer electrode 3 provided on the first dielectric layers (31, 32); second dielectric layers (33, 34) provided on the first upper layer electrode 3; a second upper layer electrode 4 provided on the second dielectric layers (33, 34) and electrically connected to the lower layer electrode 2; and third dielectric layers (35, 36) provided on the second upper layer electrode 4; and a third upper layer electrode 5 provided on the third dielectric layers (35, 36) and electrically connected to the first upper layer electrode 3. A first capacity C1 between the lower layer electrode 2 and the first upper layer electrode 3, a second capacity C2 between the first upper layer electrode 3 and the second upper layer electrode 4, and a third capacity C3 between the second upper layer electrode 4 and the third upper layer electrode 5 are connected in parallel.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] Patent Document 1 discloses a configuration in which an RC snubber circuit is connected in parallel with a half-bridge power device that performs switching in a power conversion circuit, so that surge voltages generated during turn-off switching of the power device are absorbed by the capacitive element (snubber capacitor) of the RC snubber circuit and dissipated as heat by the resistive element of the RC snubber circuit. This RC snubber circuit is used to improve the noise resistance of power conversion circuits that handle large amounts of power by suppressing overshooting and undershooting surge voltages and ringing voltages.

[0003] In order to reduce the number of passive elements on a printed circuit board in a power conversion circuit and to incorporate them into a power module, a configuration in which a resistive element and a capacitive element are formed on a single chip has been proposed as an RC snubber circuit configuration. Patent Document 2 discloses a snubber circuit chip in which a snubber capacitor is formed by using the semiconductor substrate itself as a resistive element and burying an electrode inside a trench above the semiconductor substrate via a dielectric layer.

[0004] Patent Document 3 discloses a semiconductor snubber having a substrate region and a dielectric region formed on the substrate region, where the substrate region functions as a resistor and the dielectric region functions as a capacitor. Patent Document 4 discloses a semiconductor snubber having a drift region and a high-resistivity layer provided on the substrate region, where a capacitor dielectric region is formed in contact with the high-resistivity layer, where the substrate region, drift region, and high-resistivity layer function as resistors and the capacitor dielectric region functions as a capacitor. Patent Document 5 discloses a capacitor element having four conductive layers arranged in a stepped configuration at both ends, with a first electrode made of odd-numbered conductive layers and a second electrode made of even-numbered conductive layers. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-306692 [Patent Document 2] Patent No. 6888426 [Patent Document 3] Japanese Patent Application Laid-Open No. 2010-192827 [Patent Document 4] Japanese Patent Application Laid-Open No. 2010-206106 [Patent Document 5] Japanese Patent Application Laid-Open No. 2010-98067 Summary of the Invention [Problem to be solved by the invention]

[0006] Typically, in a high-power power conversion circuit, although this depends on the voltage of the AC power supply, a surge voltage of about 1000 V is applied when a power device is turned off and switched, so the snubber capacitor connected in parallel to the power device is required to have an insulation performance of about 1000 V. Therefore, to form a thick dielectric layer compatible with high-voltage specifications in a trench shape like the snubber capacitor in the snubber circuit chip described in Patent Document 2, it is necessary to form a wide trench, which makes it difficult to achieve the effect of reducing the area of ​​the capacitor section by using a trench.

[0007] Although it depends on the current rating of the power device, a capacitance value of 1nF or more is generally required to suppress surge voltages. If we assume that the dielectric layer is a planar snubber capacitor with an oxide film permittivity ε (relative permittivity 3.9) and an oxide film thickness d of 3μm (assuming a film quality such as TEOS film with a breakdown field strength of approximately 3.3MV / cm) required for 1000V insulation performance, then, from C=ε×S / d, the area of ​​the capacitor part required for a capacitance value of 1nF is 9.32mm x 9.32mm, which is as large as the chip area of ​​the power device. This poses challenges such as making it difficult to reduce the area of ​​the printed circuit board that makes up the power conversion circuit and to incorporate it into a power module.

[0008] In view of the above problems, an object of the present invention is to provide a semiconductor device that can realize a high-voltage capacitance element with a small chip area. [Means for solving the problem]

[0009] One aspect of the present invention is a semiconductor device comprising: (a) a lower-layer electrode; (b) a first dielectric layer disposed on the lower-layer electrode; (c) a first upper-layer electrode disposed on the first dielectric layer; (d) a second dielectric layer disposed on the first upper-layer electrode; (e) a second upper-layer electrode disposed on the second dielectric layer and electrically connected to the lower-layer electrode; (f) a third dielectric layer disposed on the second upper-layer electrode; and (g) a third upper-layer electrode disposed on the third dielectric layer and electrically connected to the first upper-layer electrode, wherein a first capacitance between the lower-layer electrode and the first upper-layer electrode, a second capacitance between the first upper-layer electrode and the second upper-layer electrode, and a third capacitance between the second upper-layer electrode and the third upper-layer electrode are connected in parallel. [Effects of the Invention]

[0010] According to the present invention, it is possible to provide a semiconductor device that can realize a high-voltage-resistant capacitive element with a small chip area. [Brief explanation of the drawings]

[0011] [Figure 1] 1 is a circuit diagram showing a power conversion circuit to which the semiconductor device according to the first embodiment is applied. [Figure 2] 1 is a plan view showing a semiconductor device according to a first embodiment. [Figure 3] FIG. 2 is a cross-sectional view taken along the AA direction in FIG. [Figure 4] FIG. 4 is a cross-sectional view in which an equivalent circuit is superimposed on FIG. 3. [Figure 5] 2A to 2C are cross-sectional views illustrating a method for manufacturing the semiconductor device according to the first embodiment. [Figure 6] 6 is a cross-sectional view continuing from FIG. 5 for explaining the method for manufacturing the semiconductor device according to the first embodiment. FIG. [Figure 7] FIG. 7 is a cross-sectional view continuing from FIG. 6 for illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 8] 8 is a cross-sectional view continuing from FIG. 7 for explaining the method for manufacturing the semiconductor device according to the first embodiment. FIG. [Figure 9] FIG. 9 is a cross-sectional view continuing from FIG. 8 for explaining the method for manufacturing the semiconductor device according to the first embodiment. [Figure 10] FIG. 10 is a cross-sectional view continuing from FIG. 9 for illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 11] 11 is a cross-sectional view continuing from FIG. 10 for explaining the method for manufacturing the semiconductor device according to the first embodiment. FIG. [Figure 12] 12 is a cross-sectional view continuing from FIG. 11 for explaining the method for manufacturing the semiconductor device according to the first embodiment. FIG. [Figure 13] 13 is a cross-sectional view continuing from FIG. 12 for explaining the method for manufacturing the semiconductor device according to the first embodiment. FIG. [Figure 14] FIG. 10 is a cross-sectional view showing a semiconductor device according to a second embodiment. [Figure 15] FIG. 15 is a cross-sectional view in which an equivalent circuit is superimposed on FIG. 14. [Figure 16] FIG. 10 is a plan view showing a resistive layer of the semiconductor device according to the second embodiment. [Figure 17] FIG. 10 is another plan view showing the resistive layer of the semiconductor device according to the second embodiment. [Figure 18] FIG. 10 is a cross-sectional view showing a semiconductor device according to a third embodiment. [Figure 19] FIG. 10 is another cross-sectional view showing the semiconductor device according to the third embodiment. [Figure 20] FIG. 10 is a cross-sectional view showing a semiconductor device according to a fourth embodiment. [Figure 21] FIG. 10 is a plan view showing a semiconductor device according to a fourth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0012] Hereinafter, first to fourth embodiments of the present invention will be described with reference to the drawings. In the description of the drawings, identical or similar parts are designated by identical or similar reference numerals, and redundant explanations will be omitted. However, the drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each layer, etc. may differ from the actual ones. Furthermore, parts with different dimensional relationships and ratios may be included between the drawings. Furthermore, the first to fourth embodiments shown below are examples of devices and methods for embodying the technical concept of the present invention, and the technical concept of the present invention does not limit the materials, shapes, structures, arrangements, etc. of component parts to those described below.

[0013] Furthermore, the definitions of directions such as up / down and left / right in the following explanation are merely for the convenience of explanation and do not limit the technical idea of ​​the present invention. For example, if an object is rotated 90 degrees and observed, up / down is converted to left / right and read as such, and if it is rotated 180 degrees and observed, up / down is obviously read as reversed.

[0014] (First embodiment) <Configuration of semiconductor device> 1, a semiconductor device according to a first embodiment of the present invention is applied to a power conversion circuit, for example, as a snubber circuit (RC snubber circuit) 103. The power conversion circuit includes a DC power supply 100, a smoothing capacitor 101, a main circuit inductance 102, the snubber circuit 103, and a power conversion unit 106.

[0015] The power conversion unit 106 configures a half-bridge circuit by connecting a high-side switching element 107 and a low-side switching element 108, which are power devices, in series. Freewheeling diodes 109, 110 are connected in anti-parallel to the high-side switching element 107 and the low-side switching element 108. In FIG. 1, insulated gate bipolar transistors (IGBTs) are shown as examples of the high-side switching element 107 and the low-side switching element 108, but the high-side switching element 107 and the low-side switching element 108 may be other power switching elements such as metal oxide semiconductor field effect transistors (MOSFETs). When MOSFETs are used as the switching elements, the freewheeling diodes 109, 110 do not need to be used.

[0016] The collector of the high-potential side switching element 107 is connected to the positive electrode side of the DC power supply 100 via the main circuit inductance 102. The emitter of the low-potential side switching element 108 is connected to the negative electrode side of the low-potential side DC power supply 100. A load (not shown), such as a motor, is connected to a connection point 111 between the emitter of the high-potential side switching element 107 and the collector of the low-potential side switching element 108.

[0017] The smoothing capacitor 101 is connected in parallel to the DC power supply 100. The DC voltage supplied from the DC power supply 100 is smoothed by the smoothing capacitor 101 and is given to the power conversion unit 106 via the main circuit inductance 102.

[0018] Snubber circuit 103 is connected in parallel with high potential side switching element 107 and low potential side switching element 108. Snubber circuit 103 includes capacitance (snubber capacitor) 104, one end of which is connected to the collector of high potential side switching element 107, and resistor 105, one end of which is connected to the other end of capacitance 104 and the other end of which is connected to the emitter of low potential side switching element 108.

[0019] The snubber circuit 103 uses the snubber capacitor 104 to absorb surge voltages that occur during turn-off switching of the high-potential side switching element 107 and the low-potential side switching element 108, and dissipates the voltage as heat in the resistor 105, thereby suppressing surge voltages and ringing voltages and improving noise resistance.

[0020] Fig. 2 is a plan view of the semiconductor device 1 according to the first embodiment, and Fig. 3 is a cross-sectional view taken along the line AA in Fig. 2. The semiconductor device 1 according to the first embodiment is a snubber circuit chip (passive element chip) corresponding to the snubber circuit 103 shown in Fig. 1. As shown in Fig. 2, the semiconductor device 1 according to the first embodiment has a substantially rectangular planar shape.

[0021] 3, the semiconductor device 1 according to the first embodiment includes a semiconductor substrate 11. The conductivity type of the semiconductor substrate 11 is not particularly limited. The semiconductor substrate 11 is made of, for example, a silicon (Si) substrate. The semiconductor substrate 11 may also be made of a semiconductor substrate such as silicon carbide (SiC), gallium nitride (GaN), gallium arsenide (GaAs), or diamond.

[0022] A high-concentration region 12 of the same conductivity type as the semiconductor substrate 11 but having a higher impurity concentration than the semiconductor substrate 11 is provided on the upper surface (upper portion) of the semiconductor substrate 11. For example, if the semiconductor substrate 11 is p-type, + If the semiconductor substrate 11 is an n-type semiconductor, + A molded high concentration region 12 is provided. A lower electrode 2 is provided on the upper surface of the high concentration region 12. The lower electrode 2 is in ohmic contact with the high concentration region 12. The planar shape of the lower electrode 2 is rectangular, which matches the planar shape of the semiconductor device 1 according to the first embodiment shown in FIG.

[0023] A first upper-layer electrode 3, which is a metal electrode, is provided on the upper surface of the lower-layer electrode 2 via dielectric layers (31, 32), which are intermetal dielectric films (IMD). The dielectric layers (31, 32) include a dielectric film 31 in contact with the upper surface of the lower-layer electrode 2 and a dielectric film 32 provided on the dielectric film 31 and in contact with the lower surface of the first upper-layer electrode 3. The lower-layer electrode 2, the dielectric layers (31, 32), and the first upper-layer electrode 3 constitute a metal-insulator-metal (MIM) type capacitance element (2, 3, 31, 32).

[0024] A second upper-layer electrode 4, which is a metal electrode, is provided on the upper surface of the first upper-layer electrode 3, with dielectric layers (33, 34) which are IMDs interposed therebetween. The dielectric layers (33, 33) include a dielectric film 33 in contact with the upper surface of the first upper-layer electrode 3, and a dielectric film 34 provided on the dielectric film 33 and in contact with the lower surface of the second upper-layer electrode 4. The first upper-layer electrode 3, the dielectric layers (33, 34), and the second upper-layer electrode 4 constitute an MIM-type capacitance element (3, 4, 33, 34).

[0025] A third upper-layer electrode 5, which is a metal electrode, is provided on the upper surface of the second upper-layer electrode 4, with dielectric layers (35, 36) which are IMDs interposed therebetween. The dielectric layers (35, 36) include a dielectric film 35 in contact with the upper surface of the second upper-layer electrode 4, and a dielectric film 36 provided on the dielectric film 35 and in contact with the lower surface of the third upper-layer electrode 5. The second upper-layer electrode 4, the dielectric layers (35, 36), and the third upper-layer electrode 5 constitute an MIM-type capacitance element (4, 5, 35, 36).

[0026] The lower-layer electrode 2, the first upper-layer electrode 3, the second upper-layer electrode 4, and the third upper-layer electrode 5 can be made of metals such as aluminum (Al), an Al alloy, or copper (Cu). Examples of Al alloys include Al-silicon (Si), Al-copper (Cu)-Si, and Al-Cu. The lower-layer electrode 2, the first upper-layer electrode 3, the second upper-layer electrode 4, and the third upper-layer electrode 5 can also be made of conductive materials other than metals. For example, the lower-layer electrode 2, the first upper-layer electrode 3, the second upper-layer electrode 4, and the third upper-layer electrode 5 can be made of polysilicon doped with a high concentration of p-type or n-type impurities to form a polysilicon-insulator-polysilicon (PIP) type capacitance element.

[0027] The materials of the lower electrode 2, the first upper electrode 3, the second upper electrode 4, and the third upper electrode 5 may be the same or different from one another. The thicknesses of the lower electrode 2, the first upper electrode 3, the second upper electrode 4, and the third upper electrode 5 may be the same or different from one another.

[0028] Each of the dielectric layers (31, 32), (33, 34), and (35, 36) has a two-layer structure, but may have a single-layer structure or a multi-layer structure of three or more layers. The materials and number of layers of the dielectric layers (31, 32), (33, 34), and (35, 36) may be the same or different. The thicknesses of the dielectric layers (31, 32), (33, 34), and (35, 36) may be the same or different.

[0029] The dielectric films 31-36 may be made of, for example, silicon dioxide (SiO2), and the interlayer insulating film 4 may be made of, for example, a silicon dioxide (SiO2) film called a non-doped silica glass film (NSG film) that does not contain phosphorus (P) or boron (B), a phosphorus-doped silicon dioxide (PSG film), a boron-doped silicon dioxide (BSG film), a phosphorus- and boron-doped silicon dioxide (BPSG film), or a silicon nitride (Si3N4) film. The dielectric films 31-36 may be made of, for example, an insulating film (TEOS film) formed by chemical vapor deposition (CVD) using tetraethoxysilane (TEOS) gas, an organosilicon compound.

[0030] For example, the dielectric layers (31, 32) may be configured such that the dielectric film 31 is made of a TEOS film about 3 μm thick, and the dielectric film 32 is made of a PSG film. By making the thermal expansion coefficients of the dielectric films 31 and 32 different from each other, internal stresses can be offset, and even if the dielectric film 31 is a thick oxide film about 3 μm thick, warping of the wafer can be prevented and the flatness of the wafer can be maintained.

[0031] The lower electrode 2 and the second upper electrode 4 are electrically connected to each other through a connecting conductor (via) 7 that penetrates the dielectric layers (31, 32) and (33, 34). The first upper electrode 3 and the third upper electrode 5 are electrically connected to each other through a connecting conductor (via) 8 that penetrates the dielectric layers (33, 34) and (35, 36). The number of vias 7, 8 is not particularly limited. The lower electrode 2 and the second upper electrode 4 are connected by the via 7 that penetrates the dielectric layers, leaving the dielectric layers (31, 32) between the lower electrode 2 and the second upper electrode 4. Therefore, a capacitance C3 consisting of the second upper electrode 4, the dielectric layers (35, 36), and the third upper electrode 5 can also be formed above the via 7. This allows the area of ​​the capacitance C3 to be efficiently formed.

[0032] In FIG. 2, the positions of vias 7 and 8, the position of end 3x of first upper-layer electrode 3, and the position of end 4x of second upper-layer electrode 4 are each schematically indicated by dashed lines. As shown in FIG. 2, via 7 is disposed on one side of the rectangle formed by the planar pattern of semiconductor device 1 according to the first embodiment, spaced apart from end 3x of first upper-layer electrode 3. End 3x of first upper-layer electrode 3 on the via 7 side is disposed set back inward from the end of semiconductor device 1 according to the first embodiment in order to accommodate via 7. Via 8 is disposed on the opposite side of the rectangle formed by the planar pattern of semiconductor device 1 according to the first embodiment from the side on which via 7 is disposed, spaced apart from end 4x of second upper-layer electrode 4. End 4x of second upper-layer electrode 4 on the via 8 side is disposed set back inward from the end of semiconductor device 1 according to the first embodiment in order to accommodate via 8.

[0033] As shown in Figures 2 and 3, the third upper-layer electrode 5 is the top electrode, and a protective film 6 is provided on the upper surface of the third upper-layer electrode 5. The protective film 6 is composed of, for example, a TEOS film, a Si3N4 film, and a polyimide film. For example, the protective film 6 may be composed of a composite film in which a TEOS film, a Si3N4 film, and a polyimide film are laminated in this order. The protective film 6 is provided with an opening 6a that exposes a portion of the upper surface of the third upper-layer electrode 5. The opening 6a forms a bonding pad to which a bonding wire 9, shown schematically by a dashed line in Figure 3, is bonded.

[0034] A high-concentration region 13, which has the same conductivity type as the semiconductor substrate 11 but a higher impurity concentration than the semiconductor substrate 11, is provided on the lower surface (bottom) of the semiconductor substrate 11. A back electrode 14 is provided on the lower surface of the high-concentration region 13. The back electrode 14 can be formed, for example, of a single-layer film made of gold (Au), or a metal film laminated in this order of titanium (Ti), nickel (Ni), and gold (Au). The lower surface of the back electrode 14 of the semiconductor device 1 according to the first embodiment is bonded to a die pad 15.

[0035] Fig. 4 is a schematic diagram illustrating an equivalent circuit superimposed on the cross section of the semiconductor device 1 according to the first embodiment shown in Fig. 3. As shown in Fig. 4, a capacitance C1 of a capacitance element (2, 3, 31, 32) formed by the lower-layer electrode 2, the dielectric layers (31, 32), and the first upper-layer electrode 3, a capacitance C2 of a capacitance element (3, 4, 33, 34) formed by the first upper-layer electrode 3, the dielectric layers (33, 34), and the second upper-layer electrode 4, and a capacitance C3 of a capacitance element (4, 5, 35, 36) formed by the second upper-layer electrode 4, the dielectric layers (35, 36), and the third upper-layer electrode 5 are connected in parallel. The capacitances C1, C2, and C3 are connected in series with a resistance R1 of a resistance element formed by the semiconductor substrate 11. 4 correspond to the capacitance 105 of the snubber circuit 103 shown in FIG. 1, and the resistor R1 shown in FIG. 4 corresponds to the resistor 105 of the snubber circuit 103 shown in FIG.

[0036] In the semiconductor device 1 according to the first embodiment, the dielectric layers (31, 32), (33, 34), and (35, 36) that are IMDs and the first upper-layer electrode 3, the second upper-layer electrode 4, and the third upper-layer electrode 5 that are metal electrodes are alternately stacked on the lower-layer electrode 2, and the capacitors C1, C2, and C3 are connected in parallel. This allows the dielectric layers (31, 32), (33, 34), and (35, 36) to be stacked 3 μm thick without causing cracks or transport problems due to wafer warpage, and enables the capacitors C1, C2, and C3 to have high breakdown voltages on the order of nF. Furthermore, by connecting the capacitors C1, C2, and C3 in parallel, a capacitor area of ​​5.38 mm × 5.38 mm is sufficient to achieve a capacitance value of 1 nF, for example, and therefore reduces the chip area by approximately 42% compared to the case of a single-layer capacitor. Therefore, for example, it is possible to realize an RC snubber circuit chip that requires high voltage resistance and large capacitance value with a small chip area, which makes it possible to reduce the area of ​​printed circuit boards in power conversion circuits and to incorporate them into power modules and make them smaller.

[0037] Furthermore, since the resistor element formed by the semiconductor substrate 11 is in ohmic contact with the high concentration region 12, stable resistance characteristics with little variation can be achieved, making it possible to stably suppress surge voltages during switching of the power device.

[0038] <Method of manufacturing a semiconductor device> Next, an example of a method for manufacturing the semiconductor device 1 according to the first embodiment will be described. Note that the method for manufacturing the semiconductor device 1 according to the first embodiment described below is just one example, and it goes without saying that various other manufacturing methods, including modifications thereof, can be implemented within the scope of the spirit of the claims.

[0039] First, n-type impurities such as phosphorus (P) and arsenic (As) are ion-implanted into the upper surface of an n-type semiconductor substrate 11, and then heat treatment (annealing) is performed, thereby forming n-type impurities in the upper part of the semiconductor substrate 11, as shown in FIG. + This forms a mold high concentration region 12. Note that the ion implantation may be performed via a buffer oxide film.

[0040] 6, a lower electrode 2 made of aluminum or the like is deposited on the high concentration region 12 by sputtering, vapor deposition, or the like. The lower electrode 2 is in ohmic contact with the high concentration region 12.

[0041] Next, dielectric layers (31, 32) are formed by sequentially depositing dielectric films 31 and 32 on lower electrode 2 by chemical vapor deposition (CVD) or the like. For example, an oxide film such as a TEOS film is deposited to a thickness of about 3 μm as dielectric film 31, and a PSG film is deposited as dielectric film 32. By making the thermal expansion coefficients of dielectric films 31 and 32 different, internal stresses can be offset, preventing wafer warpage and maintaining wafer flatness even with an oxide film as thick as 3 μm.

[0042] Next, a first upper-layer electrode 3 made of aluminum or the like is deposited on the upper surface of the dielectric layer (31, 32) by sputtering, vapor deposition, or the like. A photoresist film is applied to the first upper-layer electrode 3, and the photoresist film is patterned using photolithography. Using the patterned photoresist film as an etching mask, a portion of the first upper-layer electrode 3 is selectively removed by dry etching such as reactive ion etching (RIE). The photoresist film is then removed. As a result, a portion of the upper surface of the dielectric film 32 is exposed, as shown in FIG. 7.

[0043] Next, dielectric films 33 and 34 are sequentially deposited on the first upper-layer electrode 3 and the dielectric film 32 by a CVD method or the like to form dielectric layers (33, 34). A photoresist film is applied to the dielectric film 34, and the photoresist film is patterned using photolithography. Using the patterned photoresist film as an etching mask, portions of the dielectric layers (31, 32) and the dielectric layers (33, 34) are selectively removed by dry etching or the like. The photoresist film is then removed. As a result, as shown in FIG. 8, contact holes 7x are formed that penetrate the dielectric layers (31, 32) and the dielectric layers (33, 34) and reach the lower-layer electrode 2.

[0044] Next, the contact holes 7x are filled with tungsten (W) or copper (Cu) plating by a CVD method or the like, thereby forming the vias 7. Next, a second upper-layer electrode 4 made of aluminum or the like is deposited on the dielectric film 34 by a sputtering method, a vapor deposition method or the like so as to contact the upper ends of the vias 7. Note that if the contact holes 7x are contacts that have been subjected to wide round etching, the vias 7 may be formed simultaneously with the second upper-layer electrode 4 by filling the contact holes 7x with aluminum or the like when depositing the second upper-layer electrode 4.

[0045] Next, a photoresist film is applied onto the second upper-layer electrode 4, and the photoresist film is patterned using photolithography. Using the patterned photoresist film as an etching mask, a portion of the second upper-layer electrode 4 is selectively removed by dry etching or the like. The photoresist film is then removed. As a result, a portion of the upper surface of the dielectric film 34 is exposed, as shown in FIG.

[0046] Next, dielectric films 35 and 36 are sequentially deposited on the second upper-layer electrode 4 and the dielectric film 34 by a CVD method or the like to form dielectric layers (35, 36). A photoresist film is applied to the dielectric film 36, and the photoresist film is patterned using photolithography. Using the patterned photoresist film as an etching mask, portions of the dielectric layers (33, 34) and the dielectric layers (35, 36) are selectively removed by dry etching or the like. The photoresist film is then removed. As a result, as shown in FIG. 10 , contact holes 8x are formed that penetrate the dielectric layers (33, 34) and the dielectric layers (35, 36) and reach the first upper-layer electrode 3.

[0047] Next, the contact holes 8x are filled with tungsten (W) or copper (Cu) plating by a CVD method or the like, thereby forming vias 8. Next, a third upper-layer electrode 5 made of aluminum or the like is deposited on the dielectric film 36 by a sputtering method, vapor deposition method or the like, as shown in FIG. 11 . If the contact holes 8x are contacts that have been subjected to wide round etching, the vias 8 may be formed simultaneously with the third upper-layer electrode 5 by filling the contact holes 8x with aluminum or the like when depositing the third upper-layer electrode 5.

[0048] Next, a protective film 6 such as a Si3N4 film is formed on the third upper-layer electrode 5 by plasma CVD or the like. A photoresist film is applied to the protective film 6, and the photoresist film is patterned using photolithography. Using the patterned photoresist film as an etching mask, a portion of the protective film 6 is selectively removed by dry etching or the like. As a result, as shown in FIG. 12, an opening 6a is formed in the protective film 6, and the portion of the third upper-layer electrode 5 exposed in the opening 6a becomes a pad region available for wire bonding.

[0049] Next, n-type impurities such as phosphorus (P) or arsenic (As) are ion-implanted into the rear surface of the semiconductor substrate 11, and then heat treatment (annealing) is performed to form n-type impurities in the lower part of the semiconductor substrate 11. + A high concentration region 13 of the mold is formed. Next, a back electrode 14 is deposited on the lower surface of the high concentration region 13 by sputtering, vapor deposition, or the like, as shown in Fig. 13. As a result, the semiconductor device 1 according to the first embodiment is completed.

[0050] (Second embodiment) As shown in FIG. 14 , the semiconductor device 1a according to the second embodiment differs from the semiconductor device 1 according to the first embodiment in that it further includes a thin-film resistive layer 20 provided on a semiconductor substrate 11 with an insulating film 37 interposed therebetween. The high-concentration region 12 on the upper surface of the semiconductor substrate 11 is connected to a relay wiring 17 through a via 18 that penetrates the insulating films 37 and 38. Ohmic contact is made between the lower end of the via 18 and the upper surface of the high-concentration region 12. The relay wiring 17 is provided in the same layer as the lower electrode 2 and is spaced apart from the lower electrode 2. The relay wiring 17 is connected to the upper surface of the resistive layer 20 through the via 18 that penetrates the insulating film 38. The upper surface of the resistive layer 20 is connected to the lower surface of the lower electrode 2 through a via 19 that penetrates the insulating film 38.

[0051] The resistive layer 20 is composed of, for example, a polysilicon resistor made of a polysilicon film. The region of the resistive layer 20 between the vias 18 and 19 functions as a resistor. The resistance value of the resistive layer 20 can be adjusted appropriately by adjusting the width and length of the resistive layer 20 and the concentration of n-type or p-type impurities added to the resistive layer 20. The resistance value of the resistive layer 20 can also be adjusted by adjusting the positions of the vias 18 and 19.

[0052] The temperature coefficient of the resistive layer 20 may be zero, may have a positive temperature coefficient, or may have a negative temperature coefficient. When the resistive layer 20 has a negative temperature coefficient, an increase in the resistance value during high-temperature operation can be suppressed. The temperature coefficient of the resistive layer 20 can be adjusted, for example, by adjusting the dose when impurities are ion-implanted into polysilicon.

[0053] The resistive layer 20 is not limited to a polysilicon film, but may be made of tantalum nitride (TaN x The resistive layer 20 may be a film of a nitride of a transition metal such as Cr, Ni, or a laminated film of high-melting-point metal films laminated in this order: chromium (Cr), nickel (Ni), and manganese (Mn). The resistive layer 20 may be a thin film of silver palladium (AgPd), ruthenium oxide (RuO), or the like.

[0054] Fig. 15 is a schematic diagram illustrating an equivalent circuit superimposed on the cross section of the semiconductor device 1a according to the first embodiment shown in Fig. 14. As shown in Fig. 15, a capacitance C1 of a capacitance element (2, 3, 31, 32) formed by the lower-layer electrode 2, the dielectric layers (31, 32), and the first upper-layer electrode 3, a capacitance C2 of a capacitance element (3, 4, 33, 34) formed by the first upper-layer electrode 3, the dielectric layers (33, 34), and the second upper-layer electrode 4, and a capacitance C3 of a capacitance element (4, 5, 35, 36) formed by the second upper-layer electrode 4, the dielectric layers (35, 36), and the third upper-layer electrode 5 are connected in parallel. The capacitances C1, C2, and C3 are connected in series with a resistance R2 of a resistance element formed by the resistive layer 20 and a resistance R1 of a resistance element formed by the semiconductor substrate 11 to form an RC snubber circuit.

[0055] The resistive layer 20 has a rectangular planar shape, as shown in FIG. 16 , for example. The resistive layer 20 may function as a fuse by being shaped to melt when an overcurrent flows, as shown in FIG. 17 , for example. The resistive layer 20 has wide portions 21 and 22 and a narrow portion 23 sandwiched between the wide portions 21 and 22. When an overcurrent flows through the resistive layer 20, the narrow portion 23 melts. By making the resistive layer 20 function as a fuse, the resistive layer 20 enters an open state even when dielectric breakdown occurs in the MIM capacitor, thereby preventing short-circuit failures in the power device. The other configurations of the semiconductor device 1a according to the second embodiment are substantially similar to those of the semiconductor device 1 according to the first embodiment, and therefore, redundant description will be omitted.

[0056] The semiconductor device 1a according to the second embodiment achieves the same effects as the semiconductor device 1 according to the first embodiment. Furthermore, the semiconductor device 1a according to the second embodiment further includes a resistive layer 20. By connecting the resistance R2 of the resistive element formed by the resistive layer 20 to the capacitances C1, C2, and C3, the resistance R2 of the resistive layer 20 is used as the main resistive element, and the resistivity of the resistance R1 of the resistive element formed by the semiconductor substrate 11 can be extremely low. When the resistivity of the resistance R1 of the semiconductor substrate 11 is to be low, a substrate with low resistivity, such as a silicon substrate heavily doped with n-type impurities, can be used as the semiconductor substrate 11.

[0057] (Third embodiment) 18, the semiconductor device 1b according to the third embodiment differs from the semiconductor device 1 according to the first embodiment in that it does not have a lower-layer electrode 12, which is a metal electrode, on the semiconductor substrate 11. In the semiconductor device 1b according to the third embodiment, the high-concentration region 12 in the upper part of the semiconductor substrate 11 forms the lower-layer electrode. In other words, the high-concentration region 12, the dielectric layers (31, 32), and the first upper-layer electrode 3 form the lowermost capacitor (3, 12, 31, 32).

[0058] Dielectric layers (31, 32) are in contact with the upper surface of the high concentration region 12 in the upper part of the semiconductor substrate 11. A via 7 that penetrates the dielectric layers (31, 32) is in ohmic contact with the high concentration region 12 in the upper part of the semiconductor substrate 11. The second upper-layer electrode 4 is electrically connected to the high concentration region 12 in the upper part of the semiconductor substrate 11 through the via 7 that penetrates the dielectric layers (31, 32). Other configurations of the semiconductor device 1b according to the third embodiment are substantially similar to those of the semiconductor device 1 according to the first embodiment, and therefore, redundant explanations will be omitted.

[0059] According to the semiconductor device 1b of the third embodiment, even if the lower layer electrode 12 is not provided on the semiconductor substrate 11, the same effects as those of the semiconductor device 1 of the first embodiment can be achieved.

[0060] In the semiconductor device 1b according to the third embodiment, as shown in Fig. 19, the entire semiconductor substrate 11 may be a low-resistivity substrate having a high concentration region, and the entire semiconductor substrate 11 may constitute the lower-layer electrode. In this case, the semiconductor substrate 11, the dielectric layers (31, 32), and the first upper-layer electrode 3 constitute the lowermost capacitor (11, 12, 31, 32). The semiconductor device 1b according to the third embodiment functions as a capacitive element chip.

[0061] (Fourth embodiment) 20, the semiconductor device 1c according to the fourth embodiment differs from the semiconductor device 1 according to the first embodiment in that it further includes a fourth upper-layer electrode 51 provided on the third upper-layer electrode 5 with dielectric layers (39, 40) interposed therebetween, and a fifth upper-layer electrode 52 provided on the fourth upper-layer electrode 51 with dielectric layers (41, 42) interposed therebetween. The fifth upper-layer electrode 52 is the uppermost electrode, and a protective film 6 is provided on the fifth upper-layer electrode 52.

[0062] The second upper layer electrode 4 and the fourth upper layer electrode 51 are electrically connected through a via 53 that penetrates the dielectric layers (35, 36) and the dielectric layers (39, 40). The via 53 and the via 8 are arranged so as to overlap each other, forming a stacked via structure.

[0063] The third upper-layer electrode 5 and the fifth upper-layer electrode 52 are electrically connected via a via 54 that penetrates the dielectric layers (39, 40) and the dielectric layers (41, 42). The via 54 and the via 7 are arranged in overlapping positions to form a stacked via structure. The other configurations of the semiconductor device 1c according to the fourth embodiment are substantially the same as those of the semiconductor device 1 according to the first embodiment, and therefore, redundant explanations will be omitted.

[0064] The semiconductor device 1c according to the fourth embodiment has the same effects as the semiconductor device 1 according to the first embodiment. Furthermore, according to the semiconductor device 1c according to the fourth embodiment, a capacitance formed by the third upper-layer electrode 5, the dielectric layers (39, 40), and the fourth upper-layer electrode 51, and a capacitance formed by the fourth upper-layer electrode 51, the dielectric layers (41, 42), and the fifth upper-layer electrode 52 are further connected in parallel to the parallel-connected capacitances C1, C2, and C3 shown in Fig. 4. Note that metal electrodes and IMDs may be further alternately stacked to connect more capacitances in parallel.

[0065] In the semiconductor device 1c according to the fourth embodiment, the vias 53 and 54 do not have to be positioned so as to overlap with the vias 7 and 8. For example, as shown in FIG. 2, the vias 7 and 8 are positioned at both ends in the longitudinal direction. As shown in FIG. 21, the vias 53 and 54 are positioned at both ends in the lateral direction. FIG. 21 schematically shows the positions of the vias 53 and 54, the position of the end 5x of the third upper layer electrode 5, and the position of the end 51x of the fourth upper layer electrode 51 with dashed lines.

[0066] End 5x of third upper-layer electrode 5 on the via 53 side is disposed inside the end of semiconductor device 1c according to the fourth embodiment so as to be spaced apart from via 53. End 51x of fourth upper-layer electrode 51 on the via 54 side is adjacent to and inside the end of semiconductor device 1c according to the fourth embodiment so as to be spaced apart from via 54. By differentiating the positions of vias 53 and 54 from the positions of vias 7 and 8 on the planar pattern and arranging vias 7, 8, 53, and 54 on different sides of the rectangle of semiconductor device 1c according to the fourth embodiment, the flatness of dielectric layers (39, 40), fourth upper-layer electrode 51, dielectric layers (41, 42), and fifth upper-layer electrode 52 can be maintained.

[0067] (Other embodiments) As described above, the present invention has been described with reference to the first to fourth embodiments, but the descriptions and drawings that form part of this disclosure should not be understood as limiting the present invention. Various alternative embodiments, examples, and operating techniques will become apparent to those skilled in the art from this disclosure.

[0068] For example, although the RC snubber circuit 103 of a power conversion circuit is illustrated as the semiconductor device 1 according to the first embodiment, it can be applied to various circuits other than power conversion circuits. Furthermore, when the semiconductor substrate 11 of the semiconductor devices 1, 1a, and 1c according to the first, third, and fourth embodiments is a low resistivity substrate, it can be used as a capacitance chip in various circuits.

[0069] Furthermore, the configurations disclosed in the first to fourth embodiments can be appropriately combined within a range that does not cause contradictions. As such, the present invention naturally includes various embodiments not described here. Therefore, the technical scope of the present invention is defined only by the invention-specifying matters according to the claims that are appropriate from the above description. [Explanation of symbols]

[0070] 1, 1a, 1b, 1c...Semiconductor device 2...Lower electrode 3...First upper layer electrode 4…Second upper layer electrode 5…Third upper layer electrode 3x,4x,5x…end 6...Protective film 6a...Opening 7,8…Beer 7x, 8x...contact holes 9...Bonding wire 11...Semiconductor substrate 12,13…High concentration area 14...Back electrode 15...Die pad 17...Relay wiring 18,19…Beer 20…Resistance layer 21, 22...Wide section 23…Narrow part 37, 38...Insulating film 51x...end 53,54…Beer 100…DC power supply 101...Smoothing capacitor 102...Main circuit inductance 103...Snubber circuit 104...Capacitance (snubber capacitor) 105...Resistance 106...Power conversion section 107...High potential side switching element 108...Low potential side switching element 109,110...Freewheeling diode 111...Connection point C1,C2,C3…Capacity R1, R2… Resistance

Claims

1. A lower electrode; a first dielectric layer provided on the lower electrode; a first upper layer electrode provided on the first dielectric layer; a second dielectric layer provided on the first upper layer electrode; a second upper-layer electrode provided on the second dielectric layer and electrically connected to the lower-layer electrode; a third dielectric layer provided on the second upper layer electrode; a third upper-layer electrode provided on the third dielectric layer and electrically connected to the first upper-layer electrode; a semiconductor substrate provided under the lower electrode; a resistive layer provided on the semiconductor substrate via an insulating film; Equipped with a first capacitance between the lower layer electrode and the first upper layer electrode, a second capacitance between the first upper layer electrode and the second upper layer electrode, and a third capacitance between the second upper layer electrode and the third upper layer electrode are connected in parallel; the resistive layer is electrically connected between the semiconductor substrate and the lower electrode; The semiconductor device is characterized in that the resistive layer is electrically connected to the semiconductor substrate via a relay wiring in the same layer as the lower layer electrode.

2. a first via that penetrates the first dielectric layer and the second dielectric layer and electrically connects the lower-layer electrode and the second upper-layer electrode; a second via that penetrates the second dielectric layer and the third dielectric layer and electrically connects the first upper layer electrode and the third upper layer electrode; 2. The semiconductor device according to claim 1, further comprising:

3. an end of the first upper layer electrode is disposed away from the first via; an end of the second upper layer electrode is disposed away from the second via; 3. The semiconductor device according to claim 2.

4. A lower electrode; a first dielectric layer provided on the lower electrode; a first upper layer electrode provided on the first dielectric layer; a second dielectric layer provided on the first upper layer electrode; a second upper-layer electrode provided on the second dielectric layer and electrically connected to the lower-layer electrode; a third dielectric layer provided on the second upper layer electrode; a third upper-layer electrode provided on the third dielectric layer and electrically connected to the first upper-layer electrode; a first via that penetrates the first dielectric layer and the second dielectric layer and electrically connects the lower-layer electrode and the second upper-layer electrode; a second via that penetrates the second dielectric layer and the third dielectric layer and electrically connects the first upper layer electrode and the third upper layer electrode; Equipped with a first capacitance between the lower layer electrode and the first upper layer electrode, a second capacitance between the first upper layer electrode and the second upper layer electrode, and a third capacitance between the second upper layer electrode and the third upper layer electrode are connected in parallel; The first via is disposed at a position overlapping the third upper layer electrode. A semiconductor device characterized by:

5. a protective film provided on the third upper layer electrode; an opening is provided in the protective film to expose a portion of the third upper-layer electrode; A part of the third upper layer electrode exposed in the opening becomes a pad region to which wire bonding can be performed.

5. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device having a first insulating layer and a second insulating layer.

6. 5. The semiconductor device according to claim 4, further comprising a semiconductor substrate provided below the lower electrode.

7. 7. The semiconductor device according to claim 1, wherein the semiconductor substrate is connected in series to the first to third capacitors as a resistive element.

8. a resistive layer provided on the semiconductor substrate via an insulating film; The resistive layer is electrically connected between the semiconductor substrate and the lower electrode.

7. The semiconductor device according to claim 6, wherein the semiconductor device is a semiconductor device having a first insulating layer.

9. A lower electrode; a first dielectric layer provided on the lower electrode; a first upper layer electrode provided on the first dielectric layer; a second dielectric layer provided on the first upper layer electrode; a second upper-layer electrode provided on the second dielectric layer and electrically connected to the lower-layer electrode; a third dielectric layer provided on the second upper layer electrode; a third upper-layer electrode provided on the third dielectric layer and electrically connected to the first upper-layer electrode; a semiconductor substrate provided under the lower electrode; a resistive layer provided on the semiconductor substrate via an insulating film; Equipped with a first capacitance between the lower layer electrode and the first upper layer electrode, a second capacitance between the first upper layer electrode and the second upper layer electrode, and a third capacitance between the second upper layer electrode and the third upper layer electrode are connected in parallel; the resistive layer is electrically connected between the semiconductor substrate and the lower electrode; The semiconductor device is characterized in that the resistive layer functions as a fuse.

10. the lower electrode is composed of a high concentration region provided on an upper portion of a semiconductor substrate, The semiconductor substrate is connected in series to the first to third capacitors as a resistive element.

5. The semiconductor device according to claim 4.

11. 5. The semiconductor device according to claim 4, wherein the lower electrode is made of a semiconductor substrate.

12. a fourth dielectric layer provided on the third upper-layer electrode; a fourth upper-layer electrode provided on the fourth dielectric layer and electrically connected to the second upper-layer electrode; a fifth dielectric layer provided on the fourth upper-layer electrode; a fifth upper-layer electrode provided on the fifth dielectric layer and electrically connected to the third upper-layer electrode; 2. The semiconductor device according to claim 1, further comprising:

13. a first via that penetrates the first dielectric layer and the second dielectric layer and electrically connects the lower-layer electrode and the second upper-layer electrode; a second via that penetrates the second dielectric layer and the third dielectric layer and is electrically connected to the first upper-layer electrode and the third upper-layer electrode; a third via that penetrates the third dielectric layer and the fourth dielectric layer and electrically connects the second upper-layer electrode and the fourth upper-layer electrode; a fourth via that penetrates the fourth dielectric layer and the fifth dielectric layer and is electrically connected to the third upper-layer electrode and the fifth upper-layer electrode; 13. The semiconductor device according to claim 12, further comprising:

14. the first via and the third via are arranged at positions overlapping each other on a plane pattern, The second via and the fourth via are arranged at positions overlapping each other on the plane pattern.

14. The semiconductor device according to claim 13.

15. A lower electrode; a first dielectric layer provided on the lower electrode; a first upper layer electrode provided on the first dielectric layer; a second dielectric layer provided on the first upper layer electrode; a second upper-layer electrode provided on the second dielectric layer and electrically connected to the lower-layer electrode; a third dielectric layer provided on the second upper layer electrode; a third upper-layer electrode provided on the third dielectric layer and electrically connected to the first upper-layer electrode; a fourth dielectric layer provided on the third upper-layer electrode; a fourth upper-layer electrode provided on the fourth dielectric layer and electrically connected to the second upper-layer electrode; a fifth dielectric layer provided on the fourth upper-layer electrode; a fifth upper-layer electrode provided on the fifth dielectric layer and electrically connected to the third upper-layer electrode; a first via that penetrates the first dielectric layer and the second dielectric layer and electrically connects the lower-layer electrode and the second upper-layer electrode; a second via that penetrates the second dielectric layer and the third dielectric layer and is electrically connected to the first upper-layer electrode and the third upper-layer electrode; a third via that penetrates the third dielectric layer and the fourth dielectric layer and electrically connects the second upper-layer electrode and the fourth upper-layer electrode; a fourth via that penetrates the fourth dielectric layer and the fifth dielectric layer and is electrically connected to the third upper-layer electrode and the fifth upper-layer electrode; Equipped with a first capacitance between the lower layer electrode and the first upper layer electrode, a second capacitance between the first upper layer electrode and the second upper layer electrode, and a third capacitance between the second upper layer electrode and the third upper layer electrode are connected in parallel; the lower layer electrode has a rectangular shape in a planar pattern, The first to fourth vias are arranged on different sides of the rectangle formed by the lower layer electrodes in a plane pattern. A semiconductor device characterized by:

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