NITRIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING NITRIDE SEMICONDUCTOR DEVICE

Abstract

To provide a technique that can effectively reduce the contact resistance between a p-type region and an electrode in nitride semiconductors.SOLUTION: A nitride semiconductor device has a nitride semiconductor substrate with a p-type region exposed on at least a part of a surface. The nitride semiconductor device has an intermediate layer disposed on at least a part of a top surface of the p-type region and containing magnesium and nitrogen. The nitride semiconductor device has an electrode layer disposed on at least a part of a top surface of the intermediate layer.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The technology disclosed in this specification relates to a nitride semiconductor device and a method for manufacturing the nitride semiconductor device. [Background technology]

[0002] Patent Document 1 discloses a technique for reducing the contact resistance between a p-type GaN substrate and an electrode. In this technique, a source layer (e.g., Mg, MgF2, MgO) and a cap layer (e.g., Pt, Au, Ni) are deposited on the surface of a p-type GaN substrate, followed by annealing. Gallium from the p-type GaN substrate diffuses into the cap layer, forming gallium vacancies in the p-type GaN substrate. Magnesium from the source layer also diffuses into the p-type GaN, bonding with the gallium vacancies and activating them. The source layer and cap layer are then removed, and an electrode is formed on the p-type GaN. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent Application Publication No. 2019 / 0393038 Summary of the Invention [Problem to be solved by the invention]

[0004] However, the reduction in contact resistance is not sufficient with the technique of Patent Document 1. This specification provides a technique that can effectively reduce the contact resistance between p-type GaN and an electrode. [Means for solving the problem]

[0005] One embodiment of a nitride semiconductor device disclosed herein includes a nitride semiconductor substrate having a p-type region exposed on at least a portion of its surface. The nitride semiconductor device includes an intermediate layer disposed on at least a portion of the top surface of the p-type region and containing magnesium and nitrogen. The nitride semiconductor device also includes an electrode layer disposed on at least a portion of the top surface of the intermediate layer.

[0006] The inventors discovered a structure in which an intermediate layer containing magnesium and nitrogen is placed between a p-type region of a nitride semiconductor substrate and an electrode layer, which makes it possible to significantly reduce the contact resistance between the p-type region and the electrode layer compared to when no intermediate layer is placed.

[0007] The intermediate layer may have an amorphous structure.

[0008] The intermediate layer may contain gallium, and the concentration of gallium in the intermediate layer may decrease with distance from the interface between the p-type region and the intermediate layer.

[0009] The acceptor concentration and other impurity concentrations in the p-type region are 1×10 16 ~1×10 20 cm -3 may be in the range of

[0010] The thickness of the intermediate layer may be 1000 nm or less.

[0011] The nitride semiconductor substrate may further include an n-type region exposed on a portion of its surface. The electrode layer may be disposed across the n-type region and the p-type region. An intermediate layer may be disposed between the p-type region and the electrode layer, and no intermediate layer may be disposed between the n-type region and the electrode layer.

[0012] The nitride semiconductor substrate may be gallium nitride, and the intermediate layer may be magnesium nitride.

[0013] One embodiment of a method for manufacturing a nitride semiconductor device disclosed in this specification includes a magnesium layer forming step of forming a magnesium layer containing magnesium as a main component on at least a portion of the surface of a p-type region of a nitride semiconductor substrate, the p-type region being exposed on at least a portion of the surface. The manufacturing method also includes an annealing step of annealing the nitride semiconductor substrate on which the magnesium layer has been formed in an atmosphere containing nitrogen. The annealing step transforms the magnesium layer into an intermediate layer containing magnesium and nitrogen. The manufacturing method also includes an electrode layer forming step of forming an electrode layer on at least a portion of the upper surface of the intermediate layer. Details of the effects will be described in the examples.

[0014] The method may further include a step of reducing the thickness of the intermediate layer after the annealing step. The electrode layer forming step may include forming an electrode layer on the upper surface of the intermediate layer after the thickness has been reduced.

[0015] The magnesium layer forming step may selectively form the magnesium layer in at least a specific region on the surface of the p-type region.

[0016] The magnesium layer forming step may include a step of forming a mask layer having an opening corresponding to the specific region on the surface of the nitride semiconductor substrate, and a step of depositing the magnesium layer via the mask layer.

[0017] An n-type region may be exposed on a portion of the surface of the nitride semiconductor substrate. The magnesium layer forming step may form a magnesium layer on at least a portion of the surface of the p-type region, but not on the surface of the n-type region. The electrode layer forming step may form an electrode layer so as to straddle the n-type region and the intermediate layer formed in the p-type region. [Brief explanation of the drawings]

[0018] [Figure 1] 1 is a schematic cross-sectional view of a semiconductor device 1 according to a first embodiment. [Figure 2] 1 is a flowchart illustrating a method for manufacturing the semiconductor device 1. [Figure 3] 2A to 2C are cross-sectional views illustrating a method for manufacturing the semiconductor device 1. FIG. [Figure 4] 2A to 2C are cross-sectional views illustrating a method for manufacturing the semiconductor device 1. FIG. [Figure 5] 2A to 2C are cross-sectional views illustrating a method for manufacturing the semiconductor device 1. FIG. [Figure 6] FIG. 10 is a diagram showing the measurement results of current-voltage characteristics. [Figure 7] FIG. 10 is a schematic cross-sectional view of a semiconductor device 101 according to a second embodiment. [Figure 8] 1 is a flowchart illustrating a method for manufacturing the semiconductor device 101. [Figure 9] 1A to 1C are cross-sectional views illustrating a method for manufacturing the semiconductor device 101. [Figure 10] FIG. 2 is a schematic cross-sectional view of a semiconductor device 201 of a comparative example. DETAILED DESCRIPTION OF THE INVENTION [Example]

[0019] (Configuration of semiconductor device 1) 1 shows a schematic cross-sectional view of a semiconductor device 1 according to Example 1. The semiconductor device 1 has a structure in which a semiconductor substrate 10, an intermediate layer 13, and an electrode layer 14 are stacked in this order. The semiconductor substrate 10 has a structure in which a p-type GaN layer 12 is stacked on a GaN substrate 11. That is, the p-type GaN layer 12 is exposed on the entire surface of the semiconductor substrate 10. The impurity in the p-type GaN layer 12 is magnesium, and its concentration is 1×10 16 ~1×10 20 cm -3 The range is.

[0020] The intermediate layer 13 is disposed on the entire upper surface of the p-type GaN layer 12. The intermediate layer 13 is a compound containing magnesium and nitrogen. In this example, the intermediate layer 13 is magnesium nitride (MgNx). The thickness T3 of the intermediate layer 13 is 1000 nm or less, and preferably 300 nm or less.

[0021] The nitrogen concentration in intermediate layer 13 decreases from upper surface 13u of intermediate layer 13 toward p-type GaN layer 12. As will be described later, intermediate layer 13 is formed by annealing a magnesium layer in a nitrogen atmosphere, thereby diffusing nitrogen from upper surface 13u.

[0022] The intermediate layer 13 contains gallium, and the p-type GaN layer 12 contains magnesium. The gallium concentration in the intermediate layer 13 decreases with increasing distance from the interface IF1 between the p-type GaN layer 12 and the intermediate layer 13. The magnesium concentration in the p-type GaN layer 12 decreases with increasing distance from the interface IF1. This is because interdiffusion occurs at the interface IF1 during the annealing process described below.

[0023] Furthermore, the intermediate layer 13 has an amorphous structure. This is because the intermediate layer 13 is a magnesium nitride layer formed by nitrogen annealing. The fact that the intermediate layer 13 has an amorphous structure can be confirmed by XPS (X-ray photoelectron spectroscopy).

[0024] It is also possible to form a magnesium nitride layer without nitrogen annealing. For example, this can be done by sputtering magnesium in a nitrogen atmosphere. However, a magnesium nitride layer formed without nitrogen annealing may not have an amorphous structure and may contain microcrystals. In addition, the nitrogen concentration does not vary in the thickness direction. Therefore, by analyzing the presence or absence of an amorphous structure and the distribution of the nitrogen concentration in the thickness direction, it is possible to determine whether the intermediate layer 13 is a layer formed by nitrogen annealing.

[0025] The electrode layer 14 is disposed on the entire upper surface of the intermediate layer 13. There are no particular limitations on the structure or thickness of the electrode layer 14. In this embodiment, the electrode layer 14 has a structure in which gold is laminated on nickel.

[0026] (Method of manufacturing semiconductor device 1) A method for manufacturing the semiconductor device 1 will be described with reference to the flowchart of FIG. 2 and the cross-sectional schematic views of FIGS. 3 to 5. In step S1, a semiconductor substrate 10 is formed, in which a p-type GaN layer 12 is stacked on a GaN substrate 11. The semiconductor substrate 10 may be formed by growing the p-type GaN layer 12 on the GaN substrate 11 by an epitaxial growth method (e.g., MOVPE, HVPE, or MBE). In this example, the magnesium concentration of the p-type GaN layer 12 is set to 1×10 17 cm -3 It was decided.

[0027] In step S2, a magnesium layer formation process is performed. Specifically, a magnesium layer 13A is formed on the surface of the p-type GaN layer 12 (see FIG. 3). The magnesium layer 13A is a layer containing magnesium as a main component. The magnesium layer 13A may also contain other elements such as fluorine and oxygen. In this example, the thickness T1 of the magnesium layer 13A was set to 50 nm. The magnesium layer 13A can be formed using various methods and devices. For example, an EB evaporation device, a resistance heating evaporation device, a sputtering device, etc. may be used.

[0028] In step S3, an annealing step is performed. Specifically, the semiconductor substrate 10 on which the magnesium layer 13A is formed is annealed in an atmosphere containing nitrogen. The annealing temperature can be in the range of 300 to 1000°C. The annealing time can be set appropriately. The annealing can be performed using various methods and devices. In this example, annealing at 800°C for 60 minutes was performed using an RTA (Rapid Thermal Anneal) device.

[0029] The annealing step allows nitrogen in the atmosphere to diffuse from the surface of the magnesium layer 13A. This changes the magnesium layer 13A into the intermediate layer 13 (magnesium nitride) (see FIG. 4). The thickness T2 of the intermediate layer 13 after annealing is greater than the thickness T1 before annealing. In this example, the thickness T1 was 50 nm, and the thickness T2 was 80 to 100 nm. The annealing step also allows interdiffusion to occur between the p-type GaN layer 12 and the magnesium layer 13A.

[0030] In step S4, the thickness of the intermediate layer 13 is reduced. As a result, the thickness of the intermediate layer 13 is reduced from thickness T2 (FIG. 4) to thickness T3 (FIG. 5). This process can be performed by various methods, such as wet etching using aqua regia or hydrofluoric acid, dry etching, or polishing. In this example, the thickness was reduced from T2 (80 to 100 nm) to T3 (approximately 20 nm) by wet etching using aqua regia.

[0031] In step S5, an electrode layer forming step is performed. Specifically, an electrode layer 14 is formed on the upper surface of the intermediate layer 13 after the film thickness has been reduced. In this embodiment, the electrode layer 14 has a structure in which nickel and gold are laminated in this order.

[0032] In step S6, the semiconductor device 1 on which the electrode layer 14 has been formed is annealed in an oxygen atmosphere. This allows a contact to be formed using nickel oxide. In this example, annealing was performed at 525°C for 5 minutes. This completes the semiconductor device 1 shown in FIG. 1.

[0033] (Measurement results of current-voltage characteristics) The current-voltage characteristics were measured between the p-type GaN layer 12 and the electrode layer 14. The impurity concentration of the p-type GaN layer 12 was 1×10 17 cm -3The measurement results are shown in Figure 6. The horizontal axis represents voltage. The case where a positive voltage is applied to the electrode layer 14 relative to the p-type GaN layer 12 is defined as a forward voltage. The case where a positive voltage is applied to the p-type GaN layer 12 relative to the electrode layer 14 is defined as a reverse voltage. The vertical axis represents current.

[0034] Graph G0 shows the measured values ​​for the semiconductor device of the comparative example. The semiconductor device of the comparative example does not include the intermediate layer 13, and has a structure in which the electrode layer 14 is disposed directly on the p-type GaN layer 12. Graphs G1 and G2 show the measured values ​​for the semiconductor device of this example. Graph G1 shows the measured values ​​for the semiconductor device in which the electrode layer 14 is disposed on the thick intermediate layer 13 (FIG. 4, thickness T2). Graph G2 shows the measured values ​​for the semiconductor device in which the electrode layer 14 is disposed on the thin intermediate layer 13 (FIG. 1, thickness T3).

[0035] As can be seen from graphs G0 and G1, the semiconductor device of this example can increase the current value by up to one million times compared to the semiconductor device of the comparative example. In other words, by providing intermediate layer 13, it is possible to significantly reduce contact resistance. Furthermore, as can be seen from graphs G1 and G2, by thinning intermediate layer 13, it is possible to further increase the current value by up to one thousand times. In other words, by thinning intermediate layer 13, it is possible to further reduce contact resistance.

[0036] In addition, in graph G1, the current value at the reverse voltage is about 10 times higher than the current value at the forward voltage. On the other hand, in graph G2, the current value at the reverse voltage and the current value at the forward voltage are almost equal. In other words, by thinning the intermediate layer 13, the rectification effect can be suppressed. It becomes possible to form a good ohmic contact.

[0037] A model for reducing contact resistance by interposing an intermediate layer 13 will be described. Among gallium nitride compound semiconductors, p-type gallium nitride has many defects, resulting in band bending at the material surface. This increases the energy barrier for holes. Therefore, the technology described herein deposits a magnesium layer 13A on the p-type GaN layer 12 and annealing it, thereby diffusing magnesium into the surface of the p-type GaN layer 12. Magnesium terminates defects in the gallium nitride and increases the acceptor concentration, thereby reducing the degree of band bending. This reduces the energy barrier for holes. Furthermore, the technology described herein forms an electrode layer 14 on the intermediate layer 13. This allows an electrode to be formed while maintaining a reduced energy barrier for holes. As a result, contact resistance can be reduced.

[0038] (effect) Conventionally, the impurity concentration is low (1×10 16 ~1×10 20 cm -3 It has been difficult to reduce the contact resistance or form an ohmic contact with an electrode formed on a p-type GaN layer with a low concentration (about 2 × 10 19 cm -3 This is because it is necessary to interpose a p-type GaN layer (above). Furthermore, if high-concentration p-type GaN is formed by epitaxial regrowth, a Si pile-up layer is introduced at the interface of the regrowth layer. In the technology of this specification, an intermediate layer 13 (magnesium nitride) formed by nitrogen annealing is disposed between the low-concentration p-type GaN layer and the electrode. This allows the contact resistance with the electrode to be reduced and ohmic contact to be achieved, even with a low-concentration p-type GaN layer. Furthermore, since there is no need to regrow high-concentration p-type GaN, it is possible to reduce the number of steps and costs. [Example]

[0039] (Configuration of semiconductor device 101) FIG. 7 shows a schematic cross-sectional view of a semiconductor device 101 according to a second embodiment. The semiconductor device 101 is a lateral MOSFET with a planar gate. The semiconductor device 101 includes a semiconductor substrate 110. The semiconductor substrate 110 is a heavily doped n-type (n + The drain layer 111a is made of low-concentration n-type (n-type) GaN. - The drift layer 111b is made of low-concentration p-type (p - In this example, the magnesium concentration of the body layer 112 is 1×10 18 cm -3 It was decided.

[0040] An n-type GaN source region 116 and drain region 117 are disposed on the upper part of the body layer 112. The source region 116 and drain region 117 are regions formed by ion implantation and are regions exposed on part of the surface of the semiconductor substrate 110. A gate insulating film 119 and a gate electrode 118 are disposed in the region between the source region 116 and the drain region 117. The gate electrode 118 is disposed on the upper surface of the body layer 112 with the gate insulating film 119 interposed therebetween.

[0041] An intermediate layer 113 is disposed in a region of the body layer 112 exposed on the surface of the semiconductor substrate 110 where the gate insulating film 119 is not disposed. The structure of the intermediate layer 113 is similar to that of the intermediate layer 13 in Example 1, and therefore a description thereof will be omitted.

[0042] The source electrode 114s is in contact with the upper surface of the source region 116 and the upper surface of the intermediate layer 113. That is, the source electrode 114s is disposed across the source region 116 and the body layer 112. The intermediate layer 113 is disposed between the source electrode 114s and the body layer 112. On the other hand, the intermediate layer 113 is not disposed between the source electrode 114s and the source region 116. A body contact BC is formed by the contact region between the source electrode 114s and the body layer 112. The function of the body contact BC is well known, so a description thereof will be omitted.

[0043] Similarly, the drain electrode 114d is disposed across the drain region 117 and the body layer 112. An intermediate layer 113 is disposed between the drain electrode 114d and the body layer 112. On the other hand, no intermediate layer 113 is disposed between the drain electrode 114d and the drain region 117. A body contact BC is formed by the contact region between the drain electrode 114d and the body layer 112.

[0044] (Method of manufacturing the semiconductor device 101) A method for manufacturing the semiconductor device 101 will be described with reference to the flowchart of FIG. 8 and the cross-sectional schematic diagram of FIG. 9. In step S11, a semiconductor substrate 110 is formed. Specifically, a drift layer 111b and a body layer 112 are epitaxially grown on a drain layer 111a. In step S12, a source region 116 and a drain region 117 are formed. Specifically, silicon or germanium ions are implanted into the body layer 112 through a mask having openings corresponding to the source region 116 and the drain region 117.

[0045] In step S13, a gate electrode formation process is performed. Specifically, a gate electrode 118 is formed on the upper surface of the body layer 112 in a region between the source region 116 and the drain region 117, with a gate insulating film 119 interposed therebetween. The gate insulating film 119 is an insulating film formed by depositing SiO2, Al2O3, or the like by atomic deposition or the like. The gate electrode 118 is polysilicon doped with impurities such as boron. The gate electrode 118 can be formed using well-known photolithography techniques and dry etching processes.

[0046] In step S14, a magnesium layer formation process is performed. Specifically, a mask layer having an opening corresponding to a specific region is formed. The specific region is a region where the magnesium layer 113A is to be formed. In this embodiment, the specific region is a region where the body contact BC is to be formed. Next, magnesium is deposited through the mask layer. Finally, the mask layer is removed. As a result, as shown in FIG. 9, the magnesium layer 113A is selectively formed on the surface of the body layer 112. The magnesium layer 113A is not formed on the surfaces of the source region 116 and the drain region 117. Note that the structure of the magnesium layer 113A is similar to that of the magnesium layer 13A in Example 1, and therefore a description thereof will be omitted.

[0047] In step S15, an annealing step is performed. Specifically, the semiconductor substrate 110 on which the magnesium layer 113A is formed is annealed in an atmosphere containing nitrogen. The details of the annealing step are the same as those of step S3 in Example 1, and therefore a description thereof will be omitted. This allows the magnesium layer 113A to be transformed into the intermediate layer 113, which is made of magnesium nitride. Note that the structure of the intermediate layer 113 is the same as that of the intermediate layer 13 in Example 1, and therefore a description thereof will be omitted.

[0048] Step S16 is a step of reducing the film thickness of the intermediate layer 113. The content of this step is the same as step S4 in the first embodiment, and therefore a description thereof will be omitted.

[0049] In step S17, an electrode formation process is performed. Specifically, a metal layer is deposited. Next, using well-known photolithography and dry etching, the metal layer is processed into a source electrode 114s and a drain electrode 114d. The source electrode 114s is formed so as to extend between the intermediate layer 113 formed in the body layer 112 and the source region 116. The drain electrode 114d is formed so as to extend between the intermediate layer 113 formed in the body layer 112 and the drain region 117. This completes the semiconductor device 101 shown in FIG. 7.

[0050] (effect) The problem will be explained using a semiconductor device 201 of a comparative example in FIG. 10. The semiconductor device 201 of the comparative example differs from the semiconductor device 101 of Example 2 (FIG. 7) only in that the intermediate layer 113 is replaced with a contact layer 213. The contact layer 213 is a high-concentration p-type (p + The body layer 112 of the MOSFET is a GaN layer having a magnesium concentration controlled (for example, 1×10 16 ~1×10 20 cm -3 To achieve this, a high-concentration p-type GaN layer (contact layer 213) must be interposed between the body contact BC and the body layer 112 to reduce the contact resistance and form an ohmic contact. A typical method for forming this contact layer 213 involves regrowing the contact layer 213 over the entire surface of the body layer 112, and then removing the contact layer 213 in the opening region R1 by dry etching. However, this regrowth process introduces a Si pile-up layer SL at the interface between the contact layer 213 and the body layer 112. This makes it difficult to reduce the contact resistance of the body contact BC and form an ohmic contact. Furthermore, dry etching can cause a damaged layer DL to form in the channel, potentially degrading device characteristics.

[0051] In the semiconductor device 101 (FIG. 7) of this embodiment, an intermediate layer 113 (magnesium nitride) is disposed in the region where the body contact BC is to be formed. Since regrowth of a high-concentration p-type GaN layer is not required, a Si pile-up layer SL is not formed. It is possible to reduce the contact resistance of the body contact BC and form an ohmic contact. Furthermore, by using lithography technology, the intermediate layer 113 can be selectively formed in the region where the body contact BC is to be formed. Since the process of removing the intermediate layer 113 by dry etching is not required, a damaged layer DL is not formed in the channel. Degradation of device characteristics can be suppressed.

[0052] Furthermore, the intermediate layer 113 (magnesium nitride) increases the contact resistance with n-type GaN. The semiconductor device 101 (FIG. 7) of this embodiment is structured so that the intermediate layer 113 is not disposed between the source region 116 and the source electrode 114s, and between the drain region 117 and the drain electrode 114d. This makes it possible to suppress an increase in contact resistance.

[0053] Although specific examples of the present invention have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and variations of the specific examples exemplified above. The technical elements described in this specification or drawings exhibit technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technology exemplified in this specification or drawings can achieve multiple objectives simultaneously, and achieving one of these objectives alone is technically useful.

[0054] (Variation) The steps of reducing the thickness of the intermediate layer (steps S4 and S16) can be omitted.

[0055] The magnesium nitride (MgNx) that forms the intermediate layers 13 and 113 may contain other elements such as fluorine and oxygen.

[0056] The device structure to which the technology of this specification can be applied is not limited to the lateral MOSFET shown in Example 2. The technology of this specification can be applied to various device structures. For example, the technology may be applied to a vertical MOSFET with a trench gate, a superjunction MOSFET, a PN diode, a heterojunction bipolar transistor (HBT), a HEMT, etc.

[0057] The nitride semiconductor to which the technology of this specification can be applied is not limited to GaN, but may be, for example, AlGaN (aluminum gallium nitride), AlN (aluminum nitride), InN (indium nitride), InGaN (indium gallium nitride), or a mixed crystal thereof.

[0058] The heating method used in the annealing process (steps S3 and S15) may be various methods. For example, lamp heating, heater heating, high frequency heating, etc. may be used. Furthermore, the atmosphere in the annealing process is not limited to a pure nitrogen atmosphere, and may be a mixture of, for example, H2, NH3, Ar, Xe, He, Ne, etc. [Explanation of symbols]

[0059] 1, 101: semiconductor device 10, 110: semiconductor substrate 11: GaN substrate 12: p-type GaN layer 13: intermediate layer 14: electrode layer 112: body layer 113: intermediate layer 116: source region 117: drain region 114s: source electrode 114d: drain electrode 118: gate electrode 119: gate insulating film BC: body contact

Claims

1. a magnesium layer forming step of depositing a magnesium layer containing magnesium as a main component on at least a portion of a surface of a nitride semiconductor substrate having a p-type region exposed on at least a portion of the surface of the p-type region; an annealing step of annealing the nitride semiconductor substrate on which the magnesium layer is deposited in an atmosphere containing nitrogen, the annealing step transforming the magnesium layer into an intermediate layer containing magnesium and nitrogen; after the annealing step, reducing the thickness of the intermediate layer; an electrode layer forming step of forming an electrode layer on at least a part of the upper surface of the intermediate layer after the thickness has been reduced; A method for manufacturing a nitride semiconductor device, comprising:

2. The impurity concentration of the p-type region is 1×10 １６ ~1 x 10 ２０ cm －３ 2. The method for manufacturing a nitride semiconductor device according to claim 1, wherein the thickness of the nitride semiconductor layer is in the range of 100 nm to 150 nm.

3. The magnesium layer forming step includes:

3. The method for manufacturing a nitride semiconductor device according to claim 1, wherein said magnesium layer is selectively deposited on at least a specific region on a surface of said p-type region.

4. The magnesium layer forming step includes: forming a mask layer on a surface of the nitride semiconductor substrate, the mask layer having an opening corresponding to the specific region; depositing the magnesium layer through the mask layer; The method for manufacturing a nitride semiconductor device according to claim 3 , comprising:

5. an n-type region is exposed on a portion of the surface of the nitride semiconductor substrate; the magnesium layer forming step includes depositing the magnesium layer on at least a portion of a surface of the p-type region but not on a surface of the n-type region; 5. The method for manufacturing a nitride semiconductor device according to claim 3, wherein said electrode layer forming step forms said electrode layer so as to extend between said intermediate layer formed in said p-type region and said n-type region.

6. 6. The method for manufacturing a nitride semiconductor device according to claim 1, wherein the nitride semiconductor substrate is made of gallium nitride.

Images