wiring board

Abstract

To provide a wiring board which can improve connection reliability when being connected to a semiconductor chip.SOLUTION: A wiring board has: a plurality of pads and a plurality of insulating layers which are alternately laminated; and via wiring which penetrates each of the insulating layers and are vertically laminated via each of the pads so as to connect the pads to each other. The plurality of pads has: a first pad which is provided on a top layer of the insulating layers so as to be located on the top layer electrically connected to a semiconductor chip; a second pad provided on the insulating layer which is a layer lower than that of the first pad; and a third pad provided on the insulating layer which is a layer lower than that of the second pad. The insulating layer located between the first pad and the second pad is thicker than the insulating layer located between the second pad and the third pad.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a wiring board. [Background technology]

[0002] Conventionally, wiring boards having a plurality of pads and a plurality of insulating layers stacked alternately have been known. This type of wiring board has, for example, a so-called stacked via structure in which via wirings are stacked vertically through each insulating layer and each pad. Furthermore, for example, a plurality of solder bumps to be connected to a semiconductor chip are formed on the pads on the top layer of the stacked via structure (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent No. 3786894 Summary of the Invention [Problem to be solved by the invention]

[0004] In the wiring board described in Patent Document 1, each insulating layer has roughly the same thickness, and therefore the via wiring also has roughly the same thickness. If the via wiring formed in each insulating layer has the same thickness, a recess may be formed on the top surface of the pad on the top layer. In such a case, depending on the depth of the recess, the height of the solder bump may vary, making it difficult to ensure the reliability of the connection between the wiring board and the semiconductor chip.

[0005] The present invention has been made in view of the above points, and has as its object to provide a wiring board capable of improving connection reliability when connected to a semiconductor chip. [Means for solving the problem]

[0006] The wiring board has a plurality of pads and a plurality of insulating layers stacked alternately, and via wiring that penetrates each of the insulating layers, is stacked vertically via each of the pads, and connects each of the pads to each other, the plurality of pads having a first pad located on the uppermost insulating layer and electrically connected to a semiconductor chip, a second pad located on the insulating layer below the first pad, and a third pad located on the insulating layer below the second pad, and the thickness of the insulating layer located between the first pad and the second pad is thicker than the thickness of the insulating layer located between the second pad and the third pad. The second pad and the third pad each have a recess in the center of their upper surface that is recessed from the periphery, and the recess of the second pad is shallower than the recess of the third pad. . [Effects of the Invention]

[0007] According to the disclosed technique, it is possible to provide a wiring board that can improve connection reliability when connected to a semiconductor chip. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a partial cross-sectional view illustrating a wiring board according to a first embodiment. [Figure 2] This shows the results of examining the thickness of the insulating layer and the depth of the recess in the pad. [Figure 3] FIG. 10 is a diagram illustrating the aspect ratio of a via hole. [Figure 4] 1A to 1C are views (part 1) illustrating a manufacturing process of a wiring board according to the first embodiment. [Figure 5] 5A to 5C are diagrams illustrating the manufacturing process of the wiring board according to the first embodiment (part 2). [Figure 6] 10A to 10C are views (part 3) illustrating the manufacturing process of the wiring board according to the first embodiment. [Figure 7] FIG. 10 is a partial cross-sectional view illustrating a wiring board according to a first modified example of the first embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the drawings, the same components are denoted by the same reference numerals, and redundant explanations may be omitted.

[0010] [First embodiment] [Wiring board structure] Fig. 1 is a partial cross-sectional view illustrating a wiring board according to the first embodiment. Referring to Fig. 1, the wiring board 1 according to the first embodiment is a coreless wiring board having a wiring layer 11, an insulating layer 12, a wiring layer 13, an insulating layer 14, a wiring layer 15, an insulating layer 16, and a wiring layer 17.

[0011] In the first embodiment, for convenience, the insulating layer 16 side of the wiring board 1 is referred to as the upper side, and the insulating layer 12 side is referred to as the lower side. Also, the surface of each part facing the insulating layer 16 is referred to as the upper surface, and the surface facing the insulating layer 12 is referred to as the lower surface. However, the wiring board 1 can be used upside down or placed at any angle. Furthermore, a planar view refers to viewing an object from the normal direction to the top surface of the insulating layer 16, and a planar shape refers to the shape of the object viewed from the normal direction to the top surface of the insulating layer 16.

[0012] In the wiring board 1, the wiring layer 11 includes a pad P1. The pad P1 is a pad on the first layer. The wiring layer 11 may include a wiring pattern. The wiring layer 11 may be made of, for example, copper. The wiring layer 11 may be a laminated film including a copper layer, a gold layer, or the like. The thickness of the wiring layer 11 may be, for example, approximately 1.3 μm to 2.6 μm. In the example shown in FIG. 1, the upper and lower surfaces of the wiring layer 11 are flat and have no recesses. However, a recess may be formed on the upper surface of the wiring layer 11. The lower surface of the wiring layer 11 is exposed from the insulating layer 12. The pad P1 may be used as an external connection terminal electrically connected to, for example, another wiring board. Furthermore, as will be described later with reference to FIG. 7, the pad P1 may have multiple insulating layers and wiring layers on the lower surface side of the pad P1 and be connected via via wiring.

[0013] The insulating layer 12 is the first insulating layer (the lowest insulating layer) and is formed to cover the upper and side surfaces of the wiring layer 11 and expose the lower surface. The material of the insulating layer 12 can be, for example, a thermosetting insulating resin whose main component is an epoxy resin or a polyimide resin. The insulating resin used as the material of the insulating layer 12 may be photosensitive or non-photosensitive. The insulating layer 12 may contain a filler such as silica (SiO2).

[0014] The wiring layer 13 includes a pad P2 and a via wiring V2. The pad P2 is a pad in the second layer. The wiring layer 13 may include a wiring pattern that is not connected to the via wiring. The pad P2 is formed on the upper surface of the insulating layer 12. The via wiring V2 is filled in a via hole 12x that penetrates the insulating layer 12 and exposes the upper surface of the pad P1. The via hole 12x may be a recessed portion in the shape of an inverted truncated cone, with the diameter of the opening on the pad P2 side being larger than the diameter of the bottom of the opening formed by the upper surface of the pad P1. The diameter of the opening of the via hole 12x may be, for example, approximately 5 μm to 30 μm. The pad P2 is electrically connected to the pad P1 through the via wiring V2.

[0015] The pad P2 has a recess 13z in the center of its upper surface, recessed from the periphery. The recess 13z is, for example, bowl-shaped. Here, the bowl-shaped recess is a shape in which the depth gradually deepens from the periphery toward the center, with an R-shaped inner wall surface. The depth D1 of the recess 13z is, for example, 1 μm or more and 4 μm or less. A portion of the recess 13z may be located within the via hole 12x. Note that the depth D1 is the depth from the upper surface of the pad P2 to the deepest part of the recess 13z.

[0016] The wiring layer 13 may have a structure in which an electroplated layer 13b is laminated on a seed layer 13a. The seed layer 13a is formed on the upper surface of the insulating layer 12 located around the via hole 12x and extends to the inner wall surface and bottom surface of the via hole 12x. The electroplated layer 13b fills the via hole 12x and extends above the upper surface of the insulating layer 12.

[0017] The seed layer 13a may be a laminated film in which a titanium layer and a copper layer are laminated in this order. The electroplated layer 13b may be made of, for example, copper. The thickness of the seed layer 13a may be, for example, about 0.2 μm to 0.4 μm. The thickness of the electroplated layer 13b located above the upper surface of the insulating layer 12 may be, for example, about 1.5 μm to 2.5 μm.

[0018] Insulating layer 14 is a second insulating layer and is formed on insulating layer 12 so as to cover the top and side surfaces of pads P2 of wiring layer 13. The insulating layer 14 can be made of the same insulating resin as insulating layer 12. Insulating layer 14 may contain a filler such as silica (SiO2).

[0019] The wiring layer 15 includes a pad P3 and a via wiring V3. The pad P3 is a pad in the third layer. The wiring layer 15 may include a wiring pattern that is not connected to the via wiring. The pad P3 is formed on the upper surface of the insulating layer 14. The via wiring V3 is filled in a via hole 14x that penetrates the insulating layer 14 and exposes the upper surface of the pad P2. The via hole 14x may be a recessed portion in the shape of an inverted truncated cone, with the diameter of the opening on the pad P3 side being larger than the diameter of the bottom of the opening formed by the upper surface of the pad P2. The diameter of the opening of the via hole 14x may be, for example, approximately 5 μm to 30 μm. The pad P3 is electrically connected to the pad P2 through the via wiring V3.

[0020] The pad P3 has a recess 15z in the center of its upper surface, recessed from the periphery. The recess 15z is, for example, bowl-shaped. The depth D2 of the recess 15z is shallower than the depth D1 of the recess 13z. For example, if the depth D1 of the recess 13z is 3 μm or more, the depth D2 of the recess 15z is less than 3 μm. The depth D2 is the depth from the upper surface of the pad P3 to the deepest part of the recess 15z.

[0021] The wiring layer 15 may have a structure in which an electroplated layer 15b is stacked on a seed layer 15a, for example. The seed layer 15a is formed on the upper surface of the insulating layer 14 located around the via hole 14x and extends to the inner wall surface and bottom surface of the via hole 14x. The electroplated layer 15b fills the via hole 14x and extends above the upper surface of the insulating layer 14. The material and thickness of the seed layer 15a and the electroplated layer 15b may be the same as the material and thickness of the seed layer 13a and the electroplated layer 13b, for example.

[0022] Insulating layer 16 is the third insulating layer (the uppermost insulating layer) and is formed on insulating layer 14 so as to cover the top and side surfaces of pads P3 of wiring layer 15. The insulating layer 16 can be made of the same insulating resin as insulating layer 12. Insulating layer 16 may contain a filler such as silica (SiO2).

[0023] The wiring layer 17 includes a pad P4 and a via wiring V4. The pad P4 is a pad in the fourth layer (a pad in the uppermost layer). The wiring layer 17 may include a wiring pattern that is not connected to the via wiring. The pad P4 is formed on the upper surface of the insulating layer 16. The via wiring V4 is filled in a via hole 16x that penetrates the insulating layer 16 and exposes the upper surface of the pad P3. The via hole 16x may be a recessed portion in the shape of an inverted truncated cone, with the diameter of the opening on the pad P4 side being larger than the diameter of the bottom of the opening formed by the upper surface of the pad P3. The diameter of the opening of the via hole 16x may be, for example, approximately 5 μm to 30 μm. The pad P4 is electrically connected to the pad P3 through the via wiring V4.

[0024] The upper surface of the pad P4 is approximately flat. "Approximately flat" here means that no recesses with a depth of 20% or more of the pad height are formed on the upper surface of the pad. The pad P4 is an external connection terminal that is electrically connected to the semiconductor chip. The thickness of the pad P4 can be, for example, about 5 to 10 μm. The planar shape of the pad P4 can be, for example, a circle with a diameter of about 20 to 150 μm. The pitch of the pads P4 can be, for example, about 30 to 50 μm.

[0025] The wiring layer 17 may have a structure in which an electroplated layer 17b is stacked on a seed layer 17a, for example. The seed layer 17a is formed on the upper surface of the insulating layer 16 located around the via hole 16x and extends to the inner wall surface and bottom surface of the via hole 16x. The electroplated layer 17b fills the via hole 16x and extends above the upper surface of the insulating layer 16. The material and thickness of the seed layer 17a may be the same as those of the seed layer 13a, for example. The material of the electroplated layer 17b may be the same as those of the electroplated layer 13b, for example.

[0026] A surface treatment layer may be formed only on the top surface of the pad P4, or on the top surface and side surface of the pad P4. Examples of the surface treatment layer include an Au layer, a Ni / Au layer (a metal layer formed by laminating a Ni layer and a Au layer in this order), a Ni / Pd / Au layer (a metal layer formed by laminating a Ni layer, a Pd layer, and a Au layer in this order), and an Au / Pd / Au layer (a metal layer formed by laminating a Au layer, a Pd layer, and a Au layer in this order). Furthermore, an anti-oxidation treatment such as an organic solderability preservative (OSP) treatment may be performed on only the top surface of the pad P4, or on the top surface and side surface of the pad P4.

[0027] As described above, the wiring board 1 has a plurality of alternately stacked pads (pads P1 to P4), a plurality of insulating layers (insulating layers 12, 14, and 16), and via wirings (via wirings V2, V3, and V4) that penetrate each insulating layer, are stacked vertically through each pad, and connect each pad to each other. This structure is called a stacked via structure. The wiring board 1 may include non-stacked via wirings in any insulating layer in addition to the stacked via structure.

[0028] [Insulation layer thickness and recess depth] In wiring board 1, the multiple pads are provided on uppermost insulating layer 16 and include pad P4 located on the uppermost layer electrically connected to the semiconductor chip, pad P3 provided on insulating layer 14 below pad P4, pad P2 provided on insulating layer 12 below pad P3, and pad P1 covered by insulating layer 12 below pad P2. Thickness T3 of insulating layer 16 located between pad P4 and pad P3 is thicker than thickness T2 of insulating layer 14 located between pad P3 and pad P2.

[0029] By making the thickness T3 thicker than the thickness T2, the recess 15z of the third-layer pad P3 is shallower than the recess 13z of the second-layer pad P2. Furthermore, the top surface of the fourth-layer pad P4 is substantially flat. Even if a recess is formed on the top surface of the fourth-layer pad P4, the recess will be shallower than the recess 15z of the third-layer pad P3. Furthermore, it is preferable that the thickness T2 of the insulating layer 14 located between the pads P3 and P2 is thicker than the thickness T1 of the insulating layer 12 located between the pads P2 and P1. By making the thickness T3 thicker than the thickness T2 and the thickness T2 thicker than the thickness T1, the recess 13z can be made shallower, and therefore the recess 15z can also be made shallower, thereby making the top surface of the fourth-layer pad P4 even more flat. This is based on the inventors' findings, as described below.

[0030] Figure 2 shows the results of a study on the thickness of the insulating layer and the depth of the recessed portion of the pad. Specifically, Figures 2(a) and 2(b) are SEM photographs of the cross section of the wiring board. In Figures 2(a) and 2(b), the lower photographs are enlarged versions of the upper photographs.

[0031] In FIG. 2(a), the thickness (5.0 μm) of the second insulating layer A2 located between the second-layer pad and the third-layer pad is the same as the thickness (5.0 μm) of the first insulating layer A1 located between the first-layer pad and the second-layer pad. In FIG. 2(a), the depth of the recess in the second-layer pad formed on the first insulating layer A1 is 0 μm. Also, the depth of the recess in the third-layer pad formed on the second insulating layer A2 is 1.2 μm. Thus, when the thicknesses of the insulating layers A1 and A2 are the same, the depth of the recesses formed in the pads of each layer varies, and there is no tendency for the recesses in the pads of the upper layer to be shallower than the recesses in the pads of the lower layer.

[0032] On the other hand, in FIG. 2(b), the thickness (5.0 μm) of the second insulating layer B2 located between the second-layer pad and the third-layer pad is thicker than the thickness (4.0 μm) of the first insulating layer B1 located between the first-layer pad and the second-layer pad. In FIG. 2(b), the depth of the recess of the second-layer pad formed on the first insulating layer B1 is 2.2 μm. Also, the depth of the recess of the third-layer pad formed on the second insulating layer B2 is 0.7 μm. In this way, by making the thickness of the second insulating layer B2 located between the second-layer pad and the third-layer pad thicker than the thickness of the first insulating layer B1 located between the first-layer pad and the second-layer pad, the recess of the upper layer pad can be made shallower than the recess of the lower layer pad.

[0033] Some pads connected to semiconductor chips are formed on via holes, such as pad P4 shown in FIG. 1 , while others are formed on the top surface of the insulating layer in locations where no via holes are formed. Pads formed on the top surface of the insulating layer in locations where no via holes are formed do not have recesses formed on their top surfaces. Therefore, if recesses are formed on the top surface of pad P4, variations in height from the top surface of insulating layer 16 occur between the pads. When variations in height occur between pads, the amount of solder applied to low-height pads becomes insufficient when mounting a semiconductor chip on the wiring substrate, making it difficult to ensure reliable connection between the wiring substrate and the semiconductor chip. By making the top surface of pad P4 substantially flat on wiring substrate 1, variations in height between pads are suppressed, thereby improving the reliability of connection between the wiring substrate 1 and the semiconductor chip when mounting the semiconductor chip on the wiring substrate 1. Note that even if recesses less than 2.0 μm deep are formed on the top surface of pad P4, they do not significantly affect the reliability of connection between the wiring substrate and the semiconductor chip.

[0034] While the wiring board 1 has three insulating layers and four pad layers, in a wiring board having two insulating layers and three pad layers, the pads on the third layer are the pads on the top layer connected to the semiconductor chip. Therefore, by making the thickness of the second insulating layer located between the pads on the second layer and the pads on the third layer thicker than the thickness of the first insulating layer located between the pads on the first layer and the pads on the second layer, the recesses of the pads on the top layer become shallower, and the variation in height between the pads can be suppressed.

[0035] Furthermore, in a wiring board having n insulating layers and n+1 pads, where n is an integer equal to or greater than 3, the thickness of the nth insulating layer located between the nth pad and the n+1th pad can be made thicker than the thickness of the n-1th insulating layer located between the n-1th pad and the nth pad. This makes the recesses of the pads on the top layer shallower, thereby suppressing variations in height between the pads.

[0036] The inventors also studied the relationship between the aspect ratio of a via hole (via wiring) and the recess of a pad. As shown in Figure 3, the aspect ratio of a via hole (via wiring) is defined as D / W, which is the maximum width W and maximum depth D of the opening. According to the inventors' study, the lower the aspect ratio D / W of a via hole, the deeper the recess on the top surface of the pad formed on the via hole. In other words, by increasing the aspect ratio D / W, the depth of the recess on the top surface of the pad formed on the via hole becomes shallower, and in some cases no recess is formed.

[0037] Furthermore, according to the inventors' investigations, when the aspect ratio D / W is less than 0.4, a recess is often formed on the upper surface of the pad formed on the via hole. Therefore, it is preferable that the aspect ratio D / W of each via hole (via wiring) increases from the lower insulating layer side to the uppermost insulating layer side, and it is preferable that the aspect ratio D / W of the via hole (via wiring) provided in the uppermost insulating layer is 0.4 or more. By doing so, the upper surface of the pad formed on the via hole can be made approximately flat, and height variations between pads can be suppressed, thereby ensuring connection reliability between the wiring substrate and the semiconductor chip when the semiconductor chip is mounted on the wiring substrate.

[0038] In addition, when the thickness of each wiring layer is the same and the maximum width W of the opening of the via hole formed in each insulating layer is the same, increasing the aspect ratio D / W is synonymous with thickening the insulating layer.

[0039] [Method of manufacturing wiring board] 4 to 6 are diagrams illustrating the manufacturing process of the wiring board according to the first embodiment.

[0040] First, in the step shown in FIG. 4(a), a support 500 is prepared, and a wiring layer 11 including a pad P1 is formed on the upper surface of the support 500. The support 500 can be a metal plate, a silicon plate, a glass plate, or the like. To form the wiring layer 11 including the pad P1, for example, copper foil is placed on the upper surface of the support 500, and an etching mask of a predetermined shape is further placed on the copper foil, and the copper foil is etched. When the support 500 is a metal plate, the wiring layer 11 including the pad P1 may be formed by electrolytic plating using the metal plate as a power supply layer.

[0041] 4(b), an insulating layer 12 is formed on the upper surface of the support 500 so as to cover the wiring layer 11 including the pads P1. Specifically, for example, a thermosetting film-like insulating resin containing an epoxy resin as a main component is prepared as the insulating layer 12, and laminated on the upper surface of the support 500 so as to cover the wiring layer 11 including the pads P1. Then, while pressing the laminated insulating layer 12, the insulating layer 12 is heated to a curing temperature or higher to be cured.

[0042] Alternatively, as the material for the insulating layer 12, for example, an insulating resin containing a thermosetting liquid or paste-like epoxy resin as a main component is prepared and applied by a spin coating method or the like to the upper surface of the support 500 so as to cover the wiring layer 11 including the pads P1. Then, the applied insulating resin is heated to a curing temperature or higher to be cured, thereby forming the insulating layer 12.

[0043] Next, in the step shown in FIG. 4(c), a via hole 12x is formed in the insulating layer 12, penetrating the insulating layer 12 and exposing the upper surface of the pad P1. The via hole 12x can be formed by laser processing using, for example, a CO2 laser. The via hole 12x formed by laser processing has an inverted truncated cone-shaped recess, with the diameter of the opening on the side where the pad P2 is formed being larger than the diameter of the bottom of the opening formed by the upper surface of the pad P1. Note that other via holes also have a similar shape when formed by laser processing. When the via hole 12x is formed by laser processing, it is preferable to perform a desmearing process to remove resin residue from the insulating layer 12 that is attached to the upper surface of the pad P1 exposed at the bottom of the via hole 12x.

[0044] 5(a) to 5(c), a wiring layer 13 including a pad P2 and a via wiring V2 is formed on the insulating layer 12. The pad P2 is electrically connected to the pad P1 through the via wiring V2. The wiring layer 13 including the pad P2 and the via wiring V2 can be formed using, for example, a semi-additive method.

[0045] Specifically, first, as shown in FIG. 5(a), a seed layer 13a is formed on the insulating layer 12 including the upper surface of the pad P1 exposed at the bottom of the via hole 12x and the inner wall surface of the via hole 12x by electroless plating or sputtering.

[0046] 5(b), a resist layer 510 having openings 510x corresponding to the wiring layer 13 is formed on the seed layer 13a. Then, by electrolytic plating using the seed layer 13a as a power supply layer, an electrolytic plated layer 13b is formed in the openings 510x of the resist layer 510. A recess 13z recessed from the peripheral edge is formed in the center of the upper surface of the electrolytic plated layer 13b.

[0047] 5(c), after removing the resist layer 510, the seed layer 13a that is not covered with the electroplated layer 13b is etched away using the electroplated layer 13b as a mask. This forms the wiring layer 13 in which the electroplated layer 13b is stacked on the seed layer 13a. The materials and thicknesses of the seed layer 13a and the electroplated layer 13b are as described above.

[0048] 6(a), an insulating layer 14 is formed on the upper surface of the insulating layer 12 so as to cover the pad P2, similar to FIG. 4(b). Then, a via hole 14x is formed in the insulating layer 14 so as to penetrate the insulating layer 14 and expose the upper surface of the pad P2, similar to FIG. 4(c).

[0049] The insulating layer 14 is formed to be thicker than the insulating layer 12. For example, a thermosetting insulating resin film made of an epoxy resin as a main component and thicker than the insulating layer 12 is prepared as the insulating layer 14, and laminated on the upper surface of the insulating layer 12 so as to cover the pad P2. Then, while pressing the laminated insulating layer 14, the insulating layer 14 is heated to a curing temperature or higher to be cured.

[0050] Alternatively, an insulating resin containing, for example, a thermosetting liquid or paste-like epoxy resin as a main component is prepared as the material for insulating layer 14, and is applied to the upper surface of insulating layer 12 by spin coating or the like so as to cover pad P2. The applied insulating resin is then heated to a curing temperature or higher to be cured, thereby forming insulating layer 14. At this time, by reducing the rotation speed when applying the insulating resin by spin coating or the like, it is possible to form insulating layer 14 that is thicker than insulating layer 12.

[0051] Next, in the step shown in Fig. 6(b), similar to Figs. 5(a) to 5(c), a wiring layer 15 including a pad P3 and a via wiring V3 is formed on the insulating layer 14. The pad P3 is electrically connected to the pad P2 through the via wiring V3. A recess 15z recessed from the peripheral edge is formed in the center of the upper surface of the electroplated layer 15b. The depth of the recess 15z is shallower than the depth of the recess 13z.

[0052] Next, in the step shown in FIG. 6(c), an insulating layer 16 is formed on the upper surface of the insulating layer 14 so as to cover the pad P3, similarly to FIG. 6(a). Then, a via hole 16x is formed in the insulating layer 16 so as to penetrate the insulating layer 16 and expose the upper surface of the pad P3. The insulating layer 16 is formed to the same thickness as the insulating layer 14, or to be thicker than the insulating layer 14. The thickness of the insulating layer 16 can be adjusted by a method similar to that of the step shown in FIG. 4(a).

[0053] 6(c), a wiring layer 17 including pads P4 and via wirings V4 is formed on the insulating layer 16 in the same manner as in FIGS. 3(a) to 3(c). Then, the support 500 is removed to complete the wiring substrate 1. The support 500 may be removed by mechanical peeling, etching, or the like.

[0054] <Modification 1 of the First Embodiment> In Modification 1 of the first embodiment, an example of a wiring substrate having an insulating layer and a wiring layer below the pad P1 in Fig. 1 is shown. Note that in Modification 1 of the first embodiment, the description of the same components as those in the already described embodiments may be omitted.

[0055] 7 is a partial cross-sectional view illustrating a wiring board according to Modification 1 of the first embodiment. Referring to Fig. 7, wiring board 1A according to Modification 1 of the first embodiment has wiring structure 21, solder resist layer 22 laminated below wiring structure 21, and wiring structure 23 laminated above wiring structure 21. Wiring board 1A may have a solder resist layer on insulating layer 16 of wiring structure 23 that exposes wiring layer 17.

[0056] 1, except that the wiring layer 11 is replaced with a structure in which an electroplated layer 11b is stacked on a seed layer 11a. The line and space (L / S) of the wiring layers 11, 13, 15, and 17 of the wiring structure 23 can be, for example, approximately 2 μm / 2 μm to 3 μm / 3 μm. Here, the line and space (L / S) refers to the width of the wiring and the distance between adjacent wirings.

[0057] The wiring structure 21 is a low-density wiring layer formed with a wiring layer having a lower wiring density than the wiring structure 23. The wiring structure 21 has one insulating layer 30, a wiring layer 31, and via wiring V1 penetrating the insulating layer 30 in the thickness direction.

[0058] The wiring layer 31 includes a pad P0. The wiring layer 31 may include a wiring pattern. The wiring layer 31 may be made of, for example, copper or a copper alloy. The thickness of the wiring layer 31 may be, for example, about 15 μm to 20 μm. The line and space (L / S) of the wiring layer 31 may be, for example, about 20 μm / 20 μm. In the example of FIG. 7, the upper and lower surfaces of the wiring layer 31 are flat surfaces and no recesses are formed thereon. However, a recess may be formed on the upper surface of the wiring layer 31. The lower surface of the wiring layer 31 is exposed from the insulating layer 30. The pad P0 may be used as an external connection terminal for electrical connection to, for example, another wiring board or the like.

[0059] The insulating layer 30 is formed to cover the upper and side surfaces of the wiring layer 31 and expose the lower surface. The insulating layer 30 may be made of a thermosetting insulating resin whose main component is, for example, an epoxy resin, a polyimide resin, or a cyanate resin. The insulating layer 30 may be made of a so-called glass epoxy resin substrate, which is made by impregnating a reinforcing material, glass cloth (woven glass fabric), with a thermosetting insulating resin whose main component is an epoxy resin and then curing the impregnated material. The insulating layer 30 may contain a filler such as silica (SiO2).

[0060] A via hole 30x is formed in the insulating layer 30, opening on the pad P1 side and penetrating the insulating layer 30 in the thickness direction to expose a portion of the upper surface of the wiring layer 31. The via hole 30x may be a recessed portion in the shape of an inverted truncated cone, with the diameter of the opening on the pad P1 side being larger than the diameter of the bottom of the opening formed by the upper surface of the wiring layer 31. The diameter of the opening of the via hole 30x may be, for example, approximately 50 μm to 100 μm. The pad P1 is electrically connected to the pad P0 through a via wiring V1 filling the via hole 30x.

[0061] The upper end surface of the via wiring V1 is exposed from the upper surface of the insulating layer 30. For example, the upper end surface of the via wiring V1 is formed to be substantially flush with the upper surface of the insulating layer 30. The upper end surface of the via wiring V1 is a smooth surface (low roughness surface) with few irregularities, similar to the upper surface of the insulating layer 30. For example, the upper end surface of the via wiring V1 is a polished surface. The roughness of the upper end surface of the via wiring V1 is set to be, for example, about 15 to 40 nm in terms of surface roughness Ra value.

[0062] The lower end surface of the via wiring V1 is directly connected to a part of the upper surface of the wiring layer 31. That is, a part of the upper surface of the wiring layer 31 and the lower end surface of the via wiring V1 are in contact with each other, and the wiring layer 31 and the via wiring V1 are electrically connected. In other words, the wiring layer 31 and the via wiring V1 are electrically connected, but are not integral with each other, but are formed separately. Note that the material of the via wiring V1 can be, for example, copper or a copper alloy.

[0063] The solder resist layer 22 is laminated on the lower surface of the insulating layer 30 so as to cover the wiring layer 31. Openings 22x are formed in the solder resist layer 22 to expose parts of the wiring layer 31 as external connection pads P0. If necessary, a surface treatment layer 25 is formed on the surfaces of the pads P0 exposed from the openings 22x. The surface treatment layer 25 is the same as the above-mentioned metal layer or anti-oxidation treatment such as OSP treatment.

[0064] To manufacture the wiring board 1A, first, a wiring layer 31 including pads P0 is formed on the upper surface of a support 500, similar to Fig. 4(a). Next, an insulating layer 30 is formed on the upper surface of the support 500 so as to cover the wiring layer 31 including pads P0, similar to Fig. 4(b). Next, a via hole 30x is formed in the insulating layer 30, penetrating the insulating layer 30 and exposing the upper surface of the pad P0, similar to Fig. 4(c).

[0065] Next, a conductive layer is formed by, for example, a semi-additive method, filling the via holes 30x and covering the entire upper surface of the insulating layer 30. Subsequently, by, for example, a CMP (Chemical Mechanical Polishing) method, the conductive layer protruding from the upper surface of the insulating layer 30 is polished, and a portion of the upper surface of the insulating layer 30 is polished. As a result, a via wiring V1 is formed filling the via holes 30x, and the upper end surface of the via wiring V1 and the upper surface of the insulating layer 30 become approximately flush with each other. Furthermore, by polishing a portion of the upper surface of the insulating layer 30, the upper surface of the insulating layer 30 is smoothed. For example, while the roughness of the upper surface of the insulating layer 30 before polishing is approximately 300 to 400 nm in terms of surface roughness Ra, the roughness of the upper surface of the insulating layer 30 can be reduced to approximately 15 to 40 nm in terms of surface roughness Ra after polishing.

[0066] Next, a wiring layer 11 including a pad P1 connected to the via wiring V1 is formed on the upper surface of the insulating layer 30, for example, by a semi-additive method. The wiring layer 11 has a structure in which an electrolytic plating layer 11b is laminated on a seed layer 11a. Next, after performing the same steps as those shown in FIGS. 4(b) to 6(c), a wiring layer 17 including a pad P4 and a via wiring V4 is formed on the insulating layer 16 in the same manner as those shown in FIGS. 3(a) to 3(c). Then, the support 500 is removed, and a solder resist layer 22 having an opening 22x that exposes a portion of the pad P0 is formed on the lower surface of the insulating layer 30. This completes the wiring board 1A.

[0067] In this way, an insulating layer or a wiring layer may be further provided below the pad P1. In this case, by setting T1, T2, and T3 in the same relationship as in the first embodiment, the recess 15z of the pad P3 becomes shallower than the recess 13z of the pad P2, and the upper surface of the pad P4 becomes approximately flat. Note that, although the example of FIG. 7 shows an example in which the pad P0 and the via wiring V1 are separate bodies, the pad P0 and the via wiring V1 may be formed integrally.

[0068] Although the preferred embodiments have been described in detail above, the present invention is not limited to the above-described embodiments, and various modifications and substitutions can be made to the above-described embodiments without departing from the scope of the claims.

[0069] For example, although the above embodiment has been described with respect to a coreless wiring board, the present invention can also be applied to a wiring board having a core board. In this case, the wiring layer closest to the core board is the first wiring layer (lowest wiring layer), and the insulating layer closest to the core board is the first insulating layer (lowest insulating layer). [Explanation of symbols]

[0070] 1,1A wiring board 11,13,15,17,31 wiring layer 12, 14, 16, 30 Insulating layer 12x, 14x, 16x, 30x via holes 13a, 15a, 17a seed layer 13b, 15b, 17b Electroplated layer 13z,15z recess 21,23 Wiring structure 22 Solder resist layer 22x opening 25 Surface treatment layer 500 support 510 Resist layer 510x aperture I1, I2, I3, I4 insulating layers P0, P1, P2, P3, P4 pads V1, V2, V3, V4 via wiring

Claims

1. A plurality of pads and a plurality of insulating layers stacked alternately; via wirings that penetrate each of the insulating layers, are stacked vertically through each of the pads, and connect each of the pads to each other; The plurality of pads include: a first pad located on the uppermost insulating layer and electrically connected to the semiconductor chip; a second pad provided on the insulating layer below the first pad; a third pad provided on the insulating layer below the second pad, a thickness of the insulating layer located between the first pad and the second pad is greater than a thickness of the insulating layer located between the second pad and the third pad; the second pad and the third pad have a recess in the center of their upper surfaces that is recessed from their peripheral edges, The recess of the second pad is shallower than the recess of the third pad.

2. a fourth pad covered by the insulating layer below the third pad; 2. The wiring board according to claim 1, wherein the thickness of the insulating layer located between the second pad and the third pad is thicker than the thickness of the insulating layer located between the third pad and the fourth pad.

3. 2. The wiring board according to claim 1, wherein the aspect ratio of the via wiring provided in the uppermost insulating layer is 0.4 or more.

4. 4. The wiring board according to claim 3, wherein the aspect ratio of each of the via wirings increases from the lower insulating layer side to the uppermost insulating layer side.

5. A plurality of pads and a plurality of insulating layers stacked alternately; via wirings that penetrate each of the insulating layers, are stacked vertically through each of the pads, and connect each of the pads to each other; When the number of laminations of the insulating layers is n, and n is an integer of 3 or more, the thickness of the n-th insulating layer located between the n-th pad and the n+1-th pad is greater than the thickness of the n-1-th insulating layer located between the n-1-th pad and the n-th pad; the pads in the n-th layer and the pads in the (n-1)-th layer have recesses in the central portions of their upper surfaces that are recessed from their peripheral portions, The recess of the pad in the nth layer is shallower than the recess of the pad in the (n-1)th layer.

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