Vector instruction processing method

Abstract

To solve the problem that it is impossible to increase the speed of vector instruction processing.SOLUTION: A vector instruction processing apparatus 100 of the present invention comprises: a writing unit 101 which writes a vector instruction included in loops to be executed repeatedly to mutually different reservation stations 110 corresponding to the respective loops; and a vector execution unit 102 which executes the vector instruction issued from the individual reservation stations 110.SELECTED DRAWING: Figure 10

Description

Technical Field

[0001] The present invention relates to a vector instruction processing method, a vector instruction processing device, and a program.

Background Art

[0002] In one loop of a typical vector program, the vector register is loaded within the loop (including operations with scalar registers), vector operations are performed, and the result is written back to the memory. For example, in the program shown in FIG. 1, two vector load instructions are executed to read values (lines 5 and 11), the values of the two vector registers are vector-added (line 12), and finally the result is written with a vector store instruction (line 13). And this operation is looped.

[0003] The vector program shown in FIG. 1 is the simplest example, but in reality, as in the vector program shown in FIG. 2, it often executes a plurality of vector load instructions and a plurality of vector operation instructions, and finally writes the result. However, here, for the sake of easy explanation, one loop is set as 11 vector instructions, but a longer vector instruction sequence may be set as one set. In the programs of FIGS. 1 and 2, it is assumed that an operand starting with v is a vector register and an operand starting with s is a scalar register.

[0004] At this time, due to the following three reasons, bubbles (gaps) may occur in the pipeline. (1) Since the latency of vector load is long, operations using the data cannot be executed until the memory load is completed. (2) Since multiple TATs are also required for operations, the next instruction with a dependency cannot be immediately issued. (3) Due to the limitation of the read port of the vector register, it takes time to read the operand, so the immediate instruction cannot be executed.

[0005] Specifically, looking at the program in Figure 2, (1) above applies to the vector load instructions on lines 20, 22, 24, and 26. In other words, vector load instructions sometimes read data from memory, which can take tens of clock cycles. At this time, vector operation instructions that use that data will also be delayed. Furthermore, the vector store instruction (line 30) that writes the result of the operation will also be unable to execute. Also, (2) above is the operation TAT, and in particular, multiplication (lines 23 and 29), multiply-accumulate operations (line 27), and division / modulo operations (not shown in Figure 2), which require multiple clock cycles, take time to get the result, so subsequent instructions that use that result will also be delayed. Also, (3) above is the read port constraint, and in operations such as multiply-accumulate operations (line 27) that require three operands, the data cannot be read in one clock cycle, resulting in a delay.

[0006] Furthermore, to address the aforementioned problem, namely the bubbles (gaps) in the pipeline, there is a technique called out-of-order issuance using a reservation station. This technique typically uses register renaming technology in conjunction with other techniques to eliminate inverse and output dependencies between registers, enabling more out-of-order issuance. As a result, the bubbles in the pipeline can be reduced. As an example, in the vector operation unit 2 shown in Figure 3, renaming is performed by the renaming control circuit 22, and out-of-order issuance is realized by the vector reservation station 23. As a related technique, the vector instruction overtaking determination method described in Patent Document 1 is also disclosed. [Prior art documents] [Patent Documents]

[0007] [Patent Document 1] Japanese Patent Publication No. 2010-198439 [Overview of the project] [Problems that the invention aims to solve]

[0008] However, even with the reservation station technology described above, it is not possible to issue more instructions than the number of entries in the reservation station. In particular, as in problem (1) above, the latency of vector load instructions is large, and combined with the other two problems (2) and (3) above, the reservation station is often full with instructions that cannot be issued, and there is a limit to the number of instructions that can be issued out of order.

[0009] One might consider logically mitigating the above problem by increasing the number of entries in the reservation station, thereby increasing the number of instructions that can be issued out of order. However, in that case, out-of-order issuance would occur from a large number of entries, and since logic circuits are required to find an instruction that can be issued from a large number of entries, this would affect the delay of the logic circuits. Therefore, there is a physical limit to expanding the number of entries.

[0010] Based on the above, there remains a problem in that it is still not possible to speed up vector instruction processing.

[0011] Therefore, the object of the present invention is to provide a vector instruction processing method, a vector instruction processing device, and a program that can solve the above-mentioned problems. [Means for solving the problem]

[0012] One embodiment of the present invention is a vector instruction processing method, The vector instructions included in the repeatedly executed loop are written to a different reservation station corresponding to each loop. Each of the aforementioned reservation stations executes the aforementioned vector instruction issued from each of the aforementioned reservation stations. This is the structure it takes.

[0013] Furthermore, a vector instruction processing device, which is one embodiment of the present invention, A writing unit that writes vector instructions included in a loop that is executed repeatedly to a different reservation station corresponding to each loop, A vector execution unit that executes the vector instructions issued from each of the reservation stations, Equipped with, This is the structure it takes.

[0014] Furthermore, a vector instruction processing system, which is one embodiment of the present invention, The system includes a conversion device that divides loops containing vector instructions into multiple loops where the vector instructions are not dependent on each other, and assigns a unique identifier to each of them, A vector instruction processing device comprising: a writing unit that writes the vector instructions included in each of the multiple divided loops to a different reservation station corresponding to each loop, based on the identifier assigned to each of the multiple divided loops; and a vector execution unit that executes the vector instructions issued from each of the reservation stations, respectively. This is the structure it takes.

[0015] Furthermore, a program, which is one embodiment of the present invention, In the processor, The vector instructions included in the repeatedly executed loop are written to a different reservation station corresponding to each loop. Each of the aforementioned reservation stations executes the aforementioned vector instruction issued from each of the aforementioned reservation stations. To execute the process This is the structure it takes. [Effects of the Invention]

[0016] By configuring the present invention as described above, it is possible to speed up vector instruction processing. [Brief explanation of the drawing]

[0017] [Figure 1]This is a diagram for explaining the background art of the present invention. [Figure 2] This is a diagram for explaining the background art of the present invention. [Figure 3] This is a diagram for explaining the background art of the present invention. [Figure 4] This is a diagram showing an example of a vector program exemplified in Embodiment 1 of the present invention. [Figure 5] This is a block diagram showing the configuration of a vector instruction processing system in Embodiment 1 of the present invention. [Figure 6] This is a flowchart showing the operation of the vector instruction processing apparatus disclosed in FIG. 1. [Figure 7] This is a block diagram showing an example of the configuration of the vector execution unit disclosed in FIG. 1. [Figure 8] This is a block diagram showing the configuration of a vector instruction processing apparatus in Embodiment 2 of the present invention. [Figure 9] This is a flowchart showing the operation of a vector instruction processing method in Embodiment 2 of the present invention. [Figure 10] This is a block diagram showing the configuration of a vector instruction processing apparatus in Embodiment 3 of the present invention. [Figure 11] This is a flowchart showing the operation of a vector instruction processing method in Embodiment 3 of the present invention.

Mode for Carrying Out the Invention

[0018] <Embodiment 1> The first embodiment of the present invention will be described with reference to FIGS. 4 to 7.

[0019] Figure 4 shows an example of a vector program generated by the compiler 10 that constitutes the vector instruction processing system in the present invention. This program is based on Figure 2 described above, and such a program constitutes a loop that is executed repeatedly and includes a vector instruction. In the program shown in Figure 2, the dependencies of the vector registers are contained within one loop. That is, the processing of a loop has no dependency on the next loop, and the vector processing is independent within the loop. In such a case, it is possible to parallelize the processing of each loop.

[0020] Therefore, in this embodiment, when the vector processing is independent for each loop in the vector program, the compiler 10 divides the loop into multiple parts and assigns a thread number to each, as shown in Figure 4. Specifically, in the example in Figure 4, the loop is divided into two, with thread 0 (#0) assigned to the first loop and thread 1 (#1) assigned to the second loop. At this time, each vector instruction within each loop is also assigned a thread number (#0, #1). However, the thread number can be any information as long as it is a unique identifier that can distinguish and identify the divided loops. Note that the compiler 10 is not limited to dividing the loop of the vector program into two parts, but may divide it into any number of parts, such as four or eight. Also, although the process of assigning thread numbers described above is exemplified as being performed by the compiler 10, it may be performed by any software or conversion device such as an assembler.

[0021] Here, since the parallelization in this invention concerns vector operations, the parallelization of scalar registers must be handled separately. For example, if the scalar registers on lines 20, 24, 26, and 30 of the program shown in Figure 4 require independent values ​​for each loop, then a different scalar register must be specified for each thread. In the example in Figure 4, this is resolved in lines 5 through 8. Note that if the scalar registers on lines 22 and 28 are assumed to be common between loops, then it is not necessary to define independent values ​​for each loop.

[0022] Next, the configuration of a vector instruction processing unit that executes a vector program as shown in Figure 4 will be described. As shown in Figure 5, the vector instruction processing unit is configured to include a vector arithmetic unit 2 and a scalar arithmetic unit 1 that supplies vector instructions to the vector arithmetic unit 2.

[0023] Scalar arithmetic unit 1 is the unit that first processes the program instruction sequence. Arithmetic unit 1 decodes the instructions and also executes scalar instructions, but if the decoded instruction is a vector instruction, it sends the instruction to vector arithmetic unit 2 and delegates the subsequent processing to it.

[0024] The vector operation unit 2 comprises a vector instruction buffer 21, a renaming control circuit 22, a write control circuit 25, vector reservation stations 23A and 23B, an issue arbitration circuit 26, and a vector execution unit 24. In this embodiment, two vector reservation stations 23A and 23B are provided, corresponding to thread #0 and thread #1, respectively. However, the number of vector reservation stations is not limited to two, and more may be provided. Each component of the vector operation unit 2 may be implemented using electronic circuits, or it may be implemented by a processor executing a program. The following describes each component in detail.

[0025] The vector instruction buffer 21 is a buffer that stores instructions received from the scalar arithmetic unit 1.

[0026] When the renaming control circuit 22 (renaming unit) receives an instruction from the scalar arithmetic unit 1, it works in cooperation with the vector instruction buffer 21 to perform renaming of the vector registers. At this time, the renaming control circuit 22 performs renaming of the vector registers between multiple divided loops assigned different thread numbers.

[0027] The write control circuit 25 (writing unit) instructs the writing of commands to the vector reservation stations (reservation stations) based on instructions from the renaming control circuit 22, and determines the writing destination using the thread number assigned to each loop. In this embodiment, the write control circuit 25 writes the command for thread number #0 to vector reservation station #0 (23A) and the command for thread number #1 to vector reservation station #1 (23B). In this way, the write control circuit 25 divides the loop into multiple loops and writes to different vector reservation stations 23A and 23B corresponding to each loop. In this embodiment, the case where two vector reservation stations 23A and 23B are provided is shown as an example, but more vector reservation stations may be provided.

[0028] Here, Vector Reservation Station #0 (23A) and Vector Reservation Station #1 (23B) are the same as normal reservation stations, except that there are multiple of them. In other words, Vector Reservation Stations 23A and 23B have an out-of-order issuing function and determine which instruction to issue, prioritizing older instructions from the set of instructions that are ready to be issued (when all read operands are available). No instructions can be issued when there are no instructions that can be issued. Although there are instructions that logically refer to the same vector register number in Vector Reservation Station #0 and Vector Reservation Station #1, at this stage, as mentioned above, the registers have already been renamed by the renaming control circuit 22, so there is no physical duplication of registers.

[0029] The issuance arbitration circuit 26 (arbitration unit) is a circuit that arbitrates issuance requests from multiple vector reservation stations 23A and 23B. When there are two or more issuance requests, arbitration is performed in a round-robin manner, and issuance is permitted from the vector reservation station 23A or 23B that is arbitrated.

[0030] The vector execution unit 24 (vector execution section) processes vector instructions issued from the issuance arbitration circuit 26. This is a standard vector execution unit and performs the execution of vector load and store instructions and vector arithmetic instructions.

[0031] Next, the operation of the vector instruction processing unit described above will be explained with reference to the flowchart in Figure 6. Step S1: Issue a vector instruction from the scalar arithmetic unit. When scalar arithmetic unit 1 decodes a vector instruction, it issues the instruction to vector arithmetic unit 2. Step S2: Store the instruction in the vector instruction buffer. The vector operation unit 2 stores the vector instructions received from the scalar operation unit 1 in the vector instruction buffer 21. The vector instruction buffer 21 is a FIFO (First-In, First-Out) buffer. Step S3: Rename the register in the control circuit. The renaming control circuit 22 takes the first instruction from the vector instruction buffer 21 and renames the register.

[0032] Step S4: Write to the reservation station according to the thread number. The write control circuit 25 determines which of the reservation stations 23A or 23B to store the renamed instruction retrieved from the vector instruction buffer 21. This determination is made using the thread numbers assigned to each loop by the compiler 10 or other software. Steps S5-1, S5-2: Detect issued entries at Vector Reservation Stations #0, #1 Each vector reservation station #0 (23A) and #1 (23B) detects available instructions, and if there are available vector instructions, it requests the issuance arbitration circuit 26 to issue them. Step S6: Determine the issuance entry in the issuance mediation circuit. The issuance arbitration circuit 26 arbitrates issuance requests from two (or more) vector reservation stations 23A and 23B. The arbitration is performed using a round-robin method. Step S7: Execution unit performs memory access or vector operation. The vector execution unit 24 executes the vector instructions issued from the issuance arbitration circuit 26. The vector execution unit 24 performs vector load and store processing and vector arithmetic processing. Although steps S1 to S7 were explained above by focusing on the first instruction, in reality, they operate consecutively every clock cycle, and each step operates simultaneously in a pipeline.

[0033] As described above, in this embodiment, first, a unique identifier such as a thread number # is assigned to each divided loop by software such as the compiler 10. Then, multiple vector reservation stations 23A and 23B are installed on hardware such as the vector operation unit 2, and the vector instructions of the loop are distributed to each vector reservation station 23A and 23B according to the thread number #. This makes it possible to improve the degree of parallelism between loops and increase the sufficiency of the vector execution unit, thereby speeding up the vector operation loop.

[0034] For example, if we define one reservation station as having 32 entries, then we would have two sets of 32-entry reservation stations. This makes searching easier than having 64 entries in a single reservation station, and also avoids logical delay issues.

[0035] Then, since the highest priority instructions for each thread are retrieved from each reservation station 23A, 23B, this prevents the congestion of reservation stations that could not be avoided before, and makes it possible to improve the amount of instructions supplied to the vector execution unit.

[0036] As an application of the present invention, it is conceivable to further increase the throughput of vector instructions by effectively utilizing read ports by shifting the read ports of vector registers between threads. This will be explained with reference to Figure 7.

[0037] Typically, within the vector execution unit 24, the read ports for vector registers used by vector instructions are configured as shown in Figure 7. Here, we assume that the vector execution unit 24 has 32 VPPs (VPP0 to VPP31). VPP0 (which has 32 repetitions, so the other VPPs have a similar configuration) holds the vector mask register group VM (VM0 to VM7), the vector register group VR (VR0 to VR7), the X-BAR (crossbar), and various arithmetic units (VFMA, VALU, VRCP, VPPSP). The vector register group VR is usually used starting from VR0 of VPP0, then VR0 of VPP1, and so on, resulting in a total of 256 vector register read ports (assuming a maximum VL length of 256). When the VL length (Vector Length) is 256, all of these ports are used, but when the VL length is halved to 128, VR4 to VR7 of all VPPs will be free.

[0038] The present invention is applied to the configuration characteristics described above. Specifically, when the VL length is half, or 128 (more precisely, when it is less than half), the vector registers for thread #0 will use VR0, 1, 2, and 3, and the vector registers for thread #1 will use VR4, 5, 6, and 7. As a result, the access destinations for instructions that would originally have used the VR0, 1, 2, and 3 registers are distributed. This distribution eliminates read port contention, allows two vector instructions to be issued simultaneously, and further improves performance.

[0039] <Embodiment 2> Next, a second embodiment of the present invention will be described with reference to Figures 8 and 9. Figure 8 is a block diagram showing the configuration of the vector instruction processing device in this embodiment, and Figure 9 is a flowchart showing the operation of the vector instruction processing method in this embodiment.

[0040] Figure 8 differs from Figure 5 in that there are two paths between the issuance arbitration circuit 26A and the vector execution unit 24A. When the VL length is 128 or less, the issuance arbitration circuit 26A issues instructions from both reservation stations 23A and 23B, rather than issuing from just one of the reservation stations. When the VL length is 128 or less, the vector execution unit 24A changes the register read port according to the thread number, using VR0~VR3 and VR4~VR7 respectively, as described above. This division allows for the simultaneous processing of two instructions, making effective use of the available read ports.

[0041] The operation will be explained using Figure 9. Steps S1 to S6 are the same as in the previously described embodiment. In step S6, after arbitrating either reservation station 23A or 23B, the vector length of the instruction is checked (step SA1). If the VL length is 128 or less (Yes in step SA1), the vector instruction on the unarranged side is also issued, meaning that vector instructions are emitted from both reservation stations 23A and 23B (step SA2-1). If the VL length exceeds 128 (No in step SA1), simultaneous issuance is not possible, so only the arbitrating side instruction is issued, as in the previously described embodiment (step SA2-2).

[0042] As described above, in the present invention, since vector instructions included in a loop can be issued from multiple reservation stations for each loop, the processing of vector instructions can be accelerated.

[0043] <Embodiment 3> Next, a third embodiment of the present invention will be described with reference to Figures 10 to 11. Figure 10 is a block diagram showing the configuration of the vector instruction processing device in this embodiment, and Figure 11 is a flowchart showing the operation of the vector instruction processing method in this embodiment. In this embodiment, the configuration of the vector instruction processing device and vector instruction processing method described in Embodiment 1 is shown in outline.

[0044] As shown in Figure 10, the vector instruction processing device 100 in this embodiment includes a writing unit 101 that writes vector instructions included in a loop to different reservation stations 110 corresponding to each loop, and a vector execution unit 102 that executes the vector instructions issued from each reservation station 110. Note that the writing unit 101 and the vector execution unit 102 may be realized by the vector instruction processing device 100 executing a program.

[0045] Then, as shown in Figure 11, the vector instruction processing device 100 with the above configuration writes the vector instructions included in the repeatedly executed loop to a different reservation station 110 corresponding to each loop (step S101), and executes the vector instructions issued from each reservation station 110 (step S102).

[0046] As described above, in this invention, since the vector instructions included in the loop are executed in parallel by multiple reservation stations for each loop, the processing of vector instructions can be accelerated.

[0047] <Note> Some or all of the above embodiments may also be described as follows. The following outlines the configuration of the vector instruction processing method, vector instruction processing device, and program in the present invention. However, the present invention is not limited to the following configuration.

[0048] (Note 1) The vector instructions included in the repeatedly executed loop are written to a different reservation station corresponding to each loop. Each of the aforementioned reservation stations executes the aforementioned vector instruction issued from each of the aforementioned reservation stations. Vector instruction processing method. (Note 2) The vector instruction processing method described in Appendix 1, The vector instructions included in the loops that are not dependent on each other are written to the respective different reservation stations for each loop. (Note 3) A vector instruction processing method as described in Appendix 1 or 2, Based on a unique identifier assigned to each of the loops in which the vector instructions are not dependent, the vector instructions included in each of the loops are written to a different reservation station corresponding to each of the loops. Vector instruction processing method. (Note 4) A vector instruction processing method described in any of Appendix 1 to 3, The aforementioned loops are divided into multiple loops where the vector instructions are not dependent on each other, and each is assigned a unique identifier. Based on the identifier assigned to each of the multiple divided loops, the vector instructions contained in each of the loops are written to the corresponding different reservation stations for each loop. Vector instruction processing method. (Note 5) A vector instruction processing method described in any of Appendix 1 to 4, To mediate the requests for issuance of the vector command from each of the reservation stations, and to authorize the issuance of the vector command from the mediated reservation station. Vector instruction processing method. (Note 6) A vector instruction processing method described in any of Appendix 1 to 5, Each of the reservation stations performs a renaming process on the vector instructions within the loops that are written to it. The vector instructions within each of the loops that have undergone the renaming process are written to each of the reservation stations. Vector instruction processing method. (Note 7) A writing unit that writes vector instructions included in a loop that is executed repeatedly to a different reservation station corresponding to each loop, A vector execution unit that executes the vector instructions issued from each of the reservation stations, A vector instruction processing unit equipped with the following features. (Note 7.1) The vector instruction processing device described in Appendix 7, The writing unit writes the vector instructions included in the loops that are not dependent on each other to a different reservation station corresponding to each loop. Vector instruction processing unit. (Note 7.2) A vector instruction processing device as described in Appendix 7 or 7.1, The writing unit writes the vector instructions included in each loop to a different reservation station corresponding to each loop, based on a unique identifier assigned to each loop in which the vector instructions are not dependent on each other. Vector instruction processing unit. (Appendix 7.3) A vector instruction processing device as described in any of Appendix 7 to 7.2, The system includes an arbitration unit that arbitrates requests for the issuance of vector commands from each of the reservation stations and permits the issuance of vector commands from the arbitrated reservation stations. Vector instruction processing unit. (Appendix 7.4) A vector instruction processing device as described in any of Appendix 7 to 7.3, Each of the reservation stations is equipped with a renaming unit that performs renaming processing on the vector instructions within the loops, The writing unit writes the vector instructions within each of the renamed loops to each of the reservation stations. Vector instruction processing unit. (Note 8) The system includes a conversion device that divides loops containing vector instructions into multiple loops where the vector instructions are not dependent on each other, and assigns a unique identifier to each of them, A vector instruction processing device comprising: a writing unit that writes the vector instructions included in each of the multiple divided loops to a different reservation station corresponding to each loop, based on the identifier assigned to each of the multiple divided loops; and a vector execution unit that executes the vector instructions issued from each of the reservation stations, respectively. Vector instruction processing system. (Note 9) In the processor, The vector instructions included in the repeatedly executed loop are written to a different reservation station corresponding to each loop. Each of the aforementioned reservation stations executes the aforementioned vector instruction issued from each of the aforementioned reservation stations. A program to execute a process.

[0049] The above program can be stored and supplied to a computer using various types of non-transitory computer-readable medium. Non-transitory computer-readable medium includes various types of tangible storage medium. Examples of non-transitory computer-readable medium include magnetic recording media (e.g., flexible disks, magnetic tapes, hard disk drives), magneto-optical recording media (e.g., magneto-optical disks), CD-ROMs (Read Only Memory), CD-Rs, CD-R / Ws, and semiconductor memory (e.g., mask ROMs, PROMs (Programmable ROMs), EPROMs (Erasable PROMs), flash ROMs, and RAMs (Random Access Memory)). The program may also be supplied to a computer using various types of transient computer-readable medium. Examples of transient computer-readable medium include electrical signals, optical signals, and electromagnetic waves. Transitory computer-readable medium can be supplied to a computer via wired communication channels such as electric wires and optical fibers, or via wireless communication channels.

[0050] Although the present invention has been described above with reference to the embodiments described above, the present invention is not limited to the embodiments described above. Various modifications to the structure and details of the present invention can be made within the scope of the present invention as can be understood by those skilled in the art. [Explanation of symbols]

[0051] 1 scalar arithmetic unit 2 Vector Processing Units 10 Compilers 21 Vector instruction buffer 22 Renaming Control Circuit 23A, 23B Vector Reservation Station 24 Vector Execution Units 25. Programming control circuit 26. Issuance Mediation Circuit

Claims

1. When writing vector instructions included in a loop that is repeatedly executed to a different reservation station corresponding to each loop, the loops that do not have dependencies on each other are divided into multiple loops, each is assigned a unique identifier, and based on the identifiers assigned to each of the divided loops, the vector instructions included in each of the loops are written to the different reservation station corresponding to each loop. Each of the aforementioned reservation stations executes the aforementioned vector instruction issued from each of the aforementioned reservation stations. Vector instruction processing method.

2. A vector instruction processing method according to claim 1, To mediate the requests for issuance of the vector command from each of the reservation stations, and to authorize the issuance of the vector command from the mediated reservation station. Vector instruction processing method.

3. A vector instruction processing method according to claim 1 or 2, Each of the reservation stations performs a renaming process on the vector instructions within the loops that are written to it. The vector instructions within each of the loops that have undergone the renaming process are written to each of the reservation stations. Vector instruction processing method.

4. A writing unit writes vector instructions included in a loop that is repeatedly executed to a different reservation station corresponding to each loop, divides the loops into multiple loops where the vector instructions are not dependent on each other, assigns a unique identifier to each of the multiple divided loops, and writes the vector instructions included in each of the multiple divided loops to the different reservation station corresponding to each of the multiple divided loops, A vector execution unit that executes the vector instructions issued from each of the reservation stations, A vector instruction processing unit equipped with the following features.

5. The system includes a conversion device that divides loops containing vector instructions into multiple loops where the vector instructions are not dependent on each other, and assigns a unique identifier to each of them, A vector instruction processing device comprising: a writing unit that writes the vector instructions included in each of the multiple divided loops to a different reservation station corresponding to each loop, based on the identifier assigned to each of the multiple divided loops; and a vector execution unit that executes the vector instructions issued from each of the reservation stations, respectively. Vector instruction processing system.

6. In the processor, When writing vector instructions included in a loop that is repeatedly executed to a different reservation station corresponding to each loop, the loops that do not have dependencies on each other are divided into multiple loops, each is assigned a unique identifier, and based on the identifiers assigned to each of the divided loops, the vector instructions included in each of the loops are written to the different reservation station corresponding to each loop. Each of the aforementioned reservation stations executes the aforementioned vector instruction issued from each of the aforementioned reservation stations. A program to execute a process.

Images