Semiconductor package structure having a hybrid core structure, and method for manufacturing the same.

Abstract

To provide a semiconductor package structure with a hybrid core structure, and methods for manufacturing the same.SOLUTION: In a package substrate and a method of fabrication thereof including a hybrid substrate core having different material properties in different portions of the core, a first portion of the hybrid substrate core has a lower coefficient of thermal expansion (CTE) than a second portion of the hybrid substrate core. The CTE of the first portion of the hybrid substrate core is close to the CTE of semiconductor integrated circuit dies mounted on a first side of the package substrate in an assembled semiconductor package. The CTE of the second portion of the hybrid substrate core is close to the CTE of a supporting substrate, such as a printed circuit board, on which the semiconductor package is mounted. The package substrate helps to balance stress, such as thermally-induced stress, in the semiconductor package, thereby improving package reliability.SELECTED DRAWING: Figure 4

Description

Technical Field

[0001] The present invention relates to a semiconductor package structure having a hybrid core structure and a method for manufacturing the same, and more particularly, to a package substrate having a hybrid substrate core having different material characteristics at different positions of the core and a method for manufacturing the same.

Background Art

[0002] Semiconductor devices are used in various electronic devices. Some examples include personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically formed by continuously depositing an insulating layer, or a dielectric layer, a conductive layer, and a semiconductor material layer on a semiconductor substrate and patterning the various material layers using lithography to form circuit components and elements thereon. Dozens or hundreds of integrated circuits are typically formed on a single semiconductor wafer, and each die on the wafer is singulated by cutting between the integrated circuits along a scribe line. The individual dies are usually packaged separately, for example, in multi-chip modules or other types of packaging.

[0003] As semiconductor packages become larger and more complex by integrating a large number of semiconductor IC dies, ensuring the mechanical integrity of the semiconductor package is becoming increasingly important. In many semiconductor packages, stresses, including thermally-induced stresses, increase the failure rate and reduce the reliability of the semiconductor package.

Summary of the Invention

Problems to be Solved by the Invention

[0004] The present invention aims to solve the above-mentioned problems by providing a package substrate having a hybrid substrate core with different material properties at different positions on the core, and a method for manufacturing the same. [Means for solving the problem]

[0005] In some embodiments, a substrate for a semiconductor package is provided. The substrate for the semiconductor package has a substrate core having a first surface and a second substrate opposite to the first surface, a plurality of conductive vias extending from the substrate core between the first and second surfaces of the substrate core, a first redistribution layer on the first surface of the substrate core, and a second redistribution layer on the second surface of the substrate core. The substrate core has a first portion adjacent to the first surface and a second portion adjacent to the second surface, the first portion having a coefficient of thermal expansion (CTE) less than 10 ppm / °C, and the second portion having a CTE of 10 ppm / °C to 30 ppm / °C.

[0006] In some embodiments, a semiconductor package is provided. The semiconductor package comprises a semiconductor package structure, a package substrate, and a support substrate. The semiconductor package structure has one or more semiconductor IC dies. The package substrate has a first side, a second side opposite the first side, and an electrical interconnect structure extending between the first side and the second side. The package substrate has a hybrid substrate core having a first portion closest to the first side of the package substrate and a second portion closest to the second side of the package substrate, and the semiconductor package structure is mounted on the first side of the package substrate. The second side of the package substrate is mounted on the support substrate. The first portion of the hybrid substrate core of the package substrate has a CTE that is within 5 ppm / °C of the thermal expansion coefficient (CTE) of the semiconductor IC dies of the semiconductor package structure. The second portion of the hybrid substrate core of the package substrate has a CTE that is within 10 ppm / °C of the CTE of the support substrate.

[0007] In some embodiments, a method for manufacturing a package substrate is provided. First, a hybrid substrate core is formed having a first portion adjacent to a first surface of the hybrid substrate core and a second portion adjacent to a second surface of the hybrid substrate core. The first portion of the hybrid substrate core has a coefficient of thermal expansion (CTE) less than 10 ppm / °C. The second portion of the hybrid substrate core has a CTE between 10 ppm / °C and 30 ppm / °C. Next, a plurality of conductive vias are formed through the hybrid substrate core between the first and second surfaces. Furthermore, a first redistribution layer is formed on the first surface of the hybrid substrate core. Finally, a second redistribution layer is formed on the second surface of the hybrid substrate core. [Effects of the Invention]

[0008] A package substrate having a hybrid substrate core with different material properties at different locations on the core helps maintain stress equilibrium between the package substrate, the package structure having one or more semiconductor IC dies bonded to the first side of the package substrate, and the support substrate bonded to the second side of the package substrate. This improves the reliability of the semiconductor package and reduces the failure rate. [Brief explanation of the drawing]

[0009] The embodiments of the present invention can be better understood by referring to the following detailed description while looking at the attached drawings. It should be noted that, in relation to standard industrial techniques, the various features are not depicted in exact dimensions. In fact, the dimensions of the various features may be increased or decreased as appropriate to clarify the discussion.

[0010] [Figure 1] This is a cross-sectional view of an exemplary intermediate structure in a process for forming a package substrate having a hybrid substrate core, which has a first portion adjacent to the first side of the hybrid substrate core, a second portion adjacent to the second side of the hybrid substrate core, and a third portion located between the first and second portions of the hybrid substrate core, according to various embodiments of the present invention.

[0011] [Figure 2] This is a cross-sectional view of an exemplary intermediate structure during the manufacturing process of a package substrate illustrating a plurality of conductive vias extending into a hybrid substrate core according to various embodiments of the present invention.

[0012] [Figure 3] This is a cross-sectional view of an exemplary intermediate structure during the manufacturing process of a package substrate illustrating a redistribution layer formed on the first surface of a hybrid substrate core according to various embodiments of the present invention.

[0013] [Figure 4] This is a cross-sectional view of an exemplary intermediate structure during the manufacturing process of a package substrate illustrating a redistribution layer formed on the second surface of a hybrid substrate core according to various embodiments of the present invention.

[0014] [Figure 5] This is a cross-sectional view of a package substrate having external coating layers located above and below each redistribution layer according to various embodiments of the present invention.

[0015] [Figure 6] This is a cross-sectional view of a semiconductor package having a package structure mounted on the first side of a package substrate according to various embodiments of the present invention.

[0016] [Figure 7] This is a cross-sectional view of a semiconductor package having a second underfill material portion located between the first side of the package substrate and the lower surface of the interposer, according to various embodiments of the present invention.

[0017] [Figure 8] This is a cross-sectional view of a semiconductor package mounted on a support substrate according to various embodiments of the present invention.

[0018] [Figure 9] This is a cross-sectional view of a semiconductor package mounted on a support substrate according to another embodiment of the present invention.

[0019] [Figure 10] This is a flowchart for explaining a method of manufacturing a package substrate according to various embodiments of the present invention.

Embodiments for Carrying Out the Invention

[0020] The following disclosure provides many different embodiments or examples for implementing different features of the subject matter provided. The elements and arrangements of specific examples are described below to simplify the present invention. These are of course merely examples and are not intended to be limiting. For example, when it is described that the first feature is formed on or above the second feature, this includes embodiments in which the first and second features are formed in contact, and also includes embodiments in which additional features are formed between the first and second features and the first and second features do not directly contact. Different embodiments disclosed below reuse the same reference numerals and / or symbols. These duplicates are for the purpose of being concise and clear and are not intended to limit the specific relationships between various embodiments and / or the structures disclosed below.

[0021] Furthermore, spatial relative terms such as "below", "beneath", "lower", "above", "on top", "higher", etc. are used to describe the relationship between one element or feature and another element or feature in the drawings for ease of description. Spatial relative terms include different orientations during use and operation and the orientations shown in the drawings. As the device rotates to different orientations (a 90-degree rotation or other orientations), the spatial correlative adjectives used here are similarly interpreted accordingly. Unless specifically stated otherwise, it is presumed that each element having the same reference numeral has the same material composition and a thickness within the same thickness range.

[0022] The various embodiments disclosed herein are directed to semiconductor devices, particularly substrates of semiconductor packages having hybrid substrate cores with different material properties at different positions of the substrate core, and methods for manufacturing them.

[0023] Typically, in a semiconductor package, multiple semiconductor integrated circuit (IC) dies (i.e., “chips”) are mounted on a common substrate, also called a “package substrate.” In some packages, such as fan-out wear-level packages (FOWLP) and / or fan-out panel-level packages (FOPLP), the multiple semiconductor IC dies are mounted on an interposer having interconnect structures that extend through it, such as an organic interposer or a semiconductor (e.g., silicon) interposer. The package structure, including the interposer and the semiconductor IC dies mounted thereon, is then mounted on the surface of the package substrate using solder connections to form a semiconductor package. The semiconductor package, including the package substrate and the package structure mounted thereon, is then mounted on a support substrate, such as a printed circuit board (PCB).

[0024] As semiconductor packages become larger and more complex due to the integration of large numbers of semiconductor IC dies, ensuring the mechanical stability of semiconductor packages is becoming increasingly important. In many semiconductor packages, stresses, including thermally induced stresses, increase the failure rate and decrease reliability of the semiconductor package.

[0025] The various embodiments disclosed herein include a package substrate and a method for manufacturing a package substrate having a hybrid substrate core. The hybrid substrate core has multiple parts (e.g., sublayers) of a substrate having different material properties. In various embodiments, the hybrid substrate core has a first part closest to the semiconductor package structure and a second part closest to the support substrate (e.g., PCB) in the assembled semiconductor package. The first part of the hybrid substrate core is also referred to as the “chip side” part of the hybrid substrate core, and the second part of the hybrid substrate core is also referred to as the “board side” part of the hybrid substrate core. The first part of the hybrid substrate core has a lower coefficient of thermal expansion (CTE) than the second part of the hybrid substrate core. In various embodiments, the CTE of the first part of the hybrid substrate core is relatively close to the CTE of the semiconductor IC die in the package structure (e.g., in the range of 0 to 5 ppm / °C), and the CTE of the second part of the hybrid substrate is relatively close to the CTE of the support substrate (e.g., PCB) (e.g., in the range of 0 to 10 ppm / °C). In some embodiments, the first portion of the hybrid substrate core has a higher Young's modulus than the second portion of the hybrid substrate core. In some embodiments, the hybrid substrate core further has a third portion (also referred to as a “buffer portion”) located between the first and second portions of the hybrid substrate core. The third portion has a CTE greater than that of the first portion of the hybrid substrate core and less than that of the second portion of the hybrid substrate core.

[0026] The package substrate according to various embodiments comprises the above-mentioned hybrid substrate core, a plurality of conductive interconnection structures (e.g., metal vias) extending across the hybrid substrate core between the first and second surfaces, first and second redistribution layers having conductive interconnection structures incorporated in dielectric material matrices located on the first and second surfaces of the hybrid substrate core, and arbitrary first and second external coating layers located on the first and second redistribution layers.

[0027] A package substrate having a hybrid substrate core with different material properties at different locations on the core helps maintain a balance of stress between the package substrate and the package structure having one or more semiconductor IC dies bonded to the first side of the package substrate and a support substrate bonded to the second side of the package substrate. This improves the reliability of the semiconductor package and reduces the failure rate.

[0028] Figures 1 to 5 are sequential cross-sectional views of exemplary intermediate structures formed during the manufacturing process of a package substrate according to various embodiments of the present invention. Referring to Figure 1, a hybrid substrate core 101 is described having a first portion 102 adjacent to a first surface 105 of the hybrid substrate core 101, and a second portion 104 adjacent to a second surface 106 of the hybrid substrate core 101. An optional third portion 103 of the hybrid substrate core 101 is located between the first portion 102 and the second portion 104. The first portion 102, the second portion 104, and the optional third portion 103 are each joined together using a suitable adhesive, such as an adhesive film, to form a thin sheet of structural material that forms the hybrid substrate core 101. In some embodiments, the first portion 102, the second portion 104, and the optional third portion 103 are joined together using a partially cured epoxy resin, such as a B-stage material. The B-stage material has one or more layers (i.e., flap) of prepreg material, the prepreg material having resin-impregnated glass fiber or cloth material, and the resin is partially dried by heat and / or ultraviolet radiation. In various embodiments, the first part 102, the second part 104, and an optional third part 103 are stacked with one or more layers of B-stage prepreg material located between the first part 102, the second part 104, and the third part 103, respectively, and undergo a press lamination process and final cure to form the hybrid substrate core 101. In some embodiments, during the press lamination process, copper foil layers are provided on the upper and lower surfaces of the stack to provide the hybrid substrate core 101 having copper material layers on the first surface 105 and the second surface 106 of the hybrid substrate core 101. Therefore, in the embodiment shown in Figure 1, the first part 102, the second part 104, and the third part 103 form the first sublayer 102, the second sublayer 104, and the third sublayer 103 of the bonded laminated hybrid substrate core 101, respectively.What can be understood is that alternative arrangements used for the hybrid substrate core 101 are within the expected scope of the present invention, and that embodiments include the hybrid substrate core 101 being formed as a single structure having a first portion 102 adjacent to the first surface 105, a second portion 104 adjacent to the second surface 106, and an optional third portion 103 between the first portion 102 and the second portion 104.

[0029] In some embodiments, the first portion 102, the second portion 104, and an optional third portion 103 of the hybrid substrate core 101 are each composed of a sheet of laminated reinforced resin. The laminated reinforced resin sheet has a reinforcing material (e.g., glass fiber or cloth) impregnated with a resin system, such as an epoxy-based resin system, and is cured under heat and pressure to form a sheet of laminated reinforced resin. Other suitable materials and structures for the first portion 102, the second portion 104, and an optional third portion 103 of the hybrid substrate core 101 are within the scope of the present invention. In various embodiments, the first portion 102 of the hybrid substrate core 101 has a thickness T1 in the range of about 0.2 mm to about 0.6 mm, but thicker or thinner dimensions may be used. In various embodiments, the second portion 104 of the hybrid substrate core 101 has a thickness T2 in the range of about 0.2 mm to about 0.6 mm, but thicker or thinner dimensions may be used. Any third portion 103 of the hybrid substrate core 101 has a thickness T3 in the range of approximately 0.01 mm to approximately 0.2 mm, but thicker or thinner dimensions may be used. The hybrid substrate core 101 has a total thickness T of approximately 0.4 mm to approximately 1.0 mm. c While having the same characteristics, thicker or thinner dimensions may be used.

[0030] In various embodiments, in embodiments where a first portion 102, a second portion 104, and a third portion 103 of the hybrid substrate core 101 exist, each has different material properties, such as different coefficients of thermal expansion (CTE) and / or different module elastic forces (i.e., Young's modulus). In various embodiments, the first portion 102 of the hybrid substrate core 101 has a smaller CTE than the second portion 104 of the hybrid substrate core 101. In some embodiments, the first portion 102 of the hybrid substrate core 101 has a glass transition temperature (T g At temperatures lower than ), it has a CTE less than 10 ppm / °C, for example, about 0.1 ppm / °C to about 6 ppm / °C. In some embodiments, the second portion 104 of the hybrid substrate core 101 has a glass transition temperature (T g When the temperature is lower than 10 ppm / °C, it has a CTE of 10 ppm / °C or higher, for example, between 10 ppm / °C and approximately 30 ppm / °C. In various embodiments, if a third portion 103 is present, the CTE of the third portion 103 of the hybrid substrate core 101 is between the CTEs of the first portion 102 and the second portion 102 of the hybrid substrate core 101.

[0031] In various embodiments, the first portion 102 of the hybrid substrate core 101 has a higher Young's modulus than the second portion 104 of the hybrid substrate core 101. In some embodiments, the first portion 102 of the hybrid substrate core 101 has a Young's modulus between about 30 GPa and about 50 GPa at room temperature (e.g., ~20°C). The second portion 104 of the hybrid substrate core 101 has a Young's modulus between about 10 GPa and about 40 GPa at room temperature. In embodiments where a third portion 103 of the hybrid substrate core 101 is present, the third portion 103 has a Young's modulus between about 1 GPa and about 50 GPa at room temperature.

[0032] When the package substrate is assembled into a semiconductor package, the difference in material properties between the first part 102 and the second part 104 of the hybrid substrate core 101 helps maintain equilibrium over stresses, such as thermally induced stresses. The first part 102 of the hybrid substrate core 101 is closest to the semiconductor package structure containing one or more semiconductor IC dies in the assembled semiconductor package. Therefore, the even lower CTE of the first part 102 of the hybrid substrate core 101 further matches the relatively low CTE of the components of the semiconductor package structure containing one or more semiconductor IC dies. The relatively high Young's modulus of the first part 102 of the hybrid substrate core 101 provides high resistance to mechanical strain, helping to maintain the structural integrity of the bond between the package substrate and the semiconductor package structure.

[0033] In addition, the relatively high CTE of the second portion 104 of the hybrid substrate core 101 further conforms to the CTE of the support substrate of the assembled semiconductor package, such as a printed circuit board (PCB), which typically has a higher CTE than the components of the semiconductor package structure having a semiconductor IC die. The relatively low Young's modulus of the second portion 104 of the hybrid substrate core 101 provides a “cushion” effect, helping to mitigate stress resulting from CTE mismatch between the semiconductor package structure bonded to the first side of the package substrate and the support substrate (e.g., PCB) bonded to the second side of the package substrate. In embodiments where an optional third portion 103 of the hybrid substrate core 101 exists, the third portion 103 acts as a “buffer” between the first portion 102 and the second portion 104 of the hybrid substrate core 101.

[0034] The different material properties of the first portion 102, the second portion 104, and any third portion 103 of the hybrid substrate core 101 are obtained by varying different process parameters and / or the materials used to form the first portion 102, the second portion 104, and any third portion 103 of the hybrid substrate core 101. In the case of laminated reinforced resin materials, such variations include, but are not limited to, changes in the composition of the reinforcing material, including the type of reinforcing material used (e.g., E-glass, S-glass, LowDk-glass, silica, quartz, aramid, etc.), changes in the physical properties of the reinforcing material (e.g., use of woven or nonwoven fiber reinforcing material, weave of woven fiber reinforcing material, diameter, length, and / or alignment of fiber reinforcing material, etc.), changes in the composition of the resin system used, changes in the curing process, and changes in the relative concentrations of reinforcing material and resin in the laminated reinforced resin product. Several commercially available products are suitable for use in various embodiments of the present invention. For example, in recent years, several substrate core materials characterized by low or ultra-low CTE and high Young's modulus have become available on the market and are suitable for use as the first part 102 of the hybrid substrate core 101. Examples of suitable products for the first part 102 of the hybrid substrate core 101 include, but are not limited to, the MCL-E-705G series and MCL-E-795G series from Showa Denko Materials Co., Ltd., HL832NSA(LCA) from Mitsubishi Chemical Corp., and R-1515V from Panasonic Holdings Corp. Other suitable materials used as the first part 102 of the hybrid substrate core 101 are within the expected scope of the present invention. Examples of suitable materials used as the second part 104 of the hybrid substrate core 101 include, for example, MCL-HE-679G (Type S) from Showa Denko Materials and HL832NX from Mitsubishi Chemical. Other suitable materials used as the second part 104 of the hybrid substrate core 101 are within the expected scope of the present invention.A material is selected for any third portion 103 of the hybrid substrate core 101, and the CTE of any third portion 103 is located between the CTEs of the first portion 102 and the second portion 104 of the hybrid substrate core 101.

[0035] Figure 2 is a cross-sectional view of an exemplary intermediate structure during the manufacturing process of a package substrate illustrating a plurality of conductive vias 107 extending into a hybrid substrate core 101 according to various embodiments of the present invention. Referring to Figure 2, the plurality of through-holes are formed through the hybrid substrate core 101 by extending between the first surface 105 and the second surface 106 of the hybrid substrate core 101. In the embodiment of Figure 2, the plurality of through-holes are formed through the first portion 102, the second portion 104, and the third portion 103 of the hybrid substrate core 101 after the first portion 102, the second portion 104, and the third portion 103 are joined together. In other embodiments, the through-holes are formed through one or more first portions 102, the second portion 104, and the third portion 103 before they are joined together to form the hybrid substrate core 101. The through-holes are formed by a photolithography pattern mask using any suitable process, such as a mechanical drill, laser drill, or etching process. Other suitable processes for forming through-holes are within the expected scope of the present invention.

[0036] Referring again to Figure 2, multiple conductive vias 107 are formed in each through-hole, so that the conductive vias 107 extend between the first surface 105 and the second surface 106 of the hybrid substrate core 101. The conductive vias 107 are formed from a suitable conductive material, such as Cu, Ni, W, Al, Co, Mo, Ru, etc., and combinations or alloys thereof. Other suitable materials used for the conductive vias 107 are within the expected scope of the present invention. Multiple conductive vias 107 are formed using a suitable deposition process, such as an electrochemical deposition process (e.g., electroplating). Other suitable deposition processes are within the expected scope of the present invention. In the embodiment shown in Figure 2, the multiple conductive vias 107 are formed after the first part 102, the second part 104, and the third part 103 are joined together to form the hybrid substrate core 101. Alternatively, conductive vias may be formed through one or more first portions 102, second portions 104, and third portions 103 of the hybrid substrate core 101 before they are joined together, such that when the first portion 102, second portion 104, and third portion 103 are joined together, a plurality of conductive vias 107 extend continuously through the first portion 102, second portion 104, and third portion 103 between the first surface 105 and the second surface 106 of the hybrid substrate core 101.

[0037] Figure 3 is a cross-sectional view of an exemplary intermediate structure during the manufacturing process of a package substrate illustrating a first redistribution layer 110a formed on the first surface 105 of a hybrid substrate core 101 according to various embodiments of the present invention. The first redistribution layer 110a has a plurality of conductive interconnect structures 109 (e.g., metal wires 116 and vias 117) incorporated into a dielectric material matrix 108. The conductive interconnect structures 109 are in contact with a plurality of conductive vias 107 that spread across the hybrid substrate core 101.

[0038] In some embodiments, the first redistribution layer 110a is formed by providing a first layer of conductive material (e.g., a copper-clad laminate) onto the first surface 105 of the hybrid substrate core 101 using a suitable deposition process, such as an electroplating process. In some embodiments, the first layer of conductive material on the first surface 105 of the hybrid substrate core 101 is formed entirely or partially by the press lamination process described above, which is used to form the hybrid substrate core 101. The first layer of conductive material is patterned by an etching process carried out using a photolithography pattern mask to form a plurality of first metal wires 116 (e.g., copper traces) on the first surface 105 of the hybrid substrate core 101. Subsequently, a first layer of dielectric material 108 is formed on the plurality of first metal wires 116. The first layer of dielectric material 108 has a polymer-based dielectric material, such as Ajinomoto's Build-Up Film (ABF)®. Other suitable dielectric materials are within the expected scope of the present invention. In some embodiments, the first layer of dielectric material 108 is applied as a film on the first surface 105 of the hybrid substrate core 101. The film is vacuum laminated on the first surface 105 of the hybrid substrate core 101 and partially cured (for example, by a high-temperature compression process). Multiple through-holes are formed through the first layer of dielectric material 108 using an appropriate process, for example, by mechanical drilling, laser drilling, and / or etching. Metal wires 116 and / or conductive vias 107 are exposed at the bottom of each through-hole.

[0039] A metallization process is used to form a plurality of first vias 117 in through holes through the first layer of dielectric material 108. The plurality of first vias 117 are formed using a suitable deposition process, such as electroplating. The deposition process further forms a second layer of conductive material on top of the first layer of dielectric material 108. Alternatively, a separate deposition process is used to form a second layer of conductive material on top of the first layer of dielectric material 108. The second layer of conductive material is patterned by an etching process performed by a photolithography pattern mask to form a plurality of second metal wires 116 (e.g., copper traces) on the surface of the first layer of dielectric material 108. As described above, the second layer of dielectric material 108 is formed on a plurality of second metal wires 116, and a plurality of through holes are formed through the second layer of dielectric material 108. An additional metallization process is used to form a plurality of second vias 117 in through holes formed through the second layer of dielectric material 108. These processes are optionally repeated multiple times to form a first redistribution layer 110a having multiple conductive interconnect structures 109 (e.g., metal wires 116 and vias 117) incorporated into the dielectric material matrix 108. The layer of dielectric material 108 optionally undergoes a curing process at increased temperature (e.g., 170-200°C) to form a solid dielectric material matrix 108 surrounding the conductive interconnect structures 109. Multiple first bonding pads 112 are formed on the top layer of dielectric material 108.

[0040] Figure 4 is a cross-sectional view of an exemplary intermediate structure during the manufacturing process of a package substrate illustrating the second redistribution layer 110b formed on the second surface 106 of the hybrid substrate core 101 according to various embodiments of the present invention. Referring to Figure 4, the second redistribution layer 110b on the second surface 106 of the hybrid substrate core 101 has a plurality of conductive interconnection structures 109 (e.g., metal wires 116 and vias 117) incorporated into the dielectric material matrix 108. As described in relation to Figure 3, the second redistribution layer 110b on the second surface 106 of the hybrid substrate core 101 has a similar or identical structure and is formed using a similar or identical process to the first redistribution layer 110a formed on the first surface 105 of the hybrid substrate core 101. Therefore, for brevity, a discussion of repeated similar features is omitted. Furthermore, Figures 3 and 4 illustrate an embodiment in which the first redistribution layer 110a is formed on the first surface 105 of the hybrid substrate core 101 before the second redistribution layer 110b is formed on the second surface 106 of the hybrid substrate core 101. What can be understood is that the second redistribution layer 110b on the second surface 106 of the hybrid substrate core 101 is formed before the first redistribution layer 110a on the first surface 105 of the hybrid substrate core 101 is formed, or that the first redistribution layer 110a and the second redistribution layer 110b (collectively, the redistribution layer 110) are formed simultaneously on the first surface 105 and the second surface 106 of the hybrid substrate core 101.

[0041] Referring again to Figure 4, the multiple second bonding pads 113 are formed on the second redistribution layer 110b located on the second surface 106 of the hybrid substrate core 101. In various embodiments, multiple first bonding pads 112 are provided to electrically connect the package substrate to a semiconductor package structure having at least one semiconductor IC die, and multiple second bonding pads 113 are provided to electrically connect the package substrate to a support substrate, such as a PCB.

[0042] Figure 5 is a cross-sectional view of a package substrate 120 having external coating layers 111 located above and below each redistribution layer 110 according to various embodiments of the present invention. Referring to Figure 5, the external coating layers 111 of the package substrate 120 have a layer of dielectric material formed on each redistribution layer 110 and define the corresponding first outer surface 114 and second outer surface 115 of the package substrate 120. Each external coating layer 111 provides a protective film to the package substrate 120 and the lower bonding pads 112, 113 and conductive interconnect structures 109 within the package substrate 120. The external coating layers 111 further prevent solder material from adhering to the first outer surface 114 and second outer surface 115 of the package substrate 120 during the subsequent solder reflow process.

[0043] In various embodiments, the external coating layer 111 comprises a solder resist material. The external coating layer 111 formed of the solder resist material is also referred to as a “solder mask”. The solder resist material of the external coating layer 111 comprises a suitable resin material that is resistant to moisture and high temperatures and does not strongly adhere to solder material. The solder resist material of the external coating layer 111 is formed using a suitable deposition process, for example, by screen printing, spraying, and / or vacuum lamination. Other suitable deposition processes are within the expected scope of the present invention.

[0044] Figure 6 is a cross-sectional view of a semiconductor package 140 having a package structure 130 mounted on the first side 114 of a package substrate 120 according to various embodiments of the present invention. Referring to Figure 6, the package structure 130 has one or more semiconductor IC dies 131. In the embodiment shown in Figure 6, the package structure 130 has two semiconductor IC dies 131, and it can be understood that in other embodiments, the package structure 130 has two or more semiconductor IC dies 131, or has a single semiconductor IC die 131. One or more semiconductor IC dies 131 of the package structure 130 have at least one system-on-a-chip (SoC) die. The SoC die has, for example, an application processor die, a central processing unit die, and / or a graphics processing unit die. In some embodiments, one or more semiconductor IC dies 131 have at least one memory die. At least one memory die has a high-bandwidth memory (HBM) die. In some embodiments, the HBM die has a vertical stack interconnect memory die. Alternatively, or additionally, at least one memory die is a dynamic random access memory (DRAM) die. In some embodiments, the package structure 130 has a plurality of homogeneous semiconductor IC dies 131, meaning that all semiconductor IC dies 131 are of the same type (e.g., all SoC dies, all HBM dies, all DRAM dies, etc.). Alternatively, the package structure 130 has a plurality of heterogeneous semiconductor IC dies 131, meaning that the plurality of semiconductor IC dies 131 are of different types (e.g., at least one SoC die and at least one memory die).

[0045] In various embodiments, one or more semiconductor IC dies 131 of the package structure 130 are mounted on an interposer 133, for example, an organic interposer or a semiconductor (e.g., silicon) interposer. The interposer 133 is mounted on the first outer surface 114 of the package substrate 120 to form a semiconductor package 140. The interposer 133 has a plurality of interconnection structures 134 (e.g., metal wires and vias) in an insulating matrix. One or more semiconductor IC dies 131 are mounted on the interposer 133 by a plurality of junction structures 135 having microbump (e.g., C2) junction structures. A first underfill material portion 138 is placed between one or more semiconductor IC dies 131 and the interposer 133 and surrounds the junction structures 135. For example, a mold portion 139 having an epoxy mold compound (EMC) surrounds one or more semiconductor IC dies 131 laterally.

[0046] Referring again to Figure 6, an etching process is used to selectively remove a portion of the external coating layer 111 from the first side 114 of the package substrate 120 (e.g., a solder mask) to expose the first bonding pad 112 beneath the package substrate 120. The pattern of the first bonding pad 112 exposed in the first side 114 of the package substrate 120 corresponds to the pattern of the bonding pad 137 located on the lower surface of the interposer 133. The package structure 130 is aligned on the first side 114 of the package substrate 120, and the array of solder material portions 136 is located between the first bonding pad 112 of the package substrate 120 and the corresponding first bonding pad 137 on the lower surface of the interposer 133. A reflow process is performed to reflow the solder material portions 136, thereby forming a bond between the interposer 133 of the package structure 130 and the package substrate 120. Each solder material portion 136 is bonded to a corresponding first bonding pad 112 on the package substrate 120 and to a corresponding first bonding pad 137 on the lower surface of the interposer 133. In some embodiments, the solder material portion 136 has C4 solder balls, and the package structure 130 is bonded to the package substrate 120 by an array of C4 solder balls.

[0047] In another embodiment, the interposer 133 is omitted, and one or more semiconductor IC dies 131 are mounted directly on the first side 114 of the package substrate 120, for example, by a plurality of microbump (e.g., C2) junction structures.

[0048] Figure 7 is a cross-sectional view of a semiconductor package 140 having a second underfill material portion 141 located between the first side 114 of the package substrate 120 and the lower surface of the interposer 133, according to various embodiments of the present invention. Referring to Figure 7, the second underfill material portion 141 is added to the space between the first side 114 of the package substrate 120 and the lower surface of the interposer 133. The second underfill material portion 141 surrounds and contacts each of the solder material portions 136 that join the interposer 133 and the package substrate 120 in the lateral direction.

[0049] Figure 8 is a cross-sectional view of a semiconductor package 140 mounted on a support substrate 150 according to various embodiments of the present invention. Referring to Figure 8, the support substrate 150 is a PCB having an array of bonding pads 153 exposed on the upper surface 151 of the support substrate 150. An etching process is used to selectively remove a portion of the external coating layer 111 (e.g., solder mask) from the second side 115 of the package substrate 120, and to expose the lower second bonding pads 113 of the package substrate 120. The pattern of the second bonding pads 113 on the package substrate 120 corresponds to the pattern of the bonding pads 153 on the upper surface 151 of the support substrate 150. The semiconductor package 140 is aligned on the upper surface 151 of the support substrate 150, with an array of solder material portions 154 positioned between the second bonding pads 113 of the package substrate 120 and the corresponding bonding pads 153 on the upper surface 151 of the support substrate 150. A reflow process is performed to reflow the solder material portions 154, thereby achieving bonding between the package substrate 120 and the support substrate 150 of the semiconductor package 140. Each solder material portion 154 is bonded to a corresponding second bonding pad 113 on the package substrate 120 and to a corresponding bonding pad 153 on the upper surface 151 of the support substrate 150. In some embodiments, a third underfill material portion 160 is added to the space between the second side 115 of the package substrate 120 and the upper surface 151 of the support substrate 150. The third underfill material portion 160 surrounds and contacts each solder material portion 154 that bonds the package substrate 120 and the support substrate 150 laterally.

[0050] Referring again to Figure 8, the semiconductor package 140 according to various embodiments has a package structure 130, the package structure 130 has one or more semiconductor IC dies 131 mounted on the first side 114 of the package substrate 120. The second side 115 of the package substrate 120 is mounted on a support substrate 150, for example, the upper surface 151 of a PCB. The package substrate 120 has a hybrid substrate core 101, the hybrid substrate core 101 has a first portion 102 closest to the first side 114 of the package substrate 120, a second portion 104 closest to the second side 115 of the package substrate 120, and an arbitrary third portion 103 located between the first portion 102 and the second portion 104. In various embodiments, the first portion 102 of the hybrid substrate core 101 has a CTE of 3 ppm / °C or less, including a CTE of 5 ppm / °C or less, for example, 2 ppm / °C or less, of the semiconductor IC die 131 of the semiconductor package 140. In some embodiments, the first portion 102 of the hybrid substrate core 101 has a CTE of 1 ppm / °C or less, including a CTE of 0.5 ppm / °C or less, for example, 0.1 ppm / °C or less, of the semiconductor IC die 131 of the semiconductor package 140. In some embodiments, the semiconductor package 140 has a plurality of semiconductor IC dies 131, and the first portion 102 of the hybrid substrate core 101 has a CTE of 5 ppm / °C or less, for example, 3 ppm / °C, 2 ppm / °C, 1 ppm / °C, 0.5 ppm / °C, or 0.1 ppm / °C or less, of the semiconductor IC die 131 of the semiconductor package 140. In various embodiments, the second portion 104 of the hybrid substrate core 101 has a CTE of 10 ppm / °C or less, for example, 5 ppm / °C or less, of the support substrate (e.g., PCB) on which the package substrate 120 is mounted. The third portion 103 of the hybrid substrate core 101 has a CTE located between the first portion 102 and the second portion 104 of the hybrid substrate core 101.

[0051] Figure 9 is a cross-sectional view of a semiconductor package 140 mounted on a support substrate 150 according to another embodiment of the present invention. The semiconductor package 140 shown in Figure 9 is substantially the same as the semiconductor package 140 described in relation to Figure 8. Therefore, for brevity, redundant discussion of similar features is omitted. The difference between the semiconductor package 140 in Figure 9 and the semiconductor package 140 in Figure 8 is that, in the other embodiment shown in Figure 9, any third portion 103 of the hybrid substrate core 101 is omitted from the package substrate 120. Thus, in the embodiment shown in Figure 9, the hybrid substrate core 101 of the package substrate 120 has a first portion 102 closest to the first side 114 of the package substrate 120, and a second portion 104 closest to the second side 115 of the package substrate 120, and the first portion 102 and the second portion 104 of the hybrid substrate core 101 are adjacent to each other.

[0052] As discussed above, the package substrate 120 having the hybrid substrate core 101 helps maintain stress equilibrium in the assembled semiconductor package 140, for example, as shown in Figures 8 and 9. The first portion 102 of the hybrid substrate core 101 is closest to the semiconductor package structure 130 having one or more semiconductor IC dies 131 and has a CTE (e.g., within 5 ppm / °C) close to the CTE of one or more semiconductor IC dies 131. The second portion 104 of the hybrid substrate core 101 is closest to the support substrate 150 (e.g., PCB) and has a CTE (e.g., within 10 ppm / °C) close to the CTE of the support substrate 150. In some embodiments, the first portion 102 of the hybrid substrate core 101 has a relatively high Young's modulus (e.g., ≥30 GPa) that provides high resistance to mechanical strain, and the second portion 104 of the hybrid substrate core 101 has a Young's modulus smaller than that of the first portion 102, providing a “cushion” effect to reduce stress caused by CTE mismatch between the semiconductor package structure 130 and the support substrate 150 in the assembled semiconductor package 140.

[0053] Figure 10 is a flowchart illustrating a method 200 for manufacturing a package substrate 120 according to various embodiments of the present invention. Referring to Figures 1 and 10, in step 201 of the method 200 of the present invention, a hybrid substrate core 101 is formed having a first portion 102 adjacent to the first surface 105 of the hybrid substrate core 101 and a second portion 104 adjacent to the second surface of the hybrid substrate core 101. The first portion 102 of the hybrid substrate core 101 has a coefficient of thermal expansion (CTE) less than 10 ppm / °C, and the second portion 104 of the hybrid substrate core 101 has a CTE between 10 ppm / °C and 30 ppm / °C.

[0054] Referring to Figures 2 and 10, in step 203 of the method 300, a plurality of conductive vias 107 are formed through the hybrid substrate core 101 between the first surface 105 and the second surface 106 of the hybrid substrate core 101. Referring to Figures 3, 4, and 10, in step 205 of the method 200, the redistribution layer 110 is formed on the first surface 105 and the second surface 106 of the hybrid substrate core 101.

[0055] Referring to all the drawings and according to various embodiments of the present invention, the substrate 120 of the semiconductor package 140 has a substrate core 101 having a first surface 105 and a second surface 106 opposite to the first surface 105, the substrate core 101 having a first portion 102 adjacent to the first surface 105 and a second portion 104 adjacent to the second surface 106, the first portion 102 having a coefficient of thermal expansion (CTE) less than 10 ppm / °C and the second portion 104 having a CTE of 10 ppm / °C to 30 ppm / °C, and a plurality of conductive vias 107 extending between the first surface 105 and the second surface 106 of the substrate core 101, the first redistribution layer 110a on the first surface 105 of the substrate core 101, and the second redistribution layer 110b on the second surface 106 of the substrate core 101.

[0056] In one embodiment, the first portion 102 of the substrate core 101 has a CTE of 0.1 ppm / °C to 10 ppm / °C.

[0057] In another embodiment, the first portion 102 of the substrate core 101 has a higher Young's modulus than the second portion 104 of the substrate core 101.

[0058] In another embodiment, the Young's modulus of the first portion 102 of the substrate core 101 is 30 GPa to 50 GPa, and the Young's modulus of the second portion 104 of the substrate core 101 is 10 GPa to 40 GPa.

[0059] In another embodiment, the first portion 102 of the substrate core 101 has a first laminated reinforced resin sheet, and the second portion 104 of the substrate core 101 has a second laminated reinforced resin sheet, and the first laminated reinforced resin sheet and the second laminated reinforced resin sheet are bonded together to form the substrate core 101.

[0060] In another embodiment, the first laminated reinforced resin sheet and the second laminated reinforced resin sheet each have a thickness between 0.2 mm and 0.6 mm.

[0061] In another embodiment, the substrate core 101 further has a third portion 103 located between the first portion 102 and the second portion 104, the third portion 103 having a CTE greater than that of the first portion 102 and less than that of the second portion 104, and the third portion 103 having a Young's modulus of 1 GPa to 50 GPa.

[0062] In another embodiment, the first portion 102, the second portion 104, and the third portion 103 each have a laminated reinforced resin sheet that is joined together to form a substrate core 101.

[0063] In another embodiment, the first redistribution layer 110a and the second redistribution layer 110b each have a conductive interconnection structure 109 in an insulating matrix 108, and the package substrate 120 further has an external coating layer 111 on each of the first redistribution layer 110a and the second redistribution layer 110b.

[0064] Another embodiment describes a semiconductor package 140 having a semiconductor package structure 130 having one or more semiconductor IC dies 131, a package substrate 120 having a first side 114, a second side 115 opposite the first side 114, and an electrical interconnection structure 109 extending between the first side 114 and the second side 115, wherein the package substrate 120 has a hybrid substrate core 101, the hybrid substrate core 101 having a first portion 102 closest to the first side 114 of the package substrate 120, and a second portion 1 closest to the second side 115 of the package substrate 120 The semiconductor package structure 130 has a first side 114 of the package substrate 120 and is mounted on the support substrate 150, the second side 115 of the package substrate 120 is mounted on the support substrate 150, the first part 102 of the hybrid substrate core 101 of the package substrate 120 has a CTE of 5 ppm / °C or less than the CTE of the semiconductor IC die 131 of the semiconductor package structure 130, and the second part 102 of the hybrid substrate core 101 of the package substrate 120 has a CTE of 10 ppm / °C or less than the CTE of the support substrate 150.

[0065] In one embodiment, the first portion 102 of the hybrid substrate core 101 of the package substrate 120 has a CTE that is within 0.1 ppm / °C of the thermal expansion coefficient (CTE) of the semiconductor IC die 131 of the semiconductor package structure 130, and the second portion 102 of the hybrid substrate core 101 of the package substrate 120 has a CTE that is within 3 ppm / °C of the CTE of the support substrate 150.

[0066] In another embodiment, the support substrate 150 has a printed circuit board (PCB), and the second side 115 of the package substrate 120 is mounted on the PCB by a plurality of solder connections 154.

[0067] In another embodiment, the second portion 104 of the hybrid substrate core 101 of the package substrate 120 has a Young's modulus smaller than that of the first portion 102 of the hybrid substrate core 101 of the package substrate 120.

[0068] In another embodiment, the semiconductor package structure 130 has a plurality of semiconductor IC dies 131, and the first portion 102 of the hybrid substrate core 101 of the package substrate 120 has a CTE (Coefficient of Thermal Expansion) of 5 ppm / °C or less of the CTE of the semiconductor IC die 131 of each semiconductor package structure 130.

[0069] In another embodiment, the semiconductor package structure 130 further comprises an interposer 133, a plurality of semiconductor IC dies 131 mounted on the upper surface of the interposer 133, and a plurality of solder connections 136 extending between the lower surface of the interposer 133 and the first side 114 of the package substrate 120, thereby mounting the semiconductor package structure 130 on the first side 114 of the package substrate 120.

[0070] In another embodiment, the hybrid substrate core 101 of the package substrate 120 has a third portion 103 located between the first portion 102 and the second portion 104, wherein the CTE of the third portion 103 of the hybrid substrate core 101 is greater than the CTE of the first portion 102 of the hybrid substrate core 101 and less than the CTE of the second portion 104 of the hybrid substrate core 101.

[0071] In another embodiment, a method for manufacturing a package substrate is described, which includes a step of forming a hybrid substrate core 101 having a first portion 102 adjacent to the first surface of the hybrid substrate core 101 and a second portion 104 adjacent to the second surface 106 of the hybrid substrate core 101. The first portion 102 of the hybrid substrate core 101 has a coefficient of thermal expansion (CTE) less than 10 ppm / °C, and the second portion 104 of the hybrid substrate core 101 has a CTE of 10 ppm / °C to 30 ppm / °C. Multiple conductive vias 107 are formed through the hybrid substrate core 101 between the first surface 105 and the second surface 106 of the hybrid substrate core 101. A first redistribution layer 110a is formed on the first surface 105 of the hybrid substrate core 101, and a second redistribution layer 110b is formed on the second surface 106 of the hybrid substrate core 101.

[0072] In one embodiment, the method for forming the hybrid substrate core 101 includes the steps of forming a plurality of laminated reinforced resin sheets and joining the plurality of laminated reinforced resin sheets together to form the hybrid substrate core 101, wherein the first laminated reinforced resin sheet forms the first portion 102 of the hybrid substrate core 101, and the second laminated reinforced resin sheet forms the second portion 104 of the hybrid substrate core 101.

[0073] In another embodiment, the third laminated reinforced resin sheet of the plurality of laminated reinforced resin sheets forms the third portion 103 of the hybrid substrate core 101, and the CTE of the third portion 103 of the hybrid substrate core 101 is greater than the CTE of the first portion 102 of the hybrid substrate core 101 and smaller than the CTE of the second portion 104 of the hybrid substrate core 101.

[0074] In another embodiment, the Young's modulus of the first portion 102 of the hybrid substrate core 101 is 30 GPa to 50 GPa, and the Young's modulus of the second portion 104 of the hybrid substrate core 101 is 10 GPa to 40 GPa, and the Young's modulus of the first portion 102 of the hybrid substrate core 101 is greater than the Young's modulus of the second portion 104 of the hybrid substrate core 101.

[0075] While preferred embodiments of the present invention have been disclosed above, these are by no means limiting to the present invention, and anyone familiar with the art can make various modifications without departing from the spirit of the present invention. [Explanation of Symbols]

[0076] 101…Hybrid substrate core 102...Part 1 (First Sublayer) 103...Third part (third sublayer) 104...Second part (second sublayer) 105...First surface (first side of the hybrid substrate core) 106...Second surface (second side of the hybrid substrate core) 107…Multiple conductive vias 108…Dielectric material matrix (first layer of dielectric material) 109...Conductive interconnection structure 110a…first redistribution layer 110b…Second redistribution layer 111...External coating layer 112... First Bonding Pad 113...Second bonding pad 114...First outer surface (first side of the package substrate) 115...Second outer surface (second side of the package substrate) 116… Metal wire 117...Conductive via 120…Package substrate 130…Package structure 131... Semiconductor IC die 133... Interposer 134…Interconnection structure 136, 154... Solder material part 137, 153… Bonding pads 138...First underfill material section 139...Molded part 140... Semiconductor packages 141...Second underfill material section 150...Support substrate 151…Top surface 153…Bonding pad 160...Third underfill material section T...thickness

Claims

1. A substrate for a semiconductor package, It has a first surface and a second surface opposite to the first surface, The first portion adjacent to the first surface, and A substrate core having a second portion adjacent to the second surface, wherein the first portion has a Young's modulus higher than that of the second portion and a Pa of 30 GPa to 50 GPa. A plurality of conductive vias extending across the substrate core between the first surface and the second surface of the substrate core, The first redistribution layer on the first surface of the substrate core, The second redistribution layer on the second surface of the substrate core, A semiconductor package substrate characterized by having the following features.

2. The substrate according to claim 1, characterized in that the Young's modulus of the second portion of the substrate core is 10 GPa to 40 GPa.

3. The substrate according to claim 1, wherein the first portion of the substrate core has a first laminated reinforced resin sheet, the second portion of the substrate core has a second laminated reinforced resin sheet, and the first laminated reinforced resin sheet and the second laminated reinforced resin sheet are joined together to form the substrate core.

4. The substrate according to claim 3, characterized in that the first laminated reinforced resin sheet and the second laminated reinforced resin sheet each have a thickness of 0.2 mm to 0.6 mm.

5. The substrate core further comprises a third portion located between the first portion and the second portion, wherein the third portion has a coefficient of thermal expansion (CTE) greater than that of the first portion and less than that of the second portion, and the third portion has a Young's modulus between 1 GPa and 50 GPa, as described in claim 1.

6. The substrate according to claim 5, characterized in that the first part, the second part, and the third part are each joined together to form the substrate core, and each has a laminated reinforced resin sheet.

7. A semiconductor package, It comprises a semiconductor package structure, a package substrate, and a support substrate. The aforementioned semiconductor package structure has one or more semiconductor IC dies, The package substrate has a first side, a second side opposite to the first side, and an electrical interconnection structure extending between the first side and the second side, the package substrate has a hybrid substrate core, and the hybrid substrate core is The first portion closest to the first side of the package substrate, and The semiconductor package structure has a second portion closest to the second side of the package substrate, and the semiconductor package structure is mounted on the first side of the package substrate. A semiconductor package characterized in that the second side of the package substrate is mounted on the support substrate, the first portion of the hybrid substrate core of the package substrate has a pressure of 30 GPa to 50 GPa, and has a Young's modulus higher than that of the second portion of the hybrid substrate core of the package substrate.

8. The semiconductor package according to claim 7, characterized in that the Young's modulus of the second portion of the hybrid substrate core of the package substrate is 10 GPa to 40 GPa.

9. The semiconductor package according to claim 7 or 8, wherein the hybrid substrate core of the package substrate has a third portion located between the first portion and the second portion, and the coefficient of thermal expansion (CTE) of the third portion of the hybrid substrate core is greater than the CTE of the first portion of the hybrid substrate core and less than the CTE of the second portion of the hybrid substrate core.

10. A method for manufacturing a package substrate, A step of forming a hybrid substrate core having a first portion adjacent to the first surface of the hybrid substrate core and a second portion adjacent to the second surface of the hybrid substrate core, wherein the first portion of the hybrid substrate core has a Young's modulus of 30 GPa to 50 GPa, and the second portion of the hybrid substrate core has a Young's modulus of 10 GPa to 40 GPa, A step of forming a plurality of conductive vias through the hybrid substrate core between the first surface and the second surface of the hybrid substrate core, A step of forming a first redistribution layer on the first surface of the hybrid substrate core, A step of forming a second redistribution layer on the second surface of the hybrid substrate core, A method for manufacturing a package substrate, characterized by having the following features.

Images