Printed circuit boards and communication devices having pads

Abstract

The present disclosure relates to a printed circuit board and a communication device having a pad, the printed circuit board including a signal layer and a reference layer, a pad disposed on the signal layer, the pad including a stub, a first anti-pad disposed on the reference layer, a vertically inverted image of the stub on the reference layer located within a coverage area of the first anti-pad, and the first anti-pad is used to reduce the impedance of the stub.

Description

Technical Field

[0001] [Cross - Reference to Related Applications] This disclosure claims the priority of Chinese Patent Application CN202211042562.3, titled "Printed Circuit Board with Pads and Communication Device", filed on August 29, 2022, and all of its content is incorporated herein by reference. [Technical Field] This disclosure relates to the field of printed circuit board design, and particularly to a printed circuit board with pads and a communication device.

Background Art

[0002] With the increase in signal speed, the performance requirements for the signal integrity (abbreviated as SI) of high - speed channels also increase. Among them, signal reflection caused by impedance discontinuity greatly affects high - speed signals. Therefore, impedance optimization of high - speed channels becomes extremely important.

[0003] When designing pads on a printed circuit board (abbreviated as PCB), considering the reliability of welding, the pads are designed to be long. In this way, low - impedance points are likely to appear. Long pads are likely to form stubs, and the coupling between the stub and the reference ground forms a sudden change in capacitive impedance, reducing the transmission quality of high - speed signals. Therefore, how to reduce the capacitive coupling between the pad stub and the reference ground has become a technical problem to be solved.

Summary of the Invention

Problems to be Solved by the Invention

[0004] This disclosure provides a printed circuit board with pads and a communication device to solve the technical problem of how to reduce the capacitive coupling between the pad stub and the reference ground.

Means for Solving the Problems

[0005] According to a first aspect of this disclosure, the present disclosure provides a printed circuit board having pads, the printed circuit board comprising a signal layer and a reference layer, the signal layer having pads, the pads comprising stubs, the reference layer having a first anti-pad, the vertically inverted image of the stub on the reference layer being located within the covering area of ​​the first anti-pad, and the first anti-pad being used to reduce the impedance of the stub.

[0006] According to a second aspect, the present disclosure provides a communication device including a printed circuit board as described in the first aspect. [Brief description of the drawing] The drawings herein are incorporated herein and constitute part of the disclosure, illustrating embodiments conforming to the disclosure and are used together with this specification to interpret the principles of the disclosure.

[0007] To more clearly explain the technical concepts in this disclosure or the prior art, the following briefly introduces the drawings necessary for describing the examples or the prior art, and obviously, for those skilled in the art, additional drawings can be obtained based on these drawings without any creative work. [Brief explanation of the drawing]

[0008] [Figure 1] In some cases, this is a schematic diagram of a printed circuit board with surface-mount component pads superimposed at a planar viewing angle. [Figure 2] This is a side view of a printed circuit board that may have surface-mount component pads. [Figure 3] This is a side view of a printed circuit board, possibly with a gold finger pad. [Figure 4] In some cases, this is an equivalent circuit diagram of a pad fan-out structure for a printed circuit board that has pads. [Figure 5] This is a side view 1 of a printed circuit board having pads provided in this disclosure. [Figure 6] This is a side view 2 of a printed circuit board having pads provided in this disclosure. [Figure 7]This is a schematic diagram of a printed circuit board having pads provided in this disclosure, superimposed at a planar viewing angle. [Figure 8] This diagram shows the schematic effect on channel impedance caused by adding stub anti-pads of different lengths as provided in this disclosure. [Figure 9] This diagram shows the signal insertion loss effect before and after adding the stub antipad provided in this disclosure. [Figure 10] This diagram shows the signal reflection loss effect before and after adding the stub antipad provided in this disclosure. [Figure 11] This is a schematic diagram of the fan-out structure of the first sub-reference layer provided in this disclosure. [Figure 12] This is a schematic diagram 1 of the fan-out structure of the second sub-reference layer provided in this disclosure. [Figure 13] Figure 2 shows a schematic diagram of the fan-out structure of the second sub-reference layer provided in this disclosure. [Figure 14] This is a schematic diagram 3 of the fan-out structure of the second sub-reference layer provided in this disclosure. [Modes for carrying out the invention]

[0009] To further clarify the purpose, technical proposal and merits of this disclosure, the technical proposal in this disclosure will be clearly and completely described below with reference to the drawings herein. The embodiments described herein are some of the embodiments, but not all of them. All other embodiments obtained by a person skilled in the art without creative work based on the embodiments in this disclosure are within the scope of this disclosure.

[0010] As signal speeds increase, so do the performance requirements for signal integrity (SI) in high-speed channels. In this context, signal reflection due to impedance discontinuities significantly impacts high-speed signals. Excessive reflection affects the transmission quality of high-speed signals, causing phenomena such as signal rise / fall, ringing, and ringback. Therefore, impedance optimization of high-speed channels is crucial.

[0011] When designing pads on a Printed Circuit Board (PCB), such as surface mount device (SMD) pads or goldfinger pads, the pads are designed to be long to ensure welding reliability, which often results in low impedance points. As shown in Figure 1, a conventional high-speed differential surface mount component pad (111) needs to be connected to a differential via (300) via a differential microstrip line (113) on the surface, with the inner layer fanned out via a differential strip line (121). The signal flow in this design is high-speed differential surface mount component pad (111) → differential microstrip line (113) → differential via (300) → differential strip line (121). From the standpoint of welding reliability, the high-speed differential surface mount component pad (111) needs to be longer than the end of the L-shaped fillet (400) in the longitudinal direction, and as shown in Figure 2, the branching structure in this section forms a stub (112), which affects the impedance of the high-speed differential surface mount component pad (111). Similar to surface mount component pads, to ensure the reliability of the gold finger contact, the contact between the gold finger pad (111) and the elastic sheet (500) has a stub (112) remaining from the end of the pad, which affects the impedance of the gold finger, as shown in Figure 3. Therefore, when the stub at the end of the surface mount component pad or gold finger pad is coupled to the reference ground, it creates a sudden change in capacitive impedance, and its equivalent circuit is shown in Figure 4, with C1 and C2, i.e., equivalent parts of the structure such as the equivalent capacitance of the pad stub, fillet, and path, as subscripted. Due to the influence of C1 and C2, the differential signal (P) accessed from the high-speed differential pad (111) is affected. P-IN and P N-IN This makes the signal more susceptible to reflection, degrading the transmission quality of high-speed signals. Therefore, the technical problem to be solved is how to reduce the values ​​of C1 and C2, which are capacitive couplings between the pad stub and the reference point, in order to improve the transmission quality of high-speed signals.

[0012] Referring to FIG. 5, FIG. 5 is a side view of a printed circuit board having pads provided in the present disclosure. As shown in FIG. 5, the printed circuit board includes a signal layer 100 and a reference layer 200. A pad 111 is installed on the signal layer 100, the pad 111 includes a stub 112, a first anti-pad 221 is installed on the reference layer 200, and the vertically inverted image of the stub 112 on the reference layer 200 is located within the coverage area of the first anti-pad 221. The first anti-pad 221 is used to reduce the impedance of the stub 112.

[0013] In an exemplary embodiment, the pad 111 may be a surface mount component pad, a gold finger pad, or other types of pads similar to surface mount component pads or gold finger pads, and the present disclosure is not particularly limited thereto. Whether the pad 111 is a surface mount component pad or a gold finger pad, both have a stub 112, and the principle is shown in FIGS. 2 and 3. For ease of explanation, subsequent embodiments will all be schematically described using surface mount component pads.

[0014] The signal layer 100 is used for accessing and transmitting high-speed signals, and the reference layer 200 is used to improve signal transmission quality by installing a first anti-pad 221, increasing the distance between the stub 112 and the reference, reducing capacitive coupling, and optimizing impedance. In one exemplary embodiment, the portion of the pad 111 that extends beyond the welded end a of the L-shaped fillet 400 in the longitudinal direction (i.e., the direction parallel to the information transmission direction) forms a stub 112. The signal layer 100 may have N pads 111, where N is any integer greater than or equal to 1, and each pad 111 may consist of two sub-pads, and is used for accessing high-speed differential signals. The portion of each pad 111 that extends beyond the welded end a of the L-shaped fillet 400 in the longitudinal direction forms a corresponding stub 112. The above reference layer 200 may have N first anti-pads 221 installed, with N first anti-pads 221 corresponding one-to-one with N pads 111, that is, one first anti-pad 221 is installed below the stub 112 region of each pad 111, and is used to reduce the impedance of the stub 112 region of each pad 111, thereby improving the transmission quality of each high-speed signal.

[0015] In an exemplary embodiment, as shown in FIG. 6, the signal layer 100 includes a first sub-signal layer 110 and a second sub-signal layer 120, the reference layer 200 includes a first sub-reference layer 210 and a second sub-reference layer 220, the first sub-signal layer 110, the first sub-reference layer 210, the second sub-reference layer 220, and the second sub-signal layer 120 are stacked and installed in sequence, and vias 300 that penetrate each other are installed in the first sub-signal layer 110, the first sub-reference layer 210, the second sub-reference layer 220, and the second sub-signal layer 120. A pad 111 and a first signal path 113 are installed in the first sub-signal layer 110, the pad 111 is connected to the first signal path 113, a second signal path 121 is installed in the second sub-signal layer 120, the first signal path 113 is connected to the second signal path 121 through the via 300, the second signal path 121 is used to fan out the signal, a second anti-pad 211 is installed in the first sub-reference layer 210, a first anti-pad 221 is installed in the second sub-reference layer 220, the second anti-pad 211 is used to reduce the impedance of the pad 111, and the vertically inverted image of the second anti-pad 211 in the second sub-reference layer 220 includes the covering area of the first anti-pad 221.

[0016] In an exemplary embodiment, the signal layer 100 may include a first sub-signal layer 110 and a second sub-signal layer 120 used for signal access and transmission, and the signal flow is pad 111 → first signal path 113 → via 300 → second signal path 121. The reference layer 200 may include a first sub-reference layer 210 and a second sub-reference layer 220. Therefore, the second anti-pad 211 on the first sub-reference layer 210 is used to reduce the impedance of the entire pad 111, and the first anti-pad 221 on the second sub-signal layer 120 is used to reduce the impedance of the stub 112, thereby further improving the signal transmission quality.

[0017] The installation methods for the first anti-pad 221 and the second anti-pad 211 are both implemented by removing the metal material from a portion of the metal reference layer and using an insulating medium material in place of the metal material in this region. In order to ensure that the impedance of the pad 111 can be reduced using the second anti-pad 211 on the first sub-reference layer 210, and then the impedance of the stub 112 can be reduced using the first anti-pad 221 on the second sub-signal layer 120, the vertically inverted image of the second anti-pad 211 on the second sub-reference layer 220 must include the covering region of the first anti-pad 221, meaning that the size of the second anti-pad 211 is larger than the size of the first anti-pad 221. In this way, the stub 112 and the first anti-pad 221 are not obstructed by the metal material portion of the first sub-reference layer 210, thereby ensuring the impedance optimization effect of the first anti-pad 221 on the stub 112.

[0018] In an exemplary embodiment, referring to Figure 7, Figure 7 is a schematic superimposed view in a planar field of view of a printed circuit board having the pads provided in this disclosure. As shown in Figure 7, pad 111 includes a first sub-pad 1111 and a second sub-pad 1112, first signal path 113 includes a first microstrip line 1131 and a second microstrip line 1132, second signal path 121 includes a first strip line 1211 and a second strip line 1212, first sub-pad 1111 is connected to first microstrip line 1131, first microstrip line 1131 is connected to first strip line 1211 via via 300, first sub-pad 1111 includes a first stub 1121, second sub-pad 1112 is connected to second microstrip line 1132, second microstrip line 1132 is connected to second strip line 1212 via via 300, and second sub-pad 1112 includes a second stub 1122.

[0019] In one exemplary embodiment, the number of first antipads 221 corresponds one-to-one with the number of pads 111, and the first antipads 221 are used to optimize the impedance of the first stub 1121 on the first subpad 1111 and the second stub 1122 on the second subpad 1112 within the pad 111. In this way, when the first subpad 1111 and the second subpad 1112 access the high-speed differential signal, the channel impedance of the high-speed differential signal can be optimized, reducing the effects of signal reflection on the high-speed differential signal and thereby improving the integrity of the high-speed differential signal.

[0020] In an exemplary embodiment, referring to Figure 7, the vertically inverted image of the first sub-pad 1111 on the first sub-reference layer 210 and the vertically inverted image of the second sub-pad 1112 on the first sub-reference layer 210 are both located within the covering area of ​​the second anti-pad 211, and the vertically inverted image of the first stub 1121 on the second sub-reference layer 220 and the vertically inverted image of the second stub 1122 on the second sub-reference layer 220 are both located within the covering area of ​​the first anti-pad 221.

[0021] In one exemplary embodiment, a second anti-pad 211 is added below the first sub-pad 1111 and the second sub-pad 1112 as a first reference layer 200 of pad 111, and the size of the second anti-pad 211 can be determined by simulation. By adding the second anti-pad 211 below the first sub-pad 1111 and the second sub-pad 1112 and reducing the capacitive coupling between the first sub-pad 1111 and the second sub-pad 1112 and the reference ground, the effect of lowering the impedance of the first sub-pad 1111 and the second sub-pad 1112 can be achieved. A first anti-pad 221 is added below the second anti-pad 211 as a second reference layer 200 of pad 111. The size of the first anti-pad 221 can be determined by simulation. By adding a first anti-pad 221 below the first stub 1121 and the second stub 1122, the capacitive coupling between the first stub 1121 and the second stub 1122 and the reference ground is reduced, thereby achieving the effect of lowering the impedance of the first stub 1121 and the second stub 1122. This avoids low impedance points, further reduces impedance fluctuations, and improves the channel bandwidth.

[0022] In this way, the second anti-pad 211 can effectively optimize the impedance of the first sub-pad 1111 and the second sub-pad 1112, and the first anti-pad 221 can further optimize the impedance of the first stub 1121 and the second stub 1122, thereby improving the signal transmission quality.

[0023] In an exemplary embodiment, continuing with reference to Figure 7, the first end of the vertically inverted image of the first stub 1121 and the first end of the vertically inverted image of the second stub 1122 both coincide with the first side of the covering area of ​​the first anti-pad 221, the second end of the vertically inverted image of the first stub 1121 and the second end of the vertically inverted image of the second stub 1122 both do not extend beyond the second side of the covering area of ​​the first anti-pad 221, the first end of the vertically inverted image of the first stub 1121 is the end closest to the via 300 of the vertically inverted image of the first stub 1121, and the second end of the vertically inverted image of the first stub 1121 is the The first end of the vertically inverted image of the first stub 1121 is opposite to the first end, the first end of the vertically inverted image of the second stub 1122 is the end closest to the via 300 of the vertically inverted image of the second stub 1122, the second end of the vertically inverted image of the second stub 1122 is opposite to the first end of the vertically inverted image of the second stub 1122, the first side of the covering area of ​​the first anti-pad 221 is the side closest to the via 300 of the covering area of ​​the first anti-pad 221, and the second side of the covering area of ​​the first anti-pad 221 is the side opposite to the first side of the covering area of ​​the first anti-pad 221.

[0024] Furthermore, the size and position of the first anti-pad 221 can be determined by simulation. If the first end of the vertically inverted image of the first stub 1121 and the first end of the vertically inverted image of the second stub 1122 both coincide with the first side of the covering area of ​​the first anti-pad 221, and the second end of the vertically inverted image of the first stub 1121 and the second end of the vertically inverted image of the second stub 1122 both do not exceed the second side of the covering area of ​​the first anti-pad 221, then the impedance optimization of the first stub 1121 and the second stub 1122 is relatively straightforward.

[0025] In one exemplary embodiment, the ratio of the distance from which the second side of the covering area of ​​the first anti-pad 221 exceeds the second end of the vertically inverted image of the first stub 1121 to the length of the first stub 1121 is less than 1, and the ratio of the distance from which the second side of the covering area of ​​the first anti-pad 221 exceeds the second end of the vertically inverted image of the second stub 1122 to the length of the second stub 1122 is less than 1.

[0026] In one exemplary embodiment, adding a stub anti-pad (i.e., the first anti-pad 221) can effectively reduce the impedance discontinuity problem at the end of the SMD pad, improving impedance matching and signal integrity representation, and optimizing channel reflection and insertion losses. Specifically, referring to Figures 8 to 10, Figure 8 shows the effect on channel impedance with and without a stub anti-pad and with stub anti-pads of different lengths, when the length of the stub 112 of pad 111 is 0.5 mm. In Figure 8, the horizontal axis represents the measurement time of the Time Domain Reflectometry (TDR), and the vertical axis represents the measured value (i.e., channel impedance) corresponding to each measurement time. As can be seen from Figure 8, the impedance continuity without a stub anti-pad is lower than the impedance continuity with a stub anti-pad, and the channel impedance continuity gradually increases as the length of the stub anti-pad increases, reaching optimal channel impedance continuity when the length of the stub anti-pad is 0.75 mm. At the same time, when the length of the stub anti-pad is 0.75 mm, the optimization effect on the insertion loss and reflection loss of high-speed signals becomes relatively clear, as shown in Figures 9 and 10. In Figure 9, the horizontal axis represents the signal frequency, and the vertical axis represents the insertion loss corresponding to each signal frequency. When the signal frequency reaches a certain frequency value, the insertion loss with the stub anti-pad added is higher than the insertion loss without the stub anti-pad. In Figure 10, the horizontal axis represents the signal frequency, and the vertical axis represents the reflection loss corresponding to each signal frequency. When the signal frequency reaches a certain frequency value, the reflection loss with the stub anti-pad added is lower than the reflection loss without the stub anti-pad. This disclosure represents an innovative advance in technical value compared to the prior art, achieving both signal integrity and design reliability solely from the perspective of designing the inner layer anti-pad of a printed circuit board, and solving the problem of signal distortion by optimizing the impedance of the pad stub, which could not be achieved in the prior art.

[0027] Furthermore, the length of the stub anti-pad is not necessarily better the longer it is. If the length of the stub anti-pad exceeds 1x the length of the stub 112, it will lead to a decrease in impedance continuity. Therefore, when setting the length of the stub anti-pad, the distance over which the stub anti-pad extends beyond the stub 112 is usually shorter than 1x the length of the stub 112. As shown in Figures 11 and 12, after adding the stub anti-pad, Figure 11 shows a schematic diagram of the fan-out structure of the first sub-reference layer 210 of pad 111, and Figure 12 shows a schematic diagram of the fan-out structure of the second sub-reference layer 220 of pad 111.

[0028] In one exemplary embodiment, the shape of the covering area of ​​the first anti-pad 221 is one of a rectangle, an ellipse, or a playground shape.

[0029] In one exemplary embodiment, if the covering area of ​​the first anti-pad 221 satisfies the above size requirement, the shape of the covering area of ​​the first anti-pad 221 may be any regular or irregular shape. In one exemplary embodiment, the shape of the covering area of ​​the first anti-pad 221 may be rectangular, elliptical, or playground-shaped. For example, the shape of the covering area of ​​the first anti-pad 221 may be rectangular, elliptical, or playground-shaped, as shown in Figures 13 and 14. In other words, the same effect can be obtained by replacing the rectangular first anti-pad 221 in Figure 12 with an elliptical first anti-pad 221 or a playground-shaped first anti-pad 221.

[0030] In one exemplary embodiment, referring to Figures 6 and 7, a third anti-pad 310 is further installed on the first sub-reference layer 210, and a fourth anti-pad 320 is further installed on the second sub-reference layer 220, with both the third anti-pad 310 and the fourth anti-pad 320 being used to reduce the impedance of the via 300. This further improves the transmission quality of high-speed signals.

[0031] In one exemplary embodiment, both the first sub-reference layer 210 and the second sub-reference layer 220 are metal layers connected to the grounding end.

[0032] In this way, the first anti-pad 221 and the second anti-pad 211 can be installed on the metal layer connected to the grounding end, and this can also serve as a reference point for the pad 111, thereby optimizing the impedance of the pad and the pad stub 112.

[0033] The design method for a printed circuit board having pads provided in this disclosure is as follows:

[0034] Step 1: Optimize the simulation. Step 1) Based on the connector pin specifications and system design requirements, confirm the pad size and printed circuit board stacking.

[0035] Step 2) Optimize the simulation for the printed circuit board, add pad antipads (i.e., the second antipad 211 above) and via antipads (i.e., the third antipad 310 and fourth antipad 320 above), and optimize the channel impedance by adjusting the fan-out lines.

[0036] Step 3) Add a pad stub anti-pad (i.e., the first anti-pad 221 described above), precisely optimize the impedance at the pad end position, and determine its size based on the simulation results.

[0037] Step 2: Create a light painting Gerber document. Step 1) Create a circuit diagram and add components such as connectors to create a layout and wiring.

[0038] Step 2) Output the circuit diagram and perform PCB design, designing the wire extraction method and anti-pads based on the simulation optimization results.

[0039] Step 3) Output the light painting file and arrange it for creating the printed circuit board.

[0040] In this way, if pad anti-pads and via anti-pads cannot continuously improve bandwidth, pad stub anti-pads can reduce the impedance fluctuations of the entire channel. This eliminates the need for pad resizing or pad grinding, and while ensuring welding reliability, it not only optimizes the impedance fluctuations of SMD pads but also reduces high-speed signal reflection and improves signal integrity.

[0041] Furthermore, the disclosure further provides a communication device, which includes a printed circuit board in any of the above embodiments. The communication device may be a printed circuit board including surface mount component pads or goldfinger pads, and is suitable for wired and wireless communication devices with a Gbps of 112 Gbps or higher.

[0042] This disclosure provides a printed circuit board and a communication device having pads, which solve the problem of high-speed signal transmission quality deteriorating due to the formation of capacitive impedance mutations when the stub at the end of the pad is coupled to a reference ground.

[0043] In this disclosure, the printed circuit board includes a signal layer and a reference layer. A pad is provided on the signal layer, the pad includes a stub, and a first anti-pad is provided on the reference layer, the vertically inverted image of the stub on the reference layer is located within the covering area of ​​the first anti-pad, and the first anti-pad is used to reduce the impedance of the stub. In this way, the first anti-pad is provided below the stub area of ​​the pad, and the capacitive coupling between the stub and the reference is reduced using the first anti-pad, thereby improving the transmission quality of high-speed signals.

[0044] In this specification, relational terms such as “First” and “Second” are used solely to distinguish one entity or action from the other, and do not necessarily require or suggest that any actual relationship or order exists between these entities or actions. Furthermore, the terms “includes,” “equipped with,” or any other variation thereof are intended to cover non-exclusive inclusion, and as a result, a process, method, article, or apparatus that includes a set of elements includes not only those elements, but also other elements not expressly enumerated, or elements specific to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase “includes” does not preclude the presence of other identical elements in a process, method, article, or apparatus that includes that element.

[0045] The foregoing describes only specific embodiments of the Disclosure, enabling those skilled in the art to understand or implement the Disclosure. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the Disclosure. Thus, the Disclosure is not limited to these embodiments shown herein, but rather conforms to the broadest scope that is consistent with the principles and novel features disclosed herein.

Claims

1. A printed circuit board having pads, comprising a signal layer and a reference layer, A pad is provided on the signal layer, and the pad includes a stub. A printed circuit board having a pad, wherein a first anti-pad is provided on the reference layer, the vertically inverted image of the stub on the reference layer is located within the covering area of ​​the first anti-pad, and the first anti-pad is used to reduce the impedance of the stub.

2. The signal layer includes a first sub-signal layer and a second sub-signal layer, and the reference layer includes a first sub-reference layer and a second sub-reference layer, and the first sub-signal layer, the first sub-reference layer, the second sub-reference layer and the second sub-signal layer are stacked in order, and vias are provided between the first sub-signal layer, the first sub-reference layer and the second sub-reference layer and the second sub-signal layer. The pad and the first signal path are installed in the first sub-signal layer, and the pad is connected to the first signal path. A second signal path is provided in the second sub-signal layer, the first signal path is connected to the second signal path via the via, and the second signal path is used to fan out the signal. The printed circuit board according to claim 1, wherein a second anti-pad is provided on the first sub-reference layer, a first anti-pad is provided on the second sub-reference layer, the second anti-pad is used to reduce the impedance of the pad, and the vertically inverted image of the second anti-pad on the second sub-reference layer includes the covering region of the first anti-pad.

3. The pad includes a first sub-pad and a second sub-pad, the first signal path includes a first microstrip line and a second microstrip line, and the second signal path includes a first strip line and a second strip line. The first sub-pad is connected to the first microstrip line, the first microstrip line is connected to the first strip line via the via, and the first sub-pad includes a first stub. The printed circuit board according to claim 2, wherein the second sub-pad is connected to the second microstrip line, the second microstrip line is connected to the second strip line via the via, and the second sub-pad includes a second stub.

4. The vertically inverted image of the first sub-pad on the first sub-reference layer and the vertically inverted image of the second sub-pad on the first sub-reference layer are both located within the covering area of ​​the second anti-pad. The printed circuit board according to claim 3, wherein both the vertically inverted image of the first stub on the second sub-reference layer and the vertically inverted image of the second stub on the second sub-reference layer are located within the covering area of ​​the first anti-pad.

5. The first end of the vertically inverted image of the first stub and the first end of the vertically inverted image of the second stub both coincide with the first side edge of the covering area of ​​the first anti-pad, and the second end of the vertically inverted image of the first stub and the second end of the vertically inverted image of the second stub both do not extend beyond the second side edge of the covering area of ​​the first anti-pad. The printed circuit board according to claim 4, wherein the first end of the vertically inverted image of the first stub is the end of the vertically inverted image of the first stub closest to the via, the second end of the vertically inverted image of the first stub is the end opposite to the first end of the vertically inverted image of the first stub, the first end of the vertically inverted image of the second stub is the end of the vertically inverted image of the second stub closest to the via, the second end of the vertically inverted image of the second stub is the end opposite to the first end of the vertically inverted image of the second stub, the first side of the covering area of ​​the first anti-pad is the side of the covering area of ​​the first anti-pad closest to the via, and the second side of the covering area of ​​the first anti-pad is the side opposite to the first side of the covering area of ​​the first anti-pad.

6. The printed circuit board according to claim 5, wherein the ratio of the distance from which the second side of the covering area of ​​the first antipad extends beyond the second end of the vertically inverted image of the first stub to the length of the first stub is less than 1, and the ratio of the distance from which the second side of the covering area of ​​the first antipad extends beyond the second end of the vertically inverted image of the second stub to the length of the second stub is less than 1.

7. The printed circuit board according to claim 6, wherein the shape of the covering area of ​​the first anti-pad is one of a rectangle, an ellipse, or a playground shape.

8. A third anti-pad is further installed on the first sub-reference layer, and a fourth anti-pad is further installed on the second sub-reference layer. The printed circuit board according to claim 2, wherein both the third anti-pad and the fourth anti-pad are used to reduce the impedance of the via.

9. The printed circuit board according to claim 8, wherein both the first sub-reference layer and the second sub-reference layer are metal layers connected to the ground terminal.

10. A communication device comprising a printed circuit board according to any one of claims 1 to 9.

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