Photoresist development using halogenated chemicals

Abstract

Resist development is useful, for example, for forming patterning masks in the context of high-resolution patterning. Development can be achieved using halide-containing chemicals, such as hydrogen halides. Dry or wet deposition techniques can be used to deposit metal-containing resist films onto semiconductor substrates. The resist film can be an EUV-sensitive organometallic oxide thin film resist or an organometallic-containing thin film resist. After exposure, the photopatterned metal-containing resist is developed using wet or dry development.

Description

[Background technology]

[0001] [Integration by reference] As part of this application, a PCT application is filed concurrently with this specification. As confirmed in the concurrently filed PCT application, each of the applications on which this application claims priority is incorporated herein by reference for all purposes.

[0002] The manufacturing of semiconductor devices such as integrated circuits is a multi-step process involving photolithography. Generally, this process involves depositing material onto a wafer and patterning the material using lithography techniques to form structural features (e.g., transistors and circuits) of a semiconductor device. Typical steps of a photolithography process known in the art include: preparing a substrate; applying a photoresist by spin coating or the like; exposing the photoresist in a desired pattern to make the exposed areas of the photoresist somewhat soluble in a developer; developing the photoresist by applying a developer to remove either the exposed or unexposed areas of the photoresist; and subsequently processing the areas of the substrate from which the photoresist has been removed, for example by etching or material deposition, to form features.

[0003] The evolution of semiconductor design has created the need to fabricate unprecedentedly fine features on semiconductor substrate materials, and has been driven by the ability to do so. Such technological advancements are characterized by Moore's Law, which states that transistor density in high-density integrated circuits doubles every two years. In fact, chip design and manufacturing have advanced so much that modern microprocessors can contain billions of transistors and other circuit functions on a single chip. Individual features on such chips can be on the order of 22 nanometers (nm) or less, and in some cases, less than 10 nm.

[0004] One of the challenges in manufacturing devices with such small features is the ability to reliably and reproducibly produce photolithography masks with sufficient resolution. Current photolithography processes typically use 193 nm ultraviolet (UV) light to expose photoresist. The fact that the light has a wavelength significantly larger than the desired size of the features fabricated on the semiconductor substrate creates an inherent problem. Achieving feature sizes smaller than the wavelength of light requires the use of complex resolution enhancement techniques such as multi-patterning. Therefore, there is considerable interest and research effort in developing photolithography techniques that use shorter wavelengths of light, such as extreme ultraviolet (EUV) with wavelengths of 10 nm to 15 nm, for example, 13.5 nm.

[0005] However, the EUV photolithography process can present challenges, including low light output and light loss during patterning. Conventional organic chemically amplified resists (CARs), similar to those used in 193nm UV lithography, have potential drawbacks when used in EUV lithography. In particular, they have low absorption coefficients in the EUV region, and the diffusion of photoactivating chemical species can cause blurring or line-edge roughness. Furthermore, fine features patterned on conventional CAR materials may result in a high aspect ratio, which carries the risk of pattern collapse, in order to provide the etching resistance necessary for patterning into the underlying device layer. Therefore, there remains a need for improved EUV photoresist materials with properties such as reduced thickness, greater absorbance, and greater etching resistance.

[0006] The "Background Art" provided herein is intended to provide a general overview of the context of this technology. Within the scope of the "Background Art" described herein, the work of the inventors named herein, as well as aspects of this specification that may not be considered prior art at the time of filing, are not recognized as prior art to this technology, either explicitly or implicitly. [Overview of the Initiative]

[0007] The development of a photoresist can be useful, for example, in relation to high-resolution patterning, for forming a patterning mask. Development can selectively remove either the exposed or unexposed areas of the resist using specific developing chemicals. Developing chemicals include halides, such as hydrogen halides or mixtures of hydrogen and halide gases. In some embodiments, development is dry development. In some embodiments, the resist is a photopatterned metal-containing EUV resist. In some embodiments, the dry development process is a thermal process without the use of plasma.

[0008] Disclosed herein are methods and systems for processing semiconductor substrates. The method for processing a semiconductor substrate includes, in a process chamber, providing a photopatterned metal-containing resist on a substrate layer of a semiconductor substrate, and developing the photopatterned metal-containing resist to form a resist mask by selectively removing a portion of the resist by exposure to a developing chemical containing a halide.

[0009] In some embodiments, the photopatterned metal-containing resist is a photopatterned metal-containing EUV resist. In some embodiments, developing the photopatterned metal-containing EUV resist involves selectively removing the EUV-unexposed portions of the EUV resist relative to the EUV-exposed portions using a developing chemical to form a resist mask. In some embodiments, the developing chemical includes hydrogen halides, hydrogen gas and halide gases, organic halides, acyl halides, carbonyl halides, thionyl halides, or mixtures thereof. In some embodiments, the developing chemical includes hydrogen fluoride, hydrogen chloride, hydrogen bromide, or hydrogen iodide. In some embodiments, developing the photopatterned metal-containing resist by exposure to a developing chemical includes dry developing the photopatterned metal-containing resist by exposure to a dry developing chemical. In some embodiments, dry developing the photopatterned metal-containing resist includes applying a remote plasma containing halide radicals to the resist. In some embodiments, the dry development of the photopatterned metal-containing resist is carried out at a temperature of -60°C to 120°C, a chamber pressure of 0.1 mTorr to 500 mTorr or about 0.5 Torr to about 760 Torrr, and a halide gas flow rate of 100 sccm to 2000 sccm, and the etching selectivity of the resist mask is adjustable at least partially based on temperature, chamber pressure, gas flow rate, or a combination thereof. In some embodiments, the temperature is -20°C to 20°C. In some embodiments, the photopatterned metal-containing resist contains elements selected from the group consisting of tin, hafnium, tellurium, bismuth, indium, antimony, iodine, and germanium. In some embodiments, the method further includes exposing the photopatterned metal-containing resist to an inert gas plasma after development of the photopatterned metal-containing resist.In some implementations, the method further includes depositing a metal-containing EUV resist film on a semiconductor substrate and non-selectively removing the metal-containing EUV resist film from the semiconductor substrate without removing the substrate layer before providing a photopatterned metal-containing resist.

[0010] Disclosed herein is an apparatus for developing resists. The apparatus includes a process chamber having a substrate support, a vacuum line coupled to the process chamber, and a developing chemical line coupled to the process chamber. The apparatus further includes a controller configured to have instructions for processing a semiconductor substrate, the instructions including a code for providing a photopatterned metal-containing resist on a substrate layer of a semiconductor substrate within the process chamber, and a code for developing the photopatterned metal-containing resist to form a resist mask by selectively removing a portion of the resist by exposure to a developing chemical containing a halide.

[0011] In some embodiments, the photopatterned metal-containing resist is a photopatterned metal-containing EUV resist, and the controller consists of commands, the commands including a code for developing the photopatterned metal-containing EUV resist, and a code for selectively removing the EUV-unexposed portions of the EUV resist relative to the EUV-exposed portions using developing chemicals to form a resist mask. In some embodiments, the apparatus further includes one or more heaters coupled to a substrate support, the one or more heaters including a plurality of independently controllable temperature control zones. In some embodiments, the inside of the process chamber is coated with a corrosion inhibitor. In some embodiments, the apparatus further includes a cold trap coupled to the process chamber, the cold trap configured to remove water from the process chamber. In some embodiments, the apparatus further includes a UV or IR lamp coupled to the process chamber, the UV or IR lamp configured to cure the photopatterned metal-containing resist or remove excess halides from the process chamber.

[0012] Disclosed herein is a method for processing a semiconductor substrate. The method includes: providing a dry-deposited photopatterned metal oxide EUV resist on a substrate layer of a semiconductor substrate in a process chamber; and dry-developing the photopatterned metal oxide EUV resist by selectively removing the non-EUV exposed portions of the EUV resist by exposure to a dry-developing chemical containing hydrogen halide, thereby forming a resist hard mask from the EUV exposed portions.

[0013] In some implementations, dry development is performed by a non-plasma thermal process, and exposure to dry development chemicals is carried out at temperatures of approximately -20°C to approximately 20°C. In some implementations, the photopatterned metal oxide EUV resist contains organotin oxides.

[0014] These features and other features of the disclosed embodiments will be described in detail below with reference to the accompanying drawings.

Brief Description of the Drawings

[0015] [Figure 1] FIG. 1 shows a flowchart of an exemplary method of depositing and developing a photoresist according to some embodiments.

[0016] [Figure 2A] FIG. 2A shows a schematic cross-sectional view of various processing stages of dry development according to some embodiments. [Figure 2B] FIG. 2B shows a schematic cross-sectional view of various processing stages of dry development according to some embodiments. [Figure 2C] FIG. 2C shows a schematic cross-sectional view of various processing stages of dry development according to some embodiments.

[0017] [Figure 3] FIG. 3 shows an exemplary dry development mechanism of the chemical reaction between hydrogen bromide (HBr) and the exposed and unexposed portions of an EUV photoresist according to some embodiments.

[0018] [Figure 4A] FIG. 4A shows a schematic cross-sectional view of dry development without applying an inert gas plasma according to some embodiments.

[0019] [Figure 4B] FIG. 4B shows a schematic cross-sectional view of a dry development repetitive inert gas plasma for descum treatment according to some embodiments.

[0020] [Figure 5] FIG. 5 shows a graph comparing the etching rates of an EUV photoresist using a helium plasma during dry development between the exposed and unexposed portions.

[0021] [Figure 6A]Figure 6A shows scanning electron microscope (SEM) images comparing wet development and dry development in terms of line breakdown. [Figure 6B] Figure 6B shows scanning electron microscope (SEM) images comparing wet development and dry development in terms of line breakdown.

[0022] [Figure 7A] Figure 7A shows SEM images comparing wet development and dry development in terms of roughness and critical dimension (CD) control. [Figure 7B] Figure 7B shows SEM images comparing wet development and dry development in terms of roughness and critical dimension (CD) control.

[0023] [Figure 8] Figure 8 shows SEM images comparing wet development and dry development for scum after opening the hard mask.

[0024] [Figure 9A] Figure 9A shows a graph illustrating the effect of the second post-exposure bake process on the selectivity of dry development at various pressures and temperatures. [Figure 9B] Figure 9B shows a graph illustrating the effect of the second post-exposure bake process on the selectivity of dry development at various pressures and temperatures.

[0025] [Figure 10] Figure 10 shows an SEM image illustrating the effect of pressure on the EUV resist profile.

[0026] [Figure 11A] Figure 11A shows SEM images of EUV resists at different line / space pitches and thicknesses. [Figure 11B] Figure 11B shows SEM images of EUV resists at different line / space pitches and thicknesses.

[0027] [Figure 12]Figure 12 shows a schematic diagram of an exemplary process station for maintaining a low-pressure environment suitable for performing developing, cleaning, reworking, decamming, and smoothing operations, according to several embodiments.

[0028] [Figure 13] Figure 13 shows a schematic diagram of an exemplary multi-station processing tool suitable for performing the various developing, cleaning, reworking, decamming, and smoothing operations described herein.

[0029] [Figure 14] Figure 14 shows a schematic cross-sectional view of an example of an inductively coupled plasma apparatus for performing the specific embodiments and operations described herein.

[0030] [Figure 15] Figure 15 shows a semiconductor process cluster tool architecture having a vacuum transfer module and a vacuum integrated deposition and patterning module interfaced with a vacuum transfer module, suitable for realizing the processes described herein. [Modes for carrying out the invention]

[0031] This disclosure generally relates to the field of semiconductor processing. In particular aspects, this disclosure relates to processes and apparatus for developing photoresists (e.g., EUV-sensitive metal-containing photoresists and / or metal oxide-containing photoresists) using halogenated chemicals for forming patterning masks, for example in connection with EUV patterning.

[0032] This specification provides detailed references to specific embodiments of the Disclosure. Examples of specific embodiments are shown in the accompanying drawings. While the Disclosure is described in relation to these specific embodiments, it will be understood that the Disclosure is not intended to be limited to such specific embodiments. Rather, the Disclosure is intended to cover alternative forms, modifications, and equivalents that may be included in the spirit and scope of the Disclosure. The following description contains numerous specific details to provide a complete understanding of the Disclosure. The Disclosure may be implemented without some or all of these specific details. In other cases, well-known process operations are not described in detail so as not to unnecessarily obscure the Disclosure.

[0033] introduction Thin film patterning in semiconductor processing is often a crucial step in semiconductor manufacturing. Patterning involves lithography. In conventional photolithography, such as 193nm photolithography, photons from a photon source are emitted onto a mask, and a pattern is printed onto a photosensitive photoresist. This causes a chemical reaction within the photoresist, and after development, a specific portion of the photoresist is removed to form the pattern.

[0034] Advanced technology nodes (as defined by the International Semiconductor Technology Roadmap) include 22nm, 16nm, and beyond. For example, at the 16nm node, the width of a typical via or line in a damascene structure is typically around 30nm or less. The scaling of features on advanced semiconductor integrated circuits (ICs) and other devices is driving improvements in lithography resolution.

[0035] Extreme ultraviolet (EUV) lithography can extend lithography techniques by shifting to shorter imaging light source wavelengths than those achievable with conventional photolithography methods. EUV light sources with wavelengths of approximately 10–20 nm, or 11–14 nm, for example, 13.5 nm, can be used in state-of-the-art lithography tools, also known as scanners. EUV radiation operates in a vacuum because it is strongly absorbed by a wide range of solid and fluid materials, including quartz and water vapor.

[0036] EUV lithography utilizes an EUV resist patterned to form a mask used for etching the underlying layer. The EUV resist may be a polymer-based chemically amplified resist (CAR) manufactured by liquid-based spin-on technology. An alternative to CAR is a directly photopatternable metal oxide-containing film, which is available, for example, from Inpria (Corvallis, OR) and described, for example, in U.S. Patent Publications 2017 / 0102612, 2016 / 021660, and 2016 / 0116839, which are incorporated herein by reference with respect to disclosures of at least photopatternable metal oxide-containing films. Such films may be manufactured by spin-on technology or dry vapor deposition. Metal oxide-containing films can be directly patterned (i.e., without using a separate photoresist) by EUV exposure in a vacuum environment, as described, for example, in U.S. Patent No. 9,996,004, issued June 12, 2018, titled "PHOTOPATTERNING OF VAPOR-DEPOSITED METAL OXIDE-CONTAINING HARDMASKS," and / or in International Application No. PCT / US19 / 31618, filed May 9, 2019, titled "METHODS FOR MAKING EUV PATTERNABLE HARD MASKS," providing a patterning resolution of less than 30 nm. At least the portions of these disclosures relating to the composition, deposition, and patterning of directly photopatternable metal oxide films are incorporated herein by reference. Generally, patterning involves exposing an EUV resist with EUV radiation to form a photopattern within the resist, followed by development to remove a portion of the resist corresponding to the photopattern to form a mask.

[0037] Furthermore, while this disclosure relates to lithography patterning techniques and materials exemplified by EUV lithography, it should be understood that they are also applicable to other next-generation lithography techniques. In addition to EUV, including the standard 13.5 nm EUV wavelength currently in use and under development, the radiation sources most relevant to such lithography are DUV (deep-UV), which generally refers to the use of 248 nm or 193 nm excimer laser sources; X-rays, which formally include EUV in the low-energy range of the X-ray range; and electron beams that can cover a wide energy range. Specific methods may depend on the specific materials and applications used in the semiconductor substrate and the final semiconductor device. Therefore, the methods described in this application are merely examples of methods and materials that may be used in this technique.

[0038] Directly photopatternable EUV resists consist of, or may contain, metals and / or metal oxides mixed in an organic component. Metals / metal oxides are highly promising in that they enhance EUV photon adsorption, generate secondary electrons, and / or increase etching selectivity for the underlying layer stack and device layers. To date, these resists have been developed using wet (solvent) methods, which require moving wafers to a track where they are exposed to a developing solvent, dried, and baked. Wet development not only limits productivity but can also lead to line collapse due to surface tension and / or delamination.

[0039] Dry development techniques have been proposed to overcome these problems by eliminating delamination and interface defects in substrates. Dry development can improve performance (e.g., by preventing line collapse due to surface tension and delamination in wet development) and increase throughput (e.g., by avoiding wet development tracks). Other advantages may include eliminating the use of organic solvents, reducing sensitivity to adhesion problems, increasing EUV absorption to improve dose efficiency, and being free from solubility-based limitations. Dry development can also offer greater adjustability and provide further limiting dimension (CD) control and scum removal.

[0040] Dry development presents unique challenges compared to wet development, including etching selectivity between unexposed and EUV-exposed resist materials, which can lead to larger dose-to-size requirements for effective resist exposure. If selectivity is suboptimal, prolonged exposure under etching gas can result in corner rounding of the PR corners, potentially increasing line CD variability in subsequent transfer etching steps.

[0041] Development of EUV resist According to various embodiments of this disclosure, a photopatterned metal-containing photoresist is developed by exposure to a halide-containing chemical. A film containing an EUV-sensitive metal or metal oxide, such as an organotin oxide, is placed on a semiconductor substrate. The film containing the EUV-sensitive metal or metal oxide is directly patterned by EUV exposure in a vacuum environment. The pattern is then developed using a developing chemical to form a resist mask. In some embodiments, the developing chemical is a dry developing chemical. In some embodiments, the dry developing chemical comprises hydrogen and a halide. Such dry developing techniques may be performed using either a gentle plasma (high pressure, low power) or thermal process while flowing the hydrogen and halide dry developing chemicals. This disclosure provides processes and apparatus configured to develop a metal-containing resist as part of a resist mask formation process. Various embodiments include combinations of all dry operations, including vapor deposition, EUV lithography patterning, and dry development. Various other embodiments include combinations of wet and dry processing operations, for example, a spin-on EUV photoresist (wet process) may be combined with dry development or other wet or dry processes as described herein. Various post-deposition (or post-coating) processes are also described, including bevel and back surface cleaning, chamber cleaning, decamming, smoothing, curing to modify and enhance film properties, and photoregistry work processing.

[0042] Figure 1 shows a flowchart of an exemplary method for depositing and developing a photoresist according to several embodiments. The operations of process 100 may be carried out in a different order and / or with different operations, fewer operations, or additional operations. Embodiments of process 100 can be described with reference to Figures 2A-2C, Figure 3, and Figures 4A-4B. One or more operations of process 100 may be carried out using the apparatus described in any one of Figures 12-15. In some embodiments, the operations of process 100 may be implemented at least in part according to software stored in one or more non-temporary computer-readable media.

[0043] In block 102 of process 100, a layer of photoresist is deposited. This may be either a dry deposition process such as a vapor deposition process, or a wet process such as a spin-on deposition process.

[0044] The photoresist may be a metal-containing EUV resist. Films containing an EUV-sensitive metal or metal oxide may be deposited on a semiconductor substrate by any suitable technique, including wet (e.g., spin-on) or dry (e.g., CVD) deposition techniques. For example, the described process has been demonstrated for organotin oxide-based EUV photoresist compositions and is applicable to both commercially spin-coatable formulations (e.g., those available from Inpria Corp (Corvallis, OR)) and formulations to which dry vacuum deposition techniques, further described below, are applied.

[0045] The semiconductor substrate may include any material structure suitable for photolithography, particularly suitable for the manufacture of integrated circuits and other semiconductor devices. In some embodiments, the semiconductor substrate is a silicon wafer. The semiconductor substrate may be a silicon wafer on which features having an irregular surface topography are fabricated ("underlying features"). As used herein, "surface" is a surface on which the film of the present disclosure will be deposited, or a surface that will be exposed to EUV during processing. The underlying features may include areas where material has been removed (e.g., by etching) or areas where material has been added (e.g., by deposition) during processing prior to carrying out the method of the present disclosure. Such pre-processing may include the method of the present disclosure or other processing methods in an iterative process on which two or more layers of features are formed on the substrate.

[0046] EUV photosensitive thin films may be deposited on a semiconductor substrate, and such films can be used as resists for subsequent EUV lithography and processing. Such EUV photosensitive thin films, upon exposure to EUV, undergo changes such as the loss of bulky pendant substituents bonded to metal atoms in low-density M-OH-rich materials, enabling crosslinking to higher-density MOM-bonded metal oxide materials. EUV patterning creates regions of the film with altered physical or chemical properties compared to unexposed regions. These properties can be utilized in subsequent processing, for example, by dissolving either the unexposed or exposed regions, or by selectively depositing material in either the exposed or unexposed regions. In some embodiments, under conditions in which such subsequent processing is performed, the unexposed film has a more hydrophobic surface than the exposed film. For example, material removal may be carried out by utilizing differences in chemical composition, density, and film crosslinking. Removal may be performed by wet or dry processing, as further described below.

[0047] In various embodiments, the thin film is an organometallic material, such as an organotin material containing tin oxide or other metal oxide materials / parts. The organometallic compound can be formed by a gas-phase reaction of an organometallic precursor and a reactant. In various embodiments, the organometallic compound is formed by mixing a specific combination of an organometallic precursor having a bulky alkyl group or fluoroalkyl group and a reactant, and polymerizing the mixture in the gas phase to produce a low-density EUV photosensitive material deposited on a semiconductor substrate.

[0048] In various embodiments, the organometallic precursor contains at least one alkyl group for each metal atom that can withstand a gas-phase reaction, while the ligand or ion coordinated to the metal atom can be substituted by a reactant. The organometallic precursors include those having the following chemical formula. M a R b L c (Formula 1) Where M is an element having a high patterning radiation absorption cross-section; R is alkyl, such as C n H 2n+1 where, preferably, n ≧ 2; L is a ligand, ion, or other moiety that reacts with the reactant, and a ≧ 1, b ≧ 1, and c ≧ 1.

[0049] In various embodiments, M has an atomic absorption cross-section of 1x10 7 cm 2 / mol or more. M may be selected from the group consisting of, for example, tin, hafnium, tellurium, bismuth, indium, antimony, iodine, germanium, and combinations thereof. In some embodiments, M is tin. R may be fluorinated, for example, having the chemical formula C n F x H (2n+1), has. In various embodiments, R has at least one beta-hydrogen or beta-fluorine. For example, R may be selected from the group consisting of ethyl, i-propyl, n-propyl, t-butyl, i-butyl, n-butyl, sec-butyl, n-pentyl, i-pentyl, t-pentyl, sec-pentyl, and mixtures thereof. L may be any moiety that is readily substituted with a reactant to generate an M-OH moiety, such as moieties selected from the group consisting of amines (dialkylamino, monoalkylamino, etc.), alkoxys, carboxylic acids, halogens, and mixtures thereof.

[0050] The organometallic precursor may be any of the wide variety of candidate metal-organic precursors. For example, when M is tin, such precursors include t-butyltris(dimethylamino)tin, i-butyltris(dimethylamino)tin, n-butyltris(dimethylamino)tin, sec-butyltris(dimethylamino)tin, i-propyl(tris)dimethylaminotin, n-propyltris(dimethylamino)tin, ethyltris(dimethylamino)tin, and similar alkyl(tris)(t-butoxy)tin compounds such as t-butyltris(t-butoxy)tin. In some embodiments, the organometallic precursor is partially fluorinated.

[0051] The reactant has the ability to substitute a reactive moiety, ligand, or ion (e.g., L in Formula 1 above) to bond at least two metal atoms by chemical bonding. The reactant may include water, peroxides (e.g., hydrogen peroxide), dihydroxy alcohol or polyhydroxy alcohol, fluorinated dihydroxy alcohol or fluorinated polyhydroxy alcohol, fluorinated glycol, and other sources of the hydroxyl moiety. In various embodiments, the reactant reacts with the organometallic precursor by forming oxygen bridges between adjacent metal atoms. Other potential reactants include hydrogen sulfide and hydrogen disulfide, which can bridge metal atoms by sulfur bridges.

[0052] The thin film may contain optional materials in addition to organometallic precursors and reactants to modify the chemical or physical properties of the film, for example, to alter the photosensitivity of the film to EUV or to increase its etching resistance. Such optional materials may be introduced by doping during vapor phase formation, for example, before deposition on a semiconductor substrate, after deposition of the thin film, or both. In some embodiments, a mild remote H2 plasma may be introduced to replace some Sn-L bonds with Sn-H bonds, thereby increasing the reactivity of the resist under EUV.

[0053] In various embodiments, EUV patternable films are fabricated and deposited on semiconductor substrates using vapor deposition equipment and processes known in the art. In such processes, polymerized organometallic materials are formed on the surface of the semiconductor substrate in the vapor phase or in situ. Preferred processes include, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), and ALD including CVD elements, such as discontinuous ALD-like processes in which metal precursors and reactants are separated by time or space.

[0054] Generally, the method includes mixing a vapor stream of organometallic precursors with a vapor stream of a reaction agent to form a polymerized organometallic material, and depositing the organometallic material onto the surface of a semiconductor substrate. In some embodiments, the vapor stream contains two or more organometallic precursors. In some embodiments, the vapor stream contains two or more reaction agents. As will be understood by those skilled in the art, the mixing and deposit aspects of the process may be simultaneous in a substantially continuous process.

[0055] In an exemplary continuous CVD process, two or more gas streams of organometallic precursors and reactant sources are introduced into the deposition chamber of the CVD apparatus via separate inlet pathways, where they are mixed and reacted in the gas phase to form an agglomerated polymer material (e.g., metal-oxygen-metal bond formation). These streams may be introduced, for example, using separate inlets or dual plenum showerheads. The apparatus is configured such that the organometallic precursor stream and the reactant stream are mixed in the chamber, and the organometallic precursor and reactant react to produce a polymerized organometallic material. Without limiting the mechanism, function, or utility of the present technique, it is believed that the products from such gas-phase reactions have a heavier molecular weight because the metal atoms are crosslinked by the reactant, and then condense or deposit on a semiconductor substrate. In various embodiments, the steric hindrance of bulky alkyl groups prevents the formation of densely packed networks, resulting in the formation of smooth, porous, low-density films.

[0056] The CVD process is generally carried out under reduced pressure, such as 10 millitorre to 10 torre. In some embodiments, the process is carried out at 0.5 to 2 torre. In some embodiments, the temperature of the semiconductor substrate is below the temperature of the reactant stream. For example, the substrate temperature may be 0°C to 250°C, or ambient temperature (e.g., 23°C) to 150°C. In various processes, the deposition of polymerized organometallic material onto the substrate occurs at a rate inversely proportional to the surface temperature.

[0057] In some embodiments, EUV patternable films are fabricated and deposited on semiconductor substrates using wet deposition equipment and processes known in the art. For example, organometallic materials are formed by spin coating onto the surface of a semiconductor substrate.

[0058] The thickness of the EUV patternable film formed on the surface of a semiconductor substrate may vary depending on the surface properties, the materials used, and the processing conditions. In various embodiments, the film thickness may be in the range of 0.5 nm to 100 nm and may be thick enough to absorb most of the EUV light under EUV patterning conditions. The EUV patternable film may be able to accommodate absorption of 30% or more, thereby significantly reducing the number of available EUV photons towards the bottom of the EUV patternable film. Higher EUV absorption leads to more crosslinking and densification near the top of the EUV lithography film compared to the bottom of the EUV lithography film. Insufficient crosslinking may cause the resist to lift or collapse during wet development, but this risk does not exist with dry development. All-dry lithography techniques may facilitate more efficient utilization of EUV photons by using a more opaque resist film. Efficient utilization of EUV photons can occur with an EUV patternable film with higher overall absorption, although it will be understood that in some cases the EUV patternable film may have less than approximately 30% absorption. For comparison, the maximum overall absorption of most other resist films is less than 30% (e.g., 10% or less, or 5% or less), so the resist material at the bottom of the resist film is sufficiently exposed. In some embodiments, the film thickness is 10 nm to 40 nm, or 10 nm to 20 nm. Without limiting the mechanism, function, or utility of the present disclosure, unlike wet spin coating processes of the art, the process of the present disclosure is considered to have fewer limitations on the surface adhesion properties of the substrate and can therefore be applied to a wide variety of substrates. In addition, as described above, the deposited film may closely conform to surface features, providing the advantage that a mask is formed on a substrate such as a substrate with underlying features without "filling" or planarizing such features.

[0059] In block 104, an optional cleaning process is performed to clean the back surface and / or bevel edge of the semiconductor substrate. Cleaning the back surface and / or bevel edge can non-selectively etch the EUV resist film to uniformly remove films with varying levels of oxidation or crosslinking on the back surface and bevel edge of the substrate. During the application of EUV patternable films by either wet or dry deposition, unintended deposition of resist material may occur on the bevel edge and / or back surface of the substrate. Unintended deposition can cause unwanted particles to later migrate to the top surface of the semiconductor substrate, resulting in particle defects. Furthermore, this bevel edge and back surface deposition can cause downstream processing problems, including contamination of patterning (scanner) and developing tools. Traditionally, the removal of this bevel edge and back surface deposition has been performed by wet cleaning techniques. In the case of spin-coated photoresist materials, this process is called edge bead removal (EBR) and is performed by directing a flow of solvent from above and below the bevel edge while the substrate is rotating. The same process can be applied to soluble organotin oxide-based resists deposited by vapor deposition technology.

[0060] Cleaning the bevel edges and / or back surfaces of a substrate may also be a dry cleaning process. In some embodiments, the dry cleaning process involves vapor and / or plasma having one or more of the following gases: HBr, HCl, BCl3, SOCl2, Cl2, BBr3, H2, O2, PCl3, CH4, methanol, ammonia, formic acid, NF3, and HF. In some embodiments, the dry cleaning process may use the same chemicals as the dry developing process described herein. For example, cleaning the bevel edges and back surfaces may use hydrogen halide developing chemicals. In the cleaning process of the back surfaces and bevel edges, the vapor and / or plasma must be limited to specific areas of the substrate to ensure that only the back surfaces and bevels are removed without any degradation of the film on the substrate surface.

[0061] Process conditions may be optimized for cleaning the bevel edge and back surface. In some embodiments, higher temperatures, higher pressures, and / or larger reactant flow rates may lead to increased etching rates. Suitable process conditions for dry bevel edge and back surface cleaning may be, depending on the photoresist film and its composition and properties, a reactant flow rate of 100 to 10000 sccm (e.g., 500 sccm of HCl, HBr, HI, or H2 with Cl2 or Br2, BCl3 or H2), a temperature of 20 to 140°C (e.g., 80°C), a pressure of 20 to 1000 mTorr (e.g., 100 mTorr), a plasma power of 0 to 500 W at high frequency (e.g., 13.56 MHz), and a time of approximately 10 to 20 seconds. These conditions are suitable for some processing reactors, e.g., the Kiyo etching tool available from Lam Research Corporation (Fremont, CA), but it should be understood that a wider range of process conditions may be used depending on the capabilities of the processing reactor.

[0062] Alternatively, the dry cleaning operation may be extended to complete photoresist removal or photoresist "rework" where the applied EUV photoresist is removed, and to semiconductor substrates prepared for photoresist reapplication, such as when the original photoresist is damaged or defective. Since the photoresist rework must be carried out without damaging the underlying semiconductor substrate, oxygen-based etching should be avoided. Instead, modified forms of the halide-containing chemicals described herein may be used. It will be understood that the photoregistry work operation may be applied at any stage in process 100. Thus, the photoresist rework operation may be applied after photoresist deposition, after bevel edge and back surface cleaning, after PAB treatment, after EUV exposure, after PEB treatment, or after development. In some embodiments, the photoregistry work may be carried out for removal that is non-selective to exposed and unexposed areas of the photoresist, but selective to the underlying layer.

[0063] In some embodiments, the photoregistry work process involves vapors and / or plasmas having one or more of the following gases: HBr, HCl, HI, BCl3, Cl2, BBr3, H2, PCl3, CH4, methanol, ammonia, formic acid, NF3, and HF. In some embodiments, the photoregistry work process may use the same chemicals as the dry development process described herein. For example, photoresist rework may use hydrogen halide developing chemicals.

[0064] Process conditions may be optimized for photoregistry work. In some embodiments, higher temperatures, higher pressures, and / or larger reactant flow rates can lead to increased etching rates. Suitable process conditions for photoregistry work, depending on the photoresist film and its composition and properties, include a reactant flow rate of 100-500 sccm (e.g., 500 sccm of HCl, HBr, HI, BCl3, or H2 and Cl2 or Br2), a temperature of 20-140°C (e.g., 80°C), a pressure of 20-1000 mTorr (e.g., 300 mTorr), a plasma power of 300-800 W (e.g., 500 W) at high frequency (e.g., 13.56 MHz), and a wafer bias of 0-200 V, sufficient to completely remove the EUV photoresist. b (A higher bias may be used for harder substrate materials), and the time may be approximately 20 seconds to 3 minutes. These conditions are suitable for some processing reactors, such as the Kiyo etching tool available from Lam Research Corporation (Fremont, CA), but it should be understood that a wider range of process conditions may be used depending on the capabilities of the processing reactor.

[0065] In block 106 of process 100, an optional post-application bake (PAB) is performed after the deposition of the EUV patternable film and before EUV exposure. The PAB treatment may involve a combination of heat treatment, chemical exposure, and moisture to enhance the EUV photosensitivity of the EUV patternable film, thereby reducing the EUV dose required to develop a pattern on the film. The PAB treatment temperature may be adjusted and optimized to enhance the sensitivity of the EUV patternable film. For example, the treatment temperature may be about 90°C to about 200°C, or about 150°C to about 190°C. In some embodiments, the PAB treatment may be performed at a pressure between atmospheric pressure and vacuum, and for a treatment duration of about 1 to 15 minutes, for example, about 2 minutes. In some embodiments, the PAB treatment is performed at a temperature of about 100°C to 200°C for about 1 to 2 minutes.

[0066] In block 108 of process 100, the metal-containing EUV resist film is exposed to EUV radiation to develop the pattern. Generally speaking, EUV exposure causes changes in the chemical composition and crosslinking of the metal-containing EUV resist film, generating contrast in etching selectivity, which can be utilized in subsequent development.

[0067] A metal-containing EUV resist film may then be patterned by exposing regions of the film to EUV light, typically under relatively high vacuum. Useful EUV devices and imaging methods described herein include those known in the art. Specifically, as described above, EUV patterning creates exposed regions of the film that have altered physical or chemical properties compared to unexposed regions. For example, metal-carbon bond cleavage may occur in the exposed regions, such as through the elimination of beta-hydride groups, resulting in reactive and accessible metal hydride functional groups that can be converted to hydroxide and crosslinked metal oxide moieties via metal-oxygen bridges during a subsequent post-exposure bake (PEB) step. This process can be used to create chemical contrast for development as a negative resist. Generally, a greater number of beta-H groups in the alkyl group results in a more sensitive film. This can also be described as weaker Sn-C bonds with more branching. Following exposure, the metal-containing EUV resist film may be baked to create additional crosslinking in the metal oxide film. In subsequent processing, the differences in properties between the exposed and unexposed areas may be utilized, such as dissolving the unexposed areas or depositing material in the exposed areas. For example, a metal oxide-containing mask can be formed by developing the pattern using a dry method.

[0068] Specifically, in various embodiments, hydrocarbyl-terminated tin oxide present on the surface is converted to hydrogen-terminated tin oxide in the exposed region of the imaging layer, particularly when exposure is performed in a vacuum using EUV. However, by removing the exposed imaging layer from the vacuum and exposing it to air, or by controlling the introduction of oxygen, ozone, H2O2, or water, the surface Sn-H can be oxidized to Sn-OH. For example, the difference in properties between the exposed and unexposed regions may be utilized in subsequent processing by selectively adding or removing material from the imaging layer by reacting the irradiated region, the unirradiated region, or both with one or more reagents.

[0069] Without limiting the mechanism, function, or effectiveness of this technology, for example, 10 mJ / cm² 2 ~100mJ / cm 2 EUV exposure at this dose results in the cleavage of Sn-C bonds, which in turn eliminates alkyl substituents, alleviates steric hindrance, and allows for the breakdown of low-density films. In addition, the reactive metal-H bonds generated in the beta-hydride elimination reaction react with adjacent active groups such as hydroxyls in the film, leading to further crosslinking and densification, which can create a chemical contrast between exposed and unexposed areas.

[0070] When a metal-containing EUV resist film is exposed to EUV light, a photopatterned metal-containing EUV resist is produced. The photopatterned metal-containing EUV resist includes EUV-exposed and unexposed regions.

[0071] In block 110 of process 100, an optional post-exposure bake (PEB) is performed to further increase the contrast of the etching selectivity of the photopatterned metal-containing EUV resist. The photopatterned metal-containing EUV resist may be heat-treated in the presence of various chemical species to promote crosslinking of the EUV-exposed areas, or it may simply be baked on a hot plate in ambient air at, for example, 150°C to 250°C for 1 to 5 minutes (e.g., 190°C for 2 minutes).

[0072] In various embodiments, the bake strategy includes careful control of the bake environment, introduction of reactive gases, and / or careful control of the ramp rate of the bake temperature. Examples of useful reactive gases include, for example, air, H2O, H2O2 vapor, CO2, CO, O2, O3, CH4, CH3OH, N2, H2, NH3, N2O, NO, alcohols, acetylacetone, formic acid, Ar, He, or mixtures thereof. The PEB treatment is designed to (1) promote the complete evaporation of organic fragments generated during EUV exposure, (2) oxidize any Sn-H, Sn-Sn, or Sn radical species generated in the metal hydroxide by EUV exposure, and (3) promote bridging between adjacent Sn-OH groups to form a more densely bridging network such as SnO2. The bake temperature is carefully selected to achieve optimal EUV lithography performance. If the PEB temperature is too low, bridging will be insufficient, resulting in reduced chemical contrast for development at a given dose. If the PEB temperature is too high, adverse effects will occur, including severe oxidation and film shrinkage in the unexposed areas (in this example, the areas removed by developing the patterned film to form a mask), as well as undesirable interdiffusion at the interface between the photopatterned metal-containing EUV resist and the underlying layer, both of which can lead to loss of chemical contrast and increased defect density due to insoluble scum. The PEB treatment temperature may be about 100°C to about 300°C, about 170°C to about 290°C, or about 200°C to about 240°C. In some embodiments, the PEB treatment may be carried out at a pressure between atmospheric pressure and vacuum, and for a treatment duration of about 1 to 15 minutes, for example, about 2 minutes. In some embodiments, the PEB heat treatment may be repeated to further increase etching selectivity.

[0073] In block 112 of process 100, the photopatterned metal-containing EUV resist is developed to form a resist mask. In various embodiments, either the exposed areas are removed (positive type) or the unexposed areas are removed (negative type). In some embodiments, development may include selective deposition of the photopatterned metal-containing EUV resist on either the exposed or unexposed areas, followed by etching. In various embodiments, these processes may be dry or wet processes. In some embodiments, development may be carried out without generating plasma. Alternatively, development may be carried out by a flow of hydrogen and halides (e.g., H2, and Cl2, and / or Br2) activated in a remote plasma source or activated by exposure to remote UV radiation. The photoresist for development may contain elements selected from the group consisting of tin, hafnium, tellurium, bismuth, indium, antimony, iodine, and germanium. These elements may have a large patterning radiation absorption cross-section. In some embodiments, these elements may have a large EUV absorption cross-section. In some embodiments, metal-containing EUV resists can have an overall absorption rate exceeding 30%. In a full dry lithography process, this results in more efficient utilization of EUV photons, enabling the development of thicker and more opaque resists.

[0074] An example of a development process involves applying an EUV exposure dose and post-exposure baking to an organotin oxide-containing EUV-sensitive photoresist thin film (e.g., 10-30 nm thick, e.g., 20 nm thick), followed by development. The photoresist film may be deposited based on a gas-phase reaction between an organotin precursor, such as isopropyl(tris)(dimethylamino)tin, and water vapor, or it may be a spin-on film containing tin clusters in an organic matrix.

[0075] Photopatterned metal-containing EUV resists are developed by exposure to a developing chemical, which is a halide-containing chemical. In some embodiments, the developing chemical includes hydrogen and a halide, such as hydrogen halides (e.g., HBr or HCl), or hydrogen and a halogen gas (e.g., H2 and Cl2). In some embodiments, the developing chemical includes hydrogen halides, hydrogen and a halogen gas, boron trichloride, or a combination thereof. Development of the EUV resist can be carried out by wet development using a halide-containing chemical, or by dry development using a hydrogen halide-containing chemical. In embodiments where the EUV resist is developed using wet development, the wet development may be combined with other wet processing operations, such as wet deposition of the metal-containing EUV resist film (e.g., spin-on deposition). Alternatively, the wet development may be combined with other dry processing operations, such as vapor deposition of the metal-containing EUV resist film (e.g., CVD). In embodiments where the EUV resist is developed using dry development, the dry development may be combined with other dry processing operations, such as dry deposition of the metal-containing EUV resist film (e.g., CVD). In alternative embodiments in which the EUV resist is developed using dry development, dry development may be combined with other wet processing operations, such as wet deposition of the metal-containing EUV resist film (e.g., spin-on deposition).

[0076] In some embodiments, the processing of a semiconductor substrate may be a combination of all dry processes, including film formation by vapor deposition, EUV lithography patterning, and dry development. In fact, each of operations 102-112 of process 100 may be a dry processing operation. Such processing operations can avoid the material and productivity costs associated with wet processing operations such as wet development. Dry processing offers greater adjustability and can add further limiting dimension (CD) control and scum removal. Wet processing generally involves moisture and / or oxygen, which more easily leads to scum formation. Wet development is limited by solubility and cluster size, whereas dry development is not limited by solubility and cluster size. Wet development tends to be prone to pattern collapse and delamination problems, which dry development avoids. Furthermore, using all dry processing operations can facilitate integration within interconnected vacuum processing chambers without exposure to and contamination by ambient air or trace contaminants contained therein. For example, while PEB heat treatment, which involves further crosslinking of the exposed region, may be performed in the same chamber as development, it will be understood that PEB heat treatment may be performed in a separate chamber.

[0077] The development process can be carried out by supplying developing chemicals in liquid or gas phase. In some embodiments, the dry development process can be carried out by using either a mild plasma (high pressure, low power) or thermal process while flowing a hydrogen halide-containing dry developing chemical such as HF, HCl, HBr, or HI. For example, dry development may be carried out by a thermal process using a dry developing chemical such as HCl or HBr. In some embodiments, the hydrogen halide-containing chemical can rapidly remove unexposed material, resulting in the pattern of the exposed film remaining, which can be transferred to the underlying layer by a plasma-based etching process, such as a conventional etching process.

[0078] In a thermal developing process, the substrate is exposed to a developing chemical (e.g., a Lewis acid) within a process chamber (e.g., an oven). In some embodiments, a vacuum line may be coupled to the process chamber for pressure control, and a developing chemical line may be coupled to the process chamber for delivering the developing chemical to the process chamber. The process chamber may include one or more heaters for temperature control, such as heaters coupled to a substrate support within the process chamber for substrate temperature control. In some embodiments, the interior of the chamber may be coated with a corrosion-resistant film, such as an organic polymer or an inorganic coating. One such coating is polytetrafluoroethylene (PTFE), e.g., Teflon 1M. Such materials can be used in the thermal processes of this disclosure without the risk of removal by plasma exposure.

[0079] In the thermal development process, the photopatterned metal-containing EUV resist is exposed to developing chemicals at a temperature optimized for etching selectivity between exposed and unexposed regions. Lower temperatures may increase the contrast of etching selectivity, while higher temperatures may decrease it. In some embodiments, the temperature may be about -60°C to about 120°C, about -20°C to about 60°C, or about -20°C to about 20°C, for example, about -10°C. The chamber pressure may be adjusted, and the chamber pressure may affect the etching selectivity between exposed and unexposed regions during development. In some embodiments, the chamber pressure may be relatively low and without dilution, and the chamber pressure may be about 0.1 mTorr to about 300 mTorr, about 0.2 mTorr to about 100 mTorr, or about 0.5 mTorr to about 50 mTorr. In some embodiments, the chamber pressure may be about 20 mTorr to about 800 mTorr, or about 20 mTorr to about 500 mTorr, for example, about 300 mTorr. In some embodiments, the chamber pressure may be relatively high, the flow rate may be large, and there may be no dilution, and the chamber pressure may be about 100 Torr to about 760 Torr, or about 200 Torr to about 760 Torr. The reactant flow rate may be adjusted, and the reactant flow may affect the etching selectivity between the exposed and unexposed areas during development. In some embodiments, the reactant flow rate may be about 50 sccm to about 2000 sccm, about 100 sccm to about 2000 sccm, or about 100 sccm to about 1000 sccm, for example, about 500 sccm. When the flow rate is high, the reactant flow rate may be about 1 L to about 10 L. The duration of exposure may be adjusted in the thermal development process. The duration of exposure may depend, among other factors, on how much resist to remove, the developing chemical, the amount of crosslinking in the resist, and the composition and properties of the resist. In some embodiments, the duration of exposure may be about 5 seconds to about 5 minutes, about 10 seconds to about 3 minutes, or about 10 seconds to about 1 minute.

[0080] The thermal development process may involve exposing a photopatterned metal-containing EUV resist to a specific halide-containing chemical in gaseous or liquid phase. In some embodiments, the developing chemical includes hydrogen halides, hydrogen and halogen gases, boron trichloride, organic halides, acyl halides, carbonyl halides, thionyl halides, or mixtures thereof. Hydrogen halides may include, but are not limited to, HF, HCl, HBr, and HI. For example, the hydrogen halide may be HCl or HBr. Hydrogen and halogen gases may include, but are not limited to, F2, Cl2, Br2, or I2 mixed with hydrogen gas (H2). Boron trichloride (BCl3) may be used in combination with any of the aforementioned hydrogen halides or hydrogen and halogen gases. Organic halides include C x H y F z , C x H y Cl z , C x H y Br z , and C x H y I z It may include, and x, y, and z are values ​​greater than or equal to 0. Acyl halides may include, but are not limited to, CH3COF, CH3COCl, CH3COBr, and CH3COI. Carbonyl halides may include, but are not limited to, COF2, COCl2, COBr2, and COI2. Thionyl halides may include, but are not limited to, SOF2, SOCl2, SoBr2, and SOI2. In some embodiments, the halide-containing chemical may be flowed with or without an inert gas / carrier gas such as He, Ne, Ar, Xe, and N2.

[0081] The thermal development process may be carried out without plasma. Applying a non-plasma thermal approach allows for simultaneous batch development of multiple wafers in a low-cost thermal vacuum chamber / oven, significantly improving productivity. However, in some embodiments, exposure to plasma may follow the thermal development process. Subsequent plasma exposure may occur for desorption, decamming, smoothing, or other processing operations.

[0082] In the plasma development process, the photopatterned metal-containing EUV resist is exposed to a developing chemical containing radicals / ions of one or more gases. The process chamber for processing the semiconductor substrate may be a plasma generation chamber or may be coupled to a plasma generation chamber located remotely from the process chamber. In some embodiments, dry development may be performed by remote plasma. The plasma generation chamber may be an inductively coupled plasma (ICP) reactor, a transcoupled plasma (TCP) reactor, or a capacitively coupled plasma (CCP) reactor, using equipment and techniques known in the art. An electromagnetic field acts on one or more gases to generate plasma within the plasma generation chamber. Ions and / or radicals from the remote plasma may interact with the photopatterned metal-containing EUV resist. In some embodiments, a vacuum line may be coupled to the process chamber for pressure control, and a developing chemical line may be coupled to the plasma generation chamber to deliver one or more gases to the plasma generation chamber. The process chamber may include one or more heaters for temperature control, such as heaters coupled to a substrate support within the process chamber for substrate temperature control. In some embodiments, the interior of the process chamber may be coated with a corrosion-resistant film, such as an organic polymer or inorganic coating. One such coating is polytetrafluoroethylene (PTFE), for example, Teflon 1M. Such materials can be used in the thermal processes of this disclosure without the risk of removal by plasma exposure.

[0083] In the plasma development process, the photopatterned metal-containing EUV resist is exposed to a remote plasma under conditions optimized for etching selectivity between exposed and unexposed regions. The conditions may be optimized to generate a mild plasma, which may be characterized by high pressure and low power. The chamber pressure may be adjusted, and may affect the etching selectivity between exposed and unexposed regions during development. In some embodiments, the chamber pressure may be about 5 mTorr or higher, or about 15 mTorr or higher. In some embodiments, the chamber pressure may be relatively high, with high flow rates and no dilution, and may be about 100 Torr to about 760 Torr, or about 200 Torr to about 760 Torr. The RF power level may be adjusted, and may affect etching selectivity, roughness, descamming, and other development characteristics. In some embodiments, the RF power may be about 1000 W or less, about 800 W or less, or about 500 W or less. The temperature may be adjusted, and the temperature may affect various aspects of development, such as etching selectivity. In some embodiments, the temperature may be about -60°C to about 300°C, about 0°C to about 300°C, or about 30°C to about 120°C. The gas flow rate may be adjusted, and the gas flow may affect the etching selectivity between exposed and unexposed areas during development. In some embodiments, the gas flow rate may be about 50 sccm to about 2000 sccm, about 100 sccm to about 2000 sccm, or about 200 sccm to about 1000 sccm, for example, about 500 sccm. The duration of exposure may be adjusted in the plasma development process. The duration of exposure may depend, among other factors, on how much resist is to be removed, the developing chemicals, the amount of crosslinking in the resist, and the composition and properties of the resist. In some embodiments, the duration of exposure may be about 1 second to about 50 minutes, about 3 seconds to about 20 minutes, or about 10 seconds to about 6 minutes.

[0084] A plasma development process may expose a photopatterned metal-containing EUV resist to radicals of a specific halide-containing gas. In some embodiments, the radicals are generated from a remote plasma source. For example, plasma development may expose a photopatterned metal-containing EUV resist to radicals of hydrogen and halide gases generated from a remote plasma source. In some embodiments, the halide-containing gas includes hydrogen halides, hydrogen and halogen gases, boron trichloride, organic halides, acyl halides, carbonyl halides, thionyl halides, or mixtures thereof. Hydrogen halides may include, but are not limited to, hydrogen fluoride (HF), hydrogen chloride (HCl), hydrogen bromide (HBr), and hydrogen iodide (HI). For example, the hydrogen halide may be HCl or HBr. Hydrogen and halogen gases may include, but are not limited to, fluorine gas (F2), chlorine gas (Cl2), bromine gas (Br2), or iodine gas (I2) mixed with hydrogen gas (H2). Organic halides are C x H y F z , C x H y Cl z , C x H y Br z , and C x H y I z It may include, and x, y, and z are values ​​greater than or equal to 0. Acyl halides may include, but are not limited to, CH3COF, CH3COCl, CH3COBr, and CH3COI. Carbonyl halides may include, but are not limited to, COF2, COCl2, COBr2, and COI2. Thionyl halides may include, but are not limited to, SOF2, SOCl2, SoBr2, and SOI2. In some embodiments, the halide-containing gas may be flowed with or without an inert gas / carrier gas such as He, Ne, Ar, Xe, and N2.

[0085] In addition to, or instead of, plasma activation, the activation of one or more gases in a dry development process can occur by photoactivation. In some embodiments, photoactivation can be achieved by exposure to ultraviolet (UV) radiation. For example, the process chamber may include a lamp, such as a UV lamp, configured to generate UV radiation. Exposure of one or more gases to UV radiation may generate radicals of one or more gases, which can be used in the dry development of a photopatterned metal-containing EUV resist. One or more gases may be exposed to UV radiation in a manner that does not expose the photopatterned resist to UV radiation. In other words, the photopatterned resist is not visible from the UV lamp. Therefore, the UV lamp may be located far from the process chamber or positioned to avoid exposure of the photopatterned resist to UV radiation.

[0086] It will be understood that the aforementioned thermal development, plasma development, and photoactivation development methods may be combined. Such development methods may be applied simultaneously or sequentially. The development method may involve applying a dry development chemical in liquid or gas phase, and the dry development chemical is of formula R x Z y The compound can contain R=B, Al, Si, C, S, SO, and x>0, and Z=Cl, H, Br, F, CH4, and y>0. Development can result in a positive or negative type, and R x Z y The chemical species selectively removes either the unexposed or exposed material, leaving the corresponding exposed or unexposed portion as a mask.

[0087] As described above, etching selectivity during dry development can be adjusted by controlling process conditions such as temperature, pressure, gas flow, gas composition, and plasma power, among other adjustable process conditions. By adjusting etching selectivity in a single or multiple steps, desired patterned properties can be achieved. In some embodiments, etching selectivity during dry development is adjusted over one or more steps that affect the EUV resist profile. More specifically, the amount of taper or re-entry angle of the EUV resist profile can be controlled by applying developing chemicals with different etching selectivity over one or more steps. Descamming, photoresist rework, curing, smoothing, and cleaning operations can also be adjusted according to the adjustable etching selectivity.

[0088] Figures 2A to 2C show schematic cross-sectional views of various processing stages of dry development according to several embodiments. The examples shown in Figures 2A to 2C illustrate negative-type dry development. As shown in Figure 2A, the wafer 200 includes a substrate 202 and a substrate layer 204 to be etched. In some embodiments, the substrate layer 204 includes an ashingable hard mask such as spin-on carbon (SoC), or other materials such as silicon, silicon oxide, silicon nitride, or silicon carbide. In some embodiments, the substrate layer 204 may be a layer stack disposed on the substrate 202. The wafer 200 further includes a photopatterned metal-containing EUV resist film 206. For example, the photopatterned metal-containing EUV resist film 206 may be an organometallic layer disposed on the substrate layer 204 to be etched. The photopatterned metal-containing EUV resist film 206 may have a thickness of about 5 nm to about 50 nm, or about 10 nm to about 30 nm. The photopatterned metal-containing EUV resist film 206 may be provided into the process chamber after photopatterning with an EUV scanner and / or after PEB processing, as described above. The photopatterned metal-containing EUV resist film 206 includes a non-EUV exposure region 206a and an EUV exposure region 206b. As shown in Figure 2B, the non-EUV exposure region 206a of the photopatterned metal-containing EUV resist film 206 may be removed in a dry development process by exposure to a flow of dry development chemicals without generating plasma. The dry development chemicals may include halide-containing chemicals such as hydrogen halides or hydrogen and halogen gases. Removal of the non-EUV exposure region 206a forms a resist mask 208 after development. Subsequently, the substrate layer 204 to be etched may be etched using the resist mask 208 to obtain the structure shown in Figure 2C.

[0089] Figure 3 illustrates exemplary dry development mechanisms of chemical reactions between HBr and exposed and unexposed regions of an EUV photoresist according to several embodiments. While Figure 3 illustrates expected dry development mechanisms, it will be understood that this disclosure is not limited to any particular mechanism, function, theory, or utility. The organometallic oxide film may have a tetrahedral coordination structure. The exposed region has a higher level of Sn-O-Sn crosslinking, resulting in a higher density and lower / slower reactivity with HBr or HCl. The unexposed region has a lower density due to the presence of bulky alkyl substituents that hinder the approach and condensation of the Sn-OH moiety. In the unexposed region, hydrogen halides exhibit a more tetrahedral coordination characteristic of organotin hydroxides. Basic This makes it easier to protonate the accessible oxygen lone pairs. The volatile byproduct RSnX3 (X=Cl or Br) is rapidly formed and removed from the unexposed region. In Figure 3, HBr selectively protonates the oxygen lone pairs to form the volatile byproduct R-Sn-Br. Water is also a byproduct. Removal of water can increase the reaction rate. When the alkyl group is isopropyl, at a typical EUV patterning dose, at least two out of every three isopropyl substituents are removed, resulting in the formation of a denser SnO2-like material with lower reactivity with hydrogen halides, due to the condensation of the exposed region after the PEB step, taking on a tin structure closer to hexagonal coordination where oxygen atoms are more difficult to access, resulting in much slower reactivity with hydrogen halides. In Figure 3, the exposed region shows a significant decrease in dry etching rate due to the loss of isopropyl substituents, allowing condensation into a material where more / most oxygen atoms are bonded to three (not two) tin atoms, and the reaction rate with HBr or HCl is significantly reduced.

[0090] In some cases, residue or scum may remain after development. This residue may be due to slower etching components in less homogeneous EUV resist formulations, including those applied using spin-coating techniques. Such scum may contain high concentrations of metal, which can cause problems during subsequent pattern transfer.

[0091] In addition, or instead, after development, roughness may form on the sidewalls of etched features in the developed pattern. This may be partly due to the probabilistic or suboptimal Gaussian distribution of light, resulting in partial or complete exposure of the material in areas where the resist should remain unexposed.

[0092] In some embodiments, dry development may be accompanied by a decamming / smoothing process. In some embodiments, the decamming and smoothing processes may be inert gas plasma desorption processes. For example, the inert gas plasma desorption process may be a helium plasma desorption process. The inert gas plasma desorption process may be performed after dry development or repeated in conjunction with dry development.

[0093] Figure 4A shows schematic cross-sectional views of dry development without the application of inert gas plasma according to several embodiments. The photopatterned metal-containing EUV resist film includes exposed and unexposed regions. As shown in Figure 4A, metal oxides (e.g., SnO) x ) particles or clusters may occupy unexposed areas. As dry development progresses, metal oxide clusters become more concentrated. Metal oxide clusters are generally difficult to remove. Development may be selective for the removal of organic materials. After removing unexposed areas, metal oxide clusters may remain on the substrate surface as scum. Metal oxide clusters remaining on the sidewalls of exposed areas may lead to roughness.

[0094] Figure 4B shows schematic cross-sectional views of dry-developing iterative inert gas plasma for descamming according to several embodiments. The first step involves dry development to remove a substantial portion of the unexposed areas of the photopatterned metal-containing EUV resist film. The dry-developing chemical may include, for example, HBr. A substantial portion may represent at least more than 70 vol% of the unexposed areas, more than 80 vol% of the unexposed areas, or more than 90 vol% of the unexposed areas. Clusters of metal oxide concentrate on the surface of the remaining unexposed areas of the EUV resist film. The second step involves applying an inert gas plasma, such as helium plasma, at low power and high ion energy for a short period of time. The helium plasma removes the clusters of metal oxide. In addition, the helium plasma removes clusters from the sidewalls and smooths the sidewalls. The helium plasma treatment may also play a role in curing or hardening the patterned EUV resist film to form denser metal oxides, such as hard masks. After helium plasma treatment, a less selective dry etching step can be used to remove any residue remaining in the unexposed areas of the EUV resist film.

[0095] In some embodiments, dry development may be repeated in conjunction with helium plasma treatment over one or more cycles until the unexposed areas of the EUV resist film are removed. To improve the results, helium plasma decamming / smoothing may be repeated in conjunction with dry development as described above. In this way, for example, most of the organic components in the unexposed areas of the pattern are removed by dry development, and then a short helium plasma operation removes some of the metal concentrated on the surface, allowing access to the remaining underlying organic material, which can then be removed in subsequent dry development operations / cycles. Another helium plasma cycle may be used to remove all remaining metal, leaving a clean and smooth feature surface. The cycles can continue until all or substantially all scum and roughness residue is removed, leaving a clean and smooth feature surface.

[0096] The process conditions for the descamming and smoothing operations may be controlled during or after development. In some embodiments, the reactant flow may be about 50 sccm to about 1000 sccm, about 100 sccm to about 500 sccm, for example, about 500 sccm of He. In some embodiments, the temperature may be about -60°C to about 120°C, about -20°C to about 60°C, or about 20°C to about 40°C, for example, about 20°C. In some embodiments, the chamber pressure may be about 1 mTorr to about 300 mTorr, about 5 mTorr to about 100 mTorr, about 5 mTorr to about 20 mTorr, for example, about 10 mTorr. Plasma power may be relatively low when the ion energy is high. In some embodiments, the plasma power may be about 50W to about 1000W, about 100W to about 500W, or about 100W to about 300W, for example, about 300W. In some embodiments, the wafer bias is about 10V to about 500V, about 50V to about 300V, for example, about 200V. The plasma may be generated using a high RF frequency. In some embodiments, the RF frequency is 13.56MHz. To avoid excessive exposure to UV radiation during plasma exposure, the duration of exposure to the inert gas plasma may be relatively short. In some embodiments, the duration of exposure is about 0.5 seconds to about 5 seconds, about 1 second to about 3 seconds, for example, about 2 seconds.

[0097] Inert gas plasma treatment for decamming and cleaning of unexposed resist residue may have the secondary benefit of curing and hardening the exposed resist, thereby enhancing its hard mask function in subsequent etching operations of the underlying substrate. This resist hardening is achieved by exposing the EUV-exposed resist to UV radiation generated by the inert gas plasma, which can be continued with the bias turned off after decamming / smoothing is complete. If decamming / smoothing is not required or performed, inert gas plasma curing may be performed instead.

[0098] In some embodiments, inert gas plasma desorption decamming and smoothing may be used in conjunction with a wet development process. Wet development has been shown to have very high selectivity and exhibit clear on / off behavior, and as a result, the wet development process cannot remove areas exposed by "stray" EUV photons. After the wet development process, residual material remains, resulting in scum and increased roughness of the line edges and width. Interestingly, due to the tunability of the dry development process, where etching rate and selectivity can be adjusted based on multiple knobs (e.g., time, temperature, pressure, gas / flow), metal-containing resist lines can be decammed and smoothed by further applying inert gas plasma and / or dry development to remove these partially exposed residues.

[0099] Figure 5 shows a graph comparing the etching rates of exposed and unexposed areas of an EUV photoresist using helium plasma during dry development. The EUV photoresist may be an organotin oxide EUV photoresist. The unexposed areas are etched faster than the exposed areas. However, as dry development using HBr progresses, the etching rate decreases. While not limited by any theory, the presence of tin oxide particles / clusters is thought to slow the etching rate. By applying helium desorption, more of the unexposed areas of the EUV photoresist can be etched.

[0100] Figures 6A and 6B show SEM images comparing wet development and dry development in terms of line breakdown. In Figure 6A, a photopatterned metal-containing EUV resist is exposed to a wet development chemical such as an organic solvent. After the liquid drying step, some pattern line breakdown is observed. This may be partly due to the action of surface tension due to capillary forces. In Figure 6B, a photopatterned metal-containing EUV resist is exposed to a dry development chemical such as hydrogen halide gas. Dry development by gas-phase reaction without a liquid drying step prevents pattern line breakdown or delamination.

[0101] Figures 7A and 7B show SEM images comparing wet development and dry development in terms of roughness and critical dimension (CD) control. In Figures 7A and 7B, an organotin oxide film is deposited on an ashingable hard mask. The organotin oxide film was EUV exposed at various doses and depths of focus. In Figure 7A, the organotin oxide film was wet-developed, and in Figure 7B, it was dry-developed. The organotin oxide resist mask had a square profile after wet development, while the organotin oxide resist mask had a tapered profile after dry development. Line bridging was observed after pattern transfer in wet development, but not in dry development. Due to surface tension during solvent drying after wet development, line breakdown and wiggling were observed at smaller line widths or lower doses. After dry development, line breakdown or wiggling did not occur at smaller line widths or lower doses. Dry development offers a larger process window, encompassing a wider dose and focal range.

[0102] Figure 8 shows SEM images comparing wet and dry development regarding scum after hard mask opening. As shown in Figure 8, more scum is observed after wet development compared to after dry development. Although not limited by any theory, dry development prevents scum formation by using gaseous chemicals that do not contain oxygen or moisture oxidation sources that prevent metal oxide crosslinking of unexposed EUV resists. The scum is similar to that of exposed EUV resists with metal oxide crosslinking. In Figure 8, decamming and smoothing can be performed after either wet or dry development.

[0103] Figures 9A and 9B show graphs illustrating the effect of the second post-exposure bake on dry development selectivity at various pressures and temperatures. As shown in Figure 9A, the second post-exposure bake shows improved etching selectivity. As shown in Figure 9B, etching selectivity improves with lower temperatures during dry development. In addition, etching selectivity improves with lower pressure during dry development.

[0104] Figure 10 shows an SEM image illustrating the effect of pressure on the EUV resist profile. In the case of dry development, pressure changes affect the EUV resist profile. Generally, higher pressure allows for higher etching rates. However, lower pressures have been shown to improve the EUV resist profile. In Figure 10, lower pressure resulted in a straighter EUV resist profile.

[0105] Figures 11A and 11B show SEM images of EUV resists at different line / space pitches and thicknesses. EUV resist masks with 32nm and 26nm pitches were developed. The film thickness before development was 15nm to 40nm. For the 32nm pitch, the thickness of the EUV resist mask after development was in the range of 7.8nm to 22.5nm. No wiggling was observed. For the 26nm pitch, the thickness of the EUV resist mask after development was in the range of 7.9nm to 22.2nm. Some wiggling was observed at film thicknesses of 30nm or more, due to undercuts at the bottom of the resist.

[0106] Device The apparatus of this disclosure is configured to develop EUV resist. The apparatus may be configured to perform other processing operations, such as deposition, bevel and backside cleaning, post-coating bake, EUV scanning, post-exposure bake, photoresist rework, descam, smoothing, curing, and other operations. In some embodiments, the apparatus is configured to perform all dry operations. In some embodiments, the apparatus is configured to perform all wet operations. In some embodiments, the apparatus is configured to perform a combination of wet and dry operations. The apparatus may include a single wafer chamber or may include multiple stations within the same process chamber. If there are multiple stations within the same process chamber, various processing operations as described in this disclosure may be performed at different stations within the same process chamber. For example, PEB heat treatment may be performed at one station and development at another station.

[0107] An apparatus configured for developing EUV resists includes a process chamber having a substrate support. The apparatus may include a vacuum line coupled to the process chamber for pressure control and a developing chemical line coupled to the process chamber for delivering developing chemicals. In some embodiments, the developing chemicals include a halide-containing gas or a radical of a halide-containing gas. In some embodiments, the process chamber is a plasma generation chamber or coupled to a plasma generation chamber that functions as a remote plasma source. The plasma generation chamber may be an ICP, TCP, or CCP reactor. The apparatus may include one or more heaters for temperature control. Such heaters may be located within the process chamber and / or within the substrate support.

[0108] In some embodiments, the interior of the process chamber is coated with a corrosion-resistant film, such as a polymer or inorganic coating. In one example, the interior of the process chamber is coated with anodized alumina. In another example, the interior of the process chamber is coated with yttrium oxide (Y2O3).

[0109] In some embodiments, the process chamber is made of an inexpensive material such as plastic. The process chamber does not necessarily need to be made of metal or ceramic. Plastic materials may be sufficient to withstand halide-containing chemicals during development. Vacuum lines and / or developing chemical lines may be coupled to the plastic chamber.

[0110] In some embodiments, a substrate support may be used to process the substrate using a temperature distribution having radial and azimuthal components. The substrate support may include a plurality of independently controllable temperature control zones configured to be close to the substrate position above the temperature control zone. This allows one or more heaters within the substrate support to control the temperature more precisely and locally. The temperature control zones may consist of a predetermined pattern, such as a rectangular grid, a hexagonal grid, or other suitable pattern for generating a desired temperature profile. In some embodiments, the temperature control zones may be spatially configured in an electrostatic chuck to correct azimuthal non-uniformity or local CD non-uniformity.

[0111] In some embodiments, the apparatus may further include a showerhead for delivering one or more gases into the process chamber. In some embodiments, the showerhead may supply multiple separate gases to the reaction area while keeping the gases largely separated within the showerhead. The showerhead may include multiple plenum volumes. This allows for the separation of precursor gases, carrier gases, developer gases, and cleaning gases among other chemicals.

[0112] Removing water and moisture from the process chamber can accelerate the reaction between the photopatterned metal-containing EUV resist and the developing chemicals. In some embodiments, a cold trap may be coupled to the process chamber to remove by-product water vapor. The cold trap can condense the by-product water vapor into a liquid or solid form.

[0113] In some embodiments, the apparatus may further include a UV source, such as a UV lamp, and / or an IR source, such as an IR lamp, for resist curing and dehalogenation. The UV source and / or IR source may provide exposure to radiation for curing the EUV resist. In addition or alternatively, the UV source may assist in the photoactivation of the developing chemicals. In addition or alternatively, the UV source may assist in halogen removal. Halogen residues may form on the semiconductor substrate or chamber surface, which can be removed by UV exposure.

[0114] Figure 12 shows a schematic diagram of an embodiment of a process station 1200 having a process chamber body 1202 for maintaining a low-pressure environment suitable for the described dry developing, cleaning, rework, descamming, and smoothing embodiments. Multiple process stations 1200 may be included in a common low-pressure process tool environment. For example, Figure 13 shows an embodiment of a multi-station process tool 1300, such as the VECTOR® processing tool available from Lam Research Corporation (Fremont, CA). In some embodiments, one or more hardware parameters of the process station 1200, including parameters discussed in detail below, may be programmatically adjusted by one or more computer controllers 1250.

[0115] The process station may be configured as a module within a cluster tool. Figure 15 shows a semiconductor process cluster tool architecture having vacuum integrated deposition and patterning modules suitable for realizing the embodiments described herein. Such a cluster process tool architecture may include a resist deposition module, a resist exposure (EUV scanner) module, a resist development module, and an etching module, as described above and further described later with reference to Figures 14 and 15.

[0116] In some embodiments, specific processing functions, such as dry development and etching, may be performed sequentially within the same module. Embodiments of the present disclosure relate to a method and apparatus for placing a wafer containing a photopatterned EUV resist thin film layer placed on a layer stack or layer to be etched, following photopatterning in an EUV scanner, into a dry development / etching chamber, dry developing the photopatterned EUV resist thin film layer, and then etching the underlying film using the patterned EUV resist as a mask, as described herein.

[0117] Returning to Figure 12, the process station 1200 is in fluid communication with a reactant delivery system 1201a for delivering process gas to a distribution showerhead 1206. The reactant delivery system 1201a optionally includes a mixing vessel 1204 for mixing and / or adjusting the process gas for delivery to the showerhead 1206. One or more mixing vessel inlet valves 1220 may control the introduction of process gas into the mixing vessel 1204. If plasma exposure is used, plasma may be further supplied to the showerhead 1206 or generated in the process station 1200. As described above, in at least some embodiments, non-plasma thermal exposure is preferred.

[0118] Figure 12 includes an optional vaporization point 1203 for vaporizing the liquid reactants supplied to the mixing vessel 1204. In some embodiments, a liquid flow controller (LFC) may be provided upstream of the vaporization point 1203 to control the mass flow rate of the liquid for vaporization and delivery to the process station 1200. For example, the LFC may include a thermal mass flow meter (MFM) located downstream of the LFC. The plunger valve of the LFC may then be adjusted in response to a feedback control signal supplied by a proportional-integral-derivative (PID) controller that communicates with the MFM.

[0119] The showerhead 1206 distributes the process gas toward the substrate 1212. In the embodiment shown in Figure 12, the substrate 1212 is located below the showerhead 1206 and rests on the pedestal 1208. The showerhead 1206 may have any preferred shape and may have any preferred number and configuration of ports for distributing the process gas toward the substrate 1212.

[0120] In some embodiments, the pedestal 1208 may be raised or lowered to expose the substrate 1212 to the volume between the substrate 1212 and the showerhead 1206. In some embodiments, it will be understood that the height of the pedestal may be programmatically adjusted by a suitable computer controller 1250. In some embodiments, the showerhead 1206 may have multiple plenum volumes with multiple temperature controls.

[0121] In some embodiments, the pedestal 1208 may be temperature-controlled via a heater 1210. In some embodiments, the pedestal 1208 may be heated to a temperature above 0°C and up to 300°C or above, for example 50°C to 120°C, for example about 65°C to 80°C, during non-plasma thermal exposure of the photopatterned resist to a hydrogen halide dry developing chemical such as HBr or HCl, as described in the disclosed embodiments. In some embodiments, the heater 1210 of the pedestal 1208 may include a plurality of independently controllable temperature control zones.

[0122] Furthermore, in some embodiments, pressure control for the process station 1200 may be provided by a butterfly valve 1218. As shown in the embodiment of Figure 12, the butterfly valve 1218 throttles the vacuum supplied by a downstream vacuum pump (not shown). However, in some embodiments, pressure control for the process station 1200 may also be regulated by changing the flow rate of one or more gases introduced into the process station 1200.

[0123] In some embodiments, the position of the shower head 1206 relative to the pedestal 1208 may be adjusted to change the volume between the substrate 1212 and the shower head 1206. Furthermore, it will be understood that the vertical position of the pedestal 1208 and / or the shower head 1206 may be changed by any suitable mechanism within the scope of this disclosure. In some embodiments, the pedestal 1208 may include a pivot axis for rotating the orientation of the substrate 1212. In some embodiments, it will be understood that one or more of these exemplary adjustments may be programmed by one or more suitable computer controllers 1250.

[0124] When plasma is used, for example in embodiments of mild plasma-based dry development and / or etching operations performed in the same chamber, the showerhead 1206 and pedestal 1208 telecommunicate with a radio frequency (RF) power supply 1214 and a matching network 1216 to power the plasma. In some embodiments, the plasma energy may be controlled by controlling one or more of the process station pressure, gas concentration, RF source power, RF source frequency, and plasma power pulse timing. For example, the RF power supply 1214 and the matching network 1216 may be operated at any suitable power to form a plasma having radical species of a desired composition. An example of a suitable power is up to about 500 W.

[0125] In some embodiments, instructions for the controller 1250 may be provided via input / output control (IOC) sequence instructions. For example, instructions for setting conditions for process phases may be included in the corresponding recipe phase of the process recipe. In some cases, the recipe phases may be configured in order so that all instructions for a process phase are executed simultaneously with that process phase. In some embodiments, instructions for setting one or more reactor parameters may be included in the recipe phase. For example, the recipe phase may include instructions for setting the flow rate of a dry developing chemical reaction gas such as HBr or HCl, and a time delay instruction for the recipe phase. In some embodiments, the controller 1250 may include any of the features described below with respect to the system controller 1350 in Figure 13.

[0126] As described above, one or more process stations may be included in the multi-station processing tool. Figure 13 shows a schematic diagram of an embodiment of a multi-station processing tool 1300 comprising an inbound load lock 1302 and an outbound load lock 1304, either or both of which may include a remote plasma source. A robot 1306 at atmospheric pressure is configured to move a wafer from a cassette loaded through a pod 1308 into the inbound load lock 1302 via an atmospheric pressure port 1310. The wafer is then placed by the robot 1306 on a pedestal 1312 within the inbound load lock 1302, the atmospheric pressure port 1310 is closed, and the load lock is pumped down. If the inbound load lock 1302 includes a remote plasma source, the wafer may be exposed to remote plasma processing to process the silicon nitride surface within the load lock before being introduced into the processing chamber 1314. Furthermore, the wafer may also be heated within the inbound load lock 1302, for example, to remove moisture and adsorbed gases. Next, the chamber transfer port 1316 to the processing chamber 1314 is opened, and for processing, another robot (not shown) places the wafer into the reactor and onto the pedestal of the first station shown inside the reactor. Although the embodiment shown in Figure 13 includes a load lock, it will be understood that in some embodiments, direct entry of the wafer into the process station may be provided.

[0127] The illustrated processing chamber 1314 includes four process stations numbered 1 to 4 in the embodiment shown in Figure 13. Each station has a heated pedestal (indicated as 1318 for station 1) and a gas line inlet. In some embodiments, it will be understood that each process station may have different or multiple purposes. For example, in some embodiments, a process station may be switchable between a dry developing mode and an etching process mode. In addition or instead, in some embodiments, the processing chamber 1314 may include one or more matched pairs of dry developing stations and etching process stations. Although the illustrated processing chamber 1314 includes four stations, it will be understood that the processing chamber according to this disclosure may have any preferred number of stations. For example, in some embodiments, the processing chamber may have five or more stations, while in other embodiments, the processing chamber may have three or fewer stations.

[0128] Figure 13 shows an embodiment of a wafer handling system 1390 for transferring wafers within a processing chamber 1314. In some embodiments, the wafer processing system 1390 may transfer wafers between various process stations and / or between process stations and load locks. It will be understood that any suitable wafer handling system may be employed. Non-limiting examples include wafer carousels and wafer handling robots. Figure 13 also shows an embodiment of a system controller 1350 used to control process conditions and hardware states of a process tool 1300. The system controller 1350 may include one or more memory devices 1356, one or more mass storage devices 1354, and one or more processors 1352. The processors 1352 may include a CPU or computer, analog and / or digital input / output connectors, a stepper motor controller board, and the like.

[0129] In some embodiments, the system controller 1350 controls all aspects of the operation of the process tool 1300. The system controller 1350 runs system control software 1358, which is stored in a mass storage device 1354, loaded into a memory device 1356, and executed by a processor 1352. Alternatively, the control logic may be hardcoded within the controller 1350. For these purposes, application-specific integrated circuits, programmable logic devices (e.g., field-programmable gate arrays, or FPGAs) may be used. Wherever “software” or “code” is used in the following description, functionally equivalent hardcoded logic may be used instead. The system control software 1358 may include instructions for controlling timing, gas mixing, gas flow rate, chamber and / or station pressure, chamber and / or station temperature, wafer temperature, target power level, RF power level, substrate pedestal, chuck and / or susceptor position, and other parameters of a particular process performed by the process tool 1300. The system control software 1358 may be configured in any preferred manner. For example, various subroutines or control objects for various process tool components may be written to control the work of process tool components used to carry out various process tool processes. The system control software 1358 may be coded in any suitable computer-readable programming language.

[0130] In some embodiments, the system control software 1358 may include input / output control (IOC) sequence instructions for controlling the various parameters described above. In some embodiments, other computer software and / or programs stored in the mass storage device 1354 and / or memory device 1356 associated with the system controller 1350 may be used. Examples of programs or parts of programs for this purpose include substrate positioning programs, process gas control programs, pressure control programs, heater control programs, and plasma control programs.

[0131] The substrate alignment program may include program code for process tool components used to load the substrate onto the pedestal 1318 and to control the spacing between the substrate and other components of the process tool 1300.

[0132] The process gas control program may include code for controlling the composition (e.g., HBr or HCl gas as described herein) and flow rate of a halide-containing gas, and optionally code for introducing gas into one or more process stations before deposition in order to stabilize the pressure within the process stations. The pressure control program may include code for controlling the pressure within the process stations by, for example, adjusting the throttle valve of the process station's exhaust system, the gas flow into the process stations, etc.

[0133] The heater control program may include code for controlling the current to the heating unit used to heat the substrate. Alternatively, the heater control program may control the supply of a heat transfer gas (e.g., helium) to the substrate.

[0134] The plasma control program may include code for setting RF power levels applied to process electrodes in one or more process stations according to embodiments of this specification.

[0135] The pressure control program may include code for maintaining the pressure in the reaction chamber according to the embodiments specified herein.

[0136] In some embodiments, there may be a user interface associated with the system controller 1350. The user interface may include a display screen, a graphical software display of the device and / or process conditions, and user input devices, such as a pointing device, keyboard, touchscreen, and microphone.

[0137] In some embodiments, the parameters adjusted by the system controller 1350 may relate to process conditions. Non-limiting examples include the composition and flow rate of the process gas, temperature, pressure, and plasma conditions (e.g., RF bias power level). These parameters may be provided to the user in the form of a recipe that can be entered using a user interface.

[0138] Signals for monitoring the process may be provided from various process tool sensors via the analog and / or digital input connections of the system controller 1350. Signals for controlling the process may be output to the analog and digital output connections of the process tool 1300. Non-limiting examples of process tool sensors that can be monitored include mass flow controllers, pressure sensors (e.g., manometers), thermocouples, etc. Appropriately programmed feedback and control algorithms may be used in conjunction with data from these sensors to maintain process conditions.

[0139] The system controller 1350 may provide program instructions for carrying out the deposition process described above. The program instructions may control various process parameters such as DC power level, RF bias power level, pressure, and temperature. The instructions may control parameters for operating the developing and / or etching process according to the various embodiments described herein.

[0140] The system controller 1350 typically includes one or more memory devices and one or more processors configured to execute instructions for the apparatus to carry out the method according to the disclosed embodiments. A machine-readable medium containing instructions for controlling the process operations according to the disclosed embodiments may be coupled to the system controller 1350.

[0141] In some embodiments, the system controller 1350 is part of a system, which may be part of the examples described above. Such a system may include semiconductor processing equipment, comprising one or more processing tools, one or more chambers, one or more processing platforms, and / or specific processing components (such as a wafer stand, gas flow system, etc.). These systems may be incorporated into electronics for controlling pre-processing, in-processing, and post-processing operations on semiconductor wafers or substrates. The electronics may be referred to as “controllers” that can control various components or sub-components of the system (one or more). Depending on the processing conditions and / or the type of system, the system controller 1350 may be programmed to control any of the processes disclosed herein, including, but are not limited to, the delivery of processing gases, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, radio frequency (RF) generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, position and work settings, loading and unloading of wafers to and from tools and other transfer tools connected to or interfaced with a particular system, and / or load locks.

[0142] Broadly speaking, the system controller 1350 may be defined as an electronic device having various integrated circuits, logic, memory, and / or software, which receives and issues instructions, controls operations, enables cleaning operations, enables endpoint measurements, etc. The integrated circuit may include a chip in the form of firmware that stores program instructions, a chip defined as a digital signal processor (DSP), an application-specific integrated circuit (ASIC), and / or one or more microprocessors, or a microcontroller that executes program instructions (e.g., software). Program instructions are instructions communicated to the system controller 1350 in the form of various individual settings (or program files) that may define work parameters for performing a particular process on or for a semiconductor wafer, or for the system. In some embodiments, the work parameters may be part of a recipe defined by a process engineer to implement one or more processing steps when fabricating one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or wafer dies.

[0143] In some embodiments, the system controller 1350 may be part of or coupled to a computer that is integrated into or coupled to the system, networked to or connected to the system. For example, the system controller 1350 may be in the “cloud” or all or part of a fab host computer system, thereby enabling remote access to wafer processing. The computer may enable remote access to the system to monitor the current progress of manufacturing operations, investigate the history of past manufacturing operations, investigate trends or performance indicators from multiple manufacturing operations, modify parameters of the current operation, set processing steps following the current operation, or start a new process. In some examples, a remote computer (e.g., a server) may provide process recipes to the system via a network that may include a local network or the Internet. The remote computer may include a user interface that enables input or programming of parameters and / or settings, which are then communicated from the remote computer to the system. In some examples, the system controller 1350 receives instructions in data format that specify parameters for each processing step performed during one or more operations. It should be understood that the parameters may be specific to the type of process being performed and the type of tool that the system controller 1350 is configured to interface with or control. Therefore, as described above, the system controller 1350 may be distributed, for example, by including one or more separate controllers that are networked with one another and aimed at a common purpose, such as the processes and controls described herein. An example of a distributed controller for such a purpose might be one or more integrated circuits on a chamber in communication with one or more integrated circuits located remotely (e.g., at the platform level or as part of a remote computer), which together control the process in the chamber.

[0144] Exemplary systems may include, but are not limited to, plasma etching chambers or modules, deposition chambers or modules, spin rinse chambers or modules, metal plating chambers or modules, cleaning chambers or modules, bevel edge etching chambers or modules, physical vapor deposition (PVD) chambers or modules, chemical vapor deposition (CVD) chambers or modules, ALD chambers or modules, atomic layer etching (ALE) chambers or modules, ion implantation chambers or modules, track chambers or modules, EUV lithography chambers (scanners) or modules, developing chambers or modules, and any other semiconductor processing systems that are related to or may be used in the fabrication and / or manufacture of semiconductor wafers.

[0145] As described above, depending on the process steps performed by the tool, the system controller 1350 may communicate with one or more of the following: other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, neighboring tools, tools located throughout the factory, a main computer, another controller, or tools used for material handling to load and unload wafer containers between tool locations and / or load ports within the semiconductor manufacturing plant.

[0146] In certain embodiments, inductively coupled plasma (ICP) reactors that may be suitable for etching operations are described here, which are suitable for realizing some embodiments. Although this specification describes ICP reactors, it should be understood that capacitively coupled plasma reactors may also be used in some embodiments.

[0147] Figure 14 schematically shows a cross-sectional view of an inductively coupled plasma apparatus 1400 suitable for implementing a particular embodiment or aspect of an embodiment, such as dry development and / or etching, an example of which is the Kiyo® reactor manufactured by Lam Research Corp. (Fremont, CA). In other embodiments, other tools or tool types having the capability to perform the dry development and / or etching processes described herein may be used to implement the invention.

[0148] The inductively coupled plasma apparatus 1400 includes an overall process chamber 1424 structurally defined by chamber walls 1401 and windows 1411. The chamber walls 1401 may be made of stainless steel, aluminum, or plastic. The windows 1411 may be made of quartz or other dielectric material. An optional internal plasma grid 1450 divides the overall process chamber into an upper sub-chamber 1402 and a lower sub-chamber 1403. In most embodiments, the chamber space created by the sub-chambers 1402 and 1403 may be utilized by removing the plasma grid 1450. A chuck 1417 is located inside the lower sub-chamber 1403, near the bottom inner surface. The chuck 1417 is configured to house and hold a semiconductor wafer 1419, on which etching and deposition processes are performed. The chuck 1417 may be an electrostatic chuck for supporting the wafer 1419 when it is present. In some embodiments, an edge ring (not shown) surrounds the chuck 1417 and has a top surface that is substantially coplanar with the top surface of the wafer 1419 when the wafer 1419 is on the chuck 1417. The chuck 1417 also includes electrostatic electrodes for chucking and unchucking the wafer 1419. For this purpose, a filter and a DC clamp power supply (not shown) may be provided. Other control systems for lifting the wafer 1419 from the chuck 1417 may also be provided. The chuck 1417 can be charged using an RF power supply 1423. The RF power supply 1423 is connected to a matching circuit 1421 via a connector 1427. The matching circuit 1421 is connected to the chuck 1417 via a connector 1425. In this way, the RF power supply 1423 is connected to the chuck 1417. In various embodiments, the bias power of the electrostatic chuck may be set to about 50V, or to different bias powers depending on the process carried out according to the disclosed embodiments. For example, the bias power may be approximately 20Vb to 100V, or approximately 30V to 150V.

[0149] The elements for plasma generation include a coil 1433 located above the window 1411. In some embodiments, the coil is not used in the disclosed embodiments. The coil 1433 is manufactured from a conductive material and includes at least one complete turn. The example of coil 1433 shown in Figure 14 includes three turns. The cross-section of the coil 1433 is indicated by symbols, where coils with "X" rotate and extend into the page, and coils with "·" rotate and extend outside the page. The elements for plasma generation also include an RF power supply 541 configured to supply RF power to the coil 1433. Generally, the RF power supply 1441 is connected to a matching circuit 1439 via a connector 1445. The matching circuit 1439 is connected to the coil 1433 via a connector 1443. In this way, the RF power supply 1441 is connected to the coil 1433. An optional Faraday shield 1449a is located between the coil 1433 and the window 1411. The Faraday shield 1449a may be maintained at a gap relative to the coil 1433. In some embodiments, the Faraday shield 1449a is positioned directly above the window 1411. In some embodiments, the Faraday shield 1449b is located between the window 1411 and the chuck 1417. In some embodiments, the Faraday shield 1449b is not maintained at a gap relative to the coil 1433. For example, the Faraday shield 1449b may be directly below the window 1411 without any gap. The coil 1433, the Faraday shield 1449a, and the window 1411 are each configured substantially parallel to one another. The Faraday shield 1449a can prevent metal or other chemical species from accumulating on the window 1411 of the process chamber 1424.

[0150] Process gas may flow into the process chamber through one or more main gas inlets 1460 located in the upper sub-chamber 1402 and / or through one or more side gas inlets 1470. Similarly, process gas may be supplied to the capacitively coupled plasma processing chamber using similar gas inlets, although not explicitly shown. A vacuum pump, e.g., a single or two-stage mechanical dry pump and / or turbomolecular pump 1440, may be used to draw process gas from the process chamber 1424 and maintain the internal pressure of the process chamber 1424. For example, a vacuum pump may be used to evacuate the lower sub-chamber 1403 during ALD purging operations. To selectively control the application of the vacuum environment provided by the vacuum pump, the vacuum pump may be fluidically connected to the process chamber 1424 using a valve-controlled conduit. This may be done using a closed-loop controlled flow limiting device, such as a throttle valve (not shown) or a pendulum valve (not shown), during plasma processing operations. Similarly, a valve-controlled fluid connection to the vacuum pump and the capacitively coupled plasma processing chamber may also be used.

[0151] During operation of the apparatus 1400, one or more process gases may be supplied through gas inlets 1460 and / or 1470. In certain embodiments, the process gas may be supplied only through the main gas inlet 1460 or only through the side gas inlet 1470. In some cases, the gas inlets shown in the figure may be replaced with more complex gas inlets, for example, one or more showerheads. The Faraday shield 1449a and / or optional grid 1450 may include internal channels and holes that allow the process gas to be supplied to the process chamber 1424. Either or both of the Faraday shield 1449a and / or optional grid 1450 may function as showerheads for supplying the process gas. In some embodiments, the liquid vaporization and supply system may be located upstream of the process chamber 1424 so that, once the liquid reactants or precursors have vaporized, the vaporized reactants or precursors are introduced into the process chamber 1424 through the gas inlets 1460 and / or 1470.

[0152] High-frequency power is supplied from the RF power supply 1441 to the coil 1433, causing an RF current to flow through the coil 1433. The RF current flowing through the coil 533 generates an electromagnetic field around the coil 1433. The electromagnetic field generates an induced current inside the upper sub-chamber 1402. The physical and chemical interactions between the various ions and radicals generated and the wafer 1419 etch the features of the wafer 1419 and selectively deposit layers on the wafer 1419.

[0153] When the plasma grid 1450 is used such that both an upper sub-chamber 1402 and a lower sub-chamber 1403 are present, an induced current acts on the gas present in the upper sub-chamber 1402, generating an electron-ion plasma within the upper sub-chamber 1402. An optional internal plasma grid 1450 limits the amount of hot electrons in the lower sub-chamber 1403. In some embodiments, the apparatus 1400 is designed and operated such that the plasma present in the lower sub-chamber 1403 is an ion-ion plasma.

[0154] Both the upper electron-ion plasma and the lower ion-ion plasma may contain positive and negative ions, although the ion-ion plasma will have a higher ratio of negative ions to positive ions. By-products from volatile etching and / or deposition may be removed from the lower sub-chamber 1403 via port 1422. The chuck 1417 disclosed herein may operate at high temperatures ranging from about 10°C to about 250°C. The temperature will depend on the process operation and the specific recipe.

[0155] If the apparatus 1400 is installed in a cleanroom or manufacturing facility, the apparatus 1400 may be coupled to the facility (not shown). The facility includes piping that provides processing gas, vacuum, temperature control, and environmental particle control. If the apparatus 1400 is installed in a target manufacturing facility, these facilities are coupled to the apparatus 1400. In addition, the apparatus 1400 may be coupled to a transfer chamber to allow robotics to load and unload semiconductor wafers into and out of the apparatus 1400 using typical automated equipment.

[0156] In some embodiments, a system controller 1430 (which may include one or more physical or logical controllers) controls some or all of the operation of the process chamber 1424. The system controller 1430 may include one or more memory devices and one or more processors. In some embodiments, the apparatus 1400 includes a switching system for controlling flow rate and duration when the disclosed embodiment is performed. In some embodiments, the apparatus 1400 may have a switching time of up to about 500 milliseconds, or up to about 750 milliseconds. The switching time may depend on the flow chemical, the selected recipe, the reactor architecture, and other factors.

[0157] In some embodiments, the system controller 1430 is part of a system, which may be part of the examples described above. Such a system may include semiconductor processing equipment, comprising one or more processing tools, one or more chambers, one or more processing platforms, and / or specific processing components (such as a wafer stand, gas flow system, etc.). These systems may be incorporated into electronics for controlling pre-processing, in-processing, and post-processing operations on semiconductor wafers or substrates. The electronics may be incorporated into the system controller 1430, which may control various components or sub-parts of the system. Depending on the processing parameters and / or the type of system, the system controller may be programmed to control any of the processes disclosed herein, including the delivery of processing gases, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, radio frequency (RF) generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, position and work settings, loading and unloading of wafers to and from tools and other transfer tools connected to or interfaced with a particular system, and / or load locks.

[0158] Broadly speaking, the system controller 1430 may be defined as an electronic device having various integrated circuits, logic, memory, and / or software, which receives and issues instructions, controls operations, enables cleaning operations, enables endpoint measurements, etc. The integrated circuit may include a chip in the form of firmware that stores program instructions, a chip defined as a digital signal processor (DSP), an application-specific integrated circuit (ASIC), and / or one or more microprocessors, or a microcontroller that executes program instructions (e.g., software). Program instructions are instructions communicated to the controller in the form of various individual settings (or program files) that define work parameters for performing a particular process on or for a semiconductor wafer, or for the system. In some embodiments, the work parameters may be part of a recipe defined by a process engineer to implement one or more processing steps during the fabrication or removal of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or wafer dies.

[0159] In some embodiments, the system controller 1430 may be part of or coupled to a computer that is integrated into or coupled to the system, networked to or connected to the system, or a combination thereof. For example, the controller may be in the “cloud” or all or part of a fab host computer system, thereby enabling remote access to wafer processing. The computer may enable remote access to the system to monitor the current progress of manufacturing operations, investigate the history of past manufacturing operations, investigate trends or performance indicators from multiple manufacturing operations, modify parameters of the current operation, set processing steps following the current operation, or start a new process. In some examples, a remote computer (e.g., a server) may provide process recipes to the system via a network which may include a local network or the internet. The remote computer may include a user interface that enables input or programming of parameters and / or settings, which are then communicated from the remote computer to the system. In some examples, the system controller 1430 receives instructions in data format that specify parameters for each processing step performed during one or more operations. It should be understood that the parameters may be specific to the type of process being performed and the type of tool the controller is configured to interface with or control. Therefore, as described above, the system controller 1430 may be distributed, for example, by including one or more separate controllers networked with one another and aimed at a common purpose, such as the processes and controls described herein. An example of a distributed controller for such purposes might be one or more integrated circuits on a chamber in communication with one or more integrated circuits located remotely (e.g., at the platform level or as part of a remote computer), which together control the process in the chamber.

[0160] Exemplary systems may include, but are not limited to, plasma etching chambers or modules, deposition chambers or modules, spin rinse chambers or modules, metal plating chambers or modules, cleaning chambers or modules, bevel edge etching chambers or modules, physical vapor deposition (PVD) chambers or modules, chemical vapor deposition (CVD) chambers or modules, ALD chambers or modules, ALE chambers or modules, ion implantation chambers or modules, track chambers or modules, EUV lithography chambers (scanners) or modules, dry developing chambers or modules, and any other semiconductor processing systems related to or used in the fabrication and / or manufacture of semiconductor wafers.

[0161] As described above, depending on the process steps performed by the tool, the controller may communicate with one or more of the following: other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, neighboring tools, tools located throughout the factory, the main computer, another controller, or tools used for material handling to load and unload wafer containers between tool locations and / or load ports within the semiconductor manufacturing plant.

[0162] EUVL patterning may be carried out using any suitable tool, often referred to as a scanner, such as the TWINSCAN NXE:3300B™ platform provided by ASML (Veldhoven, NL). The EUVL patterning tool may be a standalone device, with the substrate entering and exiting the tool for deposition and etching, as described herein. Alternatively, as described later, the EUVL patterning tool may be a module of a larger multi-component tool. Figure 15 shows a semiconductor process cluster tool architecture having vacuum-integrated deposition, EUV patterning, and dry developing / etching modules interfaced with a vacuum transfer module, suitable for realizing the process described herein. The process may be carried out without such vacuum integration equipment, although such equipment may be advantageous in some embodiments.

[0163] Figure 15 shows a semiconductor process cluster tool architecture having vacuum-integrated deposition and patterning modules interfaced with a vacuum transfer module, suitable for realizing the processes described herein. The configuration of transfer modules for "transferring" wafers between multiple storage facilities and processing modules is sometimes referred to as a "cluster tool architecture" system. The deposition and patterning modules are vacuum-integrated according to the requirements of a particular process. Other modules, such as those for etching, may also be included in the cluster.

[0164] The vacuum transfer module (VTM) 1538 interfaces with four processing modules 1520a to 1520d, which may be individually optimized to perform various manufacturing processes. For example, processing modules 1520a to 1520d may be implemented to perform deposition, evaporation, ELD, dry development, etching, stripping, and / or other semiconductor processes. For example, module 1520a may be an ALD reactor, which may be operated to perform thermal atomic layer deposition described herein in a non-plasma manner, such as the Vector tool available from Lam Research Corporation (Fremont, CA). Module 1520b may be a PECVD tool such as Lam Vector®. It should be understood that the drawings are not necessarily drawn to scale.

[0165] Airlocks 1542 and 1546, also called load locks or transfer modules, interface with the VTM 1538 and patterning module 1540. For example, as mentioned above, a suitable patterning module may be the TWINSCAN NXE:3300B™ platform supplied by ASML (Veldhoven, NL). This tool architecture allows for the transfer of workpieces, such as semiconductor substrates or wafers, under vacuum to prevent reaction before exposure. The fact that EUVL also requires significantly lower pressures, given the strong light absorption of incident photons by ambient gases such as H2O and O2, facilitates the integration of the deposition module and lithography tools.

[0166] As described above, this integrated architecture is merely one anticipated embodiment of the tools for realizing the process described. This process may also be realized using a conventional standalone EUVL scanner and a deposition reactor such as the Lam Vector tool, either standalone or integrated as a module with other tools such as etching, stripping (e.g., Lam Kiyo or Gamma tools) in a cluster architecture, as illustrated with reference to Figure 15, but without an integrated patterning module.

[0167] Airlock 1542 may be an "outward" load lock, referring to the transfer of a substrate from the VTM 1538, which serves the deposition module 1520a, to the patterning module 1540, and airlock 1546 may be an "inward" load lock, referring to the transfer of a substrate back from the patterning module 1540 to the VTM 1538. The inward load lock 1546 may also provide an interface to the outside of the tool for loading and unloading the substrate. Each process module has facets that interface the module to the VTM 1538. For example, the deposition process module 1520a has facet 1536. Inside each facet, sensors, such as sensors 1 to 18 as shown, are used to detect the passage of a wafer 1526 when the wafer 1526 moves between the respective stations. The patterning module 1540, as well as airlocks 1542 and 1546, may similarly be equipped with additional facets and sensors (not shown).

[0168] The main VTM robot 1522 transfers the wafer 1526 between modules, including airlocks 1542 and 1546. In one embodiment, the robot 1522 has one arm, and in another embodiment, the robot 1522 has two arms, each arm having an end effector 1524 for lifting wafers such as wafer 1526 for transport. A front-end robot 1544 is used to transfer the wafer 1526 from the outward airlock 1542 to the patterning module 1540, and from the patterning module 1540 to the inward airlock 1546. The front-end robot 1544 may also transport the wafer 1526 between the inward load lock and the outside of the tool for loading and unloading the substrate. The inward airlock module 1546 has the ability to match the environment between air and vacuum, so that the wafer 1526 can move between the two pressure environments without being damaged.

[0169] It should be noted that EUVL tools typically operate at higher vacuum levels than deposition tools. In this case, it is desirable to increase the vacuum level of the substrate environment during transfer between the deposition tool and the EUVL tool so that the substrate can be degassed before entering the patterning tool. An outward airlock 1542 may provide this function by holding the transferred wafer at a lower pressure, i.e., below the pressure inside the patterning module 1540, for a certain period of time, and exhausting any exhaust gases, thereby preventing the optics of the patterning tool 1540 from being contaminated by exhaust gases from the substrate. A suitable pressure for the outward airlock for exhaust gases is 1E-8 Torre or less.

[0170] In some embodiments, a system controller 1550 (which may include one or more physical or logical controllers) controls some or all of the work of the cluster tools and / or their separate modules. It should be noted that the controller may be local to the cluster architecture, located outside the cluster architecture on the manufacturing floor, or located remotely and connected to the cluster architecture via a network. The system controller 1550 may include one or more memory devices and one or more processors. The processors may include a central processing unit (CPU) or computer, analog and / or digital input / output connections, a stepper motor controller board, and other similar components. Instructions for performing proper control work are executed by the processors. These instructions may be stored in memory devices associated with the controller, or they may be provided via a network. In certain embodiments, the system controller runs system control software.

[0171] The system control software may include instructions that control the timing and / or magnitude of the application of any aspect of the tool or module work. The system control software may be configured in any preferred manner. For example, various process tool component subroutines or control objects may be written to control the work of process tool components necessary to carry out various process tool processes. The system control software may be coded in any preferred computer-readable programming language. In some embodiments, the system control software includes input / output control (IOC) sequence instructions that control the various parameters described above. For example, each stage of a semiconductor manufacturing process may include one or more instructions executed by the system controller. Instructions that set process conditions for condensation, deposition, evaporation, patterning, and / or etching stages may be included, for example, in the corresponding recipe stage.

[0172] In various embodiments, an apparatus for forming a negative mask is provided. The apparatus may include a processing chamber for patterning, deposition, and etching, and a controller which includes instructions for forming a negative mask. The instructions may include code for patterning features in a chemically amplified (CAR) resist on a semiconductor substrate by EUV exposure within the processing chamber to expose the substrate surface, developing the photopatterned resist, and etching the underlying layer or stack of layers using the patterned resist as a mask. Development may be carried out using a halide-containing chemical.

[0173] It should be noted that the computer controlling wafer movement can be local to the cluster architecture, located outside the cluster architecture on the manufacturing floor, or located remotely and connected to the cluster architecture via a network. A controller as described above with respect to any of Figures 12, 13, or 14 may be implemented using the tool shown in Figure 15.

[0174] conclusion For example, a process and apparatus for dry development of metal and / or metal oxide photoresists for forming a patterned mask in connection with EUV patterning is disclosed.

[0175] The examples and embodiments described herein are for illustrative purposes only, and it is understood that various modifications or changes will be proposed to those skilled in the art. Various alternative forms of design may be realized, although various details have been omitted for clarity. Accordingly, these examples should be considered illustrative and not limiting, and this disclosure is not limited to the details described herein and may be modified within the scope of this disclosure. This disclosure includes the following examples of applications. [Application Example 1] A method for processing semiconductor substrates, In a process chamber, a photopatterned metal-containing resist is placed on a substrate layer of a semiconductor substrate. A method comprising developing a photopatterned metal-containing resist to form a resist mask by selectively removing a portion of the resist by exposure to a developing chemical containing a halide. [Application Example 2] A method according to Application Example 1, wherein the photopatterned metal-containing resist is a photopatterned metal-containing EUV resist. [Application Example 3] A method according to Application Example 2, wherein developing the photopatterned metal-containing EUV resist comprises selectively removing the non-EUV exposed portions of the EUV resist with the developing chemical to form the resist mask. [Application Example 4] The method described in Application Example 3, A method further comprising non-selectively removing the EUV-unexposed and EUV-exposed portions of the photopatterned metal-containing resist without removing the substrate layer. [Application Example 5] A method according to Application Example 1, wherein the developing chemical comprises a hydrogen halide, hydrogen gas and halogen gas, an organic halide, an acyl halide, a carbonyl halide, a thionyl halide, or a mixture thereof. [Application Example 6] A method according to Application Example 5, wherein the developing chemical comprises hydrogen fluoride (HF), hydrogen chloride (HCl), hydrogen bromide (HBr), or hydrogen iodide (HI). [Application Example 7] The method according to Application Example 5, wherein the developing chemical is hydrogen gas (H 2 ) and fluorine gas (F 2 ), chlorine gas (Cl 2 ), bromine gas (Br 2 ), or iodine gas (I 2 A method that includes ) [Application Example 8] The method according to Application Example 1, wherein the halide is flowed into the process chamber together with a carrier gas, and the carrier gas is helium (He), neon (Ne), argon (Ar), xenon (Xe), or nitrogen (N) 2 Methods including ) [Application Example 9] A method according to Application Example 1, wherein the development of the photopatterned metal-containing resist by exposure to the developing chemical comprises dry developing the photopatterned metal-containing resist by exposure to a dry developing chemical. [Application Example 10] A method according to Application Example 9, wherein dry development of the photopatterned metal-containing resist comprises applying a remote plasma containing the halide radical to the resist. [Application Example 11] A method according to Application Example 9, wherein the dry development of the photopatterned metal-containing resist includes exposing it to at least the halide by a non-plasma thermal process. [Application Example 12] A method according to Application Example 9, wherein the photopatterned metal-containing resist is dry-developed at a temperature of about -60°C to about 120°C, a chamber pressure of 0.1 mTorr to about 760 Torr, and a halogen gas flow rate of 100 sccm to 2000 sccm, wherein the etching selectivity of the resist mask is adjustable at least in part on the temperature, the chamber pressure, the gas flow rate, or a combination thereof. [Application Example 13] A method according to Application Example 12, wherein the temperature is approximately -20°C to approximately 20°C. [Application Example 14] A method according to Application Example 12, wherein the profile of the resist mask is controllable at least in part on the temperature, the chamber pressure, the gas flow rate, or a combination thereof. [Application Example 15] A method according to any one of Application Examples 1 to 14, wherein the photopatterned metal-containing resist is an organometallic oxide thin film or an organometallic thin film. [Application Example 16] A method according to Application Example 15, wherein the photopatterned metal-containing resist comprises an organotin oxide. [Application Example 17] A method according to any one of Application Examples 1 to 14, wherein the photopatterned metal-containing resist comprises an element selected from the group consisting of tin, hafnium, tellurium, bismuth, indium, antimony, iodine, and germanium. [Application Example 18] A method according to any one of Application Examples 1 to 14, wherein providing the photopatterned metal-containing resist comprises vapor deposition of a metal-containing resist film on the substrate layer. [Application Example 19] A method according to any one of Application Examples 1 to 14, wherein providing the photopatterned metal-containing resist comprises spin-coating a metal-containing resist film onto the substrate layer. [Application Example 20] A method according to any one of Application Examples 1 to 14, wherein the thickness of the photopatterned metal-containing resist is about 10 nm to about 50 nm. [Application Example 21] A method according to any one of the application examples 1 to 14, A method further comprising developing the photopatterned metal-containing resist and then exposing the photopatterned metal-containing resist to an inert gas plasma. [Application Example 22] The method described in Application Example 21, A method further comprising repeatedly developing the photopatterned metal-containing resist and exposing the photopatterned metal-containing resist to the inert gas plasma. [Application Example 23] A method according to any one of the application examples 1 to 14, A method further comprising baking the photopatterned metal-containing resist at a high temperature before developing the photopatterned metal-containing resist. [Application Example 24] The method described in any one of Application Examples 1 to 14, which provides the photopatterned metal-containing resist, Depositing a metal-containing EUV resist film on the aforementioned semiconductor substrate, Non-selective removal of a portion of the metal-containing EUV resist film on the back surface and bevel edge of the semiconductor substrate, A method comprising exposing the metal-containing EUV resist film to EUV light to form the photopatterned metal-containing resist. [Application Example 25] A method according to any one of the application examples 1 to 14, Depositing a metal-containing EUV resist film on the aforementioned semiconductor substrate, A method further comprising non-selectively removing the metal-containing EUV resist film from the semiconductor substrate without removing the substrate layer before providing the photopatterned metal-containing resist. [Application Example 26] An apparatus for developing a resist, wherein the apparatus is A process chamber having a substrate support, A vacuum line coupled to the process chamber, A developing chemical line coupled to the process chamber, A controller configured to have instructions for processing a semiconductor substrate, wherein the instructions are In the process chamber, to provide a metal-containing resist that has been photopatterned on a substrate layer of the semiconductor substrate, Apparatus, including a code, for developing a photopatterned metal-containing resist to form a resist mask by selectively removing a portion of the resist by exposure to a developing chemical containing a halide. [Application Example 27] Apparatus as described in Application Example 26, wherein the photopatterned metal-containing resist is a photopatterned metal-containing EUV resist, and the controller is configured to have instructions including a code for developing the photopatterned metal-containing EUV resist, and a code for selectively removing the non-EUV exposed portions of the EUV resist from the EUV exposed portions with the developing chemical to form the resist mask. [Application Example 28] The apparatus described in Application Example 26, The apparatus further comprises one or more heaters coupled to the substrate support, wherein the one or more heaters include a plurality of independently controllable temperature control zones. [Application Example 29] The apparatus described in Application Example 26, wherein the inside of the process chamber is coated with a corrosion inhibitor. [Application Example 30] The apparatus described in Application Example 26, The apparatus further comprises a cold trap coupled to the process chamber, the cold trap configured to remove water from the process chamber. [Application Example 31] An apparatus according to any one of Application Examples 26 to 30, wherein the process chamber includes a plastic material. [Application Example 32] An apparatus according to any one of Application Examples 26 to 30, further comprising a UV lamp or an IR lamp coupled to the process chamber, wherein the UV lamp or the IR lamp is configured to cure the photopatterned metal-containing resist or to remove excess halides from the process chamber. [Application Example 33] A method for processing a semiconductor substrate, wherein the method is In a process chamber, a photopatterned metal oxide EUV resist is dry-deposited and placed on a substrate layer of a semiconductor substrate. A method comprising: dry developing a photopatterned metal oxide EUV resist by selectively removing the EUV-unexposed portions of the EUV resist by exposure to a dry developing chemical containing HCl and / or HBr, thereby forming a resist hard mask from the EUV-exposed portions. [Application Example 34] A method according to Application Example 33, wherein dry development is performed by a non-plasma thermal process, and exposure to the dry development chemical is performed at a temperature of approximately -20°C to approximately 20°C. [Application Example 35] A method according to Application Example 33, wherein the photopatterned metal oxide EUV resist comprises an organotin oxide.

Claims

1. A method for processing semiconductor substrates, A photopatterned organometallic oxide-containing EUV resist, which is dry-deposited or wet-deposited and photopatterned, comprising an unexposed organometallic oxide-containing portion and an EUV-exposed metal oxide-containing portion, is provided on a substrate layer of a semiconductor substrate in a process chamber, wherein the organometallic oxide-containing EUV resist contains an element selected from the group consisting of tin, hafnium, tellurium, bismuth, indium, antimony, iodine, and germanium. The method includes dry developing the photopatterned organometallic oxide-containing EUV resist to form a resist mask by selectively removing a portion of the photopatterned organometallic oxide-containing EUV resist by exposure to a dry developing chemical containing hydrogen halide, A method comprising using the hydrogen halide to selectively remove unexposed organometallic oxide-containing portions from the EUV-exposed metal oxide-containing portions in order to form the resist mask.

2. The method according to claim 1, A method further comprising removing the unexposed organometallic oxide-containing portion and the EUV-exposed metal oxide-containing portion of the photopatterned organometallic oxide-containing EUV resist without removing the substrate layer.

3. A method according to claim 1, wherein the dry developing chemical comprises hydrogen fluoride (HF), hydrogen chloride (HCl), hydrogen bromide (HBr), or hydrogen iodide (HI).

4. The method according to claim 1, wherein the hydrogen halide is flowed into the process chamber together with a carrier gas, the carrier gas being helium (He), neon (Ne), argon (Ar), xenon (Xe), or nitrogen (N) 2 Methods including )

5. A method according to claim 1, wherein dry developing the photopatterned organometallic oxide-containing EUV resist comprises applying a remote plasma containing hydrogen halide radicals to the photopatterned organometallic oxide-containing EUV resist.

6. A method according to claim 1, wherein the photopatterned organometallic oxide-containing EUV resist is dry-developed at a temperature of -60°C to 120°C, a chamber pressure of 0.1 mTorr to 760 Torr, and a hydrogen halide gas flow rate of 100 sccm to 2000 sccm, wherein the etching selectivity of the resist mask is adjustable at least in part on the temperature, the chamber pressure, the gas flow rate, or a combination thereof.

7. A method according to claim 6, wherein the temperature is -20°C to 20°C.

8. A method according to claim 6, wherein the profile of the resist mask is controllable at least in part on the temperature, the chamber pressure, the gas flow rate, or a combination thereof.

9. A method according to claim 1, wherein the photopatterned organometallic oxide-containing EUV resist comprises an organotin oxide.

10. A method according to claim 1, wherein the organometallic oxide-containing EUV resist is provided by vapor-depositing an organometallic oxide-containing EUV resist film on the substrate layer.

11. A method according to claim 1, wherein the organometallic oxide-containing EUV resist is provided by spin-coating an organometallic oxide-containing EUV resist film onto the substrate layer.

12. A method according to claim 1, wherein the thickness of the photopatterned organometallic oxide-containing EUV resist is 10 nm to 50 nm.

13. The method according to claim 1, A method further comprising dry developing the photopatterned organometallic oxide-containing EUV resist, and then exposing the photopatterned organometallic oxide-containing EUV resist to an inert gas plasma.

14. The method according to claim 13, A method further comprising repeatedly performing the steps of dry developing the photopatterned organometallic oxide-containing EUV resist and exposing the photopatterned organometallic oxide-containing EUV resist to the inert gas plasma.

15. The method according to claim 1, A method further comprising baking the photopatterned organometallic oxide-containing EUV resist at a temperature between 100°C and 200°C before dry developing the photopatterned organometallic oxide-containing EUV resist.

16. The method according to claim 1, wherein the photopatterned organometallic oxide-containing EUV resist is provided, Depositing an organometallic oxide-containing EUV resist film on the aforementioned semiconductor substrate, To remove a portion of the organometallic oxide-containing EUV resist film on the back surface and bevel edge of the semiconductor substrate, A method comprising: exposing the organometallic oxide-containing EUV resist film to EUV light to form the photopatterned organometallic oxide-containing EUV resist.

17. The method according to claim 1, Depositing an organometallic oxide-containing EUV resist film on the aforementioned semiconductor substrate, A method further comprising removing the organometal oxide-containing EUV resist film from the semiconductor substrate without removing the substrate layer before providing the photopatterned organometal oxide-containing EUV resist.

18. An apparatus for developing a resist, wherein the apparatus is A process chamber having a substrate support, A vacuum line coupled to the process chamber, A developing chemical line coupled to the process chamber, A controller configured to have instructions for processing a semiconductor substrate, wherein the instructions are In the process chamber, a photopatterned organometallic oxide-containing EUV resist is provided on a substrate layer of the semiconductor substrate, which is dry-deposited or wet-deposited and photopatterned, and which includes an unexposed organometallic oxide-containing portion and an EUV-exposed metal oxide-containing portion. The code includes a method for dry developing the photopatterned organometallic oxide-containing EUV resist to form a resist mask by selectively removing a portion of the photopatterned organometallic oxide-containing EUV resist by exposure to a dry developing chemical containing hydrogen halide, The apparatus uses the hydrogen halide to selectively remove the unexposed organometallic oxide-containing portions from the EUV-exposed metal oxide-containing portions in order to form the resist mask.

19. The apparatus according to claim 18, The apparatus further comprises one or more heaters coupled to the substrate support, wherein the one or more heaters include a plurality of independently controllable temperature control zones.

20. The apparatus according to claim 18, wherein the inside of the process chamber is coated with a corrosion inhibitor.

21. The apparatus according to claim 18, The apparatus further comprises a cold trap coupled to the process chamber, the cold trap configured to remove water from the process chamber.

22. An apparatus according to any one of claims 18 to 21, wherein the process chamber includes a plastic material.

23. An apparatus according to any one of claims 18 to 21, further comprising a UV lamp or an IR lamp coupled to the process chamber, wherein the UV lamp or the IR lamp is configured to cure the photopatterned organometallic oxide-containing EUV resist or to remove excess halides from the process chamber.

24. A method for processing a semiconductor substrate, wherein the method is In a process chamber, a photopatterned organometallic oxide-containing EUV resist, which includes an unexposed organometallic oxide-containing portion and an EUV-exposed metal oxide-containing portion, is provided on a substrate layer of a semiconductor substrate. The method includes dry developing the photopatterned organometallic oxide-containing EUV resist by selectively removing the EUV-unexposed portions of the photopatterned organometallic oxide-containing EUV resist by exposure to a dry developing chemical containing HCl and / or HBr, thereby forming a resist hard mask from the EUV-exposed metal oxide-containing portions. A method comprising using HCl and / or HBr to selectively remove unexposed organometallic oxide-containing portions from the EUV-exposed metal oxide-containing portions in order to form the resist hard mask.

25. A method according to claim 24, wherein the exposure to the dry developing chemical is carried out at a temperature of -20°C to 20°C.

26. A method according to claim 24, wherein the photopatterned organometallic oxide-containing EUV resist comprises an organotin oxide.

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