Trench Semiconductor Power Devices

Abstract

To provide a trench-type semiconductor power device having an electrostatic discharge protection structure.SOLUTION: There is provided a trench-type semiconductor power device 100_1 in which a first semiconductor layer 120 includes: a first part semiconductor layer 120_1 that is adjacent to a bulk doped region 106 and a source doped region 108, and used as a gate electrode having a first conductivity type; and a third part semiconductor layer 120_3 that extends in a second direction, that is away from the source doped region, and that includes a plurality of first doped regions 120n having the first conductivity type and a plurality of second doped regions 120p having a second conductivity type. The plurality of first doped regions and the plurality of second doped regions are arranged alternately, and serve as an electrostatic discharge protection structure ESD_P1 that forms a diode string having back-to-back diodes. A first end of the diode string is electrically connected to the gate electrode through a gate resistor Rg, and a second end of the diode string is electrically connected to the source doped region.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present invention relates to a trench semiconductor power device, and more specifically, to a trench semiconductor power device having an electrostatic discharge protection structure.

Background Art

[0002] Semiconductor power devices are widely applied in fields such as automotive electronics and switching power supplies. A trench power device forms a gate oxide layer on the sidewall of a gate trench and fills it with polycrystalline silicon to form a gate, and is currently one of the most popular power switching devices. The trench power device can improve the utilization efficiency of the device area, obtain a larger device cell channel width per unit area, and thereby obtain a larger current conduction ability.

[0003] Semiconductor power devices are susceptible to the influence of voltage spikes caused by electrostatic discharge (ESD) events (including human body mode and device mode). The instantaneous large current and voltage caused by an electrostatic discharge event may destroy and damage the gate oxide layer of the trench power device, and even cause burnout and high leakage. Therefore, a trench semiconductor power device having an electrostatic discharge protection structure is needed.

Summary of the Invention

[0004] Embodiments of the present disclosure relate to trench semiconductor power devices. The trench semiconductor power device includes a substrate having a first conductivity type; an epitaxial layer located on the substrate and having the first conductivity type; a bulk-doped region located within the epitaxial layer and away from the substrate and having a second conductivity type; a source-doped region located within the bulk-doped region and away from the substrate and having the first conductivity type; and a trench structure including a first semiconductor layer having a first depth in a first direction extending from the source-doped region toward the substrate and extending along a second direction perpendicular to the first direction. The first semiconductor layer includes a first portion adjacent to the bulk-doped region and the source-doped region, used as a gate electrode having the first conductivity type, and a second portion extending along the second direction and away from the source-doped region, including a plurality of first-doped regions having the first conductivity type and a plurality of second-doped regions having the second conductivity type, wherein the plurality of first-doped regions and the plurality of second-doped regions are arranged alternately to form a first diode string having one or more back-to-back diodes. The first end of the first diode string is electrically connected to the gate electrode, and the second end of the first diode string is electrically connected to the source-doped region via the first connection structure.

[0005] By reading the following detailed description in conjunction with the drawings, one can best understand the aspects of some embodiments of this disclosure. It should be noted that the various structures do not have to be constructed in proportion. In practice, the size of the various structures can be arbitrarily enlarged or reduced for the sake of clarity in the discussion. [Brief explanation of the drawing]

[0006] [Figure 1] Figure 1 is a schematic diagram of a trench semiconductor power device based on some embodiments of the present disclosure. [Figure 2] Figure 2 is a top view of a trench semiconductor power device based on some embodiments of the present disclosure. [Figure 3A]Figure 3A is a cross-sectional view of the trench semiconductor power device shown in Figure 2, along line A-A'. [Figure 3B] Figure 3B is a cross-sectional view of the trench semiconductor power device shown in Figure 2, along line B-B'. [Figure 4] Figure 4 is a top view of a trench semiconductor power device based on some embodiments of the present disclosure. [Figure 5A] Figure 5A is a cross-sectional view of the trench semiconductor power device shown in Figure 4, along line A-A'. [Figure 5B] Figure 5B is a cross-sectional view of the trench semiconductor power device shown in Figure 4, along line B-B'. [Figure 6] Figure 6 is a top view of a trench semiconductor power device based on some embodiments of the present disclosure. [Figure 7A] Figure 7A is a cross-sectional view of the trench semiconductor power device shown in Figure 6, along line A-A'. [Figure 7B] Figure 7B is a cross-sectional view along line B-B' of the trench semiconductor power device shown in Figure 6. [Figure 8] Figure 8 is a top view of a trench semiconductor power device based on some embodiments of the present disclosure. [Figure 9A] Figure 9A is a cross-sectional view of the trench semiconductor power device shown in Figure 8 along line A-A'. [Figure 9B] Figure 9B is a cross-sectional view of the trench semiconductor power device shown in Figure 8, along line B-B'. [Figure 10] Figure 10 is a top view of a trench semiconductor power device based on some embodiments of the present disclosure. [Figure 11A] Figure 11A is a cross-sectional view of the trench semiconductor power device shown in Figure 10, along line A-A'. [Figure 11B] Figure 11B is a cross-sectional view along line B-B' of the trench semiconductor power device shown in Figure 10. [Figure 12]Figure 12 is a top view of a trench semiconductor power device based on some embodiments of the present disclosure. [Figure 13A] Figure 13A is a cross-sectional view of the trench semiconductor power device shown in Figure 12 along line A-A'. [Figure 13B] Figure 13B is a cross-sectional view along line B-B' of the trench semiconductor power device shown in Figure 12. [Figure 14] Figure 14 is a top view of a trench semiconductor power device based on some embodiments of the present disclosure. [Figure 15A] Figure 15A is a cross-sectional view of the trench semiconductor power device shown in Figure 14 along line A-A'. [Figure 15B] Figure 15B is a cross-sectional view along line B-B' of the trench semiconductor power device shown in Figure 14. [Figure 16] Figure 16 is a top view of a trench semiconductor power device based on some embodiments of the present disclosure. [Figure 17A] Figure 17A is a cross-sectional view of the trench semiconductor power device shown in Figure 16 along line A-A'. [Figure 17B] Figure 17B is a cross-sectional view along line B-B' of the trench semiconductor power device shown in Figure 16. [Figure 17C] Figure 17C is a cross-sectional view along line C-C' of the trench semiconductor power device shown in Figure 16. [Figure 18] Figure 18 is a top view of a trench semiconductor power device based on some embodiments of the present disclosure. [Figure 19A] Figure 19A is a cross-sectional view of the trench semiconductor power device shown in Figure 18 along line A-A'. [Figure 19B] Figure 19B is a cross-sectional view of the trench semiconductor power device shown in Figure 18 along line B-B'. [Figure 19C] Figure 19C is a cross-sectional view along line C-C' of the trench semiconductor power device shown in Figure 18. [Figure 20]FIG. 20 is a top view of a trench semiconductor power device based on some embodiments of the present disclosure. [Figure 21A] FIG. 21A is a cross-sectional view of the trench semiconductor power device described in FIG. 20 along line A-A'. [Figure 21B] FIG. 21B is a cross-sectional view of the trench semiconductor power device described in FIG. 20 along line B-B'. [Figure 21C] FIG. 21C is a cross-sectional view of the trench semiconductor power device described in FIG. 20 along line C-C'. [Figure 22] FIG. 22 is a top view of a trench semiconductor power device based on some embodiments of the present disclosure. [Figure 23A] FIG. 23A is a cross-sectional view of the trench semiconductor power device described in FIG. 22 along line A-A'. [Figure 23B] FIG. 23B is a cross-sectional view of the trench semiconductor power device described in FIG. 22 along line B-B'. [Figure 24] FIG. 24 is a top view of a trench semiconductor power device based on some embodiments of the present disclosure. [Figure 25A] FIG. 25A is a cross-sectional view of the trench semiconductor power device described in FIG. 24 along line A-A'. [Figure 25B] FIG. 25B is a cross-sectional view of the trench semiconductor power device described in FIG. 24 along line B-B'. [Figure 26] FIG. 26 is a top view of a trench semiconductor power device based on some embodiments of the present disclosure. [Figure 27A] FIG. 27A is a cross-sectional view of the trench semiconductor power device described in FIG. 26 along line A-A'. [Figure 27B] FIG. 27B is a cross-sectional view of the trench semiconductor power device described in FIG. 26 along line B-B'. [Figure 28] FIG. 28 is a top view of a trench semiconductor power device based on some embodiments of the present disclosure. [Figure 29A]Figure 29A is a cross-sectional view of the trench semiconductor power device shown in Figure 28 along line A-A'. [Figure 29B] Figure 29B is a cross-sectional view along line B-B' of the trench semiconductor power device shown in Figure 28. [Modes for carrying out the invention]

[0007] Identical or similar assemblies are indicated by the same reference numerals in the figures and detailed description. Some embodiments of this disclosure can be readily understood from the following detailed description and drawings.

[0008] The following disclosure provides numerous different embodiments or examples for implementing various features of the target being provided. Specific examples of assemblies and arrangements are described below. Of course, these are merely examples and should not be limiting. In this disclosure, a reference to forming a first feature above or on top of a second feature may include embodiments in which the first and second features form direct contact, and may also include embodiments in which another feature is formed between the first and second features, without requiring direct contact between them. Also in this disclosure, reference numerals and / or letters may be duplicated within each example. Such duplication is done for simplicity and clarity and does not in itself indicate a relationship between each embodiment and / or arrangement discussed.

[0009] The following sections discuss in detail embodiments of this disclosure. However, it should be understood that this disclosure provides many application concepts that can be materialized in various specific environments. The specific embodiments discussed are illustrative and do not limit the scope of this disclosure.

[0010] This disclosure provides trench semiconductor power devices. Compared to conventional trench semiconductor power devices, the trench semiconductor power devices of this disclosure have diodes formed within a cell region and capable of providing electrostatic discharge (ESD) protection within the cell region. The trench semiconductor power device has a diode string formed by one or more back-to-back diodes formed within the trench. When an electrostatic discharge event occurs, a momentary large current is led out of the trench semiconductor power device through the diode string in the trench, thus preventing the momentary large current from damaging the gate of the power transistor in the trench. Compared to power devices that require the use of additional electrostatic discharge protection circuits, the trench semiconductor power devices of this disclosure ensure that the power device is protected by the diode string in the trench, thereby increasing the reliability of the power device. Furthermore, since the diode string formed in the trench does not affect the placement of the gate pad, it is possible to have flexibility in circuit design and layout and reduce manufacturing costs.

[0011] Figure 1 is a schematic diagram of a trench semiconductor power device 100 based on several embodiments of the present disclosure. The trench semiconductor power device 100 includes a vertical power transistor 10, a gate resistor 30, and a diode string 20, having a gate terminal G, a drain terminal D, and a source terminal S. The vertical power transistor 10 may be a semiconductor power device of a different type or manufactured by a different technique, and has a vertical current conduction path. The source and drain of the vertical power transistor 10 are connected to the source terminal S and the drain terminal D, respectively. In the embodiment of Figure 1, the vertical power transistor 10 is an N-type transistor. In other embodiments, the vertical power transistor 10 may be a P-type transistor.

[0012] The gate of the vertical power transistor 10 is coupled to the gate terminal G via a gate resistor 30. A diode string 20 is coupled between the gate terminal G and the source terminal S. The diode string 20 consists of one or more back-to-back diodes 22 connected in series, the number of which is determined by the breakdown voltage of the trench semiconductor power device 100 (e.g., the breakdown voltage of the gate oxide layer of the vertical power transistor 10). In the embodiment of Figure 1, the diode string 20 includes, for illustrative purposes, two back-to-back diodes 22 connected in series. In other embodiments, the diode string 20 may also be formed by more or fewer back-to-back diodes 22.

[0013] When an electrostatic discharge (ESD) event occurs, the gate resistor 30 can prevent the instantaneous large current from the gate terminal G from directly attacking the gate (e.g., the gate oxide) of the vertical power transistor 10. Furthermore, the instantaneous large current caused by the ESD event is transmitted away from the vertical power transistor 10 (e.g., to the ground terminal) by flowing through the diode string 20 to the source terminal S. In other words, when an ESD event occurs, the gate resistor 30 and the diode string 20 can provide ESD protection to the vertical power transistor 10.

[0014] Figure 2 is a top view (or layout diagram) of a trench semiconductor power device 100_1 based on several embodiments of the present disclosure. Figure 3A is a cross-sectional view of the trench semiconductor power device 100_1 shown in Figure 2 along line A-A', and Figure 3B is a cross-sectional view of the trench semiconductor power device 100_1 shown in Figure 2 along line B-B'. Line A-A' extends along the X direction, and line B-B' extends along the Y direction.

[0015] In some embodiments, the trench semiconductor power device 100_1 includes a semiconductor material layer 103, a trench structure 110, conductive plugs 152, 161 and 162, and metal wires (or electrodes) 210a, 210b and 220a. The metal wires 210a, 210b and 220a are formed in the metal layer (e.g., the M1 layer) closest to the semiconductor material layer 103 in the interconnect structure. In some embodiments, the metal wires 210a, 210b and 220a are stretched along the X direction and are parallel to each other. In some embodiments, the width of metal wire 210a is greater than that of metal wires 210b and 220a, and metal wires 210b and 220a have the same width, which is measured along the Y direction. The materials of the metal wires 210a, 210b, and 220a may include copper (Cu), gold (Au), silver (Ag), aluminum (Al), nickel (Ni), titanium (Ti), tungsten (W), tin (Sn), or other metals or alloys.

[0016] The semiconductor material layer 103 may include, for example, N-type or P-type single-crystal silicon materials, epitaxial silicon materials, silicon carbide (SiC), germanium (Ge), silicon germanium (SiGe), gallium nitride (GaN), gallium arsenide (GaAs), gallium arsenide phosphide (GaAsP), or other semiconductor materials. In some embodiments, the semiconductor material layer 103 is an N-type (first conductivity type) epitaxial material. For ease of explanation, the semiconductor material layer 103 is given as an example of an N-type material, and the N-type vertical power transistor 10 is described by having an N-type light-doped region 104, but the disclosure is not limited thereto. The N-type (first conductivity type) or P-type (second conductivity type) semiconductor material layer 103 can be adjusted based on the conductivity type of the vertical power transistor 10.

[0017] The substrate 102 is formed on the underside of the semiconductor material layer 103 and has the same conductivity type doping as the light-doped region 104, for example, N-type. The substrate 102 is the drain contact region of the vertical power transistor 10, coupled to the source end S and used to contact the drain metal layer (not shown in the drawing). In some embodiments, the substrate 102 can be located on the upper surface adjacent to a silicon wafer or other semiconductor material substrate. In some embodiments, the substrate 102 is part of the silicon wafer. The material of the substrate 102 may include single-crystal silicon material, epitaxial silicon material, silicon carbide (SiC), germanium (Ge), silicon germanium (SiGe), gallium nitride (GaN), gallium arsenide (GaAs), gallium arsenide phosphide (GaAsP), or other semiconductor materials. In some embodiments, the doping concentration of the substrate 102 is higher than that of the light-doped region 104.

[0018] The trench structures 110 extend along the Y direction, are parallel to each other, and have a depth D1 within the semiconductor material layer 103. The trench structures 110 may have vertical side walls and an arc-shaped bottom. In some embodiments, the trench structures 110 may be circular, elliptical, rectangular, or polygonal. The trench structures 110 can be formed by an etching process (e.g., a plasma dry etching process) after the position and pattern are defined by a photoresist. Three trench structures 110 are shown in the embodiment of the trench semiconductor power device 100_1, but the number of trench structures 110 is merely an example and does not limit the present disclosure.

[0019] Each trench structure 110 includes a semiconductor layer 120 and an insulating layer 115 extending along the Y direction, with the semiconductor layer 120 having a width W1 in the X direction. The semiconductor layer 120 is surrounded by the insulating layer 115. The semiconductor layer 120 is made of polycrystalline silicon and is divided into three parts 120_1, 120_2, and 120_3 (hereinafter referred to as the first partial semiconductor layer 120_1, the second partial semiconductor layer 120_2, and the third partial semiconductor layer 120_3, respectively). In some embodiments, the trench semiconductor power device 100_1 includes an interlayer dielectric layer 116 covering the semiconductor material layer 103.

[0020] The doped region 106 is formed in the light-doped region 104 of the semiconductor material layer 103 by an ion implantation process. The doped region 106 located between the first partial semiconductor layers 120_1 acts as the bulk-doped region (hereinafter collectively referred to as the bulk-doped region 106) of the vertical power transistor 10. The bulk-doped region 106 and the substrate 102 are located on opposite sides of the light-doped region 104 in the Z direction. The bulk-doped region 106 has a different conductivity type than the light-doped region 104, for example, P-type. Electrically speaking, the coverage area of ​​the bulk-doped region 106 does not have the characteristics of an N-type conductivity type. In other words, the bulk-doped region 106 is located above the light-doped region 104 and is adjacent to the light-doped region 104. In the Z direction, the depth (or thickness) of the bulk-doped region 106 is smaller than the depth D1 of the trench structure 110. In some embodiments, the semiconductor layer 120 comprises silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga2O3), or a diamond-based material.

[0021] The doped region 108 located between the first partial semiconductor layers 120_1 acts as the source for the vertical power transistor 10 (hereinafter collectively referred to as the source-doped region 108). The source-doped region 108 is located within (or above) the bulk-doped region 106 and is separated from the substrate 102. The depth of the source-doped region 108 is less than that of the bulk-doped region 106, and it has a different conductivity type, such as N-type, than the bulk-doped region 106. In some embodiments, the doping concentration of the source-doped region 108 is higher than that of the light-doped region 104.

[0022] In the trench structure 110, the second partial semiconductor layer 120_2 is located between the first partial semiconductor layer 120_1 and the third partial semiconductor layer 120_3. The first partial semiconductor layer 120_1 and the second partial semiconductor layer 120_2 have the same conductivity type doping as the light-doped region 104, for example, N-type. In some embodiments, the doping concentrations of the first partial semiconductor layer 120_1 and the second partial semiconductor layer 120_2 are higher than the doping concentrations of the light-doped region 104. The first partial semiconductor layer 120_1 is a portion of the semiconductor layer 120 adjacent to the source-doped region 108 and acts as the gate electrode of the vertical power transistor 10. The second partial semiconductor layer 120_2 extends along the Y direction, is separated from the source-doped region 108, has a length L1 (for example, the distance from the source-doped region 108 to the conductive plug 162 in the Y direction), and acts as the gate resistance Rg. The impedance of the gate resistance Rg is determined by the ratio of the length L1 to the width W1 of the second partial semiconductor layer 120_2. The third partial semiconductor layer 120_3 is located between the conductive plugs 161 and 162 in the semiconductor layer 120 and acts as an electrostatic discharge protection structure ESD_P1 that forms the diode string 20. The semiconductor layer 120 is isolated from the semiconductor material layer 103 via the insulating layer 115. Furthermore, the electrostatic discharge protection structure ESD_P1 (i.e., the third partial semiconductor layer 120_3) is further isolated from the doped region 106 via the insulating layer 115. It is important to note that the upper surface of the semiconductor layer 120 is lower than the upper surfaces of the source doped region 108 and the insulating layer 115 to ensure that the semiconductor layer 120 does not remain on the upper surface of the source doped region 108 after etching. If it does remain, it will affect the characteristics of the source doped region 108 or cause a short circuit between the source doped region 108 and the semiconductor layer 120.

[0023] The electrostatic discharge protection structure ESD_P1 includes multiple doped regions 120n and multiple doped regions 120p. Doped regions 120n and doped regions 120p have different conductivity types. For example, doped region 120n has the same conductivity type doping as light doped region 104, e.g., N-type, and doped region 120p has the same conductivity type doping as bulk doped region 106, e.g., P-type. In some embodiments, the doping concentration of doped region 120n is higher than that of light doped region 104. The interface between doped region 120n and doped region 120p forms a PN junction. In addition, each doped region 120p and two adjacent doped regions 120n form a back-to-back diode 22, for example, each doped region 120p forms the first PN junction and the second PN junction of the back-to-back diode 22 with the interface of two adjacent doped regions 120n. In an embodiment of the electrostatic discharge protection structure ESD_P1, doped regions 120n and 120p are arranged alternately to form a diode string (hereinafter collectively referred to as diode string 20_1) having two back-to-back diodes 22 connected in series.

[0024] It is important to note that in the diode string 20_1 of the electrostatic discharge protection structure ESD_P1, the number of back-to-back diodes 22 is determined by the breakdown voltage (e.g., breakdown voltage) of the gate oxide layer of the vertical power transistor 10. For example, the higher the breakdown voltage of the gate oxide layer, the more back-to-back diodes 22 there will be in the diode string 20_1. That is, the number of doped regions 120n and doped regions 120p will increase. Furthermore, by forming the diode string 20_1 within the trench structure 110, a separate electrostatic discharge protection circuit or structure is not required, thereby reducing manufacturing costs.

[0025] The first partial semiconductor layer 120_1 overlaps with the metal wire 210a and is completely covered by the metal wire 210a. The second partial semiconductor layer 120_2 partially overlaps with the metal wire 210a. The second partial semiconductor layer 120_2 and the third partial semiconductor layer 120_3 partially overlap with the metal wire 220a, and the metal wire 220a is connected to the doped region 120n of the second partial semiconductor layer 120_2 and the third partial semiconductor layer 120_3 via a conductive plug 162. The third partial semiconductor layer 120_3 partially overlaps with the metal wire 210b, and the metal wire 210b is connected to the doped region 120n of the third partial semiconductor layer 120_3 via a conductive plug 161.

[0026] The heavily doped region 112 is located within the bulk-doped region 106. The conductive plug 152 extends along the Z direction and penetrates the interlayer dielectric layer 116, connecting the metal wire 210a to the source-doped region 108 and the heavily doped region 112 in the semiconductor material layer 103. The heavily doped region 112 has a different conductivity type than the bulk-doped region 106, for example, type N. In some embodiments, the doping concentration of the heavily doped region 112 is lower than that of the source-doped region 108. The metal wire 210a is connected to the source terminal S via an interconnect structure 215. In embodiments of the present invention, other metal wires (not shown) and conductive plugs (not shown) that electrically connect the metal wire 210a to the source terminal S are collectively referred to as the interconnect structure 215. For ease of explanation, the metal wire 210a, conductive plug 152, and interconnect structure 215 can be a source connection structure.

[0027] The heavily doped region 132 is located between the second partial semiconductor layer 120_2 and the third partial semiconductor layer 120_3, and surrounds one end of the conductive plug 162. The conductive plug 162 extends along the Z direction, penetrating the interlayer dielectric layer 116 and extending into the semiconductor layer, thereby connecting the metal wire 220a and the semiconductor layer 120. The heavily doped region 132 has the same conductivity type as the semiconductor layer 120, for example, N-type. The metal wire 220a is connected to the gate end G via the interconnect structure 225. In this embodiment of the present invention, the other metal wires (not shown) and the conductive plug (not shown) that electrically connect the metal wire 220a and the gate end G are collectively referred to as the interconnect structure 225. For ease of explanation, the metal wire 220a, the conductive plug 162, and the interconnect structure 225 can be a gate connection structure.

[0028] The heavily doped region 131 is located within the outermost doped region 120n of the third partial semiconductor layer 120_3 and surrounds one end of the conductive plug 161. The conductive plug 161 extends along the Z direction, penetrating the interlayer dielectric layer 116 and extending into the third partial semiconductor layer 120_3, thereby connecting the metal wire 210b to the outermost doped region 120n. The heavily doped region 131 has the same conductivity type as the doped region 120n, for example, type N. The metal wire 210b is connected to the source terminal S and the metal wire 210a via the interconnect structure 215. In this embodiment of the present invention, other metal wires (not shown) and the conductive plug (not shown) that electrically connect the metal wire 210b and the source terminal S are collectively referred to as the interconnect structure 215. In some embodiments, the metal wire 210b is connected to the metal wire 210a via an interconnect structure 215 located in an upper layer (e.g., a conductive plug corresponding to the M2 metal wire). In some embodiments, the metal wire 210b is connected to the metal wire 210a via an interconnect structure 215 located in the same layer (e.g., the M1 metal wire).

[0029] In the X direction, doped regions 120p and 120n have a width W1. In the Y direction, the length L2 of doped region 120p exceeds the length L3 of doped region 120n. In some embodiments, length L2 is approximately 3-4 micrometers (μm), and length L3 is approximately 2 micrometers. The distance from heavily doped regions 131 and 132 to doped region 120p is length L4, respectively. In some embodiments, length L4 is less than or equal to length L3. Lengths L2, L3, and L4 are determined based on the process parameters of the vertical power transistor 10.

[0030] In trench semiconductor power devices, the arrangement of each conductive plug may vary depending on the process or electrical requirements. The material of the conductive plugs may include gold (Au), silver (Ag), copper (Cu), platinum (Pt), palladium (Pd), tungsten (W), titanium (Ti), tantalum (Ta), molybdenum (Mo), or other metals or alloys. In some embodiments, the conductive plugs 161 and 162 have a columnar structure. In some embodiments, the conductive plugs 161 or 162 have approximately the same depth along the Z direction. In some embodiments, the conductive plug 152 has a structure that is wider at the top and narrower at the bottom.

[0031] In each electrostatic discharge protection structure ESD_P1, the first end of the diode string 20_1 (i.e., the doped region 120n adjacent to the second partial semiconductor layer 120_2, or the doped region 120n where the heavily doped region 132 is located) is electrically connected to the gate of the vertical power transistor 10 via a gate resistor Rg, and the second end of the diode string 20_1 (i.e., the doped region 120n away from the second partial semiconductor layer 120_2, or the doped region 120n where the heavily doped region 131 is located) is electrically connected to the source doped region 108 via a source connection structure (e.g., interconnect structure 215). In an embodiment of the trench semiconductor power device 100_1, the gate resistor 30 in Figure 1 is formed by connecting all the gate resistors Rg of the trench structure 110 in parallel, for example, by connecting three gate resistors Rg in parallel. The diode string 20 in Figure 1 is formed by connecting all the diode strings 20_1 of the electrostatic discharge protection structure ESD_P1 in parallel, for example, by connecting three diode strings 20_1 in parallel. In the trench semiconductor power device 100_1, as the number of trench structures 110 increases, the number of electrostatic discharge protection structures ESD_P1 also increases, so that more electrostatic discharge paths can be provided to the vertical power transistor 10, thereby improving the electrostatic discharge protection capability. In conventional semiconductor power devices that require additional area to form the electrostatic discharge protection structure, as the dimensions of the power transistor increase, separate design and layout are required to adjust to the dimensions of the electrostatic discharge protection structure. Therefore, compared to conventional methods that require additional area to form the electrostatic discharge protection structure, the electrostatic discharge protection structure of the embodiment of this disclosure can be installed together with the gate structure to achieve the effect of reducing area and product dimensions, and moreover, as the dimensions of the power transistor 10 increase, the electrostatic discharge protection also increases, and separate design and layout are not required.Furthermore, compared to conventional trench semiconductor power devices with a single trench resistor, the parallel-connected gate resistor Rg can reduce the impedance of the trench resistor, thus preventing a decrease in the switching speed of the vertical power transistor 10 and significantly improving operational efficiency.

[0032] Figure 4 is a top view of a trench semiconductor power device 100_1A based on several embodiments of the present disclosure. Figure 5A is a cross-sectional view of the trench semiconductor power device 100_1A shown in Figure 4 along line A-A', and Figure 5B is a cross-sectional view of the trench semiconductor power device 100_1A shown in Figure 4 along line B-B'. The structural arrangement of the trench semiconductor power device 100_1A in Figure 4 is similar to that of the trench semiconductor power device 100_1 in Figure 2, the difference being that the trench semiconductor power device 100_1A further includes an electrostatic discharge protection structure ESD_P2. For the sake of brevity, only the differences between different embodiments will be described below, and descriptions related to structures or process methods that are identical or similar to those of the embodiments described above will be omitted.

[0033] The electrostatic discharge protection structure ESD_P2 includes a semiconductor layer 310 made of plate-shaped polycrystalline silicon. The semiconductor layer 310 includes a plurality of doped regions 310n and a plurality of doped regions 310p, where the doped regions 310n and 310p have different conductivity types. For example, doped region 310n has the same conductivity type doping as doped region 120n, e.g., N-type, and doped region 310p has the same conductivity type doping as doped region 120p, e.g., P-type. In the electrostatic discharge protection structure ESD_P2, the doped regions 310n and 310p are arranged alternately to form a diode string (hereinafter collectively referred to as diode string 20_2) having back-to-back diodes 22 connected in series. Furthermore, the number of back-to-back diodes 22 in diode string 20_2 is the same as the number of back-to-back diodes 22 in diode string 20_1. In some embodiments, in the X direction, the widths of doped regions 310p and 310n exceed the widths W1 of doped regions 120p and 120n. In the Y direction, doped regions 120p and 310p have the same length L2, and doped regions 120n and 310n have the same length L3.

[0034] The heavily doped region 141 is located in doped region 310n adjacent to the electrostatic discharge protection structure ESD_P1 and surrounds one end of the conductive plug 171. The conductive plug 171 extends along the Z direction, passing through the interlayer dielectric layer 116 to the semiconductor layer 310, thereby connecting to the metal wire 210b. The heavily doped region 142 is located in doped region 310n away from the electrostatic discharge protection structure ESD_P1 and surrounds one end of the conductive plug 172. The conductive plug 172 extends along the Z direction, passing through the interlayer dielectric layer 116, thereby connecting to the metal wire 220b. The metal wire 220b is connected to the gate end G and the metal wire 220a via the interconnect structure 225. The heavily doped regions 141 and 142 have the same conductivity type as the semiconductor layer 120, for example, N-type. To simplify the explanation, the metal wire and conductive plug connected to interconnect structure 215 can be designated as a source connection structure, and the metal wire and conductive plug connected to interconnect structure 225 can be designated as a gate connection structure.

[0035] In the trench semiconductor power device 100_1A, the electrostatic discharge protection structure ESD_P2 is separated from the electrostatic discharge protection structure ESD_P1 and surrounded by the interlayer dielectric layer 116. Furthermore, the semiconductor layer 310 of the electrostatic discharge protection structure ESD_P2 is formed above the semiconductor layer 120 and overlaps with the bulk-doped region 106. Therefore, the depth of the conductive plugs 171 and 172 in the Z direction is less than that of the conductive plugs 161 and 162.

[0036] In the electrostatic discharge protection structure ESD_P2, the first end of the diode string 20_2 (i.e., the doped region 120n away from the electrostatic discharge protection structure ESD_P1, or the doped region 310n where the heavily doped region 142 is located) is electrically connected to the gate resistor Rg via a gate connection structure (e.g., a metal wire 220b, an interconnect structure 225, etc.), and the second end of the diode string 20_2 (i.e., the doped region 120n adjacent to the electrostatic discharge protection structure ESD_P1, or the doped region 310n where the heavily doped region 141 is located) is electrically connected to the source doped region 108 via a source connection structure (e.g., a metal wire 210b, an interconnect structure 215, etc.). In an embodiment of the trench semiconductor power device 100_1A, the diode string 20 in Figure 1 is formed by connecting all the diode strings 20_1 of the electrostatic discharge protection structure ESD_P1 and the diode string 20_2 of the electrostatic discharge protection structure ESD_P2 in parallel, for example, by connecting three diode strings 20_1 and diode string 20_2 in parallel. In the trench semiconductor power device 100_1A, by using the additional electrostatic discharge protection structure ESD_P2, more electrostatic discharge paths can be provided to the vertical power transistor 10, thereby improving the electrostatic discharge protection capability.

[0037] Figure 6 is a top view of a trench semiconductor power device 100_1B based on several embodiments of the present disclosure. Figure 7A is a cross-sectional view of the trench semiconductor power device 100_1B shown in Figure 6 along line A-A', and Figure 7B is a cross-sectional view of the trench semiconductor power device 100_1B shown in Figure 6 along line B-B'. The structural arrangement of the trench semiconductor power device 100_1B in Figure 6 is similar to that of the trench semiconductor power device 100_1A in Figure 4. The difference between the two power devices is that the semiconductor layer 310 of the trench semiconductor power device 100_1B is extended in the direction of the semiconductor layer 120 and connected to the semiconductor layer 120. In other words, the two electrostatic discharge protection structures ESD_P1 and ESD_P2 of the trench semiconductor power device 100_1B are joined together via the extended semiconductor layer 310.

[0038] The cross-sectional view of the trench semiconductor power device 100_1B shown in Figure 7A is similar to that of Figures 3 and 5, so it will not be explained again here. As shown in Figure 7B of the trench semiconductor power device 100_1B, the semiconductor layer 310 forming the electrostatic discharge protection structure ESD_P2 extends toward the electrostatic discharge protection structure ESD_P1 along the Y direction, and connects to the outermost doped region 120n of the third partial semiconductor layer 120_3 which extends along the Z direction. In other words, the semiconductor layer 310 is adjacent to the semiconductor layer 120. Therefore, the conductive plug connecting the second end of the electrostatic discharge protection structure ESD_P1 of the trench semiconductor power device 100_1B does not need to penetrate deeply into the semiconductor layer 120. Furthermore, since the combined semiconductor layer 310 and semiconductor layer 120 share the same gate material (e.g., polycrystalline silicon), the trench semiconductor power device 100_1B can simplify the manufacturing process and reduce costs, compared to the trench semiconductor power device 100_1A, which requires etching all the surface gate material after forming the semiconductor layer 120 and then forming the semiconductor layer 310 again. The second end of the diode string 20_1 in the electrostatic discharge protection structure ESD_P1 is electrically connected to the metal wire 210b via the heavily doped region 143 and the conductive plug 173. The conductivity type of the heavily doped region 143 is the same as that of the heavily doped regions 141 and 142. The conductive plugs 171-173 have the same depth in the Z direction. In some embodiments, the second end of the electrostatic discharge protection structure ESD_P1 shares the same conductive plug 171 or 173 as the first end of the electrostatic discharge protection structure ESD_P2, and, for example, depending on the design needs, only one of the conductive plugs 171 and 173 may be used. In some embodiments, the second end of the electrostatic discharge protection structure ESD_P1 is connected to the first end of the electrostatic discharge protection structure ESD_P2.

[0039] Figure 8 is a top view of a trench semiconductor power device 100_1C based on several embodiments of the present disclosure. Figure 9A is a cross-sectional view of the trench semiconductor power device 100_1C shown in Figure 8 along line A-A', and Figure 9B is a cross-sectional view of the trench semiconductor power device 100_1C shown in Figure 8 along line B-B'. The structural arrangement of the trench semiconductor power device 100_1C in Figure 8 is similar to that of the trench semiconductor power device 100_1A in Figure 4, but the difference between the two power devices is that the electrostatic discharge protection structures ESD_P1 and ESD_P2 of the trench semiconductor power device 100_1C are formed on the same horizontal plane and installed in different trenches that are separated from each other.

[0040] In some embodiments of the trench semiconductor power device 100_1C, the semiconductor layer 310 of the electrostatic discharge protection structure ESD_P2 has the same depth in the Z direction as the semiconductor layer 120 of the electrostatic discharge protection structure ESD_P1. The trench of the electrostatic discharge protection structure ESD_P2 can be formed simultaneously with the trench structure 110, and the insulating layer 115 is simultaneously substrate-formed within the trench of the electrostatic discharge protection structure ESD_P2. The semiconductor layer 310 can be formed in the same steps as the semiconductor layer 120 and is surrounded by the insulating layer 115. The first end of the diode string 20_2 in the electrostatic discharge protection structure ESD_P2 is electrically connected to the metal wire 220b via a heavily doped region 134 and a conductive plug 164, and the second end of the diode string 20_2 is electrically connected to the metal wire 210b via a heavily doped region 133 and a conductive plug 163. The conductivity of the heavily doped regions 133 and 134 is the same as that of the heavily doped regions 131 and 132. Since the heavily doped regions 133 and 134 can be formed in the same steps as the heavily doped regions 131 and 132, they have the same or similar arrangement as the heavily doped regions 131 and 132, and their positions within the semiconductor layer 310 correspond to the positions of the heavily doped regions 131 and 132 within the semiconductor layer 120. The conductive plugs 161 to 164 have the same depth in the Z direction. In this embodiment, since the electrostatic discharge protection structures ESD_P1 and ESD_P2 can be completed using the same or similar manufacturing process steps, manufacturing costs can be reduced.

[0041] Figure 10 is a top view of a trench semiconductor power device 100_2 based on several embodiments of the present disclosure. Figure 11A is a cross-sectional view of the trench semiconductor power device 100_2 shown in Figure 10 along line A-A', and Figure 11B is a cross-sectional view of the trench semiconductor power device 100_2 shown in Figure 10 along line B-B'. The trench semiconductor power device 100_2 is a double trench semiconductor power device. Compared to the trench semiconductor power device 100_1 in Figure 2, the trench semiconductor power device 100_2 further includes a shield structure 111 surrounding the trench structure 110. The width of the metal wires 210a and 210b in the Y direction is greater than that of the metal wire 220a.

[0042] The shield structure 111 is a comb-shaped trench structure, composed of multiple trench structures extending along the Y direction (hereinafter referred to as the first subshield structure 111a) and one trench structure along the X direction (hereinafter referred to as the second subshield structure 111b). Each trench structure 110 is installed between two adjacent first subshield structures 111a, and the second subshield structure 111b is installed in the electrostatic discharge protection structure ESD_P1 adjacent to the trench structure 110, i.e., the second subshield structure 111b is away from the source-doped region 108. The shield structure 111 has a depth D2 within the semiconductor material layer 103, and the depth D2 of the shield structure 111 exceeds the depth D1 of the trench structure 110. The shield structure 111 includes a semiconductor layer 122. The semiconductor layer 122 has a width W2 in the X direction, and the width W2 exceeds the width W1. The semiconductor layer 122 has the same conductivity type doping as the light-doped region 104, for example, N-type doping. In the shield structure 111, the semiconductor layer 122 is surrounded by the insulating layer 115.

[0043] In the trench semiconductor power device 100_2, similar to the trench semiconductor power device 100_1, each trench structure 110 includes one electrostatic discharge protection structure ESD_P1. The electrostatic discharge protection structure ESD_P1 is isolated from the shield structure 111 via light-doped regions 104 and bulk-doped regions 106. In some embodiments, the source-doped region 108 of the trench semiconductor power device 100_2 is formed within the trench semiconductor power device 100_2 and exists only on the side of the conductive plug 152 adjacent to the trench structure 110. Heavy-doped regions 135 and 137 are located within the semiconductor layer 122 and have the same conductivity type doping as the light-doped region 104, e.g., N-type. Conductive plugs 165 and 167 extend along the Z direction and penetrate the interlayer dielectric layer 116, thereby electrically connecting the semiconductor layer 122 to the metal wires 210a and 210b. As mentioned above, the metal wire 210b is connected to the source terminal S and the metal wire 210a via the interconnect structure 215. For ease of explanation, conductive plugs 165 and 167 can be used as the source connection structure.

[0044] In an embodiment of the trench semiconductor power device 100_2, the gate resistor 30 in Figure 1 is formed by connecting all the gate resistors Rg of the trench structure 110 in parallel. The diode string 20 in Figure 1 is formed by connecting all the diode strings 20_1 of the electrostatic discharge protection structure ESD_P1 in parallel. In the trench semiconductor power device 100_2, as the number of trench structures 110 increases, the number of electrostatic discharge protection structures ESD_P1 also increases, so that more electrostatic discharge paths can be provided to the vertical power transistor 10, thereby improving the electrostatic discharge protection capability.

[0045] Figure 12 is a top view of a trench semiconductor power device 100_2A based on several embodiments of the present disclosure. Figure 13A is a cross-sectional view of the trench semiconductor power device 100_2A shown in Figure 12 along line A-A', and Figure 13B is a cross-sectional view of the trench semiconductor power device 100_2A shown in Figure 12 along line B-B'. The trench semiconductor power device 100_2A is a double trench semiconductor power device. The structural arrangement of the trench semiconductor power device 100_2A in Figure 12 is similar to that of the trench semiconductor power device 100_2 in Figure 10, the difference being that the trench semiconductor power device 100_2A further includes an electrostatic discharge protection structure ESD_P2.

[0046] The electrostatic discharge protection structure ESD_P2 includes a semiconductor layer 310 having multiple doped regions 310n and multiple doped regions 310p. In the trench semiconductor power device 100_2A, the electrostatic discharge protection structure ESD_P2 is separated from the electrostatic discharge protection structure ESD_P1 and surrounded by an interlayer dielectric layer 116. The shield structure 111 is installed between the electrostatic discharge protection structure ESD_P2 and the electrostatic discharge protection structure ESD_P1. Furthermore, the semiconductor layer 310 of the electrostatic discharge protection structure ESD_P2 is formed above the semiconductor layer 120 and overlaps with the bulk doped region 106. Therefore, the depth of the conductive plugs 171 and 172 in the Z direction is less than that of the conductive plugs 161 and 162.

[0047] In the electrostatic discharge protection structure ESD_P2, the first end of the diode string 20_2 (i.e., the doped region 120n away from the electrostatic discharge protection structure ESD_P1, or the doped region 310n where the heavily doped region 142 is installed) is electrically connected to the gate end G via a gate connection structure (e.g., a metal wire 220b, an interconnect structure 225, etc.), and the second end of the diode string 20_2 (i.e., the doped region 120n adjacent to the electrostatic discharge protection structure ESD_P1, or the doped region 310n where the heavily doped region 141 is installed) is electrically connected to the source end S via a source connection structure (e.g., a metal wire 210b, an interconnect structure 215, etc.). In an embodiment of the trench semiconductor power device 100_2A, the diode string 20 in Figure 1 is formed by connecting all the diode strings 20_1 of the electrostatic discharge protection structure ESD_P1 and the diode strings 20_2 of the electrostatic discharge protection structure ESD_P2 in parallel. In the trench semiconductor power device 100_2A, the use of an additional electrostatic discharge protection structure ESD_P2 provides more electrostatic discharge paths to the vertical power transistor 10, thereby improving the electrostatic discharge protection capability. The electrostatic discharge protection structure ESD_P2 of the trench semiconductor power device 100_2A is similar to the electrostatic discharge protection structure ESD_P2 of the trench semiconductor power device 100_1A. The difference is that in the trench semiconductor power device 100_2A, the electrostatic discharge protection structure ESD_P2 is mounted on the double trench semiconductor power device 100_2. For detailed structural information, please refer to the explanation in the section on trench semiconductor power device 100_1A, and will not be repeated here.

[0048] In other embodiments, the electrostatic discharge protection structure ESD_P2 of the trench semiconductor power device 100_2A is formed on the same horizontal plane as the electrostatic discharge protection structure ESD_P1 in the Z direction and installed in separate trenches, as shown in Figure 9B.

[0049] Figure 14 is a top view of a trench semiconductor power device 100_2B based on several embodiments of the present disclosure. Figure 15A is a cross-sectional view of the trench semiconductor power device 100_2B shown in Figure 14 along line A-A', and Figure 15B is a cross-sectional view of the trench semiconductor power device 100_2B shown in Figure 14 along line B-B'. The trench semiconductor power device 100_2B is a double trench semiconductor power device. The structural arrangement of the trench semiconductor power device 100_2B in Figure 14 is similar to that of the trench semiconductor power device 100_2A in Figure 12, the difference being that the electrostatic discharge protection structure ESD_P2 and the shield structure 111 of the trench semiconductor power device 100_2B are combined via an extended semiconductor layer 310.

[0050] In the trench semiconductor power device 100_2B, the semiconductor layer 310 forming the electrostatic discharge protection structure ESD_P2 extends along the Y direction toward the shield structure 111, thereby connecting to the semiconductor layer 122 of the second subshield structure 111b which extends along the Z direction; in other words, the semiconductor layer 310 is adjacent to the semiconductor layer 122. The semiconductor layer 122 is electrically connected to the metal wire 210b via the heavily doped region 141 and the conductive plug 171.

[0051] The electrostatic discharge protection structure of this disclosure can be integrated with a gate structure, achieving the effects of reducing manufacturing costs and decreasing product area. In other embodiments, the electrostatic discharge protection structure of this disclosure can be further integrated with a shield electrode, achieving the effect of improving electrostatic discharge protection. Several exemplary embodiments in which the electrostatic discharge protection structure is integrated with a shield electrode are provided below, but the disclosure is not limited thereto.

[0052] Figure 16 is a top view of a trench semiconductor power device 100_2C based on several embodiments of the present disclosure. Figure 17A is a cross-sectional view of the trench semiconductor power device 100_2C shown in Figure 16 along line A-A', Figure 17B is a cross-sectional view of the trench semiconductor power device 100_2C shown in Figure 16 along line B-B', and Figure 17C is a cross-sectional view of the trench semiconductor power device 100_2C shown in Figure 16 along line C-C'. The trench semiconductor power device 100_2C is a double trench semiconductor power device. The structural arrangement of the trench semiconductor power device 100_2C in Figure 16 is similar to that of the trench semiconductor power device 100_2 in Figure 10, the difference being that the shield structure 111 of the trench semiconductor power device 100_2C further includes multiple electrostatic discharge protection structures ESD_P3.

[0053] In the electrostatic discharge protection structure ESD_P3, the semiconductor layer 122 of the first subshield structure 111a is divided into a first partial semiconductor layer 122 that is far from the second subshield structure 111b and a second partial semiconductor layer 122 that is close to the second subshield structure 111b. In other words, the first partial semiconductor layer 122 is close to the source-doped region 108, and the second subshield structure 111b is far from the source-doped region 108. The first partial semiconductor layer 122 is completely covered by a metal wire 210a and is electrically connected to the metal wire 210a via a conductive plug 165. The first partial semiconductor layer 122 has the same conductivity type doping as the light-doped region 104, for example, type N. The second partial semiconductor layer 122 includes a plurality of doped regions 122n and a plurality of doped regions 122p. The doped regions 122n and doped regions 122p have different conductivity types. For example, doped region 122n has the same conductivity type dope as doped region 120n, e.g., N-type, and doped region 122p has the same conductivity type dope as doped region 120p, e.g., P-type. The interface between doped region 122n and doped region 122p can form a PN junction. In addition, each doped region 122p and two adjacent doped regions 122n can form one back-to-back diode (i.e., the back-to-back diode 22 in Figure 1). In the electrostatic discharge protection structure ESD_P3, doped regions 122n and doped regions 122p are arranged alternately to form a diode string (hereinafter collectively referred to as diode string 20_3) having two back-to-back diodes 22 connected in series. The number of back-to-back diodes 22 in diode string 20_3 is the same as the number of back-to-back diodes 22 in diode string 20_1. Each first subshield structure 111a may include one or more electrostatic discharge protection structures ESD_P3 in its semiconductor layer 122.

[0054] In embodiments of the trench semiconductor power device 100_2C, the first subshield structure 111a of the shield structure 111 (i.e., the trench structure extending along the Y direction) includes two electrostatic discharge protection structures ESD_P3, for example, an electrostatic discharge protection structure ESD_P3 installed between metal wires 210b and 220a (hereinafter collectively referred to as electrostatic discharge protection structure ESD_P3a), and an electrostatic discharge protection structure ESD_P3 installed between metal wires 210a and 220a (hereinafter collectively referred to as electrostatic discharge protection structure ESD_P3b). In some embodiments, an electrostatic discharge protection structure ESD_P1 is installed between the two electrostatic discharge protection structures ESD_P3a, and a gate resistor Rg is installed between the two electrostatic discharge protection structures ESD_P3b. In some embodiments, the first subshield structure 111a of the shield structure 111 includes only one electrostatic discharge protection structure ESD_P3, for example, electrostatic discharge protection structure ESD_P3a or ESD_P3b.

[0055] In the electrostatic discharge protection structure ESD_P3a, the first end of the diode string 20_3 (i.e., the doped region 120n adjacent to the first partial semiconductor layer 122, or the doped region 122n where the heavily doped region 136 is installed) is electrically connected to the gate end G via a gate connection structure (e.g., a conductive plug 166, a metal wire 220a, an interconnect structure 225, etc.), and the second end of the diode string 20_3 (i.e., the doped region 120n away from the first partial semiconductor layer 122, or the doped region 122n where the heavily doped region 137a is installed) is electrically connected to the source end S via a source connection structure (e.g., a conductive plug 167a, a metal wire 210b, an interconnect structure 215, etc.). In the electrostatic discharge protection structure ESD_P3b, the first end of the diode string 20_3 (i.e., the doped region 120n away from the first partial semiconductor layer 122, or the doped region 122n where the heavily doped region 136 is installed) is electrically connected to the gate end G via a gate connection structure (e.g., a conductive plug 166, a metal wire 220a, an interconnect structure 225, etc.), and the second end of the diode string 20_3 (i.e., the doped region 120n adjacent to the first partial semiconductor layer 122, or the doped region 122n where the heavily doped region 135a is installed) is electrically connected to the source end S via a source connection structure (e.g., a conductive plug 165a, a metal wire 210a, an interconnect structure 215, etc.). In an embodiment of the trench semiconductor power device 100_2C, the diode string 20 in Figure 1 is formed by connecting all the diode strings 20_1 of the electrostatic discharge protection structure ESD_P1 and all the diode strings 20_3 of the electrostatic discharge protection structure ESD_P3 in parallel, for example, by connecting two diode strings 20_1 and six diode strings 20_3 in parallel. In the trench semiconductor power device 100_2C, increasing the number of electrostatic discharge protection structures ESD_P3 can provide more electrostatic discharge paths to the vertical power transistor 10, thereby improving the electrostatic discharge protection capability.

[0056] Figure 18 is a top view of a trench semiconductor power device 100_2D based on several embodiments of the present disclosure. Figure 19A is a cross-sectional view of the trench semiconductor power device 100_2D shown in Figure 18 along line A-A', Figure 19B is a cross-sectional view of the trench semiconductor power device 100_2D shown in Figure 18 along line B-B', and Figure 19C is a cross-sectional view of the trench semiconductor power device 100_2D shown in Figure 18 along line C-C'. The trench semiconductor power device 100_2D is a double trench semiconductor power device. The structural arrangement of the trench semiconductor power device 100_2D in Figure 18 is similar to that of the trench semiconductor power device 100_2C in Figure 16, the difference between the two power devices being that the trench semiconductor power device 100_2D further includes an electrostatic discharge protection structure ESD_P2.

[0057] In the trench semiconductor power device 100_2D, the electrostatic discharge protection structure ESD_P2 is separated from the electrostatic discharge protection structures ESD_P1 and ESD_P3 and surrounded by the interlayer dielectric layer 116. Furthermore, the second subshield structure 111b of the shield structure 111 (i.e., the trench structure extending along the X direction) is positioned between the electrostatic discharge protection structure ESD_P2 and the electrostatic discharge protection structure ESD_P1 (or ESD_P3a). The semiconductor layer 310 of the electrostatic discharge protection structure ESD_P2 is formed above the semiconductor layer 120 and overlaps with the bulk-doped region 106. Therefore, the depth of the conductive plugs 171 and 172 in the Z direction is less than that of the conductive plugs 161, 162, 165a, 166, 167, and 167a.

[0058] In the electrostatic discharge protection structure ESD_P2, the first end of the diode string 20_2 (i.e., the doped region 120n away from the electrostatic discharge protection structure ESD_P1, or the doped region 310n where the heavily doped region 142 is installed) is electrically connected to the gate end G via a gate connection structure (e.g., a metal wire 220b, an interconnect structure 225, etc.), and the second end of the diode string 20_2 (i.e., the doped region 120n adjacent to the electrostatic discharge protection structure ESD_P1, or the doped region 310n where the heavily doped region 141 is installed) is electrically connected to the source end S via a source connection structure (e.g., a metal wire 210b, an interconnect structure 215, etc.). In an embodiment of the trench semiconductor power device 100_2D, the diode string 20 in Figure 1 is formed by connecting in parallel all diode strings 20_1 of the electrostatic discharge protection structure ESD_P1, all diode strings 20_3 of the electrostatic discharge protection structure ESD_P3, and diode string 20_2 of the electrostatic discharge protection structure ESD_P2. In the trench semiconductor power device 100_2D, the use of an additional electrostatic discharge protection structure ESD_P2 can provide more electrostatic discharge paths to the vertical power transistor 10, thereby improving the electrostatic discharge protection capability.

[0059] In some embodiments, the electrostatic discharge protection structure ESD_P2 of the trench semiconductor power device 100_2D is formed on the same horizontal plane as the electrostatic discharge protection structure ESD_P1 in the Z direction and is installed in separate trenches that are separated from each other. In some embodiments, the electrostatic discharge protection structure ESD_P2 of the trench semiconductor power device 100_2D is formed on the same horizontal plane as the electrostatic discharge protection structure ESD_P3 in the Z direction and is installed in separate trenches that are separated from each other.

[0060] Figure 20 is a top view of a trench semiconductor power device 100_2E based on several embodiments of the present disclosure. Figure 21A is a cross-sectional view of the trench semiconductor power device 100_2E shown in Figure 20 along line A-A', Figure 21B is a cross-sectional view of the trench semiconductor power device 100_2E shown in Figure 20 along line B-B', and Figure 21C is a cross-sectional view of the trench semiconductor power device 100_2E shown in Figure 20 along line C-C'. The trench semiconductor power device 100_2E is a double trench semiconductor power device. The structural arrangement of the trench semiconductor power device 100_2E in Figure 20 is similar to that of the trench semiconductor power device 100_2D in Figure 18, the difference being that the electrostatic discharge protection structure ESD_P2 and the shield structure 111 of the trench semiconductor power device 100_2B are combined via an extended semiconductor layer 310.

[0061] In the trench semiconductor power device 100_2E, the semiconductor layer 310 forming the electrostatic discharge protection structure ESD_P2 extends toward the shield structure 111 along the Y direction, connecting to the semiconductor layer 122 extending along the Z direction within the second subshield structure 111b; that is, the semiconductor layer 310 is adjacent to the semiconductor layer 122. The semiconductor layer 122 of the second subshield structure 111b is electrically connected to the metal wire 210b via the heavily doped region 141 and the conductive plug 171.

[0062] The above text provides several embodiments in which the electrostatic discharge protection structure and the gate structure and / or shield electrode structure are harmonized, meaning that the disclosure can be broadly applied to various types of trench semiconductor power devices. Further below, exemplary embodiments are provided in which the electrostatic discharge protection structure of the disclosure is harmonized with the gate structure and / or shield electrode structure of a split-gate semiconductor device, but the disclosure is not limited thereto.

[0063] Figure 22 is a top view of a trench semiconductor power device 100_3 based on several embodiments of the present disclosure. Figure 23A is a cross-sectional view of the trench semiconductor power device 100_3 shown in Figure 22 along line A-A', and Figure 23B is a cross-sectional view of the trench semiconductor power device 100_3 shown in Figure 22 along line B-B'. The trench semiconductor power device 100_3 is a trench split gate (SGT) semiconductor device. Compared to the trench structure 110 of the trench semiconductor power device 100_1 in Figure 2, the trench structure 110a of the trench semiconductor power device 100_3 further includes a semiconductor layer 124. Also, compared to the trench semiconductor power device 100_1 in Figure 2, the trench semiconductor power device 100_3 further includes a shield structure 113. The widths of the metal wires 210a and 210b in the Y direction are greater than that of the metal wire 220a, with the metal wire 210b having the largest width.

[0064] In embodiments of the trench semiconductor power device 100_3, the trench structure 110a has a depth D3 within the semiconductor material layer 103, and the trench structure 110a is extended along the Y direction. In some embodiments, the depth D3 of the trench structure 110a exceeds the depth D1 of the trench structure 110. The shield structure 113 has a depth D4 within the semiconductor material layer 103, and the shield structure 113 is extended along the X direction. In some embodiments, the depth D3 is the same as the depth D4. In some embodiments, the depth D3 is different from the depth D4. The shield structure 113 includes a semiconductor layer 126. The semiconductor layer 126 has the same conductivity type doping as the light-doped region 104, for example, N-type. In some embodiments, the doping concentration of the semiconductor layer 126 is higher than the doping concentration of the light-doped region 104. In the shield structure 113, the semiconductor layer 126 is surrounded by an insulating layer 115. The shield structure 113 is separated from the trench structure 110a via a light-doped region 104 and a bulk-doped region 106.

[0065] In the trench structure 110a, the semiconductor layer 124 is separated from the semiconductor layer 120 and surrounded by the insulating layer 115. The semiconductor layer 124 has the same conductivity type doping as the light-doped region 104, for example, N-type. In some embodiments, the doping concentration of the semiconductor layer 124 is higher than that of the light-doped region 104. The semiconductor layer 124 is divided into two parts 124_1 and 124_2 (hereinafter referred to as the first partial semiconductor layer 124_1 and the second partial semiconductor layer 124_2, respectively). The first partial semiconductor layer 124_1 is stretched along the Y direction and is located between the semiconductor layer 120 and the light-doped region 104. The second partial semiconductor layer 124_2 is stretched along the Z direction and is located between the electrostatic discharge protection structure ESD_P1 and the bulk-doped region 106 (or shield structure 113). In the Z direction, the first partial semiconductor layer 124_1 overlaps with the semiconductor layer 120, while the second partial semiconductor layer 124_2 does not overlap with the semiconductor layer 120. Also, in the Z direction, the thickness of the first partial semiconductor layer 124_1 and the thickness of the semiconductor layer 120 are less than the depth D3.

[0066] The heavily doped region 151 is located within the second partial semiconductor layer 124_2 and surrounds one end of the conductive plug 181. The conductive plug 181 extends along the Z direction and penetrates the interlayer dielectric layer 116, thereby connecting the metal wire 210b to the second partial semiconductor layer 124_2. The heavily doped region 139 is located within the semiconductor layer 126 and surrounds one end of the conductive plug 169. The conductive plug 169 extends along the Z direction and penetrates the interlayer dielectric layer 116, thereby connecting the metal wire 210b to the semiconductor layer 126. The heavily doped regions 151 and 139 have the same conductivity type as the light-doped region 104, for example, N-type. In the trench semiconductor power device 100_3, the semiconductor layer 124 and the semiconductor layer 126 are connected to the source end S via a source connection structure (e.g., metal wire 210b, interconnect structure 215, etc.).

[0067] Figure 24 is a top view of a trench semiconductor power device 100_3A based on several embodiments of the present disclosure. Figure 25A is a cross-sectional view of the trench semiconductor power device 100_3A shown in Figure 24 along line A-A', and Figure 25B is a cross-sectional view of the trench semiconductor power device 100_3A shown in Figure 24 along line B-B'. The trench semiconductor power device 100_3A is a trench split-gate semiconductor power device. The structural arrangement of the trench semiconductor power device 100_3A in Figure 24 is similar to that of the trench semiconductor power device 100_3 in Figure 22, the difference between the two power devices being that the trench semiconductor power device 100_3A further includes an electrostatic discharge protection structure ESD_P4.

[0068] The electrostatic discharge protection structure ESD_P4 is formed in the second partial semiconductor layer 124_2 of each trench structure 110a. The electrostatic discharge protection structure ESD_P4 includes a plurality of doped regions 124n and a plurality of doped regions 124p. The doped regions 124n and doped regions 124p have different conductivity types. For example, doped region 124n has the same conductivity type doping as doped region 120n, e.g., N-type, and doped region 124p has the same conductivity type doping as doped region 120p, e.g., P-type. The interface between doped region 124n and doped region 124p can form a PN junction. In addition, each doped region 124p and two adjacent doped regions 124n can form a back-to-back diode 22. In the electrostatic discharge protection structure ESD_P4, doped regions 124n and 124p are arranged alternately to form a diode string (hereinafter collectively referred to as diode string 20_4) having two back-to-back diodes 22 connected in series. Furthermore, the number of back-to-back diodes 22 in diode string 20_4 is the same as the number of back-to-back diodes 22 in diode string 20_1.

[0069] In some embodiments, doped regions 124n and 120n have the same length L3 in the Y direction, and doped regions 124p and 120p have the same length L2 in the Y direction. In the Z direction, the depth of doped regions 124n and 124p exceeds the depth of doped regions 120n and 120p.

[0070] The heavily doped region 151 is located within the doped region 124n at the foremost end of the second partial semiconductor layer 124_2 (for example, the portion adjacent to the first partial semiconductor layer 124_1) and surrounds one end of the conductive plug 181. The conductive plug 181 extends along the Z direction and penetrates the interlayer dielectric layer 116, thereby connecting the metal wire 210b to the foremost doped region 124n. The heavily doped region 154 is located within the doped region 124n at the very end of the second partial semiconductor layer 124_2 (for example, the portion away from the first partial semiconductor layer 124_1) and surrounds one end of the conductive plug 182. The conductive plug 182 extends along the Z direction and penetrates the interlayer dielectric layer 116, thereby connecting the metal wire 220b to the very end doped region 124n. The heavily doped regions 151 and 154 have the same conductivity type as the doped region 120n, for example, type N. The metal wire 210b is connected to the source terminal S and the metal wire 210a via the interconnect structure 215.

[0071] In electrostatic discharge protection structure ESD_P4, the first end of diode string 20_4 (i.e., the doped region 124n away from electrostatic discharge protection structure ESD_P1, or the doped region 124n where the heavily doped region 154 is installed) is electrically connected to the gate end G via a gate connection structure (e.g., metal wire 220b, interconnect structure 225, etc.), and the second end of diode string 20_4 (i.e., the doped region 124n adjacent to electrostatic discharge protection structure ESD_P1, or the doped region 124n where the heavily doped region 151 is installed) is electrically connected to the source end S via a source connection structure (e.g., metal wire 210b, interconnect structure 215, etc.). Electrostatic discharge protection structures ESD_P1 and ESD_P4 partially overlap with metal wire 210b. The metal wire 210b is connected to the doped region 120n of the electrostatic discharge protection structure ESD_P1 via the conductive plug 161 and to the doped region 124n of the electrostatic discharge protection structure ESD_P4 via the conductive plug 181. In each trench structure 110a, the electrostatic discharge protection structure ESD_P1 can be connected in parallel to the electrostatic discharge protection structure ESD_P4 via a source connection structure (e.g., the associated metal wire and conductive plug connected to the interconnect structure 215) and a gate connection structure (e.g., the associated metal wire and conductive plug connected to the interconnect structure 225). In other words, in embodiments of the trench semiconductor power device 100_3A, the diode string 20 in Figure 1 consists of all the diode strings 20_1 of the electrostatic discharge protection structure ESD_P1 and all the diode strings 20_4 of the electrostatic discharge protection structure ESD_P4 connected in parallel. In some embodiments, the number of electrostatic discharge protection structures ESD_P1 is the same as the number of electrostatic discharge protection structures ESD_P4. In the trench semiconductor power device 100_3A, the use of an additional electrostatic discharge protection structure ESD_P4 provides more electrostatic discharge paths to the vertical power transistor 10, thereby improving the electrostatic discharge protection capability.

[0072] Figure 26 is a top view of a trench semiconductor power device 100_3B based on several embodiments of the present disclosure. Figure 27A is a cross-sectional view of the trench semiconductor power device 100_3B shown in Figure 26 along line A-A', and Figure 27B is a cross-sectional view of the trench semiconductor power device 100_3B shown in Figure 26 along line B-B'. The trench semiconductor power device 100_3B is a trench split-gate semiconductor power device. The structural arrangement of the trench semiconductor power device 100_3B in Figure 26 is similar to that of the trench semiconductor power device 100_3A in Figure 24, the difference between the two power devices being that the trench semiconductor power device 100_3B further includes an electrostatic discharge protection structure ESD_P2.

[0073] In the trench semiconductor power device 100_3B, the electrostatic discharge protection structure ESD_P2 is separated from the electrostatic discharge protection structures ESD_P1 and ESD_P4 and is surrounded by the interlayer dielectric layer 116. The shield structure 113 is installed between the electrostatic discharge protection structure ESD_P2 and the electrostatic discharge protection structure ESD_P4. Furthermore, the electrostatic discharge protection structure ESD_P2 is formed above the semiconductor layer 120 and overlaps with the bulk-doped region 106.

[0074] In the electrostatic discharge protection structure ESD_P2, the first end of the diode string 20_2 (i.e., the doped region 120n adjacent to the electrostatic discharge protection structure ESD_P1, or the doped region 310n where the heavy doped region 141 is installed) is electrically connected to the gate end G via a gate connection structure (e.g., a conductive plug 171, a metal wire 220b, an interconnect structure 225, etc.), and the second end of the diode string 20_2 (i.e., the doped region 120n away from the electrostatic discharge protection structure ESD_P1, or the doped region 310n where the heavy doped region 142 is installed) is electrically connected to the source end S via a source connection structure (e.g., a conductive plug 172, a metal wire 210c, an interconnect structure 215, etc.). In an embodiment of the trench semiconductor power device 100_3A, the diode string 20 in Figure 1 is formed by connecting in parallel all diode strings 20_1 of the electrostatic discharge protection structure ESD_P1, all diode strings 20_4 of the electrostatic discharge protection structure ESD_P4, and diode string 20_2 of the electrostatic discharge protection structure ESD_P2. In the trench semiconductor power device 100_3B, by using an additional electrostatic discharge protection structure ESD_P2, more electrostatic discharge paths can be provided to the vertical power transistor 10, thereby improving the electrostatic discharge protection capability.

[0075] In some embodiments, the electrostatic discharge protection structure ESD_P2 of the trench semiconductor power device 100_3B is formed on the same horizontal plane as the electrostatic discharge protection structure ESD_P1 or ESD_P4 in the Z direction and is installed in separate trenches that are separated from each other.

[0076] Figure 28 is a top view of a trench semiconductor power device 100_3C based on several embodiments of the present disclosure. Figure 29A is a cross-sectional view of the trench semiconductor power device 100_3C shown in Figure 28 along line A-A', and Figure 29B is a cross-sectional view of the trench semiconductor power device 100_3C shown in Figure 28 along line B-B'. The trench semiconductor power device 100_3C is a trench split-gate semiconductor power device. The structural arrangement of the trench semiconductor power device 100_3C in Figure 28 is similar to that of the trench semiconductor power device 100_3B in Figure 26, the difference being that the electrostatic discharge protection structure ESD_P2 and the shield structure 113 of the trench semiconductor power device 100_3C are combined via an extended semiconductor layer 310.

[0077] In the trench semiconductor power device 100_3C, the semiconductor layer 310 forming the electrostatic discharge protection structure ESD_P2 extends along the Y direction toward the shield structure 113, thereby connecting to the semiconductor layer 126 that extends along the Z direction; in other words, the semiconductor layer 310 is adjacent to the semiconductor layer 126. The semiconductor layer 126 is electrically connected to the metal wire 220b via the heavily doped region 141 and the conductive plug 171.

[0078] In this text, for ease of description, spatial terms such as “below,” “bottom,” “lower,” “upper,” “upper,” “left,” and “right” are used to distinguish one assembly or feature shown in the drawings from one or more other assemblies or features. In addition to the directions indicated in the drawings, spatial terms may also cover different directions when the device is in use or operating. The orientation of the device (90-degree rotation, or other orientations) can be determined in other ways, and similarly, spatial terms used in this text can be interpreted in corresponding ways. When it is written that an assembly is “connected” or “linked” to another assembly, it should be understood that it may be directly connected or linked to the other assembly, or there may be an intermediate assembly.

[0079] As used in this text, the terms “approximately,” “nearly,” “basically,” and “about” are used to describe and interpret small changes. When used in connection with an event or situation, the terms may refer to instances where the event or situation has definitely occurred, and instances where the event or situation is about to occur. When used in this text in relation to a given value or range, the term “about” means that overall it is within ±10%, ±5%, ±1%, or ±0.5% of the given value or range. In this text, a range may be expressed from one endpoint to another, or between two endpoints. All ranges disclosed in this text include endpoints unless otherwise specified. The term “nearly coplane” may refer to a difference of a few micrometers (μm) between the positions of two surfaces located along the same plane, for example, a difference of 10 μm, 5 μm, 1 μm, or 0.5 μm between the positions located along the same plane. When numerical values ​​or characteristics are considered "approximately" identical, the term may refer to values ​​within ±10%, ±5%, ±1%, or ±0.5% of the mean of the aforementioned values.

[0080] The foregoing outlines the characteristics of some embodiments and the details of this disclosure. The embodiments described herein can be readily used as a basis for designing or modifying other processes and structures to accomplish the same or similar purposes and / or to realize the same or similar advantages of the embodiments described herein. Such equivalent structures can be modified, substituted and altered in various ways, without departing from the spirit and scope of this disclosure. [Explanation of symbols]

[0081] 100 Trench Semiconductor Power Devices G Gate End S Source end D drain end 10 Power Transistors 30, Rg gate resistor 20 diode strings 22 Back-to-back diodes 102 circuit boards 103 Semiconductor material layer 104 Light-doped area 106 Bulk Dope Region 108 Source-Doped Area 110,110a Trench structure 111,113 Shield structure 111a First subshield structure 111b Second Subshield Structure 115 Insulating layer 116 Interlayer dielectric layer 120, 122, 124, 126, 310 Semiconductor layers 120n, 120p, 122n, 122p, 124n, 124p, 310n, 310p doped regions 112,131,132,133,134,135, 135a,136,137,137a,139,141,142,143,151,154 Heavy dope area 152,161,162,163,164,165,165a,166,167,167a,169,171,172,173,181,182 Conductive plugs 210a,210b,210c,220a,220b metal wire 215,225 Interconnect Structure W1,2 width L1,2,3,4 Length D1,2,3,4 Depth ESD_P Electrostatic Discharge Protection Structure

Claims

1. In trench semiconductor power devices, A substrate having a first conductivity type, A light-doped region located on the substrate and having the first conductivity type, A bulk-doped region located within the light-doped region and separated from the substrate, having a second conductivity type, and a source-doped region located within the bulk-doped region and separated from the substrate, having a first conductivity type, The trench structure includes a first semiconductor layer having a first depth in a first direction extending toward the substrate from the source-doped region and extending along a second direction perpendicular to the first direction, wherein the first semiconductor layer is A first portion used as a gate electrode having the first conductivity type, A second portion extending along the second direction and separated from the source doped region, comprising a plurality of first doped regions having the first conductivity type and a plurality of second doped regions having the second conductivity type, wherein the plurality of first doped regions and the plurality of second doped regions are alternately arranged in the second direction to form a first diode string having one or more back-to-back diodes, The first end of the first diode string is electrically connected to the gate electrode, and the second end of the first diode string is electrically connected to the source-doped region via the first connection structure. Trench semiconductor power devices.

2. The trench semiconductor power device according to claim 1, characterized in that each of the second doped regions forms a first PN junction and a second PN junction of each back-to-back diode at the interface with two adjacent first doped regions.

3. The first semiconductor layer further Extending along the second direction, away from the source-doped region, and positioned between the first and second portions, includes a third portion having the first conductivity type, The first end of the first diode string is electrically connected to the second connection structure, and the third portion of the first semiconductor layer forms a gate resistor, characterized in that The trench semiconductor power device according to claim 1.

4. The trench semiconductor power device according to claim 1, characterized in that the first semiconductor layer comprises polycrystalline silicon, silicon carbide, gallium nitride, gallium oxide, or a diamond-based material.

5. The trench structure further, The invention is characterized by including an insulating layer that surrounds the first semiconductor layer and separates the first semiconductor layer from the light-doped region, the bulk-doped region, and the source-doped region. The trench semiconductor power device according to claim 1.

6. An electrostatic discharge protection structure located above or in the same horizontal plane as the first semiconductor layer, The electrostatic discharge protection structure further includes a second semiconductor layer comprising a plurality of third doped regions having the first conductivity type and a plurality of fourth doped regions having the second conductivity type, wherein the plurality of third doped regions and the plurality of fourth doped regions are alternately arranged to form a second diode string having one or more back-to-back diodes, The first end of the second diode string is electrically connected to the source-doped region via the first connection structure, and the second end of the second diode string is electrically connected to the first end of the first diode string via the second connection structure. The trench semiconductor power device according to claim 1.

7. The trench semiconductor power device according to claim 6, characterized in that the first semiconductor layer is isolated from the electrostatic discharge protection structure.

8. The trench semiconductor power device according to claim 6, characterized in that the electrostatic discharge protection structure is located above the first semiconductor layer, and the second portion of the first semiconductor layer is adjacent to the second semiconductor layer of the electrostatic discharge protection structure.

9. A shield structure comprising a second semiconductor layer, which surrounds the trench structure and is separated from the first diode string via the light-doped region and the bulk-doped region, wherein the second semiconductor layer is The shield structure further includes a fourth portion having the first conductivity type and connected to the source-doped region by the first connection structure, In the first direction, the depth of the shield structure is characterized in that it exceeds the first depth. The trench semiconductor power device according to claim 1.

10. The second semiconductor layer further A fifth portion, separate from the source-doped region, includes a plurality of third-doped regions having the first conductivity type and a plurality of fourth-doped regions having the second conductivity type, wherein the plurality of third-doped regions and the plurality of fourth-doped regions are arranged alternately to form one or more second diode strings. Each of the second diode strings comprises one or more back-to-back diodes, the first end of each of the second diode strings is connected to the first end of the first diode string via a second connection structure, and the second end is connected to the source-doped region via the first connection structure. The trench semiconductor power device according to claim 9.

11. An electrostatic discharge protection structure located above or in the same horizontal plane as the first semiconductor layer, The electrostatic discharge protection structure further includes a third semiconductor layer comprising a plurality of fifth doped regions having the first conductivity type and a plurality of sixth doped regions having the second conductivity type, wherein the plurality of fifth doped regions and the plurality of sixth doped regions are alternately arranged to form a third diode string having one or more back-to-back diodes, The first end of the third diode string is electrically connected to the first end of the first diode string, and the second end is electrically connected to the source-doped region. The trench semiconductor power device according to claim 9 or 10.

12. The trench semiconductor power device according to claim 11, characterized in that the shield structure is installed between the electrostatic discharge protection structure and the first diode string and is separated from the electrostatic discharge protection structure.

13. The trench semiconductor power device according to claim 11, characterized in that the shield structure is installed between the electrostatic discharge protection structure and the first diode string, and the second semiconductor layer of the shield structure is adjacent to the third semiconductor layer of the electrostatic discharge protection structure.

14. The shield structure further includes a second semiconductor layer having the first conductivity type, The trench structure further, A third semiconductor layer located between the first semiconductor layer and the light-doped region, wherein the third semiconductor layer is A fourth portion having the first conductivity type and overlapping with the first semiconductor layer in the first direction, The third semiconductor layer includes a fifth portion adjacent to the first diode string and not overlapping with the first semiconductor layer in the first direction, The first semiconductor layer is separated from the third semiconductor layer via an insulating layer. The shield structure is characterized in that it is adjacent to the fifth portion of the third semiconductor layer and is separated from the trench structure via the light-doped region and the bulk-doped region. The trench semiconductor power device according to claim 1.

15. The trench semiconductor power device according to claim 14, characterized in that, in the first direction, the thickness of the fourth portion of the third semiconductor layer and the thickness of the first semiconductor layer are less than the first depth.

16. The trench semiconductor power device according to claim 14, characterized in that the fifth portion of the third semiconductor layer has the first conductivity type, and the third semiconductor layer and the second semiconductor layer are electrically connected to the source-doped region via the first connection structure.

17. The fifth portion of the third semiconductor layer includes a plurality of third doped regions having the first conductivity type and a plurality of fourth doped regions having the second conductivity type, wherein the plurality of third doped regions and the plurality of fourth doped regions are arranged alternately to form a second diode string having one or more back-to-back diodes, the first end of the second diode string is electrically connected to the first end of the first diode string via a second connection structure, and the second end of the second diode string is electrically connected to the source doped region via the first connection structure. The trench semiconductor power device according to claim 14.

18. An electrostatic discharge protection structure located above or in the same horizontal plane as the first semiconductor layer, The electrostatic discharge protection structure further includes a fourth semiconductor layer comprising a plurality of fifth doped regions having the first conductivity type and a plurality of sixth doped regions having the second conductivity type, wherein the plurality of fifth doped regions and the plurality of sixth doped regions are alternately arranged to form a third diode string having one or more back-to-back diodes, The first end of the third diode string is connected to the first diode string via the second connection structure, and the second end is connected to the source-doped region via the first connection structure, characterized in that The trench semiconductor power device according to claim 17.

19. The trench semiconductor power device according to claim 18, characterized in that the shield structure is installed between the electrostatic discharge protection structure and the trench structure and is separated from the electrostatic discharge protection structure.

20. The trench semiconductor power device according to claim 18, characterized in that the shield structure is installed between the electrostatic discharge protection structure and the trench structure, and the second semiconductor layer of the shield structure is adjacent to the fourth semiconductor layer of the electrostatic discharge protection structure.

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