Strain-enhanced SiC power semiconductor device and manufacturing method

Abstract

A SiC transistor device is disclosed that includes a SiC semiconductor substrate having a top surface and a bottom surface, a SiC epitaxial layer formed on the top surface of the SiC semiconductor substrate and having a top surface, a source structure formed on the top surface of the SiC epitaxial layer and having a top surface, a source contact structure electrically coupled to the top surface of the source structure, a gate structure including a gate oxide, a metal gate, and a gate insulator, a first backside metal contact on the bottom surface of the SiC semiconductor substrate, a stress-inducing layer on the first backside metal contact, and a second backside metal contact on the stress-inducing layer.

Description

[Technical Field]

[0001] Technical field This disclosure relates to SiC (silicon carbide) power semiconductor devices and process flows for manufacturing SiC power semiconductor devices. The manufacturing method utilizes the improvement of reverse channel mobility due to stress. [Background technology]

[0002] Technical background This section provides background information relating to this disclosure, which is not necessarily prior art.

[0003] 4H-SiC is the preferred polytype for power electronics, i.e., SiC power devices such as metal-oxide-semiconductor field-effect transistors (MOSFETs) or insulated-gate bipolar transistors (IGBTs), due to advances in 4H-SiC growth technology and attractive electronic properties such as a larger bandgap and higher carrier mobility compared to other available wafer-scale polytypes such as 6H-SiC or 3C-SiC. While these SiC power devices are already commercially available, there is considerable room for improvement, particularly with respect to inversion channel mobility, to further reduce on-resistance. In the high voltage class above 3kV, the drift layer resistance R drift R on While R is more dominant, reducing the latter is essential to significantly reduce on-state power loss and switching loss, for example, in electric and hybrid electric vehicles (EVs / HEVs), solar power inverters, and the more commercially important voltage classes (≤1.7kV) used in power supplies. onThe inversion channel mobility remains significantly higher than ideal, as indicated by the distance of devices from the SiC limit line in Figure 1 for 900V to 3.3kV. For example, high-voltage devices such as 10kV or 15kV are much closer to the SiC limit than low-voltage devices. In this regard, low inversion channel mobility is one of the main challenges that can have a significant impact on the cost of devices and therefore on the widespread adoption of SiC power devices. The improvement of inversion channel mobility using improved gate stacks and SiC / oxide interfaces has not been very successful, but is known as one of the most important milestones in the development and commercialization of SiC power MOSFETs. The introduction of nitric oxide (NO) after oxidation of 6H-SiC in the late 1990s, and its application to 4H-SiC MOSFETs in 2001, showed that the introduction of N near the interface by NO annealing reduces the interface defect density D it This reduction in voltage enabled a significant improvement in inversion layer electron mobility. However, particularly in order to expand SiC power devices, especially SiC MOSFETs, into the low / medium voltage market, there is a strong demand for devices with higher mobility than power devices using NO annealing technology.

[0004] Further advantages due to higher channel mobility include: (i) The gate can be driven at a lower voltage, resulting in a smaller oxide electric field, improved threshold stability and long-term reliability of the oxide, (ii) Aggressive scaling of the transistor channel length is not required to reduce channel resistance, and therefore short-channel effects can be avoided.

[0005] U.S. Patent No. 6,563,152 discloses a method for forming a strain layer on the underside of the channel of a MOS transistor to generate mechanical stress within the channel and increase the mobility of carriers within the channel, and apparatus manufactured by such a method. Embodiments of the disclosed device include a transistor having a strain layer formed on the underside of the channel to generate mechanical stress within the channel and increase the mobility of carriers within the channel. Embodiments of the disclosed device can generate a larger amount of mechanical stress within the channel and therefore a greater improvement in the mobility of carriers within the channel compared to other methods of introducing strain into the channel, such as forming a strain layer on the top surface of the channel. The strain layer disclosed in U.S. Patent No. 6,563,152 is embedded in the substrate and requires several removal steps to construct.

[0006] U.S. Patent Application Publication 2009 / 0289284 discloses a method and semiconductor device for increasing tensile stress in the channel of an nFET device by forming a highly shrinkable stress silicon nitride layer for use as a contact etch stop layer (CESL) or capping layer in stress-controlled technology (SMT) to enhance carrier mobility. A spin-on polysilazane dielectric material is coated onto a semiconductor substrate and fired to form a film layer. By curing the film layer and removing hydrogen from the film, shrinkage of the film occurs during recrystallization to silicon nitride. The resulting silicon nitride stress layer introduces a high level of tensile stress into the transistor channel region.

[0007] U.S. Patent Application Publication No. 2017 / 194438 describes a silicon carbide semiconductor device comprising a silicon carbide semiconductor structure, an insulated gate structure including a gate insulating film in contact with the silicon carbide semiconductor structure and a gate electrode formed on the gate insulating film, an interlayer insulating film covering the insulated gate structure, a metal layer provided on the interlayer insulating film for absorbing or blocking hydrogen, and a main electrode provided on the metal layer and electrically connected to the silicon carbide semiconductor structure.

[0008] European Patent Application Publication No. 3 024 017 discloses a technique for ensuring gate insulator reliability to the same level as that of Si power MOSFETs in semiconductor devices using semiconductor materials with a larger bandgap than silicon, such as SiC power MOSFETs. To achieve this objective, in a SiC power MOSFET, the gate electrode is formed of a polycrystalline silicon film PF1 with a thickness of 200 nm or less, which is formed in contact with the gate insulator, and a polycrystalline silicon film PF2 of any thickness, which is formed in contact with the polycrystalline silicon film PF1.

[0009] From European Patent Application Publication No. 2 477 213, a method for manufacturing a semiconductor device is known, comprising the steps of forming a semiconductor layer made of SiC on a SiC substrate, forming a film on the semiconductor layer, and forming grooves in the film. A semiconductor device including a chip having an interlayer insulating film includes grooves formed in the interlayer insulating film so as to span the chip. [Overview of the project] [Means for solving the problem]

[0010] overview This section provides a general overview of this disclosure and is not a comprehensive disclosure of its entire scope or all of its features.

[0011] This disclosure provides a SiC transistor device comprising: a SiC semiconductor substrate having an upper surface and a lower surface; a SiC epitaxial layer formed on the upper surface of the SiC semiconductor substrate and having an upper surface and a lower surface; a source structure formed on the upper surface of the SiC epitaxial layer and having an upper surface and a lower surface; a source contact structure electrically coupled to the upper surface of the source structure; a gate structure including a gate oxide, a metal gate, and a gate insulator; a first back-side metal contact on the lower surface of the SiC semiconductor substrate; a stress-inducing layer on the first back-side metal contact; and a second back-side metal contact on the stress-inducing layer.

[0012] According to another aspect of this disclosure, the second back metal contact of the SiC transistor device comprises at least one of titanium (Ti), nickel (Ni), or silver (Ag).

[0013] According to another aspect of the present disclosure, the SiC transistor device comprises a second stress-inducing layer on the gate structure.

[0014] According to another aspect of the present disclosure, the SiC transistor device comprises a structured, electrically insulating second stress-inducing layer on the upper surface of the SiC epitaxial layer.

[0015] Furthermore, this disclosure provides a SiC transistor device comprising: a SiC semiconductor substrate having an upper and lower surface; a SiC epitaxial layer formed on the upper surface of the SiC semiconductor substrate and having an upper and lower surface; a source structure formed on the upper surface of the SiC epitaxial layer and having an upper and lower surface; a source contact structure electrically coupled to the upper surface of the source structure; a gate structure including a gate oxide, a metal gate, and a gate insulator; a first contact layer electrically in contact with the source contact structure; a second contact layer electrically in contact with the metal gate; a first backside metal contact on the lower surface of the SiC semiconductor substrate; and a stress-inducing layer on the gate structure, wherein the stress-inducing layer induces tensile or compressive stress in the range of 500 MPa to 2000 MPa depending on the manufacturing process.

[0016] Furthermore, the present disclosure provides a SiC transistor device comprising a SiC semiconductor substrate having an upper surface and a lower surface, a SiC epitaxial layer formed on the upper surface of the SiC semiconductor substrate and having an upper surface and a lower surface, a source structure formed on the upper surface of the SiC epitaxial layer and having an upper surface and a lower surface, a structured electrically insulating stress-inducing layer on the upper surface of the SiC epitaxial layer, a source contact structure electrically coupled to the upper surface of the source structure through the structured stress-inducing layer, a gate structure including a metal gate, a first contact layer electrically contacting the source contact structure, a second contact layer electrically contacting the metal gate, and a first backside metal contact on the lower surface of the SiC semiconductor substrate, wherein the stress-inducing layer induces a tensile or compressive stress within a range of 500 MPa to 2000 MPa according to the manufacturing process.

[0017] According to another aspect of the present disclosure, the first contact layer and / or the second contact layer is at least partially covered by a passivation layer.

[0018] According to another aspect of the present disclosure, the substrate and the SiC epitaxial layer are n-type 4H-SiC.

[0019] According to another aspect of the present disclosure, the thickness of the stress-inducing layer and / or the thickness of the second stress-inducing layer is within a range of 1 nm to 1000 nm.

[0020] According to another aspect of the present disclosure, the stress-inducing layer and / or the second stress-inducing layer contains SiN.

[0021] According to another aspect of the present disclosure, the stress-inducing layer and / or the second stress-inducing layer contains SiN.

[0022] According to another aspect of the present disclosure, the stress-inducing layer induces a tensile or compressive stress within a range of 500 MPa to 2000 MPa according to the manufacturing process.

[0023] According to another aspect of the present disclosure, the SiC transistor device is an insulated gate bipolar transistor (IGBT).

[0024] According to another aspect of the present disclosure, a method of manufacturing a SiC transistor device, comprising the steps of forming a SiC semiconductor substrate having an upper surface and a lower surface; epitaxially forming a SiC epitaxial layer having an upper surface and a lower surface on the upper surface of the SiC semiconductor substrate; forming a source structure having an upper surface and a lower surface on the upper surface of the SiC epitaxial layer; forming a source contact structure electrically coupled to the upper surface of the source structure; forming a gate structure including a gate oxide and a metal gate on the upper surface of the SiC epitaxial layer; forming a first backside metal contact on the lower surface of the SiC semiconductor substrate; forming a stress-inducing layer on the first backside metal contact; structuring the stress-inducing layer; and forming a second backside metal contact on the structured stress-inducing layer.

[0025] According to another aspect of the present disclosure, a method of manufacturing a SiC transistor device, comprising the steps of forming a SiC semiconductor substrate having an upper surface and a lower surface; epitaxially forming a SiC epitaxial layer having an upper surface and a lower surface on the upper surface of the SiC semiconductor substrate; forming a source structure having an upper surface and a lower surface on the upper surface of the SiC epitaxial layer; forming a source contact structure electrically coupled to the upper surface of the source structure; forming a gate structure including a metal gate on the upper surface of the SiC epitaxial layer; forming a first contact layer electrically contacting the source contact structure; forming a second contact layer electrically contacting the metal gate; forming a first backside metal contact on the lower surface of the SiC semiconductor substrate; and forming a stress-inducing layer on the gate structure, wherein the stress-inducing layer induces a tensile or compressive stress within a range of 500 MPa to 2000 MPa depending on the manufacturing process.

[0026] According to another aspect of the present disclosure, a method for manufacturing a SiC transistor device comprises the steps of: forming a SiC semiconductor substrate having an upper and a lower surface; forming an epitaxial SiC epitaxial layer having an upper and a lower surface on the upper surface of the SiC semiconductor substrate; forming a source structure having an upper and a lower surface on the upper surface of the SiC epitaxial layer; forming an electrically insulating stress-inducing layer on the upper surface of the SiC epitaxial layer; structuring the electrically insulating stress-inducing layer; and via the structured electrically insulating stress-inducing layer A method is disclosed that includes the steps of forming a source contact structure electrically coupled to the upper surface of a source structure; forming a gate structure including a metal gate on an electrically insulating stress-inducing layer; forming a first contact layer that electrically contacts the source contact structure; forming a second contact layer that electrically contacts the metal gate; and forming a first backside metal contact on the lower surface of a SiC semiconductor substrate, wherein the stress-inducing layer induces tensile or compressive stress in the range of 500 MPa to 2000 MPa depending on the manufacturing process.

[0027] Another aspect of the present disclosure discloses a method for manufacturing a SiC transistor device, comprising the steps of: forming a SiC semiconductor substrate having an upper and a lower surface; epitaxially forming a SiC epitaxial layer having an upper and a lower surface on the upper surface of the SiC semiconductor substrate; forming a source structure having an upper and a lower surface on the upper surface of the SiC epitaxial layer; forming a source contact structure electrically coupled to the upper surface of the source structure; forming a gate structure including a metal gate on the upper surface of the SiC epitaxial layer; forming a first stress-inducing layer on the gate structure; forming a first back-side metal contact on the lower surface of the SiC semiconductor substrate; forming a second stress-inducing layer on the first back-side metal contact; structuring the second stress-inducing layer; and forming a second back-side metal contact on the structured second stress-inducing layer.

[0028] Another aspect of the present disclosure discloses a method for manufacturing a SiC transistor device, comprising the steps of: forming a SiC semiconductor substrate having an upper and lower surface; forming an epitaxial SiC epitaxial layer having an upper and lower surface on the upper surface of the SiC semiconductor substrate; forming a source structure having an upper and lower surface on the upper surface of the SiC epitaxial layer; forming an electrically insulating first stress-inducing layer on the upper surface of the SiC epitaxial layer; structuring the electrically insulating first stress-inducing layer; forming a source contact structure electrically coupled to the upper surface of the source structure; forming a gate structure including a metal gate on the upper surface of the SiC epitaxial layer; forming a first back-side metal contact on the lower surface of the SiC semiconductor substrate; forming a second stress-inducing layer on the first back-side metal contact; structuring the second stress-inducing layer; and forming a second back-side metal contact on the structured second stress-inducing layer.

[0029] Further areas of application will become apparent from the descriptions presented herein. The descriptions and specific examples in this summary are for illustrative purposes only and are not intended to limit the scope of this disclosure.

[0030] drawing The drawings described herein are intended to illustrate only selected embodiments, and not all possible embodiments, and are not intended to limit the scope of this disclosure. [Brief explanation of the drawing]

[0031] [Figure 1] This demonstrates the performance of a 4H-SiC power MOSFET at a technologically advanced level. [Figure 2A] This shows the electrical characteristics of a lateral SiC MOSFET in its unprocessed state. [Figure 2B] This shows the electrical characteristics of a distortion-free lateral SiC MOSFET. [Figure 2C]This shows the electrical characteristics of a lateral SiC MOSFET exposed to tensile strain. [Figure 3A] This diagram shows a schematic representation of the process integration for the SiN stress-impregnation layer on the back surface. [Figure 3B] This diagram shows a schematic representation of the process integration for the SiN stress-impregnation layer on the back surface. [Figure 3C] This diagram shows a schematic representation of the process integration for the SiN stress-impregnation layer on the back surface. [Figure 3D] This diagram shows a schematic representation of the process integration for the SiN stress-impregnation layer on the back surface. [Figure 3E] This diagram shows a schematic representation of the process integration for the SiN stress-impregnation layer on the back surface. [Figure 3F] This diagram shows a schematic representation of the process integration for the SiN stress-impregnation layer on the back surface. [Figure 4A] This shows a device having a front SiN stress-applying layer. [Figure 4B] This shows a device having a front SiN stress-applying layer. [Figure 5A] This shows a device having front and back SiN stress-impregnating layers. [Figure 5B] This shows a device having front and back SiN stress-impregnating layers. [Modes for carrying out the invention]

[0032] Detailed explanation Herein, examples of embodiments will be described in more detail with reference to the attached drawings.

[0033] Exemplary embodiments are presented to ensure thoroughness of the disclosure and to fully convey its scope to those skilled in the art. Numerous specific details are described, including examples of particular components, devices, and methods, to provide a complete understanding of the embodiments of the disclosure. It will be apparent to those skilled in the art that these specific details are not necessarily required, and that the exemplary embodiments can be embodied in numerous different forms, none of which should be construed as limiting the scope of the disclosure. In some exemplary embodiments, well-known processes, well-known device structures, and well-known technologies are not described in detail.

[0034] The terms used herein are intended solely to describe specific exemplary embodiments and are not intended to be limiting. Where used herein, the singular forms “a,” “an,” and “the” may also include the plural form unless the context clearly indicates otherwise. The terms “equipped with,” “having,” “including,” and “having” are inclusive and thus specify the existence of the described features, assemblies, steps, actions, elements, and / or components, but do not exclude the existence or addition of one or more other features, assemblies, steps, actions, elements, components, and / or groups thereof. The method steps, processes, and actions described herein should not be construed as necessarily requiring them to be performed in a specific order described or illustrated unless specifically identified as the order of execution.

[0035] It should also be understood that additional or alternative steps may be used.

[0036] When an element or layer is referred to as “adjacent,” “engaged,” “connected,” or “joined” another element or layer, it may be directly adjacent, engaged, connected, or joined to the other element or layer, or there may be an intervening element or layer. In contrast, when an element is referred to as “directly adjacent,” “directly engaged,” “directly connected,” or “directly joined” to another element, there may be no intervening element or layer. Other words used to describe relationships between elements should be interpreted similarly (e.g., “between…” vs. “directly between…”, “adjacent” vs. “directly adjacent,” etc.). As used herein, the term “and / or” includes any combination of one or more of the related enumerated items.

[0037] Terms such as "first," "second," and "third" may be used herein to describe various elements, components, regions, layers, and / or parts, but these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms may only be used to distinguish one element, component, region, layer, or part from another region, layer, or part. Terms such as "first," "second," and other numerical terms, when used herein, do not imply order or sequence unless explicitly indicated by the context. Thus, the first element, component, region, layer, or part described below may be referred to as the second element, component, region, layer, or part without departing from the teaching of the exemplary embodiments.

[0038] Spatially relative terms such as "inner", "outer", "directly below", "below", "lower side", "above", "upper side", etc. may be used in this specification to facilitate descriptions of the relationship of one element or feature to another element or feature as shown in the figures. Spatially relative terms may be intended to encompass various orientations of the device in use or operation in addition to the orientation shown in the figures. For example, if the device in the figure is turned over, an element described as "below" or "directly below" another element or feature is considered to be located "above" the other element or feature. Thus, the exemplary term "below" may encompass both upward and downward orientations. The device may be oriented in other directions (rotated 90 degrees or other orientations), and the spatially relative descriptors used in this specification are to be interpreted accordingly.

[0039] According to one embodiment of the present invention, in order to improve the performance of a SiC transistor device, a stress-applying layer such as a SiN stress-applying layer, for example, is formed on the back surface of a fully processed wafer. FIGS. 2A to 2C show the electrical characteristics of variously processed lateral SiC MOSFETs, showing the advantages of an additional SiN stress-applying portion. The transfer characteristics of a MOSFET using a conventional process are shown in FIG. 2A, showing an I 5 / I on ratio of about 10 off and a subthreshold slope of 1236 mV / decade (V DS = 1V). As shown in the inset, the back surface SiO2 layer 21 remains after the last processing step, causing the wafer to bend and resulting in compressive strain on the surface of the MOSFET, i.e., the channel. However, by removing (relaxing the compressive stress) this remaining back surface layer, for example, by etching, the off-current is significantly reduced by approximately two orders of magnitude, and the subthreshold slope is 644 mV / decade (V DSThe stress decreases to 1V (see Figure 2B). Finally, in the case of a MOSFET having an additional SiN stress-impregnating layer 22 on the back surface that induces tensile stress, a further decrease in the subthreshold gradient to 377mV / decade is observed, which is less than one-third compared to the conventional process shown in Figure 2A. According to experiments conducted by the inventors of the present invention, the stress depends on the stoichiometry of the material of the stress-impregnating layer, and in particular on the N content in the SiN layer.

[0040] A schematic diagram of an example of process integration of this back-side stress-impregnating layer into an existing vertical SiC power MOSFET processing platform is shown in Figures 3A to 3F. However, a similar process can also be applied to the fabrication of SiC IGBTs or SiC diodes. n acts as a drift layer material. - -4H-SiC epitaxial layer 32, n + -4H-SiC(0001) substrate 31 is used for growth. However, the substrate may be a Si substrate or a SiC substrate having a different crystal structure such as 6H-SiC or 3C-SiC. p-channels 33, p-wells 34, and n ++After the completion of standard injection steps such as the ohmic contact 35 (source) (Figure 3A), a gate stack comprising at least a gate oxide 36, a metal gate 37, and a gate insulator 40 is processed (Figures 3B and 3C). Following the formation of silicide contacts on the front 38 and back 39 (see Figure 3C), a silicon nitride (SiN) stress-inducing layer 41 is formed on the back surface of the wafer (Figure 3D). Examples of methods for manufacturing the silicon nitride (SiN) stress-inducing layer 41 on the back surface include, for example, PE-CVD, LP-CVD, or ALD. The thickness of the stress-inducing layer 41 is in the range of 1 nm to 1000 nm. The stress induced by the stress-inducing layer 41 is in the range of 500 MPa to 2000 MPa, and in certain embodiments, it is 1000 MPa. Depending on the application of the layer to the front or back surface, for example, the stress-inducing layer is formed to induce tensile stress in the device channels. The manufacturing of the device is completed by forming a second back metal contact 42 (see Figures 3E and 3F), which includes the step of structuring a SiN layer to finally electrically contact the first back metal contact 39 with the second back metal contact 42 (see Figure 3E). The back metal contacts 39, 42 may be, for example, titanium (Ti), nickel (Ni), aluminum (Al), silver (Ag), titanium nitride (TiN), tantalum nitride (TaN), or copper (Cu).

[0041] Some of the advantages of this back surface stress-impregnating layer 41 is the improvement of the interfacial defect density of the 4H-SiC / oxide interface by introducing tensile strain to the channel surface (I on / I off This is an improvement in interface quality that results in increased ratio and decreased subthreshold gradient, and reduced carrier scattering. Thus, it is an improvement in inversion layer electron mobility, and as a result, the R of SiC power MOSFETs. on This enables a reduction in power loss, which is essential for reducing on-state power loss and switching loss, especially for commercially critical voltage classes (≤1.7kV).

[0042] For example, in another embodiment shown in Figure 4A, the stress-impregnating layer is formed on the front surface of the device. In contrast to the tensile stress of the SiN-based stress-impregnating layer 41 formed on the back surface, the SiN-based stress-impregnating layer formed on the front surface can be formed to induce tensile stress in the channels of the device. In particular, in the case of a cell layout, a continuous stress-impregnating layer can be formed on the front surface.

[0043] In another embodiment disclosed in Figure 4B, the SiN-based stress-inducing layer 41 functions as a gate dielectric. In this embodiment, the SiN-based stress-inducing layer 41 does not spread to cover the entire gate structure as shown in Figure 4A, but is formed flat as an electrically insulating stress-inducing layer 41 on the upper surface of the SiC epitaxial layer 32 and is structured after formation to contact the source structure 35 as a gate dielectric. Lateral gate insulation of the gate may be achieved by a spacer structure.

[0044] In another embodiment, the stress-applying layer is not formed to cover the entire front surface, but is formed only as stress-applying lines.

[0045] For example, to avoid non-uniform stress distribution caused by changes in the thickness of the stress-applying layer, in another embodiment, a planarization layer can be formed to flatten the surface before the stress-applying layer is applied. In another example, this planarization layer is a passivation layer.

[0046] In an alternative embodiment, the SiN-based stress-applying layer may be a conductive stress-applying portion such as titanium nitride (TiN). This embodiment has the advantage of omitting the formation of the second back metal contact described above by the preceding structuring step.

[0047] In other embodiments, as disclosed in Figures 5A and 5B, the SiC transistor device comprises stress-applying layers on the front and back surfaces of the device. As shown in Figure 5A, the front stress-applying layer 51 can extend to cover the gate structure.

[0048] Alternatively, similar to Figure 4B, the SiN-based stress-impregnating layer 51 on the front surface of the embodiment shown in Figure 5B may be formed on the upper surface of the SiC epitaxial layer 32 and can function as a gate dielectric. Depending on the timing and method of application, SiN can impart various types (tensile or compressive) and varying magnitudes of stress. Therefore, by forming stress-impregnating layers on the upper and lower surfaces of the device, the overall level of stress can be adjusted according to the requirements of the remaining elements and the desired application of the SiC transistor device.

[0049] The above description of embodiments is provided for illustrative and explanatory purposes only. It is not intended to be exhaustive or to limit the disclosure. Individual elements or features of a particular embodiment are generally interchangeable and can be used in selected embodiments, even if not specifically illustrated or described, and are not limited to that particular embodiment. They are also modifiable in many ways. Such modifications should not be considered deviations from the disclosure, and all such modifications are intended to be within the scope of the disclosure.

Claims

1. A SiC semiconductor substrate (31) having an upper surface and a lower surface, A SiC epitaxial layer (32) is formed on the upper surface of the SiC semiconductor substrate (31) and has an upper surface, A source structure (35) is formed on the upper surface of the SiC epitaxial layer (32) and has an upper surface, A source contact structure electrically coupled to the upper surface of the source structure (35), A gate structure comprising a gate dielectric (36), a metal gate (37), and a gate insulator (40), The first back metal contact (39) on the lower surface of the SiC semiconductor substrate (31) and A SiC transistor device comprising, The stress-inducing layer (41) on the first back metal contact (39), The second back metal contact (42) on the stress induction layer (41) and It is characterized by, The stress-inducing layer (41) has a penetrating portion that extends in the thickness direction of the stress-inducing layer (41), The SiC transistor device is characterized in that the second back metal contact (42) is formed such that a portion of the second back metal contact (42) contacts the first back metal contact (39) through the through portion.

2. The SiC transistor device according to claim 1, wherein the second back metal contact (42) comprises at least one of titanium (Ti), nickel (Ni), aluminum (Al), or silver (Ag).

3. The SiC transistor device according to claim 1 or 2, characterized in that the stress-inducing layer (41) on the first back metal contact (39) induces tensile or compressive stress in the range of 500 MPa to 2000 MPa.

4. The SiC transistor device according to any one of claims 1 to 3, wherein the first contact layer that electrically contacts the source contact structure and / or the second contact layer that electrically contacts the metal gate (37) are at least partially covered with a passivation layer.

5. The SiC transistor device according to any one of claims 1 to 4, wherein the SiC semiconductor substrate (31) and the SiC epitaxial layer (32) are n-type 4H-SiC.

6. The SiC transistor device according to any one of claims 1 to 5, wherein the thickness of the stress-inducing layer (41) is in the range of 1 nm to 1000 nm.

7. The gate structure further comprises a second stress-inducing layer (51), The SiC transistor device according to any one of claims 1 to 6, wherein the upper surface of the metal gate (37) is in contact with the second stress-inducing layer (51).

8. The SiC epitaxial layer (32) further comprises an electrically insulating second stress-inducing layer (51) on its upper surface, The SiC transistor device according to any one of claims 1 to 6, wherein the lower surface of the metal gate (37) is in contact with the second stress-inducing layer (51).

9. The SiC transistor device according to claim 7 or 8, wherein the stress-inducing layer (41) and / or the second stress-inducing layer (51) comprises SiN or TiN.

10. The SiC transistor device according to any one of claims 7 to 9, wherein the thickness of the second stress-inducing layer (51) is in the range of 1 nm to 1000 nm.

11. The SiC transistor device according to any one of claims 7 to 10, wherein the second stress-inducing layer (51) comprises SiN or TiN.

12. The SiC transistor device according to any one of claims 7 to 11, wherein the second stress-inducing layer (51) induces a tensile or compressive stress in the range of 500 MPa to 2000 MPa.

13. A SiC transistor device according to any one of claims 1 to 12, which is a metal-oxide-semiconductor field-effect transistor (MOSFET).

14. A SiC transistor device according to any one of claims 1 to 12, which is an insulated gate bipolar transistor (IGBT).

15. A method for manufacturing SiC transistor devices, The steps include forming a SiC semiconductor substrate having an upper surface and a lower surface, The steps include: forming an epitaxial SiC epitaxial layer having an upper surface on the upper surface of the SiC semiconductor substrate; The steps include forming a source structure having an upper surface on the upper surface of the SiC epitaxial layer, The steps include forming a source contact structure electrically coupled to the upper surface of the source structure, The steps include forming a gate structure including a gate dielectric and a metal gate on the upper surface of the SiC epitaxial layer, The steps include forming a first backside metal contact on the lower surface of the SiC semiconductor substrate, The steps include forming a stress-inducing layer on the first back metal contact having a through portion extending in the thickness direction of the stress-inducing layer, The steps include forming a second back metal contact on the stress-inducing layer such that a portion of the second back metal contact contacts the first back metal contact through the through portion, Methods that include...

Images