Circuit board

Abstract

A circuit board according to an embodiment includes a first insulating layer, a second insulating layer disposed on an upper surface of the first insulating layer, a first circuit pattern disposed embedded in a lower region of the first insulating layer and including a first via pad, a second circuit pattern disposed between the first insulating layer and the second insulating layer and including a second via pad, a third circuit pattern disposed embedded in an upper region of the second insulating layer and including a third via pad, a first via disposed in the first insulating layer and connecting the first via pad and the second via pad, and a second via disposed in the second insulating layer and connecting the second via pad and the third via pad, and at least one of the upper and lower surfaces of the second via includes a portion bulging upward or downward.

Description

Technical Field

[0001] Examples relate to a circuit board, and more particularly to a circuit board having a structure in which an outermost circuit pattern is embedded in an insulating layer and a method for manufacturing the same.

Background Art

[0002] With the accelerating miniaturization, weight reduction, and integration of electronic components, the line width of circuits is being miniaturized. In particular, as the design rules of semiconductor chips are integrated on the nanometer scale, the circuit line width of package substrates or circuit boards on which semiconductor chips are mounted is being miniaturized to several micrometers or less.

[0003] In order to increase the circuit integration density of circuit boards, that is, to miniaturize the circuit line width, various methods have been proposed. For the purpose of preventing the loss of circuit line width in the etching step for forming a pattern after copper plating, the SAP (semi-additive process) method, the MSAP (modified semi-additive process), etc. have been proposed.

[0004] After that, in order to embody a finer circuit pattern, the ETS (Embedded Trace Substrate (hereinafter referred to as "ETS")) method of embedding a copper foil in an insulating layer has been used in the industry. Since the ETS method manufactures in a form of embedding a copper foil circuit in an insulating layer instead of forming it on the surface of the insulating layer, there is no circuit loss due to etching, which is advantageous for miniaturizing circuit pitches.

[0005] On the other hand, recently, efforts have been made to develop an improved 5G (5 th generation) communication system or a pre-5G communication system to meet the demand for wireless data traffic. Here, the 5G communication system uses an ultra-high frequency (mmWave) band (sub 6GHz, 28GHz, 38GHz or higher frequencies) in order to achieve a high data transmission rate.

[0006] Furthermore, to mitigate path loss in the ultra-high frequency band and increase the transmission distance of radio waves, integration technologies such as beamforming, massive MIMO, and array antennas have been developed for 5G communication systems. Considering that the wavelengths in such frequency bands are composed of hundreds of active antennas, the antenna system becomes relatively large.

[0007] Since such antennas and AP modules are patterned or mounted on circuit boards, low loss on the circuit board is extremely important. This means that the numerous boards that make up an active antenna system—namely, the antenna board, antenna feed board, transceiver board, and baseband board—must be integrated into a single compact unit.

[0008] Furthermore, the circuit boards used in the aforementioned 5G communication systems are manufactured in line with the trend towards miniaturization and lightness, resulting in increasingly finer circuit patterns.

[0009] However, conventional circuit boards containing fine circuit patterns have a structure in which the outermost circuit pattern protrudes above the insulating layer, which has the problem that the outermost circuit pattern can easily collapse. [Overview of the Initiative] [Problems that the invention aims to solve]

[0010] The embodiment provides a circuit board with a new structure and a method for manufacturing the same.

[0011] Furthermore, the embodiment provides a circuit board having a structure in which the outermost circuit pattern is entirely embedded within an insulating layer, and a method for manufacturing the same.

[0012] Furthermore, the embodiment provides a circuit board and a method for manufacturing the same, in which the outermost circuit pattern has a symmetrical structure with respect to the center of the insulating layer.

[0013] The technical challenges that the proposed embodiments aim to address are not limited to those mentioned above, and any other technical challenges not mentioned will be clearly understood by those with ordinary skill in the art to which the embodiments belong from the following description. [Means for solving the problem]

[0014] The circuit board according to the embodiment includes a first insulating layer, a second insulating layer disposed on the upper surface of the first insulating layer, a first circuit pattern embedded in the lower region of the first insulating layer and including a first via pad, a second circuit pattern disposed between the first insulating layer and the second insulating layer and including a second via pad, a third circuit pattern embedded in the upper region of the second insulating layer and including a third via pad, a first via disposed within the first insulating layer and connecting the first via pad and the second via pad, and a second via disposed within the second insulating layer and connecting the second via pad and the third via pad, wherein at least one of the upper and lower surfaces of the second via includes a portion that bulges upward or downward.

[0015] Furthermore, the lower surface of the second via has a curved surface that bulges downward, and the upper surface of the second via pad has a curved surface that is recessed downward to correspond to the lower surface of the second via.

[0016] Furthermore, the upper surface of the second via pad includes a first portion that contacts the lower surface of the second via and a second portion other than the first portion, the first portion of the upper surface of the second via pad having a concave curved surface corresponding to the lower surface of the second via, and the second portion of the upper surface of the second via pad having a flat surface.

[0017] Furthermore, the upper surface of the second via has a curved surface that bulges upward, and the lower surface of the third via pad has a curved surface that is concave upward to correspond to the upper surface of the second via.

[0018] Furthermore, the lower surface of the third via pad includes a first portion that contacts the upper surface of the second via and a second portion other than the first portion, the first portion of the lower surface of the third via pad having a concave curved surface corresponding to the upper surface of the second via, and the second portion of the lower surface of the second circuit pattern having a flat surface.

[0019] Furthermore, the upper surface of the third via pad includes a portion that overlaps vertically with the first portion of the lower surface of the third via pad and is located higher than the upper surface of the second insulating layer.

[0020] Furthermore, the upper and lower surfaces of the first via are flat, while the upper and lower surfaces of the second via are curved.

[0021] Furthermore, the first via has a shape in which its width decreases from the top surface to the bottom surface, while the second via has the same width on both its top and bottom surfaces.

[0022] Furthermore, the second and third circuit patterns each include traces, and the upper and lower surfaces of the traces each have flat surfaces.

[0023] Furthermore, the first via has a first height, and the second via has a second height that is smaller than the first height.

[0024] On one hand, a method for manufacturing a circuit board according to an embodiment includes forming a first circuit pattern including a first via pad on a first carrier board, forming a first insulating layer covering the first circuit pattern on the first carrier board, forming a first via connected to the first via pad in the first insulating layer, forming a second circuit pattern including a second via pad connected to the first via on an upper surface of the first insulating layer, removing the first carrier board to manufacture a first substrate including the first insulating layer, the first circuit pattern, the second circuit pattern, and the first via, forming a third circuit pattern including a third via pad on a second carrier board, forming a bump corresponding to the second via on the third via pad, forming a second insulating layer having a lower surface positioned higher than a lower surface of the second via while covering the third circuit pattern on the second carrier board, removing the second carrier board to manufacture a second substrate including the second insulating layer, the third circuit pattern, and the second via, and performing a pressing process with the lower surface of the second via positioned on the second via pad of the first substrate to attach the second substrate to the first substrate. The lower surface of the second via has a curved surface bulging in a downward direction, the upper surface of the second via pad has a curved surface recessed in a downward direction corresponding to the lower surface of the second via, the upper surface of the second via has a curved surface bulging in an upward direction, and the lower surface of the third via pad has a curved surface recessed in an upward direction corresponding to the upper surface of the second via.

[0025] Further, the upper surface of the second via pad and the lower surface of the third via pad include a first portion in contact with the lower surface or the upper surface of the second via and a second portion other than the first portion. The first portion has a recessed curved surface corresponding to the second via, and the second portion has a flat surface.

[0026] Further, the upper surface of the third via pad includes a portion overlapping in a vertical direction with the first portion of the lower surface of the third via pad and positioned higher than the upper surface of the second insulating layer.

[0027] Further, the upper surface and the lower surface of the first via have flat surfaces, and the upper surface and the lower surface of the second via have curved surfaces.

[0028] Further, the first via has a shape in which the width decreases from the upper surface to the lower surface, and the second via has the same shape for the widths of the upper surface and the lower surface.

[0029] Further, the second and third circuit patterns each include a trace, and the upper and lower surfaces of the trace each have a flat surface.

[0030] Further, the first via has a first height, and the second via has a second height smaller than the first height.

Advantages of the Invention

[0031] The circuit board of the embodiment includes outermost layer circuit patterns disposed on both sides of the insulating layer. At this time, the outermost layer circuit pattern can include a first outer layer circuit pattern disposed on the lowermost side of at least one insulating layer and a second outer layer circuit pattern disposed on the uppermost side. At this time, the first outer layer circuit pattern and the second outer layer circuit pattern in the embodiment can have a structure embedded entirely within the insulating layer. According to this, in the embodiment, since the first outer layer circuit pattern and the second outer layer circuit pattern have a structure embedded entirely within the insulating layer, the thickness of the circuit board can be reduced by the thickness of the first outer layer circuit pattern and / or the second outer layer circuit pattern, and the slimming of the product can be achieved thereby.

[0032] Also, when only one of the first and second outer layer circuit patterns is embedded within the insulating layer, there is a problem that warping due to an asymmetric structure occurs during the manufacturing process of the circuit board. On the contrary, in the embodiment, since the first and second outer layer circuit patterns are entirely embedded within the insulating layer, the occurrence of warping of the circuit board can be minimized, and the reliability of the product can be improved thereby.

Brief Description of the Drawings

[0033] [Figure 1a] It is a drawing showing a circuit board manufactured by the SAP method according to a comparative example. [Figure 1b] This is a diagram showing a circuit board manufactured using the SAP method as an example. [Figure 2] This is a diagram showing a circuit board manufactured using the ETS method as a comparative example. [Figure 3] This is a diagram showing a circuit board according to the first embodiment. [Figure 4] This is a magnified view of a portion of Figure 3. [Figure 5] This is a drawing showing an example of a circuit board manufactured according to the first embodiment. [Figure 6] Figure 2 is a diagram showing the manufacturing process of the circuit board illustrated in the diagram, in order of steps. [Figure 7] Figure 2 is a diagram showing the manufacturing process of the circuit board illustrated in the diagram, in order of steps. [Figure 8] Figure 2 is a diagram showing the manufacturing process of the circuit board illustrated in the diagram, in order of steps. [Figure 9] Figure 2 is a diagram showing the manufacturing process of the circuit board illustrated in the diagram, in order of steps. [Figure 10] Figure 2 is a diagram showing the manufacturing process of the circuit board illustrated in the diagram, in order of steps. [Figure 11] Figure 2 is a diagram showing the manufacturing process of the circuit board illustrated in the diagram, in order of steps. [Figure 12] Figure 2 is a diagram showing the manufacturing process of the circuit board illustrated in the diagram, in order of steps. [Figure 13] Figure 2 is a diagram showing the manufacturing process of the circuit board illustrated in the diagram, in order of steps. [Figure 14] Figure 2 is a diagram showing the manufacturing process of the circuit board illustrated in the diagram, in order of steps. [Figure 15] This is a diagram showing a circuit board according to the second embodiment. [Figure 16] This is a diagram showing a circuit board according to the third embodiment. [Modes for carrying out the invention]

[0034] The embodiments disclosed herein will be described in detail below with reference to the attached drawings, but identical or similar components will be given the same reference numeral regardless of the drawing reference numerals, and redundant descriptions will be omitted. The suffixes “module” and “part” used for components in the following description are added or used interchangeably to facilitate the preparation of the specification and do not have any mutually distinguishing meaning or role in themselves. Furthermore, in the description of the embodiments disclosed herein, if it is determined that a specific description of such prior art would interfere with the understanding of the embodiments disclosed herein, such detailed description will be omitted. In addition, the attached drawings are provided to facilitate the understanding of the embodiments disclosed herein and should be understood as including all modifications, equivalents or substitutes that fall within the concept and scope of the present invention, rather than limiting the technical ideas disclosed herein.

[0035] Terms including ordinal numbers such as "first," "second," etc., can be used to describe a variety of components, but such components are not limited to those terms. The terms are used solely for the purpose of distinguishing one component from another.

[0036] When it is stated that one component is “linked” or “connected” to another component, it should be understood that it may be directly “linked” or “connected” to the other component, and that other components may exist in between. Conversely, when it is stated that one component is “directly linked” or “directly connected” to another component, it should be understood that there are no other components in between.

[0037] A singular expression includes plural expressions unless the context clearly indicates otherwise.

[0038] In this application, terms such as “includes” or “having” are intended to specify the presence of features, figures, steps, actions, components, parts, or combinations thereof as described in the specification, and should be understood not to preemptively exclude the presence or possibility of adding one or more other features, figures, steps, actions, components, parts, or combinations thereof.

[0039] The embodiments of the present invention will be described in detail below with reference to the attached drawings.

[0040] Before describing this embodiment, we will first describe a comparative example that is comparable to this embodiment.

[0041] Figures 1a and 1b are diagrams showing circuit boards according to comparative examples.

[0042] Referring to Figure 1a, the circuit board in the comparative example generally contains circuit patterns manufactured using the SAP method.

[0043] Specifically, the circuit board includes an insulating layer 10, a circuit pattern 20, and a protective layer 30.

[0044] The circuit pattern 20 is placed on the upper and lower surfaces of the insulating layer 10, respectively.

[0045] At this time, at least one of the circuit patterns 20 arranged on the surface of the insulating layer 10 includes a fine circuit pattern.

[0046] In Figure 1a, the circuit pattern 20 placed on the upper surface of the insulating layer 10 includes a fine circuit pattern. The fine circuit pattern includes traces 21, which are signal transmission wiring lines, and pads 22 for chip mounting, etc.

[0047] Furthermore, a protective layer 30 is placed on the surface of the insulating layer 10 to protect the circuit pattern 20.

[0048] At this time, the upper region of the insulating layer 10 includes a first region where the protective layer 30 is placed and a second region which is an open region where the protective layer 30 is not placed.

[0049] As a result, a portion of the circuit pattern 20 arranged on the upper surface of the insulating layer 10 is covered by the protective layer 30, while the remaining portion is exposed to the outside without being covered by the protective layer 30.

[0050] At this time, the second region, which is an open region of the protective layer 30, has traces 21 and pads 22 corresponding to the fine circuit patterns, as described above.

[0051] For example, at least one of the trace 21 and pad 22 is formed with a width / spacing of 15 μm / 15 μm or less.

[0052] In this case, if the circuit pattern formed in the open region of the protective layer 30 is not a fine circuit pattern but a pattern with a width exceeding 15 μm, it is resistant to external impacts.

[0053] However, as shown in Figure 1b, as the circuit pattern becomes progressively smaller, the width and spacing of the traces 21 and pads 22, which are the fine circuit patterns of the outermost layer, become smaller and smaller. This causes a problem in which, when a fine circuit pattern protruding from the upper surface of the insulating layer 10 is placed in the second region, which is an open region of the protective layer, the fine circuit pattern can easily collapse due to external impact.

[0054] In other words, as shown in Figure 1b, the trace 21 corresponding to the outermost layer's fine circuit pattern has an extremely fine pattern shape, which causes it to easily collapse or tilt even with small external impacts.

[0055] On the other hand, recently, the ETS method has been used to form fine circuit patterns that have structures embedded within the insulating layer and are placed in the open regions of the protective layer.

[0056] Figure 2 is a diagram showing a circuit board manufactured using the ETS method as a comparative example.

[0057] Referring to Figure 2, specifically, the circuit board includes an insulating layer 10A, a circuit pattern 20A, and a protective layer 30A.

[0058] The circuit pattern 20A is placed on the upper and lower surfaces of the insulating layer 10A, respectively.

[0059] At this time, at least one of the circuit patterns 20A arranged on the surface of the insulating layer 10A includes a fine circuit pattern.

[0060] In this case, when forming a circuit pattern using the ETS method, the initially formed circuit pattern has a structure embedded within the insulating layer 10A. Therefore, when the initially formed circuit pattern is formed as a fine circuit pattern, the comparative example can also have a structure embedded within the insulating layer 10A.

[0061] In other words, the circuit board manufactured by the ETS method includes a fine circuit pattern having a structure embedded within the surface of the insulating layer 10A. Specifically, the fine circuit pattern includes traces 21A, which are signal transmission wiring lines, and pads 22A for chip mounting, etc.

[0062] Furthermore, in the case of circuit boards manufactured by the ETS method as described above, the fine circuit patterns are embedded within an insulating layer, thus protecting the fine circuit patterns from external impacts.

[0063] However, in the circuit board manufactured by the ETS method in the comparative example, the last formed circuit pattern has the problem of protruding above the surface of the insulating layer 10A.

[0064] Specifically, the circuit board of the comparative example includes traces 21A and pads 22A having a structure embedded on one side of the insulating layer 10A. The circuit board of the comparative example also includes traces 21B and pads 22B having a structure protruding from the other side of the insulating layer 10A.

[0065] However, as described above, in the comparative example, the circuit board has a structure in which the circuit pattern on one side is embedded within the insulating layer, while the circuit pattern on the other side has a structure that protrudes above the surface of the insulating layer. This results in a problem where the degree of warping due to the asymmetric structure increases.

[0066] Furthermore, in the comparative example, the circuit board cannot form fine circuit patterns on the other side, and if the protruding circuit pattern is a fine pattern, it suffers from the reliability problems described in Figures 1a and 1b.

[0067] Furthermore, with the recent advancement of 5G technology, there is growing interest in circuit boards that can accommodate it. For 5G technology to be applied, the circuit board must have a highly multilayered structure, resulting in miniaturized circuit patterns. However, while comparative examples can form fine patterns, they suffer from the problem of not being able to stably protect them, leading to various issues such as product warping and increased thickness.

[0068] Thus, the embodiment aims to provide a new circuit board structure and a method for manufacturing the same that can solve the reliability problem of the fine patterns placed on the outermost surface.

[0069] Figure 3 is a diagram showing a circuit board according to the first embodiment, Figure 4 is an enlarged view of a part of Figure 3, and Figure 5 is a diagram showing an example of a circuit board manufactured according to the first embodiment.

[0070] In the following, we will describe the circuit board according to the first embodiment with reference to Figures 3 to 5.

[0071] Before explaining Figures 3 to 5, it should be noted that the circuit board according to the embodiment may have a multilayer structure. Preferably, the circuit board according to the embodiment may have a three-layer structure based on the number of layers of the circuit pattern. However, this is only one embodiment and is not limited thereto. That is, the circuit board in the embodiment may have fewer than three layers, or differently, it may have more than three layers.

[0072] However, the circuit board in the embodiment is intended to solve the problems of the ETS method and SAP method in the comparative example. In this case, the ETS method in the comparative example has a structure in which only one side of the circuit pattern of the outermost layer is embedded in the insulating layer. Therefore, in the embodiment, we will explain using a three-layer circuit board having a double-sided embedded structure.

[0073] Referring to Figures 3 to 5, the circuit board 100 includes an insulating layer. Preferably, the circuit board 100 may include first and second insulating layers 110 and 120 to embody a three-layer circuit pattern structure. That is, in the embodiment, the first insulating layer 110 may refer to the insulating layer located at the bottom of the multilayer insulating layer laminated structure. The second insulating layer 120 may refer to the insulating layer located at the top of the multilayer insulating layer laminated structure. Furthermore, as described above, the circuit board in the embodiment may have at least one additional insulating layer located between the first insulating layer 110 and the second insulating layer 120.

[0074] The first insulating layer 110 and the second insulating layer 120 can include all printed circuit boards and insulating substrates made of insulating material on which a circuit pattern can be formed on the surface, as substrates on which electrical circuits can be arranged and on which the wiring can be changed.

[0075] For example, at least one of the first insulating layer 110 and the second insulating layer 120 may be rigid or flexible. For example, at least one of the first insulating layer 110 and the second insulating layer 120 may include glass or plastic. More specifically, at least one of the first insulating layer 110 and the second insulating layer 120 may include chemically strengthened / semi-strengthened glass such as soda-lime glass or aluminosilicate glass, or it may include reinforced or flexible plastics such as polyimide (PI), polyethylene terephthalate (PET), propylene glycol (PPG), polycarbonate (PC), or sapphire.

[0076] Furthermore, at least one of the first insulating layer 110 and the second insulating layer 120 may include an optically isotropic film. For example, at least one of the first insulating layer 110 and the second insulating layer 120 may include COC (Cyclic Olefin Copolymer), COP (Cyclic Olefin Polymer), optically isotropic polycarbonate (PC), or optically isotropic polymethyl methacrylate (PMMA).

[0077] Furthermore, at least one of the first insulating layer 110 and the second insulating layer 120 can bend while having a partially curved surface. That is, at least one of the first insulating layer 110 and the second insulating layer 120 can bend while having a partially flat surface and a partially curved surface. More specifically, at least one of the first insulating layer 110 and the second insulating layer 120 can bend while having a curved surface at its end, or can bend or bend while having a surface that includes random curvature.

[0078] Furthermore, at least one of the first insulating layer 110 and the second insulating layer 120 may be a flexible substrate having flexible properties. Also, at least one of the first insulating layer 110 and the second insulating layer 120 may be a curved or bent substrate. In this case, at least one of the first insulating layer 110 and the second insulating layer 120 can represent electrical wiring connecting circuit components based on the circuit design using wiring diagrams, and reproduce electrical conductors on the insulating material. Furthermore, at least one of the first insulating layer 110 and the second insulating layer 120 can mount electrical components and form wiring that connects them circuit-wise, and can mechanically fix components other than those that provide electrical connection functions.

[0079] Circuit patterns are arranged on the surfaces of the first insulating layer 110 and the second insulating layer 120.

[0080] Specifically, circuit patterns are arranged on the surfaces of the first insulating layer 110 and the second insulating layer 120, respectively.

[0081] Here, the circuit pattern in the embodiment may include an inner layer circuit pattern and an outer layer circuit pattern. The inner layer circuit pattern may mean a circuit pattern arranged between the first insulating layer 110 and the second insulating layer 120. The outer layer circuit pattern may mean a circuit pattern arranged on the lower surface of the first insulating layer 110, which is located at the bottom, and a circuit pattern arranged on the upper surface of the second insulating layer 120, which is located at the top.

[0082] Preferably, the circuit pattern may include a first circuit pattern disposed on the lower surface of the first insulating layer 110, a second circuit pattern disposed on the upper surface of the first insulating layer 110, and a third circuit pattern disposed on the upper surface of the second insulating layer 120. In this case, the first and third circuit patterns may be outer layer circuit patterns, and the second circuit pattern may be an inner layer circuit pattern.

[0083] On the other hand, although the above description states that the outer layer circuit patterns are arranged on the lower surface of the first insulating layer 110 and the upper surface of the second insulating layer 120, the outer layer circuit patterns can substantially have a structure in which they are embedded in the lower part of the first insulating layer 110 and the upper part of the second insulating layer 120, respectively.

[0084] The first circuit pattern is embedded in the lower surface of the first insulating layer 110. For example, the upper surface of the first circuit pattern may be positioned higher than the lower surface of the first insulating layer 110. For example, the lower surface of the first circuit pattern may be positioned on the same plane as the lower surface of the first insulating layer 110. However, the embodiment is not limited thereto, and the lower surface of the first circuit pattern may be positioned higher than the lower surface of the first insulating layer 110 by processing the lower surface of the first circuit pattern (e.g., chemical or physical polishing, etching, etc.).

[0085] The first circuit pattern may include a trace 135 and a pad 130. The pad 130 may include a via pad that is connected to a via as described later.

[0086] The second circuit pattern is positioned on the upper surface of the first insulating layer 110. For example, the upper surface of the second circuit pattern can be positioned higher than the upper surface of the first insulating layer 110. For example, the lower surface of the second circuit pattern is positioned in direct contact with the upper surface of the first insulating layer 110. That is, the second circuit pattern is positioned in a structure that protrudes above the upper surface of the first insulating layer 110.

[0087] Furthermore, the second circuit pattern is an inner layer circuit pattern, and as a result, although the second circuit pattern has a structure that protrudes above the first insulating layer 110, it is covered by the second insulating layer 120.

[0088] The second circuit pattern may include trace 145 and pad 140.

[0089] The third circuit pattern is embedded and positioned on the upper surface of the second insulating layer 120. For example, the lower surface of the third circuit pattern may be positioned lower than the upper surface of the second insulating layer 120. For example, the upper surface of the third circuit pattern may be positioned on the same plane as the upper surface of the second insulating layer 120. However, the embodiment is not limited thereto, and the upper surface of the third circuit pattern may be positioned lower than the upper surface of the second insulating layer 120 by processing the upper surface of the third circuit pattern (e.g., chemical or physical polishing, etching, etc.).

[0090] The third circuit pattern may include a trace 155 and a pad 150. The pad 150 may include a via pad connected to a via, which will be described later. In this case, the pad 150 and the trace 155 of the third circuit pattern may have different heights. Here, having different heights means that the upper surface of the pad 150 and the upper surface of the trace 155 of the third circuit pattern are at different heights. For example, the upper surface of the pad 150 of the third circuit pattern may be higher than the upper surface of the trace 155. For example, the upper surface of the pad 150 of the third circuit pattern may include a portion that is higher than the upper surface of the trace 155.

[0091] The first to third circuit patterns may include fine circuit patterns. Preferably, the first to third circuit patterns may include fine circuit patterns with a line width of 10 μm or less and a spacing between patterns of 10 μm or less. If the first and third circuit patterns have structures that protrude below the lower surface of the first insulating layer 110 or above the upper surface of the second insulating layer 120, the fine circuit patterns may be subjected to impact from external factors, which may cause reliability problems. Therefore, in the embodiment, the first circuit pattern has a structure embedded in the lower part of the first insulating layer 110, and the third circuit pattern has a structure embedded in the upper part of the second insulating layer 120, thereby improving the reliability of the outer layer circuit patterns.

[0092] The first to third circuit patterns can be made of a highly electrically conductive metallic material as wiring for transmitting electrical signals. For this purpose, the first to third circuit patterns can be made of at least one metallic material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn). Alternatively, the first to third circuit patterns can be made of a paste or solder paste containing at least one metallic material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn), which have excellent bonding strength. Preferably, the first to third circuit patterns can be made of copper (Cu), which has high electrical conductivity and is relatively inexpensive.

[0093] At least one of the first to third circuit patterns can be formed using conventional circuit board manufacturing processes such as the additive process, subtractive process, MSAP (Modified Semi Additive Process), and SAP (Semi Additive Process), and a detailed explanation is omitted here.

[0094] On the other hand, vias are placed in the first insulating layer 110 and the second insulating layer 120. The vias are placed within each insulating layer, thereby electrically connecting circuit patterns placed in different layers.

[0095] A first via 160 is arranged within the first insulating layer 110. The first via 160 can electrically connect a first circuit pattern embedded in the lower part of the first insulating layer 110 to a second circuit pattern protruding above the upper surface of the first insulating layer 110. For example, one end of the first via 160 can be in direct contact with the upper surface of the first circuit pattern, and the other end of the first via 160 can be in direct contact with the lower surface of the second circuit pattern.

[0096] A second via 165 is placed within the second insulating layer 120. The second via 165 can electrically connect a third circuit pattern embedded in the upper part of the second insulating layer 120 to a second circuit pattern protruding above the upper surface of the first insulating layer 110. For example, one end of the second via 165 can directly contact the upper surface of the first circuit pattern, and the other end of the first via 160 can directly contact the lower surface of the second circuit pattern.

[0097] The first via 160 described above is formed by filling the inside of a via hole formed in the first insulating layer 110 with a metallic substance.

[0098] The via holes are formed by one of the following processing methods: mechanical, laser, or chemical processing. When the via holes are formed by mechanical processing, methods such as milling, drilling, and routing can be used; when they are formed by laser processing, UV or CO2 laser methods can be used; and when they are formed by chemical processing, chemicals containing aminosilanes, ketones, etc., can be used to open the insulating layer 110.

[0099] On the other hand, the laser processing method concentrates optical energy on the surface to melt and evaporate a portion of the material, creating a desired shape. This cutting method can easily process complex shapes created by computer programs, and can also process composite materials that are difficult to cut by other methods.

[0100] Furthermore, the laser processing method has the advantage of being able to cut materials down to a minimum diameter of 0.005 mm and having a wide range of thicknesses that can be processed.

[0101] It is preferable to use a YAG (Yttrium Aluminum Garnet) laser, a CO2 laser, or an ultraviolet (UV) laser as the laser processing drill. A YAG laser is a laser that can process both the copper foil layer and the insulating layer, while a CO2 laser is a laser that can process only the insulating layer.

[0102] Once the via hole is formed, the inside of the via hole can be filled with a conductive material to form the first via 160. The metallic material used to form the first via 160 may be any one of the following: copper (Cu), silver (Ag), tin (Sn), gold (Au), nickel (Ni), and palladium (Pd). The filling of the conductive material can be carried out using any one of the following methods, or a combination thereof: electroless plating, electrolytic plating, screen printing, sputtering, evaporation, inkjet method, and dispensing.

[0103] On the other hand, the second via 165 may be formed in a different manner than the first via 160. That is, the first via 160 can be formed by filling the inside of a via hole formed in the first insulating layer 110 with a metallic substance. In contrast, the second via 165 can be formed by forming a bump using a mask (not shown), and then performing a pressing process with the formed via positioned on the second circuit pattern. That is, in the embodiment, after forming the third circuit pattern and bump on a carrier board, a second insulating layer 120 surrounding the third circuit pattern and bump is formed to manufacture a bump substrate, and then the manufactured bump substrate is placed on the first insulating layer 110 and a pressing process is performed to adhere the second insulating layer 120 to the first insulating layer 110.

[0104] As a result, the first via 160 and the second insulating layer 120 can have different shapes from each other. For example, the first via 160 and the second via 165 may have the same basic shape. That is, the basic shape of the first via 160 and the second via 165 may be a trapezoidal shape in which the width decreases from one surface to the other. However, the shape of the surface of the first insulating layer 110 may differ from the shape of the surface of the second via 165. The surface of the first via 160 may be flat. In contrast, the surface of the second via 165 may be curved. For example, the second via 165 may be a convex surface projecting upward or downward.

[0105] I will explain this in more detail below. On the other hand, a protective layer is placed on the outermost surface of the circuit board 100. Preferably, a first protective layer 170 is placed on the lower surface of the first insulating layer 110. Also, a second protective layer 175 is placed on the upper surface of the second insulating layer 120.

[0106] The first protective layer 170 and the second protective layer 175 are formed from at least one layer using one or more of SR (Solder Resist), oxide, and Au. Preferably, the first protective layer 170 and the second protective layer 175 are solder resist.

[0107] The first protective layer 170 and the second protective layer 175 can function to protect the lower surface of the first insulating layer 110 and the upper surface of the second insulating layer 120, respectively. Furthermore, the first protective layer 170 and the second protective layer 175 can function to protect the lower surface of the first circuit pattern and the upper surface of the second circuit pattern.

[0108] The first protective layer 170 can partially overlap the first circuit pattern. In the drawings, the first protective layer 170 is shown as having no overlap with the first circuit pattern, but this is only one embodiment, and substantially the first protective layer 170 is positioned to cover at least a portion of the lower surface of the first circuit pattern. The second protective layer 175 can also partially overlap the third circuit pattern. In the drawings, the second protective layer 175 is shown as having no overlap with the third circuit pattern, but this is only one embodiment, and substantially the second protective layer 175 is positioned to cover at least a portion of the upper surface of the third circuit pattern.

[0109] The area of ​​the first protective layer 170 may be smaller than the area of ​​the first insulating layer 110. Similarly, the area of ​​the second protective layer 175 may be smaller than the area of ​​the second insulating layer 120. That is, the first protective layer 170 may include an open region that exposes the lower surface of the first circuit pattern embedded beneath the first insulating layer 110. Furthermore, the second protective layer 175 may include an open region that exposes the upper surface of the third circuit pattern embedded above the second insulating layer 120.

[0110] The following will provide a more detailed explanation of the circuit patterns and via shapes related to the embodiment.

[0111] The first via 160 in the embodiment can have the same shape as the via in the comparative example. The first via 160 can have a shape in which the top and bottom surfaces are flat and the width decreases from one surface to the other, by forming a via hole in the first insulating layer 110 and filling the inside of the formed via hole with a metallic substance.

[0112] On the other hand, the second via 165 can have a different shape from the first via 160. The second via 165 is formed by performing a pressing process with a separately formed bump positioned on the second circuit pattern. As a result, the second via 165 in the embodiment can have a curved surface that bulges in a specific direction rather than having a flat top and bottom surface.

[0113] In other words, the height of the upper surface of the second via 165 can change from one end to the other. For example, the height of the upper surface of the second via 165 can increase from the edge to the center. As a result, the upper surface of the second via 165 can have a curved surface that bulges upward.

[0114] Furthermore, the height of the lower surface of the second via 165 can change from one end to the other. For example, the height of the lower surface of the second via 165 can decrease from the edge to the center. This allows the lower surface of the second via 165 to have a curved surface that bulges downwards.

[0115] Referring to Figure 4, the circuit board includes vias for interlayer conductivity. In this case, the vias are substantially located within an insulating layer. The vias may also include pads (more precisely, via pads) which are circuit patterns located on the surface of the insulating layer.

[0116] Therefore, the vias on the circuit board in the embodiment may include a first via 160, a first via pad 130 connected to the lower surface of the first via 160, a second via pad 140 connected to the upper surface of the first via 160, a second via 165 connected to the upper surface of the second via pad 140, and a third via pad 150 connected to the upper surface of the second via 165.

[0117] In this embodiment, the pressing process is performed with the second via 160 and the third via pad 150 positioned on the second via pad 140 to adhere the second via 165 and the third via pad 150 to the second via pad 140. As a result, the lower surface of the second via 165, the upper surface of the second via pad 140 that contacts the lower surface of the second via 165, the upper surface of the second via 165, the lower surface of the third via pad 150 that contacts the upper surface of the second via 165, and the upper surface that overlaps perpendicularly with the lower surface of the third via pad 150 can have curved surfaces rather than flat surfaces.

[0118] For example, the upper surface of the second via pad 140 may include a first portion that contacts the lower surface of the second via 165 and a second portion other than that. The first portion of the upper surface of the second via pad 140 may have a shape that is recessed downwards. For example, the first portion of the upper surface of the second via pad 140 may be a curved surface. The second portion of the upper surface of the second via pad 140 may be a flat surface.

[0119] The lower surface of the second via 165 may have a shape corresponding to the first portion of the upper surface of the second via pad 140. For example, the lower surface of the second via 165 may have a shape that bulges downward to correspond to the first portion of the upper surface of the second via pad 140. For example, the lower surface of the second via 165 may be curved. This allows at least a portion of the lower surface of the second via 165 to be positioned lower than the second portion of the upper surface of the second via pad 140.

[0120] The upper surface of the second via 165 may have a shape that bulges upward. For example, the upper surface of the second via 165 may have a curved surface. This allows at least a portion of the upper surface of the second via 165 to be positioned higher than at least a portion of the lower surface of the third via pad 150.

[0121] The lower surface of the third via pad 150 may include a first portion that contacts the upper surface of the second via 165 and a second portion other than that. The first portion of the lower surface of the third via pad 150 may have a shape corresponding to the upper surface of the second via 165. For example, the first portion of the upper surface of the third via pad 150 may have a shape that is recessed in the upward direction. For example, the first portion of the lower surface of the third via pad 150 may be a curved surface. The second portion of the upper surface of the second via pad 140 may be a flat surface.

[0122] The upper surface of the third beer pad 150 may include a first portion that overlaps vertically with the first portion of the lower surface of the third beer pad 150, and a second portion that is not the first portion. The first portion of the upper surface of the third beer pad 150 may have a shape corresponding to the first portion of the lower surface of the third beer pad 150. For example, the first portion of the upper surface of the third beer pad 150 may have a shape that bulges upward. For example, the first portion of the upper surface of the third beer pad 150 may have a curved surface.

[0123] Furthermore, the second portion of the upper surface and the second portion of the lower surface of the third via pad 150 may each be flat.

[0124] This is a structural feature that appears during the process of joining the first insulating layer 110 and the second insulating layer 120.

[0125] Specifically, the second insulating layer 120 has a second via 165 and a third via pad 150 formed on it. Then, with the second via 165 positioned on the second via pad 140, a pressing process is performed to bond the second insulating layer 120 onto the first insulating layer 110. At this time, during the pressing process, the lower surface of the second via 165 and the first portion of the upper surface of the second via pad 140 are pressed together in contact. Due to this pressing, the first portion of the upper surface of the second via pad 140 can have a shape that is recessed downwards. The lower surface of the second via 165 can have a bulging shape that fills the first portion of the upper surface of the second via pad 140. At this time, deformation of the lower surface of the second via pad 140 may also occur due to the deformation of the upper surface of the second via pad 140. However, the first via 160 is positioned beneath the second via pad 140, and the support of the first via 160 prevents deformation of the lower surface of the second via pad 140, or if deformation occurs, it cannot be distinguished with the naked eye.

[0126] Furthermore, during the pressing process, the upper surface of the second via 165 and the first portion of the lower surface of the third via pad 150 are pressed together. This pressurization allows the first portion of the lower surface of the third via pad 150 to have an upwardly concave shape. The upper surface of the second via 165 can then have a bulging shape that fills the first portion of the lower surface of the third via pad 150. At this time, the deformation of the first portion of the lower surface of the third via pad 150 causes deformation to occur on the upper surface of the third via pad 150 that is perpendicularly overlapping it. That is, the first portion of the upper surface of the third via pad 150 can have a curved shape that bulges upward to correspond to the first portion of the lower surface of the third via pad 150.

[0127] That is, the embodiment includes a second via pad 140, a third via pad 150, and a second via 165 between them. The contact surface S1 between the upper surface of the second via pad 140 and the lower surface of the second via 165 may have a shape that bulges downward. That is, the lower surface of the second via 165 may bulge downward by a first height H1 from the upper surface of the second via pad 140.

[0128] Furthermore, the contact surface S2 between the lower surface of the third via pad 150 and the upper surface of the second via 165 may have a shape that bulges upward. That is, the upper surface of the second via 165 may bulge upward from the lower surface of the third via pad 150 by a second height H2. In this case, the second height H2 may be greater than the first height H1.

[0129] Furthermore, the portion S3 of the upper surface of the third via pad 150 that overlaps perpendicularly with the contact surface S2 can bulge upward by a third height H3 compared to the other portions of the upper surface of the third via pad 150. In this case, the third height H3 can correspond to the second height H2.

[0130] In this embodiment, a bump substrate including the second insulating layer 120, the third via pad 150, and the second via 165 is positioned on the first insulating layer 110 as described above, and a pressing process is performed to form a circuit board.

[0131] As a result, the third via pad 150 in the embodiment can have a structure embedded within the second insulating layer 120. Furthermore, in the embodiment, the overall thickness of the circuit board can be reduced by the thickness of the third via pad 150.

[0132] That is, the first insulating layer 110 in the embodiment may have a first thickness T1. The first thickness T1 may correspond to the distance from the top surface to the bottom surface of the first insulating layer 110. Also, the second insulating layer 120 in the embodiment may have a second thickness T1. The second thickness T2 may correspond to the distance from the top surface to the bottom surface of the second insulating layer 120. And the first thickness T1 may correspond to the second thickness T2. At this time, the second via pad 140 and the third via pad 150 are all placed within the second insulating layer 120 in the embodiment. As a result, the first via 160 in the embodiment may have a third thickness T3. And the second via 165 in the embodiment may have a fourth thickness T4 which is smaller than the third thickness T3. That is, the first via and the second via in a typical circuit board will have the same thickness as each other. In contrast, in this embodiment, the thickness of the circuit board can be reduced by the thickness of the third circuit pattern, such as the third via pad 150, by embedding the third via pad 150 within the second insulating layer 120. The thickness of the second via 165 is reduced by the thickness of the third circuit pattern, such as the third via pad 150.

[0133] On the other hand, when the second insulating layer 120, the second via 165, and the third circuit pattern are pressed onto the first insulating layer 110 and the second circuit pattern, the second via 165, the second via pad 140, and the third via pad 150 of the second circuit pattern deform due to being pressed while in mutual contact, as described above. In contrast, the second circuit pattern without the second via pad 140, and the third circuit pattern without the third via pad 150, do not deform.

[0134] In other words, as described above, the second and third circuit patterns may include traces and via pads depending on their function. The via pads undergo deformation due to pressure during the pressing process. In contrast, the traces do not undergo deformation due to pressure as described above, thereby maintaining the planar state in which the surface was initially formed.

[0135] That is, the second circuit pattern includes via pads 140 and traces 145. The upper surface of the via pads 140 undergoes a downward deformation due to the pressure from the second vias 165. However, the traces 145 of the second circuit pattern are simply covered by the second insulating layer 120 during the pressing process, and thus no surface deformation occurs. For example, unlike the via pads 140, the upper surface of the traces 145 of the second circuit pattern does not deform, and thus maintains a flat surface corresponding to the initially formed state.

[0136] Furthermore, the third circuit pattern includes via pads 150 and traces 155. The lower surface of the via pad 150 undergoes deformation that causes it to indent upward due to the pressure from the second via 165. The upper surface of the via pad 150 undergoes deformation that causes it to bulge upward due to the pressure from the second via 165. The traces 155 of the third circuit pattern remain simply embedded in the second insulating layer 120 during the pressing process, and thus no surface deformation occurs. For example, unlike the via pad 150, the upper surface of the traces 155 of the third circuit pattern does not deform, and thus maintains a flat surface corresponding to its initially formed state.

[0137] The circuit board of the embodiment includes an outermost circuit pattern arranged on both sides of the insulating layer. In this case, the outermost circuit pattern may include a first outer circuit pattern arranged on the bottom side of at least one insulating layer and a second outer circuit pattern arranged on the top side. In this case, the first outer circuit pattern and the second outer circuit pattern in the embodiment may have a structure in which they are entirely embedded within the insulating layer. Accordingly, in the embodiment, by having a structure in which the first outer circuit pattern and the second outer circuit pattern are entirely embedded within the insulating layer, the thickness of the circuit board can be reduced by the thickness of the first outer circuit pattern and / or the second outer circuit pattern, thereby achieving a slimmer product.

[0138] Furthermore, if only one of the first and second outer layer circuit patterns is embedded in the insulating layer, there is a problem of warping due to the asymmetric structure occurring during the manufacturing process of the circuit board. On the other hand, in this embodiment, since both the first and second outer layer circuit patterns are embedded in the insulating layer, the occurrence of warping of the circuit board can be minimized, thereby improving the reliability of the product.

[0139] Figures 6 to 14 are diagrams showing the manufacturing method of the circuit board illustrated in Figure 2, in order of steps.

[0140] The circuit board in the first embodiment is manufactured by forming a first substrate and a second substrate, and then pressing the second substrate onto the first substrate using a pressing process.

[0141] The first substrate is a circuit board as described in Figures 2 to 5 and may include a first insulating layer 110, a first circuit pattern, a first via 160, and a second circuit pattern. The second substrate is also a circuit board as described in Figures 2 to 5 and may include a second insulating layer 120, a third circuit pattern, and a second via 165.

[0142] Below, we will explain the manufacturing process of circuit boards in detail, focusing on this point.

[0143] Referring to Figure 6, the embodiment allows for the manufacturing of first substrates on both sides of the carrier board 200. That is, in the embodiment of the present application, multiple first substrates can be manufactured simultaneously around the carrier board 200.

[0144] The first substrate is manufactured using the ETS method. For this purpose, in this embodiment, a carrier board 200 can be provided.

[0145] The carrier board 200 may include a carrier film 210 and metal layers 220 and 230 disposed on the upper and lower surfaces of the carrier film 210, respectively.

[0146] The metal layers 220 and 230 are used as seed layers for forming the first circuit pattern on the first substrate.

[0147] In other words, in this embodiment, once the carrier board 200 is prepared, the metal layers 220 and 230 are used as seed layers, and a first circuit pattern is formed on the metal layers 220 and 230.

[0148] At this time, the first circuit pattern is manufactured by the following process. In this embodiment, to form the first circuit pattern, a mask (not shown) having openings can be preferentially formed on the metal layers 220 and 230. The openings in the mask may have openings that expose the area on the surface of the metal layers 220 and 230 in which the first circuit pattern is formed. Next, once the mask is formed, the first circuit pattern can be formed by plating the openings in the mask using the metal layers 220 and 230 as seed layers. The mask is then removed after the first circuit pattern has been formed.

[0149] The first circuit pattern may include a via pad 130 which will be connected to a first via 160 which will be formed later, and a trace 135 which is a signal trace.

[0150] Next, referring to Figure 7, the process of laminating the first insulating layer 110 on the metal layers 220 and 230 can be carried out.

[0151] The first insulating layer 110 is placed on the metal layers 220 and 230, thereby covering the first circuit pattern formed on the metal layers 220 and 230.

[0152] Next, referring to Figure 8, the process of forming a second circuit pattern and a first via 160 on the first insulating layer 110 can be carried out.

[0153] For this purpose, in the embodiment, via holes (not shown) can be formed in the first insulating layer 110. The via holes are formed by penetrating the first insulating layer 110, thereby exposing the upper surface of the via pad 130 of the first circuit pattern arranged on the metal layers 220, 230.

[0154] Once the via hole is formed, the inside of the via hole can be filled with a conductive material to form the first via 160. The metallic material used to form the first via 160 may be any one of the following: copper (Cu), silver (Ag), tin (Sn), gold (Au), nickel (Ni), and palladium (Pd). The filling of the conductive material can be carried out using any one of the following methods, or a combination thereof: electroless plating, electrolytic plating, screen printing, sputtering, evaporation, inkjet method, and dispensing.

[0155] Furthermore, once the first via 160 is formed, the process of forming a second circuit pattern on the first insulating layer 110 can be carried out. The second circuit pattern may include a via pad 140 connected to the first via 160 and traces 145 corresponding to signal wiring.

[0156] Next, referring to Figure 9, the first substrate manufactured according to Figures 6 to 8 above can be separated from the carrier board 200.

[0157] Specifically, the first substrate is manufactured on the upper and lower sides of the carrier board 200, respectively. Then, the first substrate, which includes the metal layer 220 located on the upper side, and the first substrate, which includes the metal layer 230 located on the lower side, can be separated from each other with respect to the carrier film 210 of the carrier board 200.

[0158] As described above, once the first substrate manufactured through the carrier board 200 is separated, the process of manufacturing the second substrate can be carried out. The second substrate is manufactured by a bump formation process. The bumps are used as vias.

[0159] Specifically, referring to Figure 10, in this embodiment, an additional carrier board 200 can be prepared for manufacturing a second substrate. The carrier board 200 may include a carrier film 210 corresponding to the carrier board used in manufacturing the first substrate, and metal layers 220 and 230 disposed on the upper and lower surfaces of the carrier film 210, respectively.

[0160] Once the carrier board 200 is prepared, the process of forming the third circuit pattern and the second via 150 on the carrier board 200 can be carried out.

[0161] Specifically, a process of forming a third circuit pattern on the metal layers 220 and 230 of the carrier board 200 can be carried out. Since the process of forming the third circuit pattern is substantially the same as the process of forming the first circuit pattern, a detailed explanation thereof will be omitted.

[0162] The third circuit pattern may include via pads 150 and traces 155, as shown in the drawing.

[0163] Thereafter, once the third circuit pattern is formed, a step can be performed to form the second via 160 on the via pad 150 of the third circuit pattern. Preferably, in the embodiment, a general post-bump formation step can be performed to form bumps on the via pad 150 of the third circuit pattern. At this time, the bumps are used as the second via 165 on the circuit board.

[0164] Next, referring to Figure 11, once the third circuit pattern and the second via 165 are formed, the process of forming the second insulating layer 120 on the metal layers 220 and 230 can be carried out.

[0165] At this time, the second insulating layer 120 covers the third circuit pattern placed on the metal layers 220 and 230, while the surface of the second via 165 is exposed. Preferably, the surface of the second insulating layer 120 can be positioned lower than the surface of the second via 165, so that the surface of the second via 165 and some of the sides connected thereto remain exposed even after the second insulating layer 120 is formed.

[0166] Next, referring to Figure 12, a process can be carried out to press and bond the manufactured first substrate and the second substrate together.

[0167] That is, the second circuit pattern of the manufactured first substrate is positioned so that it faces upward, and the lower surface of the second via 165 of the second substrate faces downward. Then, the pressing process can be performed with the lower surface of the second via 165 exposed through the second insulating layer 120 aligned with the via pad 140 of the second circuit pattern of the first substrate.

[0168] Then, when the pressing process is performed, the second substrate is attached to the first substrate by the second insulating layer 120.

[0169] Referring to Figure 13, in this embodiment, the first substrate and the second substrate manufactured by the pressing process are bonded together as described above.

[0170] As a result, the first via 160 in the embodiment can have the same shape as the via in the comparative example. The first via 160 can have a shape in which the top and bottom surfaces are flat and the width decreases from one surface to the other, by forming a via hole in the first insulating layer 110 and filling the inside of the formed via hole with a metallic substance.

[0171] On the other hand, the second via 165 can have a different shape from the first via 160. The second via 165 is formed by performing a pressing process with a separately formed bump positioned on the second circuit pattern. As a result, the second via 165 in the embodiment can have a curved surface that bulges in a specific direction rather than having a flat top and bottom surface.

[0172] That is, in the embodiment, the pressing process is performed with the second via 160 and the third via pad 150 positioned on the second via pad 140 to adhere the second via 165 and the third via pad 150 to the second via pad 140. As a result, the lower surface of the second via 165, the upper surface of the second via pad 140 that contacts the lower surface of the second via 165, the upper surface of the second via 165, the lower surface of the third via pad 150 that contacts the upper surface of the second via 165, and the upper surface that overlaps perpendicularly with the lower surface of the third via pad 150 can have curved surfaces rather than flat surfaces.

[0173] For example, the upper surface of the second via pad 140 may include a first portion that contacts the lower surface of the second via 165 and a second portion other than that. The first portion of the upper surface of the second via pad 140 may have a shape that is recessed downwards. For example, the first portion of the upper surface of the second via pad 140 may be a curved surface. The second portion of the upper surface of the second via pad 140 may be a flat surface.

[0174] The lower surface of the second via 165 may have a shape corresponding to the first portion of the upper surface of the second via pad 140. For example, the lower surface of the second via 165 may have a shape that bulges downward to correspond to the first portion of the upper surface of the second via pad 140. For example, the lower surface of the second via 165 may be curved. This allows at least a portion of the lower surface of the second via 165 to be positioned lower than the second portion of the upper surface of the second via pad 140.

[0175] The upper surface of the second via 165 may have a shape that bulges upward. For example, the upper surface of the second via 165 may have a curved surface. This allows at least a portion of the upper surface of the second via 165 to be positioned higher than at least a portion of the lower surface of the third via pad 150.

[0176] The lower surface of the third via pad 150 may include a first portion that contacts the upper surface of the second via 165 and a second portion other than that. The first portion of the lower surface of the third via pad 150 may have a shape corresponding to the upper surface of the second via 165. For example, the first portion of the upper surface of the third via pad 150 may have a shape that is recessed in the upward direction. For example, the first portion of the lower surface of the third via pad 150 may be a curved surface. The second portion of the upper surface of the second via pad 140 may be a flat surface.

[0177] The upper surface of the third beer pad 150 may include a first portion that overlaps vertically with the first portion of the lower surface of the third beer pad 150, and a second portion that is not the first portion. The first portion of the upper surface of the third beer pad 150 may have a shape corresponding to the first portion of the lower surface of the third beer pad 150. For example, the first portion of the upper surface of the third beer pad 150 may have a shape that bulges upward. For example, the first portion of the upper surface of the third beer pad 150 may have a curved surface.

[0178] Furthermore, the second portion of the upper surface and the second portion of the lower surface of the third via pad 150 may each be flat.

[0179] This is a structural feature that appears during the process of joining the first insulating layer 110 and the second insulating layer 120.

[0180] Specifically, the second insulating layer 120 has a second via 165 and a third via pad 150 formed on it. Then, with the second via 165 positioned on the second via pad 140, a pressing process is performed to bond the second insulating layer 120 onto the first insulating layer 110. At this time, during the pressing process, the lower surface of the second via 165 and the first portion of the upper surface of the second via pad 140 are pressed together in contact. Due to this pressing, the first portion of the upper surface of the second via pad 140 can have a shape that is recessed downwards. The lower surface of the second via 165 can have a bulging shape that fills the first portion of the upper surface of the second via pad 140. At this time, deformation of the lower surface of the second via pad 140 may also occur due to the deformation of the upper surface of the second via pad 140. However, the first via 160 is positioned beneath the second via pad 140, and the support of the first via 160 prevents deformation of the lower surface of the second via pad 140, or if deformation occurs, it cannot be distinguished with the naked eye.

[0181] Furthermore, during the pressing process, the upper surface of the second via 165 and the first portion of the lower surface of the third via pad 150 are pressed together. This pressurization allows the first portion of the lower surface of the third via pad 150 to have an upwardly concave shape. The upper surface of the second via 165 can then have a bulging shape that fills the first portion of the lower surface of the third via pad 150. At this time, the deformation of the first portion of the lower surface of the third via pad 150 causes deformation to occur on the upper surface of the third via pad 150 that is perpendicularly overlapping it. That is, the first portion of the upper surface of the third via pad 150 can have a curved shape that bulges upward to correspond to the first portion of the lower surface of the third via pad 150.

[0182] That is, the embodiment includes a second via pad 140, a third via pad 150, and a second via 165 between them. The contact surface S1 between the upper surface of the second via pad 140 and the lower surface of the second via 165 may have a shape that bulges downward. That is, the lower surface of the second via 165 may bulge downward by a first height H1 from the upper surface of the second via pad 140.

[0183] Furthermore, the contact surface S2 between the lower surface of the third via pad 150 and the upper surface of the second via 165 may have a shape that bulges upward. That is, the upper surface of the second via 165 may bulge upward from the lower surface of the third via pad 150 by a second height H2. In this case, the second height H2 may be greater than the first height H1.

[0184] Furthermore, the portion S3 of the upper surface of the third via pad 150 that overlaps perpendicularly with the contact surface S2 can bulge upward by a third height H3 compared to the other portions of the upper surface of the third via pad 150. In this case, the third height H3 can correspond to the second height H2.

[0185] In this embodiment, a bump substrate including the second insulating layer 120, the third via pad 150, and the second via 165 is positioned on the first insulating layer 110 as described above, and a pressing process is performed to form a circuit board.

[0186] As a result, the third via pad 150 in the embodiment can have a structure embedded within the second insulating layer 120. Furthermore, in the embodiment, the overall thickness of the circuit board can be reduced by the thickness of the third via pad 150.

[0187] That is, the first insulating layer 110 in the embodiment may have a first thickness T1. The first thickness T1 may correspond to the distance from the top surface to the bottom surface of the first insulating layer 110. Also, the second insulating layer 120 in the embodiment may have a second thickness T1. The second thickness T2 may correspond to the distance from the top surface to the bottom surface of the second insulating layer 120. And the first thickness T1 may correspond to the second thickness T2. At this time, the second via pad 140 and the third via pad 150 are all placed within the second insulating layer 120 in the embodiment. As a result, the first via 160 in the embodiment may have a third thickness T3. And the second via 165 in the embodiment may have a fourth thickness T4 which is smaller than the third thickness T3. That is, the first via and the second via in a typical circuit board will have the same thickness as each other. In contrast, in this embodiment, the thickness of the circuit board can be reduced by the thickness of the third circuit pattern, such as the third via pad 150, by embedding the third via pad 150 within the second insulating layer 120. The thickness of the second via 165 is reduced by the thickness of the third circuit pattern, such as the third via pad 150.

[0188] On the other hand, when the second insulating layer 120, the second via 165, and the third circuit pattern are pressed onto the first insulating layer 110 and the second circuit pattern, the second via 165, the second via pad 140, and the third via pad 150 of the second circuit pattern deform due to being pressed while in mutual contact, as described above. In contrast, the second circuit pattern without the second via pad 140, and the third circuit pattern without the third via pad 150, do not deform.

[0189] In other words, as described above, the second and third circuit patterns may include traces and via pads depending on their function. The via pads undergo deformation due to pressure during the pressing process. In contrast, the traces do not undergo deformation due to pressure as described above, thereby maintaining the planar state in which the surface was initially formed.

[0190] That is, the second circuit pattern includes via pads 140 and traces 145. The upper surface of the via pads 140 undergoes a downward deformation due to the pressure from the second vias 165. However, the traces 145 of the second circuit pattern are simply covered by the second insulating layer 120 during the pressing process, and thus no surface deformation occurs. For example, unlike the via pads 140, the upper surface of the traces 145 of the second circuit pattern does not deform, and thus maintains a flat surface corresponding to the initially formed state.

[0191] Furthermore, the third circuit pattern includes via pads 150 and traces 155. The lower surface of the via pad 150 undergoes deformation that causes it to indent upward due to the pressure from the second via 165. The upper surface of the via pad 150 undergoes deformation that causes it to bulge upward due to the pressure from the second via 165. The traces 155 of the third circuit pattern remain simply embedded in the second insulating layer 120 during the pressing process, and thus no surface deformation occurs. For example, unlike the via pad 150, the upper surface of the traces 155 of the third circuit pattern does not deform, and thus maintains a flat surface corresponding to its initially formed state.

[0192] Next, in the embodiment, a step can be performed to remove the metal layer disposed on the lower surface of the first insulating layer 110 and the upper surface of the second insulating layer 120.

[0193] Then, once the metal layer is removed, a step can be performed to form protective layers 170 and 175 on the lower surface of the first insulating layer 110 and the upper surface of the second insulating layer 120, respectively.

[0194] The circuit board of the embodiment includes an outermost circuit pattern arranged on both sides of the insulating layer. In this case, the outermost circuit pattern may include a first outer circuit pattern arranged on the bottom side of at least one insulating layer and a second outer circuit pattern arranged on the top side. In this case, the first outer circuit pattern and the second outer circuit pattern in the embodiment may have a structure in which they are entirely embedded within the insulating layer. Accordingly, in the embodiment, by having a structure in which the first outer circuit pattern and the second outer circuit pattern are entirely embedded within the insulating layer, the thickness of the circuit board can be reduced by the thickness of the first outer circuit pattern and / or the second outer circuit pattern, thereby achieving a slimmer product.

[0195] Furthermore, if only one of the first and second outer layer circuit patterns is embedded in the insulating layer, there is a problem of warping due to the asymmetric structure occurring during the manufacturing process of the circuit board. On the other hand, in this embodiment, since both the first and second outer layer circuit patterns are embedded in the insulating layer, the occurrence of warping of the circuit board can be minimized, thereby improving the reliability of the product.

[0196] Figure 15 is a diagram showing a circuit board according to the second embodiment. Referring to Figure 15, the circuit board 300 according to the second embodiment has a difference in the number of insulating layers compared to the circuit board 100 according to the first embodiment.

[0197] That is, while the circuit board 100 of the first embodiment included two insulating layers, the circuit board 300 of the second embodiment may include one insulating layer.

[0198] In other words, the circuit board 300 includes an insulating layer 310. Furthermore, the circuit board 300 may include a first circuit pattern and a second circuit pattern, which are embedded and positioned above and below the insulating layer 310, respectively.

[0199] The first circuit pattern may be embedded beneath the insulating layer 310 and may include via pads 320.

[0200] Furthermore, the second circuit pattern may be embedded on top of the insulating layer 310 and may include via pads 330.

[0201] Furthermore, vias 340 are formed within the insulating layer 310 to electrically connect the first circuit pattern and the second circuit pattern.

[0202] Furthermore, protective layers 350 and 360 are formed on the upper and lower surfaces of the insulating layer, respectively.

[0203] In this case, the first substrate in the second embodiment may include only the first circuit pattern. Furthermore, the second substrate may be identical to the second substrate in the first embodiment.

[0204] As a result, via 340 in the second embodiment can have the same structure as the second via 165 in the first embodiment.

[0205] Furthermore, the first circuit pattern in the second embodiment may have the same structure as the second circuit pattern in the first embodiment. However, in the first embodiment, the presence of the first via below the second circuit pattern prevented deformation of the lower surface of the second circuit pattern during the pressing process. In contrast, in the second embodiment, the absence of an additional metal layer below the first circuit pattern allows deformation to occur during the pressing process. For example, the lower surface of the first circuit pattern in the second embodiment may include a portion that bulges downward in the region that overlaps perpendicularly with the lower surface of the via 340.

[0206] Furthermore, the second circuit pattern in the second embodiment can have the same structure as the third circuit pattern in the first embodiment.

[0207] Figure 16 is a diagram showing a circuit board according to the third embodiment. Referring to Figure 16, the circuit board 100A may include a first insulating layer 110, a second insulating layer 120, a first circuit pattern, a second circuit pattern, a third circuit pattern, a first via 160, a second via 165a, a first protective layer 170, and a second protective layer 175.

[0208] In this case, the difference between the configuration of the circuit board 100A in the third embodiment and the configuration of the circuit board in the first embodiment lies in the shape of the second via.

[0209] In other words, the second via 165 in the first embodiment had a trapezoidal shape in which the width gradually decreased from the top to the bottom. In contrast, the second via 165a in the second embodiment can have the same width on its top and bottom surfaces. For example, the second via 165 can be formed by a bump formation process, thereby having a columnar shape with the same area on its top and bottom surfaces.

[0210] Furthermore, the shapes of the upper and lower surfaces of the second via 165a, the upper surface of the second circuit pattern, and the upper and lower surfaces of the third circuit pattern in the third embodiment can correspond to the shapes of the upper and lower surfaces of the second via 165, the upper surface of the second circuit pattern, and the upper and lower surfaces of the third circuit pattern in the first embodiment.

[0211] On the other hand, in the embodiment, a package substrate can be manufactured using the circuit board described above.

[0212] For example, an adhesive portion (not shown) may be placed on the pad 150 of the circuit board. A chip is then placed on the adhesive portion.

[0213] For example, multiple pads 150 are formed spaced apart in the width direction, and multiple chips are mounted on top of the multiple pads.

[0214] For example, one of the following chips may be mounted on the pad 150: a central processor (e.g., a CPU), a graphics processor (e.g., a GPU), a digital signal processor, an encryption processor, a microprocessor, or a microcontroller.

[0215] For example, at least two different chips from among a central processor (e.g., CPU), a graphics processor (e.g., GPU), a digital signal processor, an encryption processor, a microprocessor, and a microcontroller may be mounted on the pad.

[0216] The circuit board of the embodiment includes an outermost circuit pattern arranged on both sides of the insulating layer. In this case, the outermost circuit pattern may include a first outer circuit pattern arranged on the bottom side of at least one insulating layer and a second outer circuit pattern arranged on the top side. In this case, the first outer circuit pattern and the second outer circuit pattern in the embodiment may have a structure in which they are entirely embedded within the insulating layer. Accordingly, in the embodiment, by having a structure in which the first outer circuit pattern and the second outer circuit pattern are entirely embedded within the insulating layer, the thickness of the circuit board can be reduced by the thickness of the first outer circuit pattern and / or the second outer circuit pattern, thereby achieving a slimmer product.

[0217] Furthermore, if only one of the first and second outer layer circuit patterns is embedded in the insulating layer, there is a problem of warping due to the asymmetric structure occurring during the manufacturing process of the circuit board. On the other hand, in this embodiment, since both the first and second outer layer circuit patterns are embedded in the insulating layer, the occurrence of warping of the circuit board can be minimized, thereby improving the reliability of the product.

[0218] Furthermore, the circuit board in the embodiment is applicable to 5G communication systems, thereby minimizing high-frequency transmission loss and further improving reliability. Specifically, the circuit board in the embodiment can be used at high frequencies and can reduce radio wave loss.

[0219] The features, structures, and effects described in the above embodiments are included in at least one embodiment of the present invention, and are not necessarily limited to a single embodiment. Furthermore, the features, structures, and effects exemplified in each embodiment can be combined or modified for implementation in other embodiments by a person with ordinary skill in the art to which the embodiment belongs. Therefore, such combinations and modifications should be interpreted as being included within the scope of the present invention.

[0220] Furthermore, although the above description has focused on embodiments, these are merely examples and do not limit the present invention. Anyone with ordinary skill in the art to which the present invention belongs can make various modifications and applications not exemplified above, without departing from the essential characteristics of these embodiments. For example, each component specifically presented in the embodiments can be modified and implemented. Such differences resulting from modifications and applications should be interpreted as being within the scope of the present invention as defined in the appended claims.

Claims

1. Insulating layer and, A first electrode disposed on the lower surface of the insulating layer, A second electrode disposed on the upper surface of the insulating layer, The present invention includes a third electrode positioned between the first electrode and the second electrode, and penetrating at least a portion of the insulating layer in a vertical direction, The third electrode has a width that decreases horizontally from the second electrode toward the first electrode. The lower surface of the third electrode includes a first convex portion that is convex toward the first electrode. The upper surface of the first electrode includes a first recess that is concave toward the lower surface of the first electrode. The first recess and the first protrusion have the same width along the horizontal direction. The upper surface of the second electrode includes a second convex portion that is convex in the direction away from the first electrode, wherein the circuit board.

2. The circuit board according to claim 1, wherein the second protrusion of the second electrode overlaps with the first protrusion of the third electrode along the vertical direction.

3. The upper surface of the second electrode includes a first flat portion that extends horizontally from the second protrusion, The circuit board according to claim 2, wherein the first flat portion is located lower than the second convex portion with reference to the upper surface of the insulating layer.

4. The circuit board according to claim 3, wherein the first flat portion of the second electrode is parallel to the upper surface of the insulating layer.

5. The circuit board according to any one of claims 2 to 4, wherein the lower surface of the second electrode includes a second recess that is concave toward the second convex portion and a second flat portion that extends from the second recess along the horizontal direction.

6. The circuit board according to claim 5, wherein the second flat portion of the second electrode is positioned lower than the second recess of the second electrode and is parallel to the upper surface of the insulating layer.

7. The circuit board according to claim 5, wherein the upper surface of the third electrode is in contact with the second recess and includes a third convex portion that is convex toward the second convex portion of the second electrode.

8. The lower surface of the first electrode includes a fourth convex portion that is convex in the direction away from the third electrode. The circuit board according to any one of claims 1 to 7, wherein the fourth protrusion of the first electrode overlaps with the first protrusion of the third electrode along the vertical direction.

9. The lower surface of the first electrode includes a third flat portion that extends horizontally from the fourth protrusion, The circuit board according to claim 8, wherein the third flat portion of the first electrode is positioned higher than the fourth convex portion of the first electrode.

10. The circuit board according to claim 9, wherein the third flat portion of the first electrode is parallel to the lower surface of the insulating layer.

11. The circuit board according to claim 9 or 10, wherein the first recess and the first protrusion have the same width along the horizontal direction.

12. The upper surface of the first electrode includes a fourth flat portion extending from the first recess along the horizontal direction, The circuit board according to any one of claims 1 to 11, wherein the fourth flat portion is located higher than the first recess of the first electrode and is parallel to the lower surface of the insulating layer.

13. The circuit board according to claim 9, wherein the first recess of the first electrode does not overlap with the inclination of the side surface of the third electrode along the vertical direction.

14. The trace further includes a trace that is separated from the second electrode along the horizontal direction and overlaps with the second electrode along the horizontal direction, The circuit board according to claim 3, wherein the upper surface of the trace is positioned lower than the second protrusion of the second electrode with reference to the upper surface of the insulating layer.

15. The circuit board according to claim 14, wherein the upper surface of the insulating layer, the upper surface of the trace, and the first flat portion of the second electrode are located on the same plane.

16. The circuit board according to any one of claims 1 to 15, wherein the first electrode, the second electrode, and the third electrode are embedded in the insulating layer.

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