Method and apparatus for testing multi-die integrated circuits

Abstract

An integrated circuit (IC) die in a multi-die IC package is described having a test access port (TAP) with a test data input (TDI), a test data output (TDO), a test clock (TCK), and a test mode select (TMS). The IC die includes a joint test action group (JTAG) controller having a JTAG interface including the TDI, TDO, TCK, and TMS, a first output coupled to a first routing in the multi-die IC package, a first input coupled to either the first routing or a second routing in the multi-die IC package, a master return path coupled to the first input, and a wrapper circuit configured to couple the TDI of the TAP to the TDI of the JTAG controller and to selectively couple the TDO of the TAP to either the master return path or the TDO of the JTAG controller in response to a first control signal.

Description

Technical Field

[0001] Technical Field Examples of the present disclosure generally relate to electronic circuits, and more particularly to implementing a JTAG device chain within a multi-die integrated circuit.

Background Art

[0002] Background The JTAG interface is a well-known interface established by the Joint Test Action Group (JTAG). The JTAG interface is incorporated into IEEE 1149.1 (referred to herein as the "JTAG standard"), a standard that defines boundary scan test logic for integrated circuits (ICs). The JTAG interface provides a 4-pin interface that uses serial data shifting to perform a number of test and debug functions on a device. The JTAG standard includes various rules that define how the JTAG controller should operate, such as the IDCODE register being 32 bits and the BYPASS instruction inserting a one-register delay on the shift chain. The standard further specifies that the JTAG controller operates in two phases. First, an instruction phase in which instructions are sequentially shifted into the controller. Second, a data phase in which data associated with an active instruction is shifted into a selected JTAG data register. The length of the data register varies depending on the instruction, but the length of the instruction register should remain constant.

[0003] The JTAG standard also includes methods for chaining multiple JTAG controllers together. One technique involves daisy-chaining each JTAG controller across multiple devices such that one output is coupled to the next input, with the JTAG input on the first device and the JTAG output on the last device. This technique makes it possible to create a single long series shift chain on a circuit board with multiple devices. The daisy-chain technique was developed to connect multiple chips on a board. However, consider a multi-die integrated circuit (IC) package having multiple devices, each having a JTAG controller coupled in a daisy-chain manner as described above. From the outside, the JTAG network within the IC package is designed to appear to the user as a single JTAG controller. Achieving this and maintaining compliance with the JTAG standard requires some sacrifices that affect JTAG performance. For example, as mentioned above, the BYPASS instruction requires that only a single delay be set between the data input and the data output. However, the data input is to the first device in the chain, and the data output is from the last device in the chain. To comply with the JTAG standard, multi-die IC packages must include long wires running through all the dies from start to finish. Such long wires limit the maximum frequency at which the JTAG interface can operate for multi-die packages. [Overview of the project] [Means for solving the problem]

[0004] overview Techniques for implementing a JTAG device chain in a multi-die integrated circuit are described. One example describes an integrated circuit (IC) package having a test access port (TAP) with a test data input (TDI), test data output (TDO), test clock (TCK), and test mode selector (TMS). The IC package includes a master integrated circuit (IC) die including a master joint test action group (JTAG) controller and a master wrapper circuit coupled to the master JTAG controller; a slave IC die including a slave JTAG controller and a slave wrapper circuit coupled to the slave JTAG controller; a transfer path coupling the output of the master wrapper circuit to a first input of the slave wrapper circuit; and a master return path coupling the first output of the slave wrapper circuit to the input of the master wrapper circuit, wherein the master wrapper circuit couples the TDI of the TAP to the TDI of the master JTAG controller and, in response to a first control signal, selectively couples the TDO of the TAP to either the master return path or the TDO of the master JTAG controller.

[0005] Another example describes an integrated circuit (IC) die in a multi-die IC package having a test access port (TAP) with a test data input (TDI), test data output (TDO), test clock (TCK), and test mode selector (TMS). The IC die comprises a Joint Test Action Group (JTAG) controller having a JTAG interface including TDI, TDO, TCK, and TMS; a first output coupled to a first routing in the multi-die IC package; a first input coupled to either a first or second routing in the multi-die IC package; a master return path coupled to the first input; and a wrapper circuit configured to couple the TDI of the TAP to the TDI of the JTAG controller and to selectively couple the TDO of the TAP to either the master return path or the TDO of the JTAG controller in response to a first control signal.

[0006] Another example describes a method for testing a multi-die integrated circuit (IC) package having a test access port (TAP) including a test data input (TDI), a test data output (TDO), a test clock (TCK), and a test mode selector (TMS), wherein the multi-die IC package further includes a master IC die and a slave IC die. The method includes the steps of: coupling the TDO of the TAP to a master return path from the slave IC die to the master IC die by a master wrapper circuit in the master IC die in response to a first control signal output by a first control circuit in the master IC die; receiving an instruction in a master JTAG controller in the master IC die via the TDI of the TAP and in a slave JTAG controller in the slave IC die via a transfer path from the master IC die to the slave IC die; determining by the first control circuit that the instruction requires data to be routed only through the master IC die and changing the state of the first control signal; and coupling the TDO of the TAP to the TDO of the master JTAG controller by the master wrapper circuit in response to a first control signal output by the first control circuit.

[0007] These and other embodiments can be understood by referring to the detailed description below. Brief explanation of the drawing To ensure a detailed understanding of the above features, more specific explanations than those briefly summarized above can be obtained by referring to exemplary implementations, some of which are shown in the attached diagrams. However, it should be noted that the attached diagrams only show typical exemplary implementations and should therefore not be considered limiting. [Brief explanation of the drawing]

[0008] [Figure 1A] A carbon atom representing an example of an integrated circuit (IC) device. [Figure 1B] A block diagram showing different signal interfaces of an IC die as an example. [Figure 2] This is a block diagram showing an example of a JTAG circuit. [Figure 3] This block diagram shows, as an example, a wrapper circuit, a master return circuit, and a control circuit coupled to a JTAG controller. [Figure 4] This is a block diagram showing an example of a JTAG controller. [Figure 5] A block diagram showing a master IC die coupled to a slave IC die as an example. [Figure 6A] A side view of an example multi-die IC package is shown. [Figure 6B] Another example of a multi-die IC package is shown in the side view. [Figure 7] This block diagram shows an example of an IC test system. [Figure 8] This flowchart illustrates the operation of a master IC die during testing of a multi-die IC package, as an example. [Figure 9] This flowchart illustrates the operation of a slave IC die during testing of a multi-die IC package as an example. [Figure 10A] This block diagram shows an example of a programmable device. [Figure 10B] This is a block diagram showing an example of a programmable IC. [Figure 10C] Figure 10B shows an example of a field-programmable gate array (FPGA) implementation of the programmable IC, including its programmable logic. [Modes for carrying out the invention]

[0009] For ease of understanding, the same reference number is used to indicate identical elements common to multiple figures, where possible. An element from one example may be usefully incorporated into another.

[0010] Detailed explanation Various features are described below with reference to the drawings. Note that the drawings may or may not be drawn to scale, and elements of similar structure or function are represented by the same reference numerals throughout the drawings. Note that the drawings are intended solely to facilitate the description of the features. They are not intended as an exhaustive description of the claimed invention or as a limitation on the scope of the claimed invention. Furthermore, the illustrated examples do not necessarily have all the embodiments or advantages shown. Embodiments or advantages described in relation to the examples are not necessarily limited to those examples and may be implemented in any other examples, even if not shown or explicitly described as such.

[0011] This document describes a technique for implementing a JTAG device chain in a multi-die integrated circuit. In the example, JTAG controllers on master and slave IC dies within a package are daisy-chained together via the package (e.g., via an interposer). The primary JTAG interface, a four-signal interface exposed to the user, is active only on the master IC die. A serial shift chain is initiated at the master and propagated to the first slave. The connection from master to slave is made using the JTAG interface connected via the package (e.g., via an interposer). This connection continues among the slaves up to the last slave. The package configures the last slave to loop the chain to the master return path. The master return path is used to return JTAG data to the master die in order to send the TDO of the package's JTAG interface. In the example, the return path on each die has a re-buffering element to improve the performance of the JTAG interface. These and further aspects of the disclosed technique can be understood by referring to the description of the drawings.

[0012] Figure 1A is a block diagram showing an example of a multi-die integrated circuit (IC) device 100. The multi-die IC device 100 includes a master IC die 102M and at least one slave IC die 102S-1...102S-n, where n is an integer greater than 0 (collectively referred to as slave die 102S). The master IC die 102M and the slave IC dies 102S are collectively referred to as IC die 102. The master IC die 102M and the slave IC dies 102S are arranged within a multi-die IC package 104. In this example, the IC dies 102 are arranged side by side on an interposer (sometimes referred to as a 2.5D package). In other examples, the IC dies are arranged vertically within a three-dimensional stack (referred to as a 3D package). The coupling of the master IC die 102M and slave IC die 102S described herein does not presuppose a specific structure of IC die 102 within the multi-die IC package 104. Figures 6A and 6B, described below, show two exemplary structures of a multi-die IC package 104 that can be used to connect JTAG devices using the techniques described herein.

[0013] The multi-die IC package 104 includes a test access port (TAP) 106 with a test data input (TDI), test data output (TDO), test mode selection (TMS), and test clock (TCK). The TDI, TDO, TMS, and TCK of the TAP 106 have external contacts on the multi-die IC package 104 and are accessible by an external tester. Each of the master IC die 102M and slave IC die 102S includes a JTAG controller 201 and a wrapper circuit 204 coupled to the JTAG controller 201. The TMS and TCK of the TAP 106 are coupled to the TMS and TCK of each JTAG controller in the IC die 102, respectively. Together with the control logic, the wrapper circuit 204 in each IC die 102 configures the IC die 102 as either a master or a slave. In this example, the master IC die 102M is configured as the master. Along with the control logic, the wrapper circuit 204 within each IC die 102 configures the IC die 102 to route the JTAG input to the same die or the next die in the chain. In this example, the master IC die 102M is configured in a master configuration, and each slave IC die 102S is configured in a slave configuration.

[0014] In the master configuration, within the master IC die 102M, the wrapper circuit 204 couples the TDI to the JTAG controller 201. The master IC die 102M dynamically operates in either the same die configuration or the next die configuration according to the JTAG commands. In the same die configuration, the wrapper circuit 204 within the master IC die 102M couples the TDO of the JTAG controller 201 to the TDO of the TAP 106. Therefore, in the same die configuration, the JTAG data propagates only through the master IC die 102M during the data phase. During the instruction phase, the data propagates through all the IC dies 102 regardless of the same / next die configuration. In the next die configuration, the wrapper circuit 204 within the master die 102M couples the TDO of the JTAG controller 201 to the transfer path 108 that serially couples each slave IC die 102S to the master IC die 102M. Therefore, in the next die configuration, the JTAG data propagates from the master IC die 102M to the slave IC die 102S-1.

[0015] In the slave configuration, the wrapper circuit 204 within each slave IC die 102S couples the transfer path 108 to the TDI of each respective JTAG controller 201. Also, each slave IC die 102S operates in the next die configuration. In the next die configuration, the wrapper circuit 204 within each slave IC die 102S couples the TDO of its respective JTAG controller 201 to the transfer path 108. Therefore, the JTAG data propagates serially from the master IC die 102M through each slave IC die 102S until it is consumed by the slave IC die 102S-n.

[0016] The master return path 110 couples each slave IC die 102S in series to the master IC die 102M. The multi-die IC package 104 is configured to couple the transfer path 108 to the master return path 110 after the slave IC die 102S-n. In the next die configuration, the wrapper circuit 204 within the slave IC die 102S functions to form the master return path 110 to the master IC die 102M. In the next die configuration, the wrapper circuit 204 within the master IC die 102M couples the master return path 110 to the TDO of the TAP 106. Thereby, JTAG data can be shifted into each IC die 102 via the TDI of the TAP 106 and backed out via the TDO of the TAP 106. As will be described later, the master IC die 102M can be configured in the same die configuration when the instruction requirement instructs that only the master IC die 102M is connected to the TAP 106 (e.g., in the case of the BYPASS or IDCODE instruction). The master IC die 102M can be configured in the next die configuration when the instruction requirement instructs that all IC dies 102 are connected to the TAP 106 (e.g., in the case of the EXTEST and SAMPLE / PRELOAD instructions).

[0017] FIG. 1B is a block diagram showing different signal interfaces of the IC die 102 according to an example. The IC die 102 includes an interface 112 having four contacts EXT_TDI, EXT_TDO, EXT_TCK, and EXT_TMS designated by contacts 112-1 to 112-4, respectively. Contacts 112-3 and 112-4 of the interface 112 are coupled to the TCK and TMS of the TAP 106, respectively (e.g., EXT_TCK receives TCK and EXT_TMS receives TMS). When the IC die 102 is a master, contacts 112-1 and 112-2 of the interface 112 are coupled to the TDI and TDO of the TAP 106, respectively (e.g., EXT_TDI receives TDI and EXT_TDO supplies TDO). When the IC die 102 is a slave, contacts 112-1 and 112-2 are not connected (e.g., high impedance).

[0018] The IC die 102 includes an interface 116 having four contacts INT_TDO, INT_TDI, INT_TDO_MR_OUT, and INT_TDO_MR_IN, which are designated by contacts 116-1 to 116-4, respectively. Interface 116 is not exposed outside the multi-die IC package 104. Rather, interface 116 is coupled only to routing located within the multi-die IC package 104.

[0019] The JTAG controller 201 includes an interface 114 with JTAG_TDI, JTAG_TDO, JTAG_TCK, and JTAG_TMS, which are specified by contacts 118-1 to 118-4, respectively. A wrapper circuit 204 in the IC die 102 (shown in Figure 1A) couples EXT_TCK and EXT_TMS to JTAG_TCK and JTAG_TMS, respectively. That is, the clock and mode selection signals pass through the wrapper circuit 204 to the JTAG controller 201. The wrapper circuit 204 selectively couples JTAG_TDI and JTAG_TDO to interfaces 112 and 116, depending on the master / slave and same / next configuration.

[0020] Figure 2 is a block diagram showing an example of a JTAG circuit 203. The JTAG circuit 203 includes a wrapper circuit 204, a JTAG controller 201, a control circuit 208, and a master return circuit 209. EXT_TDI, EXT_TDO, INT_TDI, INT_TDO, and INT_TDO_MR_OUT are each coupled to the wrapper circuit 204. The wrapper circuit 204 passes EXT_TCK and EXT_TMS to the JTAG controller 201. The JTAG controller 201 is coupled to the boundary scan register (BSCAN210) in the IC die 102. The wrapper circuit 204 receives a control signal 228 from the control circuit 208. The wrapper circuit 204 is further coupled to the master return circuit 209. The master return circuit 209 provides an interface between INT_TDO_MR_IN and the wrapper circuit 204. The wrapper circuit 204 includes multiplexed logic controlled by the control circuit 208, as will be further described below.

[0021] Figure 3 is a block diagram showing an example of a wrapper circuit 204 coupled to a JTAG controller 201, a master return circuit 209, and a control circuit 208. The wrapper circuit 204 includes multiplexers 302 and 314, and demultiplexers 306 and 312. Multiplexer 302 includes a first input ("0" input) coupled to EXT_TDI, a second input ("1" input) coupled to INT_TDI, and an output coupled to JTAG_TDI of the JTAG controller 201. Demultiplexer 306 includes an input coupled to JTAG_TDO of the JTAG controller 201, a first output ("0" output) coupled to INT_TDO, and a second output ("1" output) coupled to the second input ("1" input) of multiplexer 314. Multiplexer 314 includes a first input ("0" input) coupled to the output of master return circuit 209, the second input described above, and an output coupled to the input of demultiplexer 312. Demultiplexer 312 includes a first output ("0" output) coupled to EXT_TDO and a second output ("1" output) coupled to INT_TDO_MR_OUT.

[0022] In one example, the master return circuit 209 includes a flip-flop 308 and a falling-edge flip-flop 310. As used herein, a “falling-edge” flip-flop loads data into its input on each falling edge of the applied clock signal, as opposed to each rising edge of the clock signal. The falling-edge flip-flop is indicated in the drawing by a sphere in its clock port. The input (D) of flip-flop 308 is connected to INT_TDO_MR_IN. The output (Q) of the flip-flop is coupled to the input (D) of the falling-edge flip-flop 310. The output (Q) of the falling-edge flip-flop 310 is coupled to the first input (0) of the multiplexer 314. The clock ports of flip-flop 308 and the falling-edge flip-flop 310 are coupled to EXT_TCK.

[0023] The control circuit 208 includes an input 316 coupled to the output of the JTAG controller 201. The control circuit 208 generates control signals 228-1 and 228-2, respectively, called the slave and the same. Control signal 228-1 is coupled to the control ports of the multiplexer 302 and the demultiplexer 312. Control signal 228-2 is coupled to the control ports of the demultiplexer 306 and the multiplexer 314.

[0024] Figure 4 is a block diagram of an example JTAG controller 201. The BSCAN register 210 is shown for clarity and is not part of the JTAG controller 201, but rather distributed throughout the inputs / outputs of the IC die 102. The JTAG controller 201 includes a TAP controller 402, instruction logic 420, device ID register 404, bypass register 406, other registers 408, demultiplexer 403, multiplexer 412, and multiplexer 413. The instruction logic 420 includes instruction register 414 and instruction decoder 416. The other registers 408, along with the device ID register 404, bypass register 406, and BSCAN register 210, comprise data logic 418.

[0025] JTAG_TDI is coupled to the input of demultiplexer 403. The output of demultiplexer 403 is coupled to the inputs of BSCAN register 210, other registers 408, bypass register 406, device ID register 404, and instruction register 414. The outputs of BSCAN register 210, other registers 408, bypass register 406, and device ID register 404 are coupled to the input of multiplexer 412. The output of multiplexer 412 is coupled to the first input of multiplexer 413. The first output of instruction register 414 is coupled to the second input of multiplexer 413. The second output of instruction register 414 is coupled to the input of instruction decoder 416. The output of multiplexer 413 is coupled to JTAG_TDO.

[0026] The first output of the instruction decoder 416 is coupled to the control input of the multiplexer 412. The second output of the instruction decoder 416 is coupled to the first input 316-1 of the control circuit 208. The inputs of the TAP controller 402 are coupled to JTAG_TCK and JTAG_TMS. The first output of the TAP controller 402 is coupled to the input 316-2 of the control circuit 208. The second output of the TAP controller 402 is coupled to the instruction logic 420. The third output of the TAP controller 402 is coupled to the data logic 418. The fourth output of the TAP controller 402 is coupled to the control input of the demultiplexer 403.

[0027] During operation, the TAP controller 402 implements a state machine having multiple states that control the retrieval of information from set and selected registers. Transitions between states of the TAP controller 402 are controlled by the JTAG_TMS signal, sampled according to the JTAG_TCK signal. The demultiplexer 403 selectively couples JTAG_TDI to one input of a register, and the multiplexer 412 selectively couples one output of a data register to the input of the multiplexer 413. The multiplexer 413 then selects either one output of the data register or the output of the instruction register 414. The TAP controller 402 controls the demultiplexer 403 and the multiplexer 413 based on its phase (instruction phase or data phase). The instruction decoder 416 controls the multiplexer 412 based on the current instruction. The states of the TAP controller 402 are described in detail in the IEEE 1149.1 standard and are well known. In particular, the TAP controller 402 includes a shift data state that controls when data is shifted to one of the data registers. Serial data transfer occurs when the shift data state is an active logic state (e.g., active logic row according to IEEE 1149.1). The bypass register 406 is typically a one-bit register that allows information on the JTAG bus directed to another device to bypass the JTAG controller of the preceding device. The device ID register 404 can store the identifier of a device. Note that the configuration of the JTAG controller 201 shown in Figure 4 is merely one example of a configuration. Those skilled in the art will understand that the techniques described herein can be used with JTAG controllers having other configurations.

[0028] Figure 5 is a block diagram showing a master IC die 102M coupled to a slave IC die 102S-1 in one example. In the example in Figure 5, the slave IC die 102S includes only the slave IC die 102S-1. The master IC die 102M includes the master wrapper circuit 204M and the master JTAG controller 201M. The slave IC die 102S-1 includes the slave wrapper circuit 204S and the slave JTAG controller 201S. In Figure 5, the master IC die 102M is associated with the suffix "M", and the slave IC die 102S is associated with the suffix "S".

[0029] Referring to Figure 3-5, the master IC die 102M is configured as the master. The control circuit 208 within the master IC die 102M sets the slave signal to select "0" so that the multiplexer 302 selects EXT_TDI (112M-1) and the demultiplexer 312 selects EXT_TDO (112M-2). The multi-die IC package 104 includes routing 504-1 which couples EXT_TDI to the TDI of TAP106 and routing 504-2 which couples EXT_TDO to the TDO of TAP106. As mentioned above, the TMS and TCK of TAP106 are coupled to EXT_TMS and EXT_TCK of each IC die 102, and are omitted from Figure 5 for clarity. Since the control circuit 208 sets the signal slave to logic "0", the master wrapper circuit 204M couples EXT_TDI to the JTAG_TDI of the master JTAG controller 201M. The INT_TDI(116M-2) and INT_TDO_MR_OUT(116M-3) of the master IC die 102M are not connected within the multi-die IC package 104 (e.g., high impedance).

[0030] The multi-die IC package 104 includes routing 502-1 that couples the INT_TDO (116M-1) of the master IC die 102M to the INT_TDI (116S-2) of the slave IC die 102S-1. The slave IC die 102S-1 is configured as a slave. The control circuit 208 within the slave IC die 102S-1 sets the slave signal to select "1" so that the multiplexer 302 selects INT_TDI and the demultiplexer 312 selects INT_TDO_MR_OUT. The EXT_TDI (112S-1) and EXT_TDO (112S-2) of the slave IC die 102S-1 are not connected within the multi-die IC package 104 (e.g., high impedance). The multi-die IC package 104 includes routing 502-2 that connects INT_TDO(116S-1) of slave IC die 102S-1 to INT_TDO_MR_IN(116S-4) of slave IC die 102S-1. That is, the multi-die IC package 104 connects the forwarding path 108 to the master return path 110 after slave IC die 102S-1 (because slave IC die 102S-1 is the last slave in the chain).

[0031] Since the slave IC die 102S-1 is configured as a slave, the control circuit 208 selects "0" for the signal "same", causing the demultiplexer 306 to couple the JTAG_TDO of the slave JTAG controller 201S to INT_TDO(116S-1), and the multiplexer 314 to couple the output (Q) of the falling edge flip-flop 310 to the demultiplexer 312. The control circuit 208 sets the signal slave to logic "1", causing the demultiplexer 312 to select INT_TDO_MR_OUT(116S-3). Therefore, the master return circuit 209 of the master return path 110 is coupled to INT_TDO_MR_OUT(116S-3) of the slave IC die 102S-1.

[0032] The multi-die IC package 104 includes routing 502-3 that connects INT_TDO_MR_OUT (116S-3) of the slave IC die 102S-1 to INT_TDO_MR_IN (116M-4) of the master IC die 102M. This connects the master return circuit 209 of the master IC die 102M to the master return path 110. The control circuit 208 in the master IC die 102M dynamically sets the signal state to "same" according to the instruction loaded into the instruction register 414 in the master JTAG controller 201M. If the instruction is of a type that only requires shifting JTAG data through the master IC die 102M, the control circuit 208 sets the "same" signal to logical "1" (e.g., BYPASS, IDCODE). If the instruction is of a type that requires shifting JTAG data through both the master IC die 102M and the slave IC die 102S-1, the control circuit 208 sets the "same" signal to logical "0" (e.g., EXTEST, sample / preload).

[0033] When the signal "same" is set to logic "0", the demultiplexer 306 connects the JTAG_TDO of the master JTAG controller 201M to the INT_TDO(116M-1) of the master IC die 102M. The multiplexer 314 also connects the output (Q) of the falling edge flip-flop 310 to the input of the demultiplexer 312. Since the master IC die 102M is configured as the master, the demultiplexer 312 connects the output of the multiplexer 314 to the EXT_TDO(112M-2), which is connected to the TDO of the TAP 106 by routing 504-2. Therefore, when the signal "same" is set to logic "0", the master wrapper circuit 204M connects the JTAG_TDO of the master JTAG controller 201M to the transfer path 108 and the master return path 110 to the EXT_TDO of the master IC die 102M.

[0034] When the signal "same" is logically "1", demultiplexer 306 connects the JTAG_TDO of master JTAG controller 201M to the input ("1") of multiplexer 314. That is, the JTAG_TDO of master JTAG controller 201M is disconnected from INT_TDO(116M-1) and the transfer path 108. Multiplexer 314 connects the JTAG_TDO of master JTAG controller 201M to the input of demultiplexer 312, which has selected EXT_TDO(112M-2) within master IC die 102M. Thus, when the signal "same" is set to logically "1", master wrapper circuit 204M connects the JTAG_TDO of master JTAG controller 201M to EXT_TDO(112M-2), which is then connected to the TDO of TAP 106. In this case, the master IC die 102M is disconnected from the transfer path 108 and the master return path 110.

[0035] Table 1 shows the truth table for the control circuit 208 within the IC die 102.

[0036] [Table 1]

[0037] In summary, when IC die 102 is configured as a slave, the "slave" signal is set to logical "1" (true) and the "same" signal is set to logical "0" (false), regardless of the instruction type. Therefore, the slave IC die 102S is always configured to connect its JTAG controller 201's JTAG_TDO to the transfer path 108 and its master return circuit 209 to the master return path 110. When IC die 102 is configured as a master, its control circuit 208 performs dynamic routing to EXT_TDO based on the instruction type. If the instruction is of a type that points to the same die (for example, JTAG data only for master IC die 102M), the control circuit 208 sets the "same" signal to logical "1" (true). Otherwise, the control circuit 208 sets the "same" signal to logical "0" (false).

[0038] The control circuit 208 receives information about the type of instruction from the instruction decoder 416. Based on the result from the instruction decoder 416, the control circuit 208 sets the signal state to "same" and routes the JTAG data as needed (either within the master only or across the entire chain). The instruction data is routed to all IC dies 102 on the chain. Therefore, the control circuit 208 in the master IC die 102M first sets the "same" signal to logical "0" (false). Once the instruction is decoded, the control circuit 208M in the master IC die 102M can change the state of the "same" signal to "1" (true) (for example, in the case of a BYPASS instruction). After the instruction has been executed, the control circuit 208 in the master IC die 102M resets the "same" signal to logical "0" (false) for the next instruction. The control circuit 208 can reset the "same" signal to logical "0" (false) based on the output from the TAP controller 402, which indicates that the previous instruction has been completed.

[0039] In the example described, the control circuit 208 is external to the JTAG controller 201. In other examples, parts of the control circuit 208 can be integrated into the JTAG controller 201. For example, the function of the control circuit 208 regarding the signal "same" can be performed by the instruction decoder 416. In such a case, the JTAG controller 201 can output the signal "same" for use by the wrapper circuit 204. The IC dies 102 within the multi-die IC package 104 are arranged in a fixed configuration regarding which die is the master and which is the slave. In this case, the signal "slave" is a fixed value for the master IC die 102M and each slave IC die 102S. In the example, the signal "slave" can be generated by a non-volatile memory element (e.g., an e-fuse).

[0040] Figure 6A shows a side view of an example multi-die IC package 104. The multi-die IC package 104 includes a substrate 602 (e.g., an interposer or package substrate) having a plurality of contacts 608 on one side and one or more layers of routing 604 on the opposite side. The substrate 602 includes vias 606 that connect the contacts 608 to the routing 604. The IC dies 102 are mounted on the substrate 602 and electrically communicate with the routing 604 via contacts 610. In this example, the multi-die IC package 104 includes a master IC die 102M and a slave IC die 102S-1. The routing 502 and 504 shown in Figure 5 are implemented in the routing 604 of the substrate 602. The contacts 610 include contacts for interfaces 112 and 116 of each IC die 102. As described above, some contacts of interface 112 or interface 116 can be disconnected depending on the master / slave configuration of the IC die 102. Contact 608 includes contacts for TAP106.

[0041] Figure 6B shows a side view of a multi-die IC package 104 according to another example. In this example, the multi-die IC package 104 includes a substrate 614 (e.g., an interposer or package substrate) having a plurality of contacts 616 on one side and one or more layers of routing 620 on the opposite side. The substrate 614 includes vias 618 that connect the contacts 616 to the routing 620. An IC die 102 (e.g., a master IC die 102M) is mounted on the substrate 614, electrically communicating with the routing 620 via contacts 622. The master IC die 102M includes a layer of routing 626 electrically coupled to contacts 622 via vias 624. Another IC die 102 (e.g., a slave IC die 102S-1) is mounted on top of the master IC die 102M. The slave IC die 102S-1 includes a layer of routing 628 facing the routing 626 of the master IC die 102M. This is called an "active-on-active" configuration. Routing 628 is electrically connected to routing 626 by contact 630. Routing 502 shown in Figure 5 can be implemented using routing 626, contact 630, and routing 628. Routing 504 shown in Figure 5 can be implemented using contact 622, via 624, and routing 626. Contact 616 includes a contact for TAP 106.

[0042] Figure 7 is a block diagram illustrating an example IC test system 700. The IC test system 700 includes a tester 701 having a hardware platform 710 and a software platform 712. As shown, the hardware platform 710 includes conventional components of a computing device, such as one or more central processing units (CPUs) 702, system memory (e.g., random access memory (RAM) 704), storage 706, and a JTAG interface 708. The CPU 702 is configured to execute instructions that can be stored in the RAM 704, for example, executable instructions that perform one or more operations described herein. The storage 706 can store files, such as one or more boundary scan description language (BSDL) files 716. The JTAG interface 708 is coupled to a multi-die IC device 100. The software platform 712 includes an operating system (OS) 720, a test program generator 714, and a test program executor 718. The OS 720 can be any operating system known in the art. The test program generator 714 accepts computer-aided design (CAD) data as input in the form of netlists, bills of materials, schematics, layout information, or any combination thereof. The test program generator 714 uses the CAD data to generate test patterns for fault detection and isolation using JTAG. The test program executor 718 interfaces with the multi-die IC device 100, performs the tests, and compares the results to expected values. The test program generator 714 and / or the test program executor 718 can consume a BSDL file 716. The BSDL file 716 describes the boundary scan behavior of the device, including which JTAG standards are supported, signal mapping and package information, available instructions and registers that access those instructions, and the types of boundary cancellation available for each signal.

[0043] As described above, the shift instruction register state (e.g., load an instruction) is treated as a “next die” instruction (e.g., the signal “same” is logical “0” or false). This ensures that the instruction register length of the multi-die IC package 104 remains constant. During the instruction phase, the flip-flops on the master return path 110 used for retiming must be taken into consideration when specifying the instruction. Within a single IC die 102, the instruction register can be, for example, 6 bits long. Since the multi-die IC package 104 contains multiple IC dies 102, the instruction register length increases by 7 bits (6 instruction bits and 1 return path bit) + 1 additional bit for the return flip-flop in the master return circuit for each additional IC die 102. The instruction register sequence for the master IC die 102M and one slave IC die 102S-1 is TDI → 6 bits (master instruction register) → 6 bits (slave instruction register) → 1 bit (slave return flop) → 1 bit (master return flop) → TDO. In this example, the total instruction register length is 14 bits.

[0044] JTAG instruction decoding is extended to account for extra bits. For example, the IDCODE instruction for a single IC die is 6'h09(6'b001001). In the notation, the first digit (e.g., 6) indicates the number of bits, the next character (e.g., h or b) indicates the hexadecimal or binary number, and the rest indicates the value. The IDCODE instruction for a multi-die IC package 104 having one master IC die 102M and one slave IC die 102S is 14'h927, and the instruction is formatted as follows:

[0045] IDCODE=14'h927(14'b001001_001001_1_1) Master instruction register = 6'h09(6'b001001) Slave instruction register = 6'h09(6'b001001) Slave return = 1'h1(1'b1) Master return = 1'h1(1'b1) Since the IDCODE instruction is a “same” die instruction, the data is not shifted via the slave IC die 102S, so the code loaded into the slave instruction register is not important. This is illustrated as 6'h09 in the example, but in reality it can be any value. The instruction register length for the multi-die IC package 104 is described in the BSDL file 716 for the device.

[0046] Figures 8 and 9 are flowcharts illustrating a method for testing a multi-die IC package 104 as an example. Figure 8 shows method 800 for operating the master IC die 102M during testing. Figure 9 shows method for operating the slave IC die 102S during testing.

[0047] Method 800 begins with step 802, in which the master IC die 102M configures itself as a master. The master wrapper circuit 204M within the master IC die 102M couples the TDI of TAP 106 to the JTAG_TDI of the master JTAG controller 201M (via EXT_TDI) (804). The master wrapper circuit 204M couples the TDO of TAP 106 to itself (via EXT_TDO) (806). Steps 802 (including 804 and 806) can be performed when the master IC die 102M is powered on and can remain static throughout the operation of the master IC die 102M.

[0048] In step 808, the control circuit 208 in the master IC die 102M configures the master wrapper circuit 204M to propagate JTAG data to the next die (for example, in the master IC die 102M, the signal "same" is set to logic "0"). The JTAG_TDO of the master JTAG controller 201M is coupled to the transfer path 108 (810). The master return path 110 is coupled to the TDO of TAP 106 (via the master wrapper circuit 204M and EXT_TDO) (812). In step 814, the JTAG controller 201 in the multi-die IC package 104 receives the instruction formatted as described above.

[0049] In step 816, the control circuit 208 in the master IC die 102M determines whether the instruction is for the same die or for all dies. If the instruction is for all dies, method 800 proceeds to step 818, where the control circuit 208 maintains the signal state as "same" (as logical "0" or false) and the configuration of the master wrapper circuit 204M remains the same (connecting the transfer path 108 and the master return path 110). If the instruction is for the same die, method 800 proceeds to step 820. In step 820, the control circuit 208 in the master IC die 102M sets the signal "same" to logical "1" (true) to disable the propagation of JTAG data to the next die. The master wrapper circuit 204M connects the JTAG_TDO of the master JTAG controller 201M to the TDO of TAP106 and disconnects the transfer path 108 and the master return path 110 (822). In step 824, the tester loads data into / reads data from the JTAG controller in the multi-die IC package 104.

[0050] Referring to Figure 9, method 900 begins in step 902. In step 902, the slave IC die 102S configures itself as a slave. The JTAG_TDI of the slave JTAG controller 201S is coupled to the previous master / slave on the transfer path 108 (904). The slave wrapper circuit 204S couples itself to the next master / slave on the master return path 110 (906). Steps 902 (including 904 and 906) can be performed when the slave IC die 102S is powered on and can remain static throughout the operation of the slave IC die 102S.

[0051] In step 908, the control circuit 208 in the slave IC die 102S is configured to propagate the slave wrapper circuit 204S to the next die. The control circuit 208 in the slave IC die 102S sets the signal "same" to "0" (false). The slave wrapper circuit 204S connects the JTAG_TDO of the slave JTAG controller 201S to the transfer path 108 (910). The slave wrapper circuit 204S connects the master return circuit 209 to the master return circuit of the next master / slave (912).

[0052] The JTAG circuit 203 shown in Figure 2 can be used with programmable devices such as those shown in Figures 10A to 10C below.

[0053] Figure 10A is a block diagram showing an example of a programmable device 54. The programmable device 54 includes a plurality of programmable integrated circuits (ICs) 1, for example, programmable ICs 1A, 1B, 1C, and 1D. In this example, each programmable IC 1 is an IC die located on an interposer 60. Each programmable IC 1 comprises a super logic area (SLR) 53 of the programmable device 54, for example, (SLR 53) A, 53B, 53C, and 53D. The programmable ICs 1 are interconnected via conductors (called super long lines (SLLs) 52) on the interposer 60. A JTAG circuit 203 can be located within each programmable IC 1, with one of the programmable ICs 1 configured as a master and the remaining programmable ICs 1 configured as slaves.

[0054] Figure 10B is a block diagram illustrating an example of a programmable IC1. The programmable IC1 can be used to implement one of the programmable ICs 1A to 1D within a programmable device 54. The programmable IC1 comprises a programmable logic (PL) 3 (also called a programmable fabric), a configuration logic 25, and a configuration memory 26. The programmable IC1 can be coupled with external circuits such as non-volatile memory 27, DRAM 28, and other circuits 29. The PL3 includes a logic cell 30, a support circuit 31, and a programmable interconnect 32. The logic cell 30 includes circuits that can be configured to perform common logic functions for multiple inputs. The support circuit 31 includes dedicated circuits such as transceivers, input / output blocks, digital signal processors, and memory. The logic cell and support circuit 31 can be interconnected using the programmable interconnect 32. Information for programming the logic cell 30, setting parameters for the support circuit 31, and programming the programmable interconnect 32 is stored in the configuration memory 26 by the configuration logic 25. The configuration logic 25 can obtain configuration data from non-volatile memory 27 or from any other source (e.g., DRAM 28 or other circuitry 29). In some examples, the programmable IC 1 includes a processing system (PS) 2. The PS 2 may include a microprocessor, memory, support circuitry, I / O circuitry, etc. In some examples, the programmable IC 1 includes a network-on-chip (NOC) 55 and a data processing engine (DPE) array 56. The NOC 55 is configured to provide communication between subsystems of the programmable IC 1, such as between the PS 2, PL 3, and the DPE array 56. The DPE array 56 may include an array of DPEs configured to perform data processing, such as an array of vector processors. The programmable IC 1 may include a BSCAN register 210 coupled to the JTAG circuitry 203 described above.

[0055] Figure 10C shows a field-programmable gate array (FPGA) implementation of the programmable IC1 including PL3. The PL3 shown in Figure 10C can be used in any example of the programmable devices described herein. PL3 includes a number of different programmable tiles, including a programmable logic block ("CLB") 33, a random access memory block ("BRAM") 34, an input / output block ("IOB") 36, configuration and clocking logic ("CONFIG / CLOCKS") 42, a digital signal processing block ("DSP") 35, special input / output blocks ("I / O") 41 (e.g., configuration ports and clock ports), as well as other programmable logic 39 such as a digital clock manager, analog-to-digital converter, and system monitoring logic. In the example, the programmable IC1 may include a BSCAN register 210 coupled to the JTAG circuit 203 described above.

[0056] In some PLs, each programmable tile may include at least one programmable interconnect element ("INT") 43 having connections to the input and output terminals 48 of a programmable logical element within the same tile, as shown by the example included at the top of Figure 10C. Each programmable interconnect element 43 may also include connections for interconnecting segments 49 of adjacent programmable interconnect elements within the same tile or other tiles. Each programmable interconnect element 43 may also include connections for interconnecting segments 50 of a generic routing resource between logical blocks (not shown). A generic routing resource may include routing channels between logical blocks (not shown) having tracks of interconnect segments (e.g., interconnect segment 50) and switch blocks (not shown) for connecting the interconnect segments. The interconnect segments of a generic routing resource (e.g., interconnect segment 50) may span one or more logical blocks. The programmable interconnect element 43, together with the generic routing resource, implements a programmable interconnect structure ("programmable interconnect") for the illustrated PL.

[0057] In an exemplary implementation, the CLB 33 may include a configurable logic element ("CLE") 44 that can be programmed to implement a single programmable interconnect element ("INT") 43 in addition to user logic. The BRAM 34 may include a BRAM logic element ("BRL") 45 in addition to one or more programmable interconnect elements. Typically, the number of interconnect elements included in a tile depends on the height of the tile. In the illustrated example, the BRAM tile has the same height as five CLBs, but other numbers (e.g., four) can also be used. The DSP tile 35 may include a DSP logic element ("DSPL") 46 in addition to an appropriate number of programmable interconnect elements. The IOB 36 may include, for example, one instance of a programmable interconnect element 43 in addition to two instances of an input / output logic element ("IOL") 47. As will be apparent to those skilled in the art, the actual I / O pads connected to, for example, the I / O logic element 47 are not typically limited to the area of ​​the input / output logic element 47.

[0058] In the illustrated example, the horizontal region near the center of the die (shown in Figure 3D) is used for configuration, clock, and other control logic. The vertical column 51 extending from this horizontal region or column is used to distribute the clock and configuration signals across the width of the PL.

[0059] Some PLs that utilize the architecture shown in Figure 10C include additional logic blocks that break the regular columnar structure that makes up the majority of the PL. These additional logic blocks can be programmable blocks and / or dedicated logic.

[0060] It should be noted that Figure 10C is intended to show only an illustrative PL architecture. For example, the number of logical blocks in the rows included at the top of Figure 9C, the relative width of the rows, the number and order of the rows, the types of logical blocks included in the rows, the relative size of the logical blocks, and the implementation of interconnections / logic are purely illustrative. For example, in a real PL, multiple adjacent CLB rows are usually included where CLBs appear to facilitate efficient implementation of user logic, but the number of adjacent CLB rows will vary depending on the overall size of the PL.

[0061] The above disclosure may also be expressed by one or more of the non-limiting examples provided below.

[0062] Example 1 An integrated circuit (IC) package having a test access port (TAP) with a test data input (TDI), a test data output (TDO), a test clock (TCK), and a test mode selector (TMS), wherein the IC package includes a master integrated circuit (IC) die including a master joint test action group (JTAG) controller and a master wrapper circuit coupled to the master JTAG controller; a slave IC die including a slave JTAG controller and a slave wrapper circuit coupled to the slave JTAG controller; a transfer path coupling the output of the master wrapper circuit to a first input of the slave wrapper circuit; and a master return path coupling the first output of the slave wrapper circuit to the input of the master wrapper circuit, wherein the master wrapper circuit couples the TDI of the TAP to the TDI of the master JTAG controller and selectively couples the TDO of the TAP to either the master return path or the TDO of the master JTAG controller in response to a first control signal.

[0063] Example 2 The IC package according to claim 1, wherein the master wrapper circuit includes a first demultiplexer having an input coupled to the TDO of a master JTAG controller and a first output coupled to the output of the master wrapper circuit, and a first multiplexer having a first input coupled to the master return path, a second input coupled to the second output of the first demultiplexer and an output coupled to the TDO of a TAP, the control inputs of the first demultiplexer and the first multiplexer being coupled to receive a first control signal.

[0064] Example 3 The IC package according to claim 2, wherein the master wrapper circuit includes a second multiplexer having a first input coupled to the TDI of a TAP, a second input coupled to the unconnected input of a master IC die, and an output coupled to the TDI of a master JTAG controller; and a second demultiplexer having an input coupled to the output of the first multiplexer, a first output coupled to the TDO of a TAP, and a second output coupled to the unconnected output of a master IC die, the control inputs of the second multiplexer and the second demultiplexer being coupled to a second control signal that selects the first input of the second multiplexer and the first output of the second demultiplexer.

[0065] Example 4 The IC package according to claim 1, wherein the slave wrapper circuit includes a first demultiplexer having an input coupled to the TDO of a slave JTAG controller and a first output coupled to a second output of the slave wrapper circuit, and a first multiplexer having a first input coupled to the master return path, a second input coupled to the second output of the first demultiplexer and an output coupled to the second output of the slave wrapper circuit, the control inputs of the first demultiplexer and the first multiplexer being coupled to receive a first control signal.

[0066] Example 5 The slave wrapper circuit includes a second multiplexer having a first input coupled to the unconnected input of the slave IC die, a second input coupled to the first input of the slave wrapper circuit, and an output coupled to the TDI of the slave JTAG controller. The IC package according to claim 4, comprising: a second demultiplexer having an input coupled to the output of a first multiplexer, a first output coupled to the disconnected output of a slave IC die, and a second output coupled to the first output of a slave wrapper circuit, wherein the control inputs of the second multiplexer and the second demultiplexer are coupled to a second control signal for selecting the second input of the second multiplexer and the second output of the second demultiplexer.

[0067] Example 6 The IC package according to claim 1, wherein the master return path includes a master return circuit on each of the master IC die and the slave IC die, and the master return circuit includes a flip-flop coupled to a falling edge flip-flop in the master return path.

[0068] Example 7: The IC package according to claim 1, wherein the TCK and TMS of the master JTAG controller and the slave JTAG controller are respectively coupled to the TCK and TMS of the TAP.

[0069] Example 8 An IC die in a multi-die integrated circuit (IC) package, wherein the multi-die IC package has a test access port (TAP) including a test data input (TDI), a test data output (TDO), a test clock (TCK), and a test mode selector (TMS), and the IC die includes a Joint Test Action Group (JTAG) controller having a JTAG interface including the TDI, TDO, TCK, and TMS; a first output coupled to a first routing in the multi-die IC package; a first input coupled to either a first or second routing in the multi-die IC package; a master return path coupled to the first input; and a wrapper circuit configured to couple the TDI of the TAP to the TDI of the JTAG controller and to selectively couple the TDO of the TAP to either the master return path or the TDO of the JTAG controller in response to a first control signal.

[0070] Example 9 The wrapper circuit includes a first demultiplexer having an input coupled to the TDO of a JTAG controller and a first output coupled to a first output, and a first multiplexer having a first input coupled to the master return path, a second input coupled to the second output of the first demultiplexer and an output coupled to the TDO of a TAP, wherein the control inputs of the first demultiplexer and the first multiplexer are coupled to receive a first control signal, the IC die according to claim 8.

[0071] Example 10 The IC die according to claim 9, wherein the master return path includes a master return circuit, the master return circuit includes a flip-flop coupled to a falling edge flip-flop, the input of the flip-flop is coupled to a first input, and the output of the falling edge flip-flop is coupled to a first input of a first multiplexer.

[0072] Example 11 The IC die according to claim 9, further comprising a second input not connected to or coupled to a third routing in the multi-die IC package, and a second output not connected to or coupled to a fourth routing in the multi-die IC package, wherein the wrapper circuit includes a second multiplexer having a first input coupled to the TDI of the TAP, a second input coupled to the second input, and an output coupled to the TDI of the JTAG controller, and a second demultiplexer having an input coupled to the output of the first multiplexer, a first output coupled to the TDO of the TAP, and a second output coupled to the output of the second, wherein the control inputs of the second multiplexer and the second demultiplexer are coupled to a second control signal.

[0073] Example 12 The IC die according to claim 8, further comprising a control circuit configured to generate a first control signal.

[0074] Example 13 The IC die according to claim 12, wherein the control circuit is coupled to an instruction decoder and a TAP controller in a JTAG controller, and the control circuit is configured to set the state of a first control signal based on the outputs of the instruction decoder and the TAP controller.

[0075] Example 14 The IC die according to claim 13, wherein the control circuit is located within the instruction decoder of the JTAG controller, and the control circuit is configured to set the state of a first control signal based on the output decoded by the instruction decoder and supplied by the TAP controller of the JTAG controller.

[0076] Example 15 The IC die according to claim 8, wherein each TCK and TMS of the JTAG controller is coupled to the TCK and TMS of the TAP, respectively.

[0077] Example 16 A method for testing a multi-die integrated circuit (IC) package having a test access port (TAP) including a test data input (TDI), a test data output (TDO), a test clock (TCK), and a test mode selector (TMS), wherein the multi-die IC package further includes a master IC die and a slave IC die, the method comprising: coupling the TDO of the TAP to a master return path from the slave IC die to the master IC die by a master wrapper circuit in the master IC die in response to a first control signal output by a first control circuit in the master IC die; receiving an instruction in a master JTAG controller in the master IC die via the TDI of the TAP and in a slave JTAG controller in the slave IC die via a transfer path from the master IC die to the slave IC die; determining by the first control circuit that the instruction requires data to be routed only through the master IC die, and changing the state of the first control signal; and coupling the TDO of the TAP to the TDO of the master JTAG controller by a master wrapper circuit in response to a first control signal output by the first control circuit.

[0078] Example 17: The method according to claim 16, wherein the instruction includes a BYPASS instruction or an IDCODE instruction.

[0079] Example 18 The method according to claim 16, wherein the master return path includes a master return circuit on each of the master IC die and the slave IC die, and the master return circuit includes a flip-flop coupled to a falling edge flip-flop in the master return path.

[0080] Example 19 The method according to claim 16, further comprising the step of coupling the TDI of the TAP to the TDI of the master JTAG controller in response to a second control signal output by the first control circuit, by a master wrapper circuit.

[0081] Example 20 The method according to claim 16, further comprising the steps of: coupling a transfer path to the TDI of a slave JTAG controller by a slave wrapper circuit in a slave IC die in response to a first control signal output by a second control circuit in a slave IC die; and coupling a master return path to the master IC die by a slave wrapper circuit in response to a first control signal output by a second control circuit.

[0082] While the above describes specific examples, other and further examples can be devised without deviating from their basic scope, and the scope is determined by the following claims.

Claims

1. An integrated circuit (IC) package having a test access port (TAP) comprising a test data input (TDI), a test data output (TDO), a test clock (TCK), and a test mode selector (TMS), wherein the IC package is The IC package comprises a master integrated circuit (IC) die including a master joint test action group (JTAG) controller and a master wrapper circuit coupled to the master JTAG controller, wherein the master wrapper circuit includes a first demultiplexer having an input coupled to the TDO of the master JTAG controller and an output coupled to the output of the master wrapper circuit, and a first multiplexer having a first input coupled to the master return path, a second input coupled to the second output of the first demultiplexer, and an output coupled to the TDO of the TAP, wherein the control inputs of the first demultiplexer and the first multiplexer are coupled to receive a first control signal, and the IC package further includes A slave IC die including a slave JTAG controller and a slave wrapper circuit coupled to the slave JTAG controller, A transfer path that connects the output of the master wrapper circuit to the first input of the slave wrapper circuit, The system includes a master return path which couples the first output of the slave wrapper circuit to the input of the master wrapper circuit, The master wrapper circuit is an IC package that couples the TDI of the TAP to the TDI of the master JTAG controller, and in response to the first control signal, selectively couples the TDO of the TAP to either the master return path or the TDO of the master JTAG controller.

2. The master wrapper circuit is, A second multiplexer having a first input coupled to the TDI of the TAP, a second input coupled to the unconnected input of the master IC die, and an output coupled to the TDI of the master JTAG controller, The second demultiplexer has an input coupled to the output of the first multiplexer, a first output coupled to the TDO of the TAP, and a second output coupled to the unconnected output of the master IC die. The IC package according to claim 1, wherein the control inputs of the second multiplexer and the second demultiplexer are coupled to a second control signal that selects the first input of the second multiplexer and the first output of the second demultiplexer.

3. The aforementioned slave wrapper circuit is A second demultiplexer having an input coupled to the TDO of the slave JTAG controller and a first output coupled to the second output of the slave wrapper circuit, The system comprises a second multiplexer having a first input coupled to a master return path coupled to the output of a second slave wrapper circuit, a second input coupled to the second output of the second demultiplexer, and an output coupled to the second output of the slave wrapper circuit, The IC package according to claim 1, wherein the second demultiplexer and the control input of the second multiplexer are coupled to receive the first control signal.

4. The aforementioned slave wrapper circuit is A third multiplexer having a first input coupled to the unconnected input of the slave IC die, a second input coupled to the first input of the slave wrapper circuit, and an output coupled to the TDI of the slave JTAG controller, A third demultiplexer having an input coupled to the output of the second multiplexer, a first output coupled to the unconnected output of the slave IC die, and a second output coupled to the first output of the slave wrapper circuit, The IC package according to claim 3, wherein the control inputs of the third multiplexer and the third demultiplexer are coupled to a second control signal that selects the second input of the third multiplexer and the second output of the third demultiplexer.

5. The IC package according to claim 1, wherein the master return path of the master IC die and the master return path of the slave IC die each include a master return circuit, and each master return circuit includes a flip-flop coupled to a falling edge flip-flop in the master return path.

6. The IC package according to claim 1, wherein the TCK and TMS of the master JTAG controller and the slave JTAG controller are respectively coupled to the TCK and TMS of the TAP.

7. An IC die within a multi-die integrated circuit (IC) package, wherein the multi-die IC package has a test access port (TAP) comprising a test data input (TDI), a test data output (TDO), a test clock (TCK), and a test mode selector (TMS), and the IC die is A Joint Test Action Group (JTAG) controller having a JTAG interface including TDI, TDO, TCK, and TMS, A first output coupled to the first routing within the multi-die IC package, A first input coupled to the first routing or second routing within the multi-die IC package, The master return path coupled to the first input, An IC die comprising: a wrapper circuit, a first demultiplexer having an input coupled to the TDO of the JTAG controller and an output coupled to the first output; a first multiplexer having a first input coupled to the master return path, a second input coupled to the second output of the first demultiplexer, and an output coupled to the TDO of the TAP, wherein the control inputs of the first demultiplexer and the first multiplexer are coupled to receive a first control signal; and the wrapper circuit is configured to couple the TDI of the TAP to the TDI of the JTAG controller and to selectively couple the TDO of the TAP to either the master return path or the TDO of the JTAG controller in response to the first control signal.

8. The IC die according to claim 7, wherein the master return path includes a master return circuit, the master return circuit includes a flip-flop coupled to a falling edge flip-flop, the input of the flip-flop is coupled to the first input, and the output of the falling edge flip-flop is coupled to the first input of the first multiplexer.

9. A second input that is not connected to or coupled to the third routing within the multi-die IC package, The system further comprises a second output that is not connected to or coupled to a fourth routing within the multi-die IC package, The aforementioned trumpet circuit is A second multiplexer having a first input coupled to the TDI of the TAP, a second input coupled to the second input, and an output coupled to the TDI of the JTAG controller, A second demultiplexer having an input coupled to the output of the first multiplexer, a first output coupled to the TDO of the TAP, and a second output coupled to the second output, The IC die according to claim 7, wherein the control inputs of the second multiplexer and the second demultiplexer are coupled to a second control signal.

10. The IC die according to claim 7, further comprising a control circuit configured to generate the first control signal.

11. The IC die according to claim 10, wherein the control circuit is coupled to the instruction decoder and TAP controller in the JTAG controller, and the control circuit is configured to set the state of the first control signal based on the output of the instruction decoder and the TAP controller.

12. A method for testing a multi-die integrated circuit (IC) package having a test access port (TAP) comprising a test data input (TDI), a test data output (TDO), a test clock (TCK), and a test mode selector (TMS), wherein the multi-die IC package further comprises a master IC die and a slave IC die, and the method is In response to a first control signal output by a first control circuit in the master IC die, the master wrapper circuit in the master IC die couples the TDO of the TAP to the master return path from the slave IC die to the master IC die. The steps include receiving an instruction via the TDI of the TAP in the master JTAG controller within the master IC die, and via the transfer path from the master IC die to the slave IC die in the slave JTAG controller within the slave IC die, The first control circuit determines that the instruction requires data to be routed only through the master IC die, and modifies the state of the first control signal. The first step of the master wrapper circuit is to use a first demultiplexer to couple the TDO of the TAP to the TDO of the master JTAG controller in response to the first control signal output by the first control circuit, The master wrapper circuit comprises a first demultiplexer having an input coupled to the TDO of the master JTAG controller and an output coupled to the output of the master wrapper circuit, and a first multiplexer having a first input coupled to the master return path, a second input coupled to the second output of the first demultiplexer, and an output coupled to the TDO of the TAP, wherein the control inputs of the first demultiplexer and the first multiplexer are coupled to receive the first control signal.

13. The master wrapper circuit performs the steps of coupling the TDI of the TAP to the TDI of the master JTAG controller in response to the second control signal output by the first control circuit, The steps include: coupling the transfer path to the TDI of the slave JTAG controller via a slave wrapper circuit in the slave IC die in response to a first control signal output by a second control circuit in the slave IC die; The slave wrapper circuit provides the master return path to the master IC die in response to the first control signal output by the second control circuit, and The method according to claim 12, further comprising:

Images