Methods, systems, computer programs, and computer-readable recording media for diagnosing faulty circuit elements.

Abstract

To diagnose faulty circuit elements using built-in self-test circuits.SOLUTION: A method includes executing a test for a first structure and a second structure of a built-in self-test circuit. Each of the first and second structures includes a plurality of latches arranged as a plurality of stump chains. The method also includes unloading a first result of the test from the plurality of stump chains of the first structure, and unloading a second result of the test from the plurality of stump chains of the second structure. The method further includes determining that the stump chains of the first structure include a faulty latch on the basis of the first result not matching the second result.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a built-in self-test circuit, and more particularly to diagnosing a failed circuit element using a built-in self-test circuit.

Background Art

[0002] A built-in self-test (BIST) circuit is designed with a structure that enables direct testing of the circuit logic connected to the BIST circuit. The test result indicates whether the BIST circuit or the circuit logic is faulty.

Summary of the Invention

Problems to be Solved by the Invention

[0003] Embodiments of the present disclosure aim to provide a diagnostic extension function for multiple instances of the same structure.

Means for Solving the Problems

[0004] According to one embodiment, the method includes performing tests on a first structure and a second structure of a built-in self-test circuit. Each of the first and second structures includes a plurality of latches arranged as a plurality of stamp chains. The method also includes unloading a first test result from the plurality of stamp chains of the first structure and unloading a second test result from the plurality of stamp chains of the second structure. The method further includes determining that the plurality of stamp chains of the first structure includes a faulty latch based on the first result not matching the second result. Other embodiments include an apparatus and a system for performing the method.

Brief Description of the Drawings

[0005] [Figure 1] A diagram showing an exemplary system. [Figure 2]This figure shows an example of unloading in the system shown in Figure 1. [Figure 3] This figure shows an example of unloading in the system shown in Figure 1. [Figure 4] This figure shows an example of unloading in the system shown in Figure 1. [Figure 5] This figure shows an example of compression in the system shown in Figure 1. [Figure 6] This figure shows an exemplary spreader circuit in the system shown in Figure 5. [Figure 7] This figure shows an exemplary XOR / rotation circuit in the system shown in Figure 5. [Figure 8] This figure shows an example of unloading in the system shown in Figure 1. [Figure 9] This is a flowchart illustrating an exemplary method in the system shown in Figure 1. [Modes for carrying out the invention]

[0006] A built-in self-test (BIST) circuit is designed with a structure that allows direct testing of the circuit logic connected to the BIST circuit. The test results indicate whether the BIST circuit or circuit logic is faulty. However, these tests cannot reveal which component is faulty. This disclosure envisions various methods for unloading and analyzing test results from a BIST circuit to determine which component of the BIST circuit or circuit logic is faulty. In one embodiment, results from the same test are unloaded from different structures of the BIST circuit, and the results are compared with each other. If a discrepancy in the results is found, the logged test loop and shift counter reveal the faulty component of the BIST circuit or circuit logic corresponding to the discrepancy. These processes are discussed in more detail with reference to Figures 1 to 9.

[0007] Here, we refer to Figure 1, which shows an exemplary system 100. As seen in Figure 1, system 100 includes a control circuit 101, one or more test structures 102, and a circuit 116 that includes circuit logic between the latches of the STUMP chain 104. Generally, the control circuit 101 uses one or more test structures 102 to test not only the STUMP chain 104 but also the circuit 116. After loading test data into the test structures 102, the control circuit 101 performs tests on the circuit 116. The control circuit 101 then unloads the test results from the test structures 102. The test results can be analyzed to determine the fault detection location within the structures 102. In some embodiments, the test structures 102 may be logically identical to one another.

[0008] System 100 may include any number of control circuits 101 to control any number of test structures 102. In some embodiments, system 100 includes multiple instances of test structures 102, represented as rows of test structures 102. Each row of test structures is controlled by a control circuit 101. Separate control circuits 101 may be used to control separate rows of test structures 102, or one control circuit 101 may be used to control multiple rows of test structures 102. For clarity, Figure 1 shows one control circuit 101 and one row of test structures 102.

[0009] The control circuit 101 includes a phase-locked loop 112, a clock generator 114, and a BIST control engine 116. Generally, the phase-locked loop 112 and the clock generator 114 work together to generate one or more clock signals that control other components of the system 100 (e.g., test structures 102). The engine 116 controls clocking, loading test data, and unloading test results from one or more test structures 102.

[0010] The phase-locked loop 112 generates a signal of a specific frequency. For example, the phase-locked loop 112 may include a variable frequency oscillator and a phase detector within the feedback loop. The phase-locked loop 112 uses this feedback loop to generate an output signal of a specific frequency.

[0011] The clock generator 114 can generate one or more clock signals using the output signals of the phase-locked loop 112. For example, the clock generator 114 may include circuit elements that multiply or divide the output signals of the phase-locked loop 112 by one or more ratios. In this way, the clock generator 114 generates output signals having frequencies that are ratios of the frequencies of the output signals of the phase-locked loop 112. The clock generator 114 transmits these clock signals to other components of the system 100 to control the timing and operation of these components.

[0012] The engine 116 controls the loading of test data and the unloading of test results from the test structure 102. As shown in Figure 1, the engine 116 may include a processor 118 and memory 120 configured to perform any of the functions or operations of the control circuit 101 described herein. In certain embodiments, the control circuit 101 can determine fault detection locations within the structure 102 by unloading and analyzing test results from the test structure 102.

[0013] The processor 118 is any electronic circuit including, but not limited to, a microprocessor, an application-specific integrated circuit (ASIC), an application-specific instruction set processor (ASIP), or a state machine, or a combination thereof, which is communicatively coupled to the memory 120 and controls the operation of the control circuit 101. The processor 118 may be 8-bit, 16-bit, 32-bit, 64-bit, or any other suitable architecture. The processor 118 may include an arithmetic and logic unit (ALU) for performing arithmetic and logical operations, processor registers for supplying operands to the ALU and storing the results of ALU operations, and a control unit for executing those instructions by fetching instructions from memory and directing the coordinated operation of the ALU, registers, and other components. The processor 118 may include other hardware for running software to control and process information. The processor 118 performs any of the functions described herein by running software stored in memory. The processor 118 controls the operation and management of the control circuit 101 by processing information (e.g., information received and loaded from an external test system). The processor 118 may be a programmable logic device, a microcontroller, a microprocessor, any suitable processing device, or any suitable combination of the aforementioned. The processor 118 is not limited to a single processing unit but may encompass multiple processing units.

[0014] Memory 120 can permanently or temporarily store data, operational software, or other information for the processor 118. Memory 120 may include one or a combination of registers or built-in array memories suitable for storing BIST test sequences and data logging information. For example, memory 120 may include random access memory (RAM), read-only memory (ROM), magnetic storage devices, optical storage devices, or any other suitable information storage devices, or a combination of these devices. Software represents any suitable set of instructions, logic, or code embodied in a computer-readable storage medium. For example, software may be embodied in memory 120, a disk, a CD, or a flash drive. In certain embodiments, software may include applications executable by the processor 118 to perform one or more of the functions described herein. In some embodiments, engine 116 is an integrated state machine for controlling the execution of tests. Engine 116 is set up or loaded by an external test system and does not access external memory during test execution.

[0015] Each test structure 102 includes a pseudo-random pattern generator (PRPG) 103, one or more stamp chains 104, each containing one or more latches 105, a channel mask 106, and a multi-input signature register (MISR) 107. For clarity, only the components of one test structure 102 in Figure 1 are labeled, but the system 100 can contain any appropriate number of test structures 102 containing these components.

[0016] The control circuit 101 loads test data into one or more PRPGs 103. In some embodiments, the control circuit 101 provides data to the PRPGs 103, which use this data to generate pseudo-random test data. Each PRPG 103 loads test data into a stamp chain 104 of the corresponding test structure 102.

[0017] Each stamp chain 104 includes one or more latches 105. The stamp chains 104 in the test structure 102 are arranged in parallel. The latches 105 of the stamp chains 104 are arranged serially (for example, linked together like a scan chain). The PRPG 103 of the test structure 102 loads test data serially into the stamp chains 104 of the test structure 102. Test data may also be loaded simultaneously into all stamp chains 104 in parallel by all PRPG 103. Each latch 105 can be used to test different components or parts of the logic circuit 116 between the scan chains of an instance. For example, when a latch is clocked, test data propagates from the latch 105 through the latch 105, stimulating various components of the logic test circuit 116 between the stamp chains. The response is captured by the corresponding stamp latch 105 of the test structure 102. In this way, after the test data has been propagated by the system clock 114, the latches 105 of the stamp chains 104 can hold the test results.

[0018] Channel mask 106 and MISR 107 collect and compress the test results from the stamp chain 104. The channel mask 106 can block (via gating) any combination of the stamp chain 104 from reaching the MISR 107. The MISR 107 reads the results from the unblocked stamp chain 104 and compresses these results into a signature. The control circuit 101 compares the signature in the MISR 107 with a reference signature to determine whether the circuit 116 has passed the test. For example, if the signature in the MISR 107 matches the reference signature, the control circuit 101 can determine that the circuit 116 has passed the test. On the other hand, if the signature in the MISR 107 does not match the reference signature, the control circuit 101 can determine that the circuit 116 has not passed the test.

[0019] As shown in FIG. 1, some components of the test structure 102 arranged in a row may be arranged serially. For example, the PRPG 103 and the MISR 107 may be serialized such that the control circuit can load data into the first PRPG 103 and MISR 107 (e.g., the left side), and that data propagates to the last PRPG 103 and MISR 107 (e.g., the right side). In some embodiments, these components may not be serialized and instead may allow parallel loading and unloading. In some embodiments, the MISR 107 includes a feedback disable to allow serial loading and unloading of the MISR 1 (e.g., the left side), and that data propagates to the last PRPG 103 and MISR 107 (e.g., the right side). In some embodiments, these components may not be serialized and instead may allow parallel loading and unloading. In some embodiments, the MISR 107 includes a feedback disable to allow serial loading and unloading of the MISR 107.

[0020] The present disclosure describes various ways in which the control circuit 101 can unload, analyze, and determine the failed components in the tested circuit from the test results of the stamp chain 104. These processes are described with respect to FIGS. 2-8.

[0021] Figure 2 shows an exemplary unloading in the system 100 of FIG. 1. As seen in FIG. 2, the system 100 includes multiple instances of the stamp structure 102 (shown as rows). The control circuit 101 controls each instance of the stamp structure 102. In the example of FIG. 2, the control circuit 101A controls the instances including the stamp structures 102A, 102B, and 102C. The control circuit 101B controls the instances including the stamp structures 102D, 102E, and 102F. The control circuit 101C controls the instances including the stamp structures 102G, 102H, and 102I. The system 100 also includes a selector 205, a comparator 206, a selection register 210, a recorder 211, and a database 215. In certain embodiments, the control circuits 101A, 101B, and 101C may be replaced by a single control circuit 101 that controls all instances of the stamp structure 102. Alternatively, there may be a separate control circuit for each stamp structure. In some embodiments, the selection register 210, the recorder 211, and the database 215 may be implemented as part of the control circuit 101 and interface with an external test system for clarity. Some components of the system 100 are shown in FIG. 2 without labeling, but these components share the labels provided in FIG. 1.

[0022] In the example in Figure 2, the control circuit 101 first performs the same test across all instances of the stamp structure 102. Each stamp structure 102 can test different parts of the logic circuit between its stamp chains, but stamp structures 102 in the same column (e.g., stamp structures 102A, 102D, and 102G) test the same part of the logic circuit. Therefore, if the same test is propagated through the stamp structures 102 in the column, it is expected that the MISR 107 within those stamp structures 102 should contain the same signature for "good" or "passed the test". Once the test is complete, the test results are compressed into the MISR 107, forming a signature. These signatures in the MISR 107 are compared to a reference signature to determine which instances failed the test and which instances passed. In the example in Figure 2, the MISR 107 clearly shows that the top instance failed the test and the middle instance passed the test. However, these signatures do not reveal which circuit elements, stamp chain 104, and latch 105 failed the test, or which test cycle they failed.

[0023] After the pass and fail instances are determined, the control circuit 101 toggles the system 100 into a second phase to diagnose the failure and determine the faulty component. The selection register 210 generates a control signal to the selector 205 to select the outputs of the upper (e.g., fail) instance and the middle (e.g., pass) instance for comparison. Furthermore, the control circuit 101 toggles the MISR 107 of the upper and middle instances to act as shift registers. The control circuit 101 reruns the test using the upper and middle instances. Generally, the control circuit 101 unloads and compares the test results from the two instances, in which case the pass instance is used as the reference. In the example in Figure 2, the upper instance failed the initial test and the middle instance passed the initial test, so the result from the middle instance is compared to the result from the upper instance, and the result from the middle instance serves as the reference.

[0024] Generally, after the test results are loaded into the stamp chain 104, the control circuit 101 toggles the channel mask 106 to unload the test results from a pair of corresponding stamp chains 104 within the instance (for example, the same stamp chain 104 in the same column of the test structure 102). These test results are compared to determine any mismatches indicating a test failure. The comparison and results are then logged. The control circuit 101 then toggles the channel mask 106 to unload the test results from the next pair of corresponding stamp chains 104 within the instance. These test results are compared to determine any mismatches indicating a test failure. The comparison and results are then logged. This process continues until the results from all stamp chains 104 within the instance have been unloaded and compared.

[0025] In the example in Figure 2, the control circuit 101 toggles the channel mask 106 to unload the test results from the second stamp chain 104 of the test structures 102B and 102E. The remaining stamp chains 104 in the instance are blocked. The test results from these stamp chains 104 are loaded into the corresponding MISR 107. Since MISR 107 is toggled to act as a shift register, with compression disabled, the test results from the stamp chains 104 are shifted towards selector 205 via MISR 107 in the instance. Based on the control signal generated by the selection register 210, selector 205 selects the results from the upper and middle instances for comparison by comparator 206.

[0026] Next, the recorder 211 records the comparison results and information regarding the test results. If there is a discrepancy in the test results, the recorder 211 logs the discrepancy in the database 215. Furthermore, the recorder 211 increments the failure count 214. The recorder 211 also logs the test loop 213 in which the discrepancy occurred. In addition, based on where in the test result sequence the discrepancy occurred, the recorder 211 logs information indicating the latch 105 in the stamp chain 104 where the discrepancy occurred. For example, the shift counter 212 may show a value A that identifies the location of the latch 105 in the stamp chain 104, a value B that indicates the stamp chain 104 in the test structure 102, and a value C that indicates the test structure 102 in the instance. This information can be used to identify the exact latch 105 where the discrepancy occurred.

[0027] In the example in Figure 2, a mismatch is detected between latch 105A and the corresponding latch 105B in the stamp chain 104. As a result, the recorder 211 logs values ​​A, B, and C in the shift counter 212, identifying the latch 105, the stamp chain 104, and the test structure 102 where the mismatch occurred. Furthermore, the recorder 211 logs the test result indicating the mismatch in the database 215. The recorder 211 also logs the test loop 213, allowing the test data for that test loop to be identified. Using all this information, the control circuit 101 or administrator can determine the test result that resulted in the mismatch, the circuit elements being tested by the latch 105 that triggered the mismatch, and the test data used to test these faulty circuit elements. As a result, the control circuit 101 and the administrator can pinpoint and diagnose the cause of the failure. In some embodiments, by repeating the diagnostic process, multiple faulty latches 105 within the same stamp chain 104 or different stamp chains 104 can be identified.

[0028] After the results from a pair of stamp chains 104 are unloaded and compared, the control circuit 101 adjusts the channel mask 106 to begin unloading the next stamp chain 104 in the instance (for example, the third stamp chain 104 in test structures 102B and 102E). The results from the next stamp chain 104 are compared and analyzed to determine any discrepancies. This process can continue until all discrepancies in all stamp chains 104 within the instance have been unloaded, compared, and analyzed. After the test results from all stamp chains 104 have been unloaded and compared, the control circuit 101 and the administrator can check the failure count 214 to determine the number of discrepancies determined. Furthermore, the control circuit 101 and the administrator can check the shift counter 212, test loop 213, and database 215 to identify the failed latch 105 and the corresponding failed circuit element and diagnose the reason for the failure.

[0029] Figure 3 shows an exemplary unload in system 100 of Figure 1. Generally, the process shown in Figure 3 is similar to the process shown in Figure 2, except that each unload and comparison in the process of Figure 3 is performed on a slice 305 of latches 105, rather than on the stamp chain 104. As seen in Figure 3, during a single unload and comparison, latches 105 from all instances of stamp chain 104 in the upper and middle are unloaded and sent to selector 205. The results from these latches 105 are then compared, and any mismatches are recorded. The next latch 105 in stamp chain 104 may then be unloaded and compared in a similar manner. This process can continue until all latches 105 in stamp chain 104 have been unloaded and compared. For clarity, some components of system 100 are shown in Figure 3 without labels, although these components share the labels provided in Figure 1.

[0030] Similar to the example in Figure 2, the control circuit 101 can perform an initial test on instances of the test structure 102. The control circuit 101 can then compare the MISR 107 of the various instances to determine which instances passed the initial test and which failed. In the example in Figure 3, the control circuit 101 determines that the top instance failed the initial test and the middle instance passed. The selection register 210 can then generate a control signal that causes the selector 205 to select the outputs of the top and middle instances. The control circuit 101 can then toggle the channel masks 106 of the top and middle instances to allow all the outputs of the stamp chains 104 in the test structure 102 of the top and middle instances to pass through. The MISR 107 can then read slices 305 of the latch 105 from the stamp chains 104 of the instances. Once the results of these latches 105 are read into the MISR 107, the MISR 107 shifts these results to the selector 205 and comparator 206. Comparator 206 compares these results, and recorder 211 records any discrepancies along with the corresponding information. MISR 107 can then unload the next slice 305 of latch 105 from stamp chain 104 for comparison by comparator 206. In the example in Figure 3, slice 305A of latch 105 is unloaded from the top instance, and slice 305B of latch 105 is unloaded from the middle instance. Latch 105 is shifted to comparator 205 and compared by comparator 206 to detect discrepancies.

[0031] As shown in Figure 3, system 100 includes one or more single-input signature registers 303. When the results are unloaded from the stamp chain 104, the results are compressed into SISR303 to generate signatures of the compared instances. In some embodiments, instead of first performing tests and comparing MISR107 to a reference signature, the signatures in SISR303 are used to determine which instances passed or failed the initial tests. For example, the tests may be performed on the instances, and then the test results from slices of latch 105 are unloaded and compared. These test results are also compressed into SISR303 to generate signatures of the instances. At the end of the unload comparison, the signatures in SISR303 can be compared to a reference signature to determine which instances passed and which failed. The control circuit 101 can then determine, for any discrepancies, which instances contain a failed latch 105 and which instances contain a passing latch 105.

[0032] Figure 4 shows an exemplary unload in system 100 of Figure 1. Generally, the process shown in Figure 4 is similar to the process shown in Figure 2, except that the process in Figure 4 serially unloads the latch 105 of the stamp chain 104. As seen in Figure 4, the stamp chain 104 in the test structure 102 can be toggled to unload the test results to the channel mask 106 or serially through the stamp chain 104. For example, test structure 102A includes stamp chains 104A, 104B, and 104C. Stamp chains 104A, 104B, and 104C can, for example, during an initial test run, unload their test results in parallel to MISR 107 via the channel mask 106 to compare the signatures in MISR 107 with a reference signature to determine whether test structure 102A passed the test. Furthermore, stamp chains 104A, 104B, and 104C may be toggled so that they serially unload their results through each other. For example, stamp chain 104A can unload its results to stamp chain 104B. Stamp chain 104B can unload its test results to stamp chain 104C, and stamp chain 104C can unload its test results to MISR 107 via channel mask 106. Serial unloading can be used when unloading and comparing test results from test structure 102. For clarity, some components of system 100 are shown in Figure 4 without labels, but these components share the labels provided in Figure 1.

[0033] During test execution, the control circuit 101 can send test data from the PRPG 103 to the stamp chain 104. The test can then be executed, and the results can be stored in the stamp chain 104. During unloading and comparison, the control circuit 101 can toggle the multiplexer 404 to unload data serially through the stamp chain 104. Furthermore, the control circuit 101 can toggle the channel mask 106 to allow information from the last stamp chain 104 to pass through to subsequent test structures 102. The control circuit 101 can also toggle the MISR 107 to act as a shift register, causing the results from the last stamp chain 104 to shift toward the other test structures 102 towards the selector 205. The control circuit 101 can also toggle the multiplexer 402 of each test structure 102 to shift the test results from the previous MISR 107 to the stamp chain 104 of the test structure 102. In this way, test results from stamp chain 104 are unloaded serially through the stamp chain 104 of each test structure 102. For example, test results from test structure 102A are shifted toward test structure 102B by MISR 107 in test structure 102A. The multiplexer 402 in test structure 102B then sends these test results to the stamp chain 104 of test structure 102B. The stamp chain 104 in test structure 102B then unloads these test results serially through the channel mask 106 and MISR 107 of test structure 102B. MISR 107 in test structure 102B shifts the test results toward selector 205. In this way, test results from an instance are shifted serially toward selector 205. Similarly, test results from another instance, including test structures 102C and 102D, are also shifted toward selector 205. The comparator 206 compares these test results, and the recorder 211 identifies and logs any discrepancies. Furthermore, the results may be compressed into SISR303.As discussed in the example in Figure 2, the signature of SISR303 can be used to determine which instances contained a failed latch 105 or a failed component, rather than performing an initial test and comparing the signature of MISR107 to a baseline signature. As shown in Figure 4, each instance can contain any number of appropriate test structures 102. For clarity, each test structure 102 is shown with three stamp chains 104, but each test structure 102 can contain any number of appropriate stamp chains 104.

[0034] Figures 5–7 show exemplary compression extensions in the system 100 of Figure 1 that can be performed for one or more of the unload processes described herein. Generally, compression is performed during unloading by distributing the results of multiple stamp chains 104 within a test structure 102, then rotating the distributed results and combining them with the distributed results of other test structures 102 within the instance. The compressed results of the instance are then compared to determine any discrepancies. The recorder 511 may include extensions that enable the recorder 511 to decompress or interpret the comparison results. For clarity, certain components of the system 100 are shown in Figure 5 without labels, although these components share the labels provided in Figure 1.

[0035] In the example in Figure 5, the test structure 102 includes a spreader circuit 501 and an XOR / rotation circuit 502. Generally, the spreader circuit 501 distributes the test results from the stamp chain 104 within the test structure 102. The XOR / rotation circuit 502 then combines the results from the spreader circuit 501 with the rotated results from the test structure 102 immediately preceding the instance. The XOR / rotation circuit 502 then passes the combined results to the MISR 107. The MISR 107 shifts the combined results to the next test structure 102 of the instance via the multiplexer 503 and combines the combined results again with the rotated distributed results from that test structure 102. The combined results of the instance are finally passed to the selector 205. The comparator 206 then compares the combined results from the two instances to determine any discrepancies. The combined results from the instances are compressed into MISR508 for subsequent analysis, allowing for the determination of which instances contained a faulty latch 105 or faulty circuit element.

[0036] Recorder 511 records the combined results from the instance and logs information about all detected mismatches. Recorder 511 may include extensions that allow it to decompress or interpret the combined results from the instance. For example, Recorder 511 can decompress or interpret the combined results to identify the test structure 102, the stamp chain 104, and the faulty latch 105. The spreader circuit 501 and the XOR / rotation circuit 502 are described in more detail with respect to Figures 6 and 7. In some embodiments, the decompression or interpretation of the combined results to identify the faulty latch 105 may be performed by an external test system after the test.

[0037] Figure 6 shows an exemplary spreader circuit 501 in system 100 of Figure 5. As seen in Figure 6, the spreader circuit 501 includes multiple XOR gates that receive inputs from one or more stamp chains 104 of the test structure 102. The results from the stamp chains 104 are distributed to the various XOR gates in the spreader circuit 501. As seen in Figure 6, the outputs from the stamp chains 104 (e.g., outputs 0-31) are presented sequentially as the first inputs to the XOR gates of the spreader circuit 501. Each XOR gate also receives inputs from two further stamp chains 104. The two further stamp chains 104 for any XOR gate may be arranged so that each XOR gate receives a set of outputs from different combinations of stamp chains 104. For example, the first XOR gate (XOR0) receives inputs from stamp chains 0, 1, and 2, and the second XOR gate (XOR1) receives inputs from stamp chains 1, 3, and 31. Next, the output of the XOR gate is output from the spreader circuit 501.

[0038] Furthermore, the spreader circuit 501 includes enable signals associated with the second and third inputs of each XOR gate. When the enable signal is low, each XOR gate passes its first input, which means that the XOR gates pass the outputs of the stamp chain 104 in sequence. When the enable signal is high, the spreader circuit 501 begins distributing the outputs of the stamp chain 104 by allowing the XOR gates to receive input from their second and third inputs. In other words, when the enable signal is low, the spreader circuit 501 does not distribute the outputs of the stamp chain 104. When the enable signal is high, the spreader circuit 501 distributes the outputs of the stamp chain 104.

[0039] Figure 7 shows an exemplary XOR / rotation circuit 502 in system 100 of Figure 5. As seen in Figure 7, the XOR / rotation circuit 502 includes a series of XOR gates that receive the output of the spreader circuit 501 of the test structure 102. Furthermore, these XOR gates receive the output of the previous test structure 102. The output of the previous test structure 102 can be rotated by one bit (for example, XOR0 receives the last bit (p31) of the result from the previous test structure 102, and XOR1 receives the first bit (p0) of the result from the previous test structure 102). The output of this XOR gate is then sent to the next test structure 102. In certain embodiments, the results from instances are compressed before comparison by using the spreader circuit 501 to distribute the results from the stamp chain 104 and then combining them with the rotated results from the previous test structure 102 using the XOR / rotation circuit 502.

[0040] Figure 8 shows an exemplary unload in system 100 of Figure 1, such that all stamp chains of each instance can be linked into a serial scan chain during the diagnostic unload process. Generally, the test structure 802 shown in Figure 8 can be used with both BIST structures and deterministic test data. For example, deterministic test data can be loaded serially and simultaneously into all instance channels of the test structure 802. A feedback loop 803 can feed back the output through the test structure 802 for compression purposes. Results from instances can be selected and compared by a comparator 507. The recorder 811 can then log any discrepancies in the test results.

[0041] Figure 9 is a flowchart of an exemplary method 900 in system 100 of Figure 1. Generally, one or more control circuits 101 can perform the steps of method 900. In a particular embodiment, by performing method 900, the control circuit 101 unloads and analyzes the test results to determine the faulty latch 105 and the faulty circuit component. Furthermore, the control circuit 101 diagnoses the cause of the faulty latch 105 and the faulty circuit component.

[0042] In step 902, the control circuit 101 performs tests on the first and second test structures 102 of the built-in self-test circuit. Performing a test may include transmitting deterministic test data or pseudo-random test data through the test structures 102. The test data may be transmitted through latches 105 organized as a stamp chain 104. Circuit elements can be tested using the test data in latches 105, and then the results of that test are loaded back into latches 105. Latch 105 propagates the test data to another latch 105 before loading the test results into latch 105. The test is completed when the test data has propagated through latches 105 and latches 105 hold the test results.

[0043] In step 904, the control circuit 101 unloads the first result from the first test structure 102. Simultaneously, in step 906, the control circuit 101 unloads the second result from the second test structure 102. The control circuit 101 can unload these test results using any appropriate process. For example, the control circuit 101 can unload these test results one at a time from the stamp chain 104 according to the process shown in Figure 2. The control circuit 101 can unload the test results as slices 305 of the latch 105 according to the process shown in Figure 3. The control circuit 101 can also unload the test results serially according to the process shown in Figure 4. Once the test results are unloaded, they are compared to determine any discrepancies.

[0044] In step 908, the control circuit 101 determines that the first structure 102 contains a faulty latch 105 based on the fact that the first result does not match the second result. For example, the control circuit 101 may implement a recorder 211 in the shift counter 212 that records mismatch and related information, thereby allowing the control circuit 101 to identify the test structure 102, stamp chain 104, and latch 105 corresponding to the mismatch. After identifying the faulty latch 105, the control circuit 101 can determine the circuit elements that were tested using the test data of the faulty latch 105. In this way, the control circuit 101 can identify the faulty circuit elements. Furthermore, the recorder 211 can log the test loop 213 in which the mismatch occurred. The control circuit 101 can use this information to identify the test data that caused the mismatch. The recorder 211 can also log the test results in which the mismatch occurred. The control circuit 101 can review the test results in which the mismatch occurred and diagnose the cause of the mismatch. In this way, the control circuit 101 can, in a particular embodiment, identify the faulty latch 105 and the faulty circuit element and diagnose the cause of the failure.

[0045] The descriptions of various embodiments of the present invention are presented for illustrative purposes only and are not intended to be exhaustive or limitful to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the embodiments described. The terminology used herein has been selected to best describe the principles, practical applications, or technical improvements to the technologies available on the market, or to enable those skilled in the art to understand the embodiments disclosed herein.

[0046] The above refers to embodiments presented in this disclosure. However, the scope of this disclosure is not limited to the specific embodiments described. Rather, any combination of features and elements, whether related to different embodiments or not, is intended to carry out and practice the intended embodiments. Furthermore, while embodiments disclosed herein may achieve advantages over other possible solutions or prior art, whether a particular advantage is achieved by a given embodiment does not limit the scope of this disclosure. Accordingly, the aspects, features, embodiments, and advantages discussed herein are merely illustrative and should not be considered elements or limitations of the appended claims unless expressly stated in the claims. Similarly, references to “the present invention” should not be interpreted as a generalization of the subject matter of the present invention disclosed herein and should not be considered elements or limitations of the appended claims unless expressly stated in the claims.

[0047] Aspects of the present invention may take the form of entirely hardware embodiments, entirely software embodiments (including firmware, resident software, microcode, etc.), or embodiments combining software and hardware embodiments, all of which may be generally referred to herein as “circuits,” “modules,” or “systems.”

[0048] The present invention may, in any possible level of technical detail integration, be a system, method, or computer program product, or a combination thereof. The computer program product may include a computer-readable storage medium having computer-readable program instructions for causing a processor to perform an aspect of the present invention.

[0049] A computer-readable storage medium can be a tangible device capable of holding and storing instructions for use by an instruction-executing device. A computer-readable storage medium may, but is not limited to, electronic storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination of the aforementioned. A non-exhaustive list of more specific examples of computer-readable storage media includes portable computer diskettes, hard disks, random-access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random-access memory (SRAM), portable compact disk read-only memory (CD-ROM), digital versatile disks (DVDs), memory sticks, floppy disks, mechanically encoded devices such as punch cards or grooved raised structures on which instructions are recorded, and any suitable combination of the aforementioned. Computer-readable storage media as used herein should not be interpreted as transient signals themselves, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., light pulses passing through optical fiber cables), or electrical signals transmitted through wires.

[0050] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to each computing / processing device, or to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network, or a wireless network, or a combination thereof. The network may include copper transmission cables, optical transmission fibers, wireless transmissions, routers, firewalls, switches, gateway computers, or edge servers, or a combination thereof. The network adapter card or network interface of each computing / processing device receives computer-readable program instructions from the network and transfers the computer-readable program instructions for storage in a computer-readable storage medium within each computing / processing device.

[0051] The computer-readable program instructions for performing the operation of the present invention may be assembler instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, integrated circuit configuration data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk and C++, and procedural programming languages ​​such as the "C" programming language or similar programming languages. The computer-readable program instructions can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or wide area network (WAN), or it may be connected to an external computer (for example, via the Internet using an Internet service provider). In some embodiments, for example, an electronic circuit including a programmable logic circuit, a field-programmable gate array (FPGA), or a programmable logic array (PLA) can execute computer-readable program instructions by personalizing the electronic circuit using state information of computer-readable program instructions in order to perform aspects of the present invention.

[0052] Aspects of the present invention are described herein with reference to flowcharts or block diagrams, or both, of methods, apparatus (systems), and computer program products according to embodiments of the present invention. It will be understood that each block in a flowchart or block diagram, or both, and any combination of blocks in a flowchart or block diagram, or both, can be implemented by computer-readable program instructions.

[0053] These computer-readable program instructions can be provided to a computer or other programmable data processing device processor to create a machine, such that instructions executed via the processor of the computer or other programmable data processing device create means for performing a function / operation specified in one or more blocks of a flowchart or block diagram, or both. These computer-readable program instructions can also be stored in a computer-readable storage medium that can instruct a computer, a programmable data processing device, or other device, or a combination thereof, to function in a particular manner, such that the storage medium containing the instructions internally contains a product containing instructions that perform a mode of function / operation specified in one or more blocks of a flowchart or block diagram, or both.

[0054] Computer-readable program instructions can also be used to create a computer implementation process by loading instructions that are executed on a computer, other programmable device, or other device into a computer, other programmable device, or other device, so that they perform a function / operation specified in one or more blocks of a flowchart or block diagram, or both, and causing a series of operational steps to be executed on the computer, other programmable device, or other device.

[0055] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible embodiments of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or part of an instruction that constitutes one or more executable instructions for implementing a specified logical function. In some alternative embodiments, the functions shown in the blocks may be performed in a different order than shown in the figures. For example, two consecutively shown blocks may actually be achieved as a single step, executed simultaneously or substantially simultaneously, partially or entirely in overlapping time, or the blocks may be executed in reverse order depending on the functions they relate to. It should also be noted that each block in a block diagram or flowchart or both, and any combination of blocks in a block diagram or flowchart or both, can be implemented by a dedicated hardware-based system that performs a specified function or operation, or a dedicated combination of hardware and computer instructions.

[0056] While the foregoing applies to embodiments of the present invention, other and further embodiments of the present invention may be devised without departing from the basic scope of the invention, and the scope of the invention is determined by the following claims. [Explanation of symbols]

[0057] 100 Systems 101 Control circuit 101A Control Circuit 101B Control Circuit 101C control circuit 102 Test structure, stamp structure, first test structure, second test structure 102A Stamp structure 102B Stamp structure 102C Stamp structure 102D Stamp Structure 102E Stamp structure 102F Stamp structure 103 Pseudo-Random Pattern Generator (PRPG) 104 Stump Chains, Stamp Chains 104A Stamp Chain, 104B, and 104C 104B Stamp Chain 104C Stamp Chain 105 Latch 106-channel mask 107 Multi-Input Signature Register (MISR) 112 Phase-Locked Loops 114 Clock Generator 116 Logic Circuits, BIST Control Engine 118 processors 120 memory 205 Selector 206 Comparator 210 Selection Register 211 Recorder 212 Shift Counter 213 Test Loop 214 Failure count, malfunction count 215 Databases, Failure Data 303 Single Input Signature Register, SISR 305 slices 305A slice 305B slice 402 Multiplexer 404 Multiplexer 501 Spreader Circuit 502 XOR / Rotation Circuit 503 Multiplexer 507 Comparator 508 MISR 511 Recorder 802 Test Structure 803 Feedback Loop 811 Recorder

Claims

1. Performing a test on a first structure and a second structure of a built-in self-test circuit, wherein each of the first and second structures comprises a plurality of latches arranged as a plurality of stamp chains, The first result of the test is unloaded from the plurality of stamp chains of the first structure, and the second result of the test is unloaded from the plurality of stamp chains of the second structure, Based on the fact that the first result does not match the second result, it is determined that the plurality of stamp chains of the first structure include a faulty latch, Includes, Unloading the first and second results described above is Unloading the first stamp chain of the first structure and the first stamp chain of the second structure, After unloading the first stamp chain of the first structure and the first stamp chain of the second structure, the second stamp chain of the first structure and the second stamp chain of the second structure are unloaded. Methods that include...

2. The method according to claim 1, further comprising loading deterministic test data serially and simultaneously into the first and second structures.

3. Performing a test on a first structure and a second structure of a built-in self-test circuit and on a corresponding target circuit, wherein each of the first and second structures comprises a plurality of latches arranged as a plurality of stamp chains, and each of the plurality of latches is connected to the corresponding circuit logic in the corresponding target circuit, The first result of the test is unloaded from the plurality of stamp chains of the first structure, and the second result of the test is unloaded from the plurality of stamp chains of the second structure, To generate a first signature based on the first result and a second signature based on the second result, Determining that the first structure failed the test based on the first signature which does not match the reference signature, and that the second structure passed the test based on the second signature which matches the reference signature, The unloaded first result is compared with the unloaded second result as a reference, and the discrepancy between the first result and the second result is compared. Based on where the discrepancy between the first result and the second result occurred, the faulty latch corresponding to the discrepancy in the first structure is identified, A method that includes this.

4. The method according to any one of claims 1 to 3, further comprising toggling the multi-input signature registers (MISRs) of the first and second structures to operate as shift registers.

5. Unloading the first and second results described above is Unloading the first latch from each of the stamp chains of the plurality of stamp chains of the first and second structures, After unloading the first latch from each of the multiple stamp chains of the first and second structures, the second latch is unloaded from each of the multiple stamp chains of the first and second structures. The method according to claim 3 or claim 4 (limited to the method relating to claim 3), including the following.

6. Unloading the first and second results described above is Unloading each of the multiple stamp chains of the first structure in serial order, Unloading each of the multiple stamp chains of the second structure in serial order, The method according to claim 3 or claim 4 (limited to the method relating to claim 3), including the following.

7. The method according to any one of claims 1 to 6, wherein unloading the first result includes unloading each latch of the first stamp chain of the plurality of stamp chains of the first structure such that the output of each latch is input to an XOR gate together with the outputs of at least two other latches of the first stamp chain of the plurality of stamp chains of the first structure.

8. Memory and A hardware processor that is communicatively coupled to the memory, The device is equipped with the hardware processor, Performing a test on a first structure and a second structure of a built-in self-test circuit, wherein each of the first and second structures comprises a plurality of latches arranged as a plurality of stamp chains, The first result of the test is unloaded from the plurality of stamp chains of the first structure, and the second result of the test is unloaded from the plurality of stamp chains of the second structure, Based on the fact that the first result does not match the second result, the system is configured to determine that the plurality of stamp chains of the first structure include a faulty latch, Unloading the first and second results described above is Unloading the first latch from each of the stamp chains of the plurality of stamp chains of the first and second structures, After unloading the first latch from each of the multiple stamp chains of the first and second structures, the second latch is unloaded from each of the multiple stamp chains of the first and second structures. A system that includes this.

9. The system according to claim 8, wherein the hardware processor is further configured to toggle the multi-input signature registers (MISRs) of the first and second structures to operate as shift registers.

10. Unloading the first and second results described above is Unloading the first stamp chain of the first structure and the first stamp chain of the second structure, After unloading the first stamp chain of the first structure and the first stamp chain of the second structure, the second stamp chain of the first structure and the second stamp chain of the second structure are unloaded. The system according to claim 8 or 9, including the system described in claim 8 or 9.

11. Memory and A hardware processor that is communicatively coupled to the memory, The device is equipped with the hardware processor, Performing a test on a first structure and a second structure of a built-in self-test circuit and on a corresponding target circuit, wherein each of the first and second structures comprises a plurality of latches arranged as a plurality of stamp chains, and each of the plurality of latches is connected to the corresponding circuit logic in the corresponding target circuit, The first result of the test is unloaded from the plurality of stamp chains of the first structure, and the second result of the test is unloaded from the plurality of stamp chains of the second structure, To generate a first signature based on the first result and a second signature based on the second result, Determining that the first structure failed the test based on the first signature which does not match the reference signature, and that the second structure passed the test based on the second signature which matches the reference signature, The unloaded first result is compared with the unloaded second result as a reference, and the discrepancy between the first result and the second result is compared. A system configured to identify a faulty latch corresponding to a discrepancy in the first structure, based on where the discrepancy between the first result and the second result occurred.

12. Unloading the first and second results described above is Unloading each of the multiple stamp chains of the first structure in serial order, Unloading each of the multiple stamp chains of the second structure in serial order, The system according to claim 11, including the following:

13. The system according to claim 11 or 12, wherein unloading the first result includes unloading each latch of the first stamp chain of the plurality of stamp chains of the first structure such that the output of each latch is input to an XOR gate together with the outputs of at least two other latches of the first stamp chain of the plurality of stamp chains of the first structure.

14. A computer program for causing a computer to execute the computer implementation method described in any one of claims 1 to 7.

15. A computer-readable recording medium having the computer program described in claim 14 recorded on it.

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