Support for 8-bit floating-point operands in the arithmetic architecture

Abstract

To provide a hardware for calculation using a 8-bit floating point operand.SOLUTION: A processing system 100 has a decoder for decoding fetched instructions. The decoded instructions are matrix instructions for use in using a 8-bit floating point operand to carry out parallel dot product operation. The system has a controller for scheduling the decoded instructions. The controller provides the 8-bit floating point operand with the input data in accordance with a 8-bit floating point data format designated by the decoded instructions. The system further has a systolic dot product circuit using a systolic layer to execute the decoded instructions. Each of the systolic layers has one or more sets each having a multiplier, a shifter and an adder which are connected to one another. Each set of the multiplier, the shifter and the adder generates a dot product of the 8-bit floating point operand.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001]

[0001] This generally relates to data processing, and more particularly to supporting 8-bit floating-point format operands in arithmetic architectures.

Background Art

[0002]

[0002] Current parallel graphics data processing includes systems and methods developed to perform specific operations on graphics data such as, for example, linear interpolation, tessellation, rasterization, texture mapping, depth testing, etc. Conventionally, graphics processors have used fixed-function calculation units to process graphics data; however, more recently, some graphics processors have been made programmable, allowing such processors to support a wider range of operations for processing vertex data and fragment data. [[ID=第十三]] [[ID=第十四]]

[0003] [[ID=第十五]] [[ID=第十六]]

[0003] To further improve performance, graphics processors typically implement processing techniques such as pipelining that attempt to process as much graphics data as possible in parallel through different parts of the graphics pipeline. Parallel graphics processors with single instruction, multiple data (SIMD) or single instruction, multiple thread (SIMT) architectures are designed to maximize the amount of parallel processing in the graphics pipeline. In the SIMD architecture, a computer with multiple processing elements attempts to simultaneously execute the same operation at multiple data points. In the SIMT architecture, a group of parallel threads attempts to synchronize and execute program instructions together as frequently as possible to increase processing efficiency. [[ID=第十七]]

[0004] [[ID=第十八]]

[0004] Graphics processors are frequently used in applications in the fields of artificial intelligence (AI) and machine learning (ML). Advances in these fields have made it possible for ML models to utilize low-precision computation for training neural networks. Conventional training platforms support floating-point 16 (FP16) and brain floating-point 16 (bfloat16 or BF16) data formats in high-performance systolic array implementations. More recently, there has been a need to support the training of deep neural networks using low-precision data formats such as 8-bit data formats. However, conventional systems do not provide hardware support for performing calculations using 8-bit floating-point format operands. [Brief explanation of the drawing]

[0005]

[0005] In order to allow for a detailed understanding of the above-described features of this embodiment, a more detailed description of the embodiment briefly summarized herein is given by reference to the embodiments, some of which are shown in the accompanying drawings. However, it should be noted that the accompanying drawings show only typical embodiments and should therefore not be interpreted as limiting their scope.

[0006]

[0006] [Figure 1] This is a block diagram of the processing system.

[0007] [Figure 2A] This refers to computing systems and graphics processors. [Figure 2B] This refers to computing systems and graphics processors. [Figure 2C] This refers to computing systems and graphics processors. [Figure 2D] This refers to computing systems and graphics processors.

[0008] [Figure 3A]A block diagram of the additional graphics processor and computing accelerator architecture is shown. [Figure 3B] A block diagram of the additional graphics processor and computing accelerator architecture is shown. [Figure 3C] A block diagram of the additional graphics processor and computing accelerator architecture is shown.

[0009] [Figure 4] This is a block diagram of the graphics processing engine of the graphics processor.

[0011] [Figure 5A] This shows the thread execution logic, which includes an array of processing elements used by the graphics processor core. [Figure 5B] This shows thread execution logic including an array of processing elements used in the graphics processor core.

[0011] [Figure 6] An additional execution unit is shown.

[0012] [Figure 7] This is a block diagram of the graphics processor instruction format.

[0013] [Figure 8] This is a block diagram of an additional graphics processor architecture.

[0014] [Figure 9A] This shows the graphics processor command format and command sequence. [Figure 9B] The graphics processor command format and command sequence are shown.

[0015] [Figure 10] An exemplary graphics software architecture for a data processing system is shown.

[0016] [Figure 11A] This is a block diagram of the IP core development system.

[0017] [Figure 11B] A side cross-sectional view of an integrated circuit package assembly is shown.

[0018] [Figure 11C]A package assembly is shown that includes a plurality of units of a hardware logic chiplet connected to a substrate (e.g., a base die).

[0019] [Figure 11D] A package assembly is shown that includes a replaceable chiplet.

[0020] [Figure 12] A block diagram showing an exemplary system in a chip integrated circuit.

[0021] [Figure 13A] A block diagram showing an exemplary graphics processor for use within a SoC. [Figure 13B] A block diagram showing an exemplary graphics processor for use within a SoC.

[0022] [Figure 14] A block diagram of a data processing system according to an embodiment.

[0023] [Figure 15] A block diagram showing the binary format of brain float8 (BFLOAT8 or BF8) according to an embodiment.

[0024] [Figure 16] A block diagram showing systolic DP 8-bit FP format operations executed by an instruction pipeline according to an embodiment.

[0025] [Figure 17A] A block diagram showing a systolic array circuit that executes a systolic dot product on an 8-bit floating point format input operand according to an embodiment. [Figure 17B] A block diagram showing a systolic array circuit that executes a systolic dot product on an 8-bit floating point format input operand according to an embodiment.

[0026] [Figure 18A] Instructions that can be executed by a systolic array circuit according to the embodiments described herein are shown.

[0027] [Figure 18B] A program code compilation process according to an embodiment is shown.

[0028] [Figure 19]A flowchart showing an embodiment of a method for executing a systolic dot product accumulation instruction on an input operand in an 8-bit floating-point format.

[0029] [Figure 20] A flowchart showing an embodiment of a method for systolic dot product accumulation on an input operand in an 8-bit floating-point format.

[0030] [Figure 21] A block diagram showing an 8-bit FP format conversion operation executed by an instruction pipeline according to an embodiment.

[0031] [Figure 22A] Instructions that can be executed by a processing unit according to the embodiments described herein are shown.

[0032] [Figure 22B] The program code compilation process according to an embodiment is shown.

[0033] [Figure 23] A flowchart showing an embodiment of a method for executing an instruction to convert floating-point data into 8-bit floating-point format data.

[0034] [Figure 24] A flowchart showing an embodiment of a method for converting floating-point data into 8-bit floating-point format data.

[0035] [Figure 25] A block diagram showing an 8-bit FP format conversion with a probabilistic rounding operation executed by an instruction pipeline according to an embodiment.

[0036] [Figure 26] A block diagram showing the fixed-point addition of the mantissa and random number sign-magnitude representation according to an embodiment.

[0037] [Figure 27A] Instructions that can be executed by a processing unit according to the embodiments described herein are shown.

[0038] [Figure 27B] The program code compilation process according to an embodiment is shown.

[0039] [Figure 28] A flowchart showing an embodiment of a method for executing an instruction to perform efficient probabilistic rounding on a floating-point value.

[0040] [Figure 29] This flowchart shows an embodiment of a method for performing efficient stochastic rounding on floating-point values.

[0041] [Figure 30] Block diagram showing two 8-bit floating-point formats using different binary encoding and exponential bias according to the embodiment.

[0042] [Figure 31] This is a block diagram showing the systolic operation of a hybrid 8-bit FP format executed by an instruction pipeline according to an embodiment.

[0043] [Figure 32] This is a block diagram showing a hybrid FMA unit of a systolic array circuit for performing hybrid floating-point stochastic operation according to an embodiment.

[0044] [Figure 33A] The following are instructions that can be executed by a systolic array circuit according to the embodiment described herein.

[0045] [Figure 33B] The program code compilation process according to the embodiment is shown.

[0046] [Figure 34] This is a flowchart illustrating an embodiment of a method for executing instructions for hybrid floating-point systolic operation.

[0047] [Figure 35] This is a flowchart illustrating an embodiment of a method for hybrid floating-point systolic operation.

[0048] [Figure 36] A block diagram showing the mixed-mode 8-bit FP format operation performed by the instruction pipeline according to the embodiment.

[0049] [Figure 37] An illustrative schematic diagram of hardware circuitry for performing mixed-mode MAC operation using at least one 8-bit FP format operand according to the embodiment is shown.

[0050] [Figure 38A] The following is a set of instructions that can be executed by the processing unit according to the embodiments described herein.

[0051] [Figure 38B] The program code compilation process according to the embodiment is shown.

[0052] [Figure 39] This flowchart shows an embodiment of a method for executing instructions to perform mixed-mode arithmetic using an 8-bit floating-point format operand.

[0053] [Figure 40] This flowchart shows an embodiment of a method for performing mixed-mode arithmetic using 8-bit floating-point format operands. [Modes for carrying out the invention]

[0007]

[0054] A graphics processing unit (GPU) is communicatively coupled to a host / processor core to accelerate, for example, graphics calculations, machine learning calculations, pattern analysis calculations, and / or various general-purpose GPU (GPGPU) functions. The GPU may be communicatively coupled to the host processor / core via a bus or other interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). Alternatively, the GPU may be integrated on the same package or chip as the core, or communicatively coupled to the core via an internal processor bus / interconnect (i.e., inside the package or chip). Regardless of how the GPU is connected, the processor core can assign work to the GPU in the form of a set of commands / instructions contained in a work descriptor. The GPU then uses dedicated circuitry / logic to efficiently process these commands / instructions.

[0008]

[0055] The following description includes many specific details for the sake of a more complete understanding. However, it will be apparent to those skilled in the art that the embodiments described herein may be carried out without adhering to one or more of these specific details. In other examples, well-known features are omitted to avoid obscuring the details of these embodiments.

[0009] System Overview

[0056] Figure 1 is a block diagram of a processing system 100 according to an embodiment. System 100 may be used in a single-processor desktop system, a multi-processor workstation system, or a server system having a number of processors 102 or processor cores 107. In one embodiment, system 100 is a processing platform embedded in a system-on-a-chip (SoC) integrated circuit for use in mobile, handheld, or embedded devices, such as those in Internet of Things (IoT) devices that utilize wired or wireless connectivity to a local or wide-area network.

[0010]

[0057] In one embodiment, System 100 may include, combine with, or be integrated into a server-based game platform; a game console including game and media consoles; a mobile game console, a handheld game console, or an online game console. In some embodiments, System 100 may be part of a mobile internet-connected device such as a mobile phone, smartphone, tablet computing device, or laptop with limited internal storage capacity. Alternatively, Processing System 100 may include, combine with, or be integrated into a wearable device such as a smartwatch wearable device; smart eyewear or clothing enhanced with augmented reality (AR) or virtual reality (VR) capabilities to provide visual, auditory, or tactile output to complement real-world visual, auditory, or tactile experiences, or to provide other text, audio, graphics, video, holographic images or videos, or haptic feedback; other augmented reality (AR) devices; or other virtual reality (VR) devices. In some embodiments, the processing system 100 includes or is part of a television or set-top box device. In one embodiment, the system 100 can include, be coupled to, or be integrated with an autonomous vehicle such as a bus, tractor trailer, automobile, motor or electric bicycle, airplane or glider (or any combination thereof). The autonomous vehicle can use the system 100 to process the environment sensed around the vehicle.

[0058] In some embodiments, one or more processors 102 each include one or more processor cores 107 to process instructions that, when executed, perform calculations for the system or user software. In the embodiments herein, a processor may be referred to as a dedicated hardware circuit for efficiently processing commands / instructions, or it may be referred to as a processor circuit. In some embodiments, at least one of the one or more processor cores 107 is configured to process a particular instruction set 109. In some embodiments, the instruction set 109 can facilitate calculations using composite instruction set arithmetic (CISC), reduced instruction set arithmetic (RISC), or very long instruction word (VLIW). One or more processor cores 107 can process different instruction sets 109, which may include instructions to facilitate the emulation of other instruction sets. The processor cores 107 may also include other processing devices, such as digital signal processors (DSPs).

[0011]

[0059] In some embodiments, the processor 102 includes cache memory 104. Depending on the architecture, the processor 102 may have a single internal cache or multiple levels of internal caches. In some embodiments, the cache memory is shared among various components of the processor 102. In some embodiments, the processor 102 also uses an external cache (e.g., a Level 3 (L3) cache or a Last Level Cache (LLC)) (not shown), which may be shared within the processor core 107 using known cache coherency techniques. A register file 106 may be additionally included in the processor 102 and may contain different types of registers for storing different types of data (e.g., integer registers, floating-point registers, state registers, and instruction pointer registers). Some registers may be general-purpose registers, while others may be specific to the design of the processor 102.

[0012]

[0060] In some embodiments, one or more processors 102 are coupled to one or more interface buses 110 to transmit communication signals, such as addresses, data, or control signals, between the processors 102 and other components in the system 100. In one embodiment, the interface bus 110 may be a processor bus such as a version of a Direct Media Interface (DMI) bus. However, the processor bus is not limited to a DMI bus and may include one or more peripheral component interconnect buses (e.g., PCI, PCI Express), a memory bus, or other types of interface buses. In one embodiment, the processor 102 includes an integrated memory controller 116 and a platform controller hub 130. The memory controller 116 facilitates communication between memory devices and other components of the system 100, while the platform controller hub (PCH) 130 provides connectivity to I / O devices via a local I / O bus.

[0013]

[0061] The memory device 120 can be a dynamic random-access memory (DRAM) device, a static random-access memory (SRAM) device, a flash memory device, a phase-change memory device, or any other memory device having performance suitable for functioning as process memory. In one embodiment, the memory device 120 can operate as system memory of the system 100 to store data 122 and instructions 121 for use when one or more processors 102 execute an application or process. The memory controller 116 also couples with an optional external graphics processor 118 capable of performing graphics and media operations by communicating with one or more graphics processors 108 within the processor 102. In some embodiments, graphics, media, and / or arithmetic operations may be supported by an accelerator 112, which is a coprocessor that can be configured to perform a specialized set of graphics, media, or arithmetic operations. For example, in one embodiment, the accelerator 112 is a matrix multiplication accelerator used to optimize machine learning or arithmetic operations. In one embodiment, accelerator 112 is a ray tracing accelerator that can be used to perform ray tracing processing in cooperation with graphics processor 108. In one embodiment, external accelerator 119 can be used instead of accelerator 112 or in cooperation with accelerator 112.

[0014]

[0062] In some embodiments, the display device 111 can be connected to the processor 102. The display device 111 can be one or more internal display devices, such as those in a mobile electronic device or laptop device, or an external display device attached via a display interface (e.g., DisplayPort). In one embodiment, the display device 111 can be a head-mounted display (HMD), such as a stereoscopic display device for use in a virtual reality (VR) or augmented reality (AR) application.

[0015]

[0063] In some embodiments, the platform controller hub 130 allows peripheral devices to connect to the memory device 120 and processor 102 via a high-speed I / O bus. I / O peripheral devices include, but are not limited to, an audio controller 146, a network controller 134, a firmware interface 128, a wireless transceiver 126, a touch sensor 125, and a data storage device 124 (e.g., non-volatile memory, volatile memory, hard disk drive, flash memory, NAND, 3D NAND, 3D XPoint, etc.). The data storage device 124 can be connected via a storage interface (e.g., SATA) or via a peripheral bus such as a peripheral component interconnect bus (e.g., PCI, PCI Express). The touch sensor 125 may include a touchscreen sensor, a pressure sensor, or a fingerprint sensor. The wireless transceiver 126 can be a Wi-Fi transceiver, a Bluetooth® transceiver, or a mobile network transceiver such as a 3G, 4G, 5G, or Long-Term Evolution (LTE) transceiver. The firmware interface 128 enables communication with the system firmware and can be, for example, a Unified Extensible Firmware Interface (UEFI). The network controller 134 can enable network connectivity to a wired network. In some embodiments, a high-performance network controller (not shown) is coupled to the interface bus 110. The audio controller 146 is, in one embodiment, a multi-channel high-definition audio controller. In one embodiment, the system 100 includes an optional legacy I / O controller 140 for coupling legacy (e.g., Personal System 2 (PS / 2)) devices to the system.The platform controller hub 130 can also be connected to one or more Universal Serial Bus (USB) controllers 142, and input devices such as a keyboard and mouse combination 143, a camera 144, or other USB input devices can be connected to it.

[0016]

[0064] It will be understood that the illustrated system 100 is illustrative and not limiting, as other types of data processing systems configured in different ways may be used. For example, instances of the platform controller hub 130 and memory controller 116 may be integrated into a separate external graphics processor, such as an external graphics processor 118. In one embodiment, the platform controller hub 130 and / or memory controller 116 may be external to one or more processors 102. For example, system 100 may include an external memory controller 116 and platform controller hub 130, which can be configured as a memory controller hub and peripheral controller hub within a system chipset that communicate with the processor 102.

[0017]

[0065] For example, the circuit board (thread) on which components such as the CPU, memory, and other components are arranged is designed to withstand rising thermal characteristics. In some examples, processing components such as the processor are located on the top side of the thread, while components near memory such as DIMMs are located on the bottom side of the thread. As a result of the increased airflow provided by this design, the components can operate at higher frequencies and power levels than in a typical system, thereby improving performance. Furthermore, the thread is configured to mate hands-free with power and data communication cables in the rack, thereby increasing the ability to quickly remove, upgrade, reinstall, and / or replace the thread. Similarly, individual components located on the thread, such as the processor, accelerator, memory, and data storage drives, are configured to be easily upgraded due to the increased spacing between them. In exemplary embodiments, the components further include hardware authentication features to prove their authenticity.

[0018]

[0066] A data center can utilize a single network architecture ("fabric") that supports multiple other network architectures, including Ethernet and Omni-Path. Threads can be coupled to switches via optical fiber, which provides higher bandwidth and lower latency than typical twisted-pair cables (e.g., Category 5, Category 5e, Category 6, etc.). Due to the high-bandwidth, low-latency interconnects and network architecture, a data center can pool resources such as memory, accelerators (e.g., GPUs, graphics accelerators, FPGAs, ASICs, neural networks, and / or artificial intelligence accelerators, etc.), and physically disassembled data storage drives when needed, and provide them to computing resources (e.g., processors) as needed, allowing those computing resources to access the pooled resources as if they were local.

[0019]

[0067] A power supply or power source can provide voltage and / or current to system 100 or any component or system described herein. In one example, the power source includes an AC-DC (alternating current-to-direct current) adapter for plugging into a wall outlet. Such AC power can be a renewable energy (e.g., solar power) power source. In one example, the power source includes a DC power source such as an external AC-DC converter. In one example, the power source or power supply includes wireless charging hardware for charging via proximity to a charging field. In one example, the power source can include an internal battery, an AC power source, a motion-based power source, a solar power source, or a fuel cell power source.

[0068] Figures 2A-2D show a computing system and graphics processor provided by embodiments described herein. Elements in Figure 2A-2D having the same reference numeral (or designation) as any other element in the figures herein may, but are not limited to, operate or function in any way similar to those described elsewhere in the Application.

[0020]

[0069] Figure 2A is a block diagram of an embodiment of a processor 200 having one or more processor cores 202A-202N, an integrated memory controller 214, and an integrated graphics processor 208. The processor 200 may include additional cores up to an additional core 202N, represented by dashed boxes. Each of the processor cores 202A-202N includes one or more internal cache units 204A-204N. In some embodiments, each processor core also has access to one or more shared cache units 206. The internal cache units 204A-204N and the shared cache units 206 represent a cache memory hierarchy within the processor 200. The cache memory hierarchy may include at least one level of instruction and data cache within each processor core, one or more levels of shared intermediate cache levels such as Level 2 (L2), Level 3 (L3), and Level 4 (L4), and other cache levels, where the highest level of cache prior to external memory is classified as LLC. In some embodiments, cache coherence logic maintains coherence between various cache units 206 and 204A-204N.

[0021]

[0070] In some embodiments, the processor 200 may include one or more bus controller units 216 and a set of system agent cores 210. One or more bus controller units 216 manage a set of peripheral buses, such as one or more PCI or PCI Express buses. The system agent cores 210 provide management functions for various processor components. In some embodiments, the system agent cores 210 include one or more integrated memory controllers 214 to manage access to various external memory devices (not shown).

[0022]

[0071] In some embodiments, one or more processor cores 202A-202N include support for simultaneous multithreading. In such embodiments, the system agent core 210 includes components for coordinating and operating the cores 202A-202N during multithreading. The system agent core 210 may further include a power control unit (PCU) which includes logic and components for coordinating the power states of the processor cores 202A-202N and the graphics processor 208.

[0023]

[0072] In some embodiments, the processor 200 additionally includes a graphics processor 208 to perform graphics processing operations. In some embodiments, the graphics processor 208 is coupled with a set of shared cache units 206 and a system agent core 210, which include one or more integrated memory controllers 214. In some embodiments, the system agent core 210 also includes a display controller 211 that drives the graphics processor output to one or more coupled displays. In some embodiments, the display controller 211 may also be a separate module coupled to the graphics processor via at least one interconnect, or it may be integrated within the graphics processor 208.

[0024]

[0073] In some embodiments, a ring-based interconnect unit 212 is used to connect the internal components of the processor 200. However, other interconnect units, such as point-to-point interconnects, switched interconnects, or other techniques including those well known in the art, may be used. In some embodiments, a graphics processor 208 is connected to the ring interconnect 212 via an I / O link 213.

[0025]

[0074] An exemplary I / O link 213 represents at least one of several types of I / O interconnects, including on-package I / O interconnects that facilitate communication between various processor components and high-performance embedded memory modules 218, such as eDRAM modules. In some embodiments, each of the processor cores 202A-202N and the graphics processor 208 can use the embedded memory module 218 as a shared final-level cache.

[0026]

[0075] In some embodiments, the processor cores 202A-202N are homogeneous cores that execute the same instruction set architecture. In other embodiments, the processor cores 202A-202N are heterogeneous with respect to the instruction set architecture (ISA), where one or more of the processor cores 202A-202N execute a first instruction set and at least one of the other cores executes a subset of the first instruction set or a different instruction set. In one embodiment, the processor cores 202A-202N are heterogeneous with respect to the microarchitecture, where one or more cores with relatively high power consumption are coupled with one or more power cores with lower power consumption. In one embodiment, the processor cores 202A-202N are heterogeneous with respect to computing power. Furthermore, the processor 200 can be implemented as one or more chips or SoC integrated circuits having the illustrated components in addition to the other components.

[0027]

[0076] Figure 2B is a block diagram of the hardware logic of a graphics processor core 219 according to several embodiments described herein. Elements in Figure 2B having the same reference numeral (or name) as elements in any other drawings of this application may, but are not limited to, operate or function in any way similar to those described elsewhere in this application. The graphics processor core 219 may often be referred to as a core slice and may be one or more graphics cores in a modular graphics processor. The graphics processor core 219 is an example of a single graphics core slice, and a graphics processor as described herein may include multiple graphics core slices based on target power and performance envelopes. Each graphics processor core 219 may include a fixed-function block 230 coupled with a plurality of sub-cores 221A-221F, also called sub-slices, the fixed-function block including modular blocks of general-purpose and fixed-function logic.

[0028]

[0077] In some embodiments, the fixed-function block 230 includes a geometry / fixed-function pipeline 231 that can be shared by all subcores within the graphics processor core 219, for example, in implementations of low-performance and / or low-power graphics processors. In various embodiments, the geometry / fixed-function pipeline 231 includes a video front-end unit, a thread spawner and thread dispatcher, and a unified return buffer manager that manages the unified return buffer (e.g., the unified return buffer 418 in Figure 4, as described later), and a 3D fixed-function pipeline (e.g., the 3D pipeline 312 as shown in Figures 3A and 4).

[0029]

[0078] In one embodiment, the fixed-function block 230 also includes a graphics SoC interface 232, a graphics microcontroller 233, and a media pipeline 234. The graphics SoC interface 232 provides an interface between the graphics processor core 219 and other processor cores in the system on the chip integrated circuit. The graphics microcontroller 233 is a programmable sub-processor that can be configured to manage various functions of the graphics processor core 219, including thread dispatch, scheduling, and preemption. The media pipeline 234 (e.g., media pipeline 316 in Figures 3A and 4) includes logic that facilitates decoding, encoding, preprocessing, and / or postprocessing of multimedia data, including image and video data. The media pipeline 234 performs media operations via requests for arithmetic or sampling logic within sub-cores 221-221F.

[0030]

[0079] In one embodiment, the SoC interface 232 enables the graphics processor core 219 to communicate with general-purpose application processor cores and / or other components within the SoC, including memory hierarchy elements such as shared final-level cache memory, system RAM, and / or embedded on-chip or on-package DRAM. The SoC interface 232 also enables communication with fixed-function devices within the SoC, such as camera imaging pipelines, and enables and / or implements the use of global memory atomics that can be shared between the CPU and the graphics processor core 219 within the SoC. Furthermore, the SoC interface 232 can implement power management controls for the graphics processor core 219 and enable facilitating the interfacing between the clock domain of the graphics core 219 and other clock domains within the SoC. In one embodiment, the SoC interface 232 enables the reception of command buffers from a command streamer and a global thread dispatcher configured to provide commands and instructions to each of one or more graphics cores within the graphics processor. Commands and instructions can be dispatched to the media pipeline 234 when media calculations are performed, and to the geometry and fixed function pipeline (for example, to the geometry and fixed function pipeline 231 or geometry and fixed function pipeline 237) when graphics processing calculations are performed.

[0031]

[0080] The graphics microcontroller 233 can be configured to perform various scheduling and management tasks for the graphics processor core 219. In one embodiment, the graphics microcontroller 233 can perform graphics and / or computation workload scheduling in various graphics parallel engines in the execution unit (EU) arrays 222A-222F and 224A-224F within the sub-cores 221A-221F. In this scheduling model, host software running on the CPU core of the SoC, including the graphics processor core 219, can submit workloads to one of several graphics processor doorbells that trigger scheduling operations in the appropriate graphics engine. Scheduling operations include determining the next workload to run, submitting the workload to a command streamer, preempting existing workloads running in the engine, monitoring the progress of the workload, and notifying the host software when the workload is complete. In one embodiment, the graphics microcontroller 233 can also facilitate low-power or idle states of the graphics processor core 219 and provide the graphics processor core 219 with the ability to save and restore registers within the graphics processor core 219 across low-power state transitions, independently of the system's operating system and / or graphics driver software.

[0032]

[0081] The graphics processor core 219 may have more or less than the illustrated subcores 221A-221F, and may have up to N modular subcores. For each set of N subcores, the graphics processor core 219 may also include shared function logic 235, shared and / or cache memory 236, geometry / fixed function pipeline 237, and additional fixed function logic 238 for accelerating and performing various graphics operations. The shared function logic 235 may include logic units (e.g., sampler, mathematical, and / or inter-thread communication logic) related to the shared function logic 420 in Figure 4, which can be shared by each of the N subcores in the graphics processor core 219. The shared and / or cache memory 236 can be the final-level cache for the set of N subcores 221A-221F in the graphics processor core 219, and can also function as shared memory accessible by multiple subcores. The geometry / fixed function pipeline 237 can be contained in place of the geometry / fixed function pipeline 231 within the fixed function block 230 and may contain identical or similar logical units.

[0033]

[0082] In one embodiment, the graphics processor core 219 includes an additional fixed-function logic 238 which may include various fixed-function acceleration logic used by the graphics processor core 219. In one embodiment, the additional fixed-function logic 238 includes an additional geometric pipeline for use in position-only shading. In position-only shading, there are two geometry pipelines: a full geometry pipeline in geometry / fixed-function pipelines 238, 231, and a cull pipeline, which is an additional geometry pipeline that may be included in the additional fixed-function logic 238. In one embodiment, the cull pipeline is a trimmed-down version of the full geometry pipeline. The full pipeline and the cull pipeline can run different instances of the same application, each instance having a separate context. Position-only shading can hide long cull runs of discarded triangles, and in some cases, allows shading to complete earlier. For example, in one embodiment, the cul-pipeline logic within the additional fixed-function logic 238 can execute the position shader in parallel with the main application, and generally, the cul-pipeline is faster than the full pipeline and produces critical results because it fetches and shades only the position attributes of vertices without rasterizing and rendering pixels into the frame buffer. The cul-pipeline can use the generated critical results to compute visibility information for all triangles, regardless of whether those triangles are sparse or not. The full pipeline (which may be referred to as the replay pipeline in this example) can use the visibility information to skip sparse triangles in order to occlude only the visible triangles that will ultimately be passed to the rasterization stage.

[0034]

[0083] In one embodiment, the additional fixed-function logic 238 may also include machine learning acceleration logic, such as fixed-function matrix multiplication logic, for implementations that include optimization for machine learning training or inference.

[0035]

[0084] Each graphics sub-core 221A-221F contains a set of execution resources that can be used to perform graphics, media, and computational processing as requested by the graphics pipeline, media pipeline, or shader program. The graphics sub-core 221A-221F includes multiple EU arrays 222A-222F, 224A-224F, thread dispatch and inter-thread communication (TD / IC) logic 223A-223F, 3D (e.g., texture) sampler 225A-225F, media sampler 206A-206F, shader processor 227A-227F, and shared local memory (SLM) 228A-228F. The EU arrays 222A-222F and 224A-224F each contain multiple execution units, which are general-purpose graphics processing units capable of performing floating-point and integer / fixed-point logical operations, including graphics, media, or computation shader programs, in graphics, media, or computation services. The TD / IC logic 223A-223F performs local thread dispatch and thread control operations for execution units within the subcore, facilitating communication between threads running on the subcore's execution units. The 3D sampler 225A-225F can load textures or other 3D graphics-related data into memory. The 3D sampler can load texture data differently based on the set sample state and the texture format associated with a given texture. The media sampler 206A-206F can perform similar loading operations based on the type and format associated with media data. In one embodiment, each graphics sub-core 221A-221F may alternatively include a unified 3D and media sampler. Threads running in the execution units within each sub-core 221A-221F can use shared local memory 228A-228F within each sub-core, allowing threads running within a thread group to use a common pool of on-chip memory.

[0036]

[0085] Figure 2C shows a graphics processing unit (GPU) 239 containing a dedicated set of graphics processing resources located in multi-core groups 240A–240N. While details are provided for only one multi-core group 240A, it will be understood that the other multi-core groups 240B–240N may have the same or similar sets of graphics processing resources.

[0037]

[0086] As illustrated, the multi-core group 240A may include a set of graphics cores 243, a set of tensor cores 244, and a set of ray tracing cores 245. The scheduler / dispatcher 241 schedules and dispatches graphics threads to run on the various cores 243, 244, and 245. A set of register files 242 stores operand values ​​used by cores 243, 244, and 245 when the graphics threads are running. These may include, for example, integer registers for storing integer values, floating-point registers for storing floating-point values, vector registers for storing packed data elements (integer and / or floating-point data elements), and tile registers for storing tensor / matrix values. In one embodiment, the tile registers are implemented as a combined set of vector registers.

[0038]

[0087] One or more coupled level 1 (L1) caches and shared memory units 247 locally store graphics data such as texture data, vertex data, pixel data, ray data, and boundary volume data within each multi-core group 240A. One or more texture units 247 can also be used to perform texturing operations such as texture mapping and sampling. A level 2 (L2) cache 253, shared by all or a subset of the multi-core groups 240A-240N, stores graphics data and / or instructions for multiple concurrent graphics threads. As shown in the figure, the L2 cache 253 may be shared across multiple multi-core groups 240A-240N. One or more memory controllers 248 couple the GPU 239 to memory 249, which may be system memory (e.g., DRAM) and / or dedicated graphics memory (e.g., GDDR6 memory).

[0039]

[0088] The input / output (I / O) circuit 250 connects the GPU 239 to one or more input / output devices 252, such as a digital signal processor (DSP), a network controller, or a user input device. On-chip interconnects can be used to connect the I / O devices 252 to the GPU 239 and memory 249. One or more I / O memory management units (IOMMUs) 251 of the I / O circuit 250 directly connect the I / O devices 252 to system memory 249. In one embodiment, the IOMMU 251 manages multiple sets of page tables to map virtual addresses to physical addresses in system memory 249. In this embodiment, the I / O devices 252, CPU 246, and GPU 239 may share the same virtual address space.

[0040]

[0089] In some implementations, the IOMMU251 supports virtualization. In this case, it can manage a first set of page tables for mapping guest / graphics virtual addresses to guest / graphics physical addresses, and a second set of page tables for mapping guest / graphics physical addresses to system / host physical addresses (e.g., within system memory 249). The base addresses of each of the first and second sets of page tables are stored in control registers and can be swapped by a context switch (e.g., resulting in a new context providing access to the relevant sets of page tables). Although not shown in Figure 2C, each of the cores 243, 244, 245, and / or multi-core groups 240A-240N may include a translation lookaside buffer (TLB) for caching translations from guest virtual to guest physical, from guest physical to guest virtual, and from guest virtual to host physical.

[0041]

[0090] In one embodiment, the CPU 246, GPU 239, and I / O device 252 are integrated on a single semiconductor chip and / or chip package. The illustrated memory 249 may be integrated on the same chip or may be coupled to the memory controller 248 via an off-chip interface. In one implementation, the memory 249 includes GDDR6 memory that shares the same virtual address space as other physical system-level memory, but the underlying principles of the present invention are not limited to this particular implementation.

[0042]

[0091] In one embodiment, the TensorCore 244 includes multiple execution units specifically designed to perform matrix operations, which are fundamental arithmetic operations used to perform deep learning operations. For example, simultaneous matrix multiplication can be used for neural network training and inference. The TensorCore 244 can perform matrix operations using various operand accuracies, including single-precision floating-point (e.g., 32 bits), half-precision floating-point (e.g., 16 bits), integer word (16 bits), byte (8 bits), and half-byte (4 bits). In one embodiment, the neural network implementation potentially combines details from multiple frames to extract features from each rendered scene and construct a high-quality final image.

[0043]

[0092] In deep learning implementations, parallel matrix multiplication operations may be scheduled for execution on the TensorCore 244. Training neural networks, in particular, requires a significant number of matrix dot product operations. To handle the dot product formula for N×N×N matrix multiplication, the TensorCore 244 may include at least N dot product processing elements. Before matrix multiplication begins, an entire matrix is ​​loaded into a tile register, and at least one column of a second matrix is ​​loaded in each of the N cycles. In each cycle, there are N dot products processed.

[0044]

[0093] Matrix elements can be stored with different precisions depending on the specific implementation, including 16-bit words, 8-bit bytes (e.g., INT8), and 4-bit half-bytes (e.g., INT4). Different precision modes may be specified for TensorCore244 to ensure that the most efficient precision is used for various workloads (e.g., inference workloads that can withstand quantization to bytes and half-bytes).

[0045]

[0094] In one embodiment, the ray tracing core 245 accelerates ray tracing operations for both real-time and non-real-time ray tracing implementations. In particular, the ray tracing core 245 performs ray traverse using a boundary volume hierarchy (BVH) and includes a ray traverse / intersection circuit for identifying intersections between rays and primitives enclosed by the BVH volume. The ray tracing core 245 may also include circuitry for performing depth testing and screening (e.g., using a Z-buffer or similar configuration). In one embodiment, the ray tracing core 245 performs traverse and intersection operations in cooperation with the image denoising techniques described herein, at least part of which may be performed in the tensor core 244. For example, in one embodiment, the tensor core 244 implements a deep learning neural network to perform denoising of frames generated by the ray tracing core 245. However, CPU 246, graphics core 243, and / or ray tracing core 245 may also implement all or part of the denoising and / or deep learning algorithms.

[0046]

[0095] Furthermore, as described above, a distributed approach to denoising may be used in a situation where the GPU239 is located within a computing device that is coupled to other computing devices via a network or high-speed interconnect. In this embodiment, the interconnected computing devices share neural network training / training data to improve the speed at which the entire system learns to perform denoising for different types of image frames and / or different graphics applications.

[0047]

[0096] In one embodiment, the ray tracing core 245 handles all BVH traverses and ray-primitive intersections, preventing the graphics core 243 from becoming overloaded with thousands of instructions per ray. In one embodiment, each ray tracing core 245 includes a first set of special circuits for performing bounding box tests (e.g., traverse operations) and a second set of special circuits for performing ray-triangle intersection tests (e.g., intersecting rays). Thus, in one embodiment, the multi-core group 240A can simply initiate ray probing, and the ray tracing cores 245 independently perform ray traverses and intersections, returning hit data (e.g., hit, no hit, multi-hit, etc.) to the thread context. The other cores 243, 244 are freed to perform other graphics or compute other tasks while the ray tracing cores 245 perform traverse and intersection operations.

[0048]

[0097] In one embodiment, each ray tracing core 245 includes a crossing unit for performing BVH test calculations and a crossing unit for performing ray-primitive crossing tests. The crossing unit generates "hit," "no hit," or "multi-hit" responses and provides them to the appropriate thread. During the crossing and crossing calculations, the execution resources of other cores (e.g., graphics core 243 and tensor core 244) are freed up to perform other forms of graphics work.

[0049]

[0098] In one particular embodiment described below, a hybrid rasterization / ray tracing approach is used in which the work is distributed between the graphics core 243 and the ray tracing core 245.

[0050]

[0099] In one embodiment, the ray tracing core 245 (and / or other cores 243, 244) includes hardware support for Microsoft's DirectX Ray Tracing (DXR), including the DispatchRays command, and ray tracing instruction sets such as ray generation, nearest hit, arbitrary hit, and miss shader, which enables the assignment of a set of shaders and textures to each object. Another ray tracing platform that may be supported by the ray tracing core 245, graphics core 243, and tensor core 244 is Vulkan 1.1.85. However, the basic principles of this embodiment are not limited to a particular ray tracing ISA.

[0051]

[0100] In general, various cores 245, 244, and 243 can support a set of ray tracing instructions that include instructions / functions related to ray generation, nearest hit, arbitrary hit, ray-primitive intersection, primitive and hierarchy-related bounding box construction, miss, visit, and exception. More specifically, one embodiment includes ray tracing instructions for performing the following functions:

[0101] ray generation - Ray generation commands can be executed for each pixel, sample, or other user-defined work assignment.

[0052]

[0102] Nearest hit - The nearest hit command can be executed to find the nearest intersection point of rays that have primitives in the scene.

[0053]

[0103] Any hit - The arbitrary hit command identifies multiple intersections between rays and primitives in the scene and identifies the potentially newest nearest intersection.

[0054]

[0104] Crossing - The crossing command performs a ray-primitive crossing test and outputs the result.

[0055]

[0105] Primitive-related bounding box configuration - This instruction constructs a bounding box around a given primitive or group of primitives (for example, when constructing a new BVH or other accelerated data structure).

[0056]

[0106] Miss - Indicates that the light ray missed all geometry in the scene, or a specific area of ​​the scene.

[0057]

[0107] Visit - Indicates the subvolume through which the light rays will pass.

[0058]

[0107] exception - Includes handling of various types of exceptions (called for various error conditions)

[0109] Figure 2D is a block diagram of a general-purpose graphics processing unit (GPGPU) 270 that can be configured as a graphics processor and / or computer accelerator according to embodiments described herein. The GPGPU 270 can interconnect with a host processor (e.g., one or more CPUs 246) and memories 271, 272 via one or more system and / or memory buses. In one embodiment, memory 271 is system memory that may be shared with one or more CPUs 246, and memory 272 is device memory dedicated to the GPGPU 270. In one embodiment, components within the GPGPU 270 and device memory 272 may be mapped to memory addresses that can access one or more CPUs 246. Access to memories 271 and 272 can be facilitated by a memory controller 268. In one embodiment, the memory controller 268 may include an internal direct memory access (DMA) controller 269 or include logic for performing operations, otherwise the operations will be performed by the DMA controller.

[0059]

[0110] The GPGPU270 includes multiple cache memories, including an L2 cache 253, an L1 cache 254, an instruction cache 255, and shared memory 256, at least a portion of which may be allocated as cache memory. The GPGPU270 also includes multiple arithmetic units 260A-260N. Each computer unit 260A-260N includes a set of vector registers 261, scalar registers 262, vector logic units 263, and scalar logic units 264. The arithmetic units 260A-260N may also include local shared memory 265 and a program counter 266. The arithmetic units 260A-260N can be coupled with a constant cache 267, which can be used to store constant data, which is data that does not change during the execution of a kernel or shader program running on the GPGPU270. In one embodiment, the constant cache 267 is a scalar data cache, and the cached data can be directly fetched into the scalar register 262.

[0060]

[0111] During operation, one or more CPUs 246 can write commands to registers or memory within the GPGPU 270 that are mapped to an accessible address space. The command processor 257 can read the commands from the registers or memory and determine how these commands will be processed within the GPGPU 270. The thread dispatcher 258 can then dispatch threads to arithmetic units 260A-260N to execute these commands. Each arithmetic unit 260A-260N can execute threads independently of the other arithmetic units. Furthermore, each arithmetic unit 260A-260N can be independently configured for conditional calculations and can conditionally output calculation results to memory. The command processor 257 can suspend one or more CPUs 246 when a submitted command has completed.

[0061]

[0112] Figures 3A-3C show block diagrams of additional graphics processor and computing accelerator architectures provided by embodiments described herein. Elements in Figure 3A-3C having the same reference numeral (or designation) as elements in any other figures of this application may, but are not limited to, operate or function in a manner similar to that described elsewhere in this application.

[0062]

[0113] Figure 3A is a block diagram of a graphics processor 300, which may be a separate graphics processing unit or a graphics processor integrated with multiple processing cores or other semiconductor devices such as memory devices or network interfaces, but is not limited to these. In some embodiments, the graphics processor communicates via a memory-mapped I / O interface to registers on the graphics processor and by commands located in processor memory. In some embodiments, the graphics processor 300 includes a memory interface 314 for accessing memory. The memory interface 314 may be an interface to local memory, one or more internal caches, one or more shared external caches, and / or system memory.

[0063]

[0114] In some embodiments, the graphics processor 300 also includes a display controller 302 that drives display output data to the display device 318. The display controller 302 includes hardware for one or more overlay planes for displaying and configuring multiple layers of video or user interface elements. The display device 318 can be an internal or external display device. In one embodiment, the display device 318 is a head-mounted display device such as a virtual reality (VR) display device or an augmented reality (AR) display device. In some embodiments, the graphics processor 300 includes a video codec engine 306 for encoding, decoding, or transcoding media to, from, or between one or more media encoding formats, including, but not limited to, MPEG (Moving Picture Experts Group) formats such as MPEG-2, AVC (Advanced Video Coding) formats such as H.264 / MPEG-4 AVC, H.265 / HEVC, AOMedia (Alliance for Open Media) VP8, VP9, ​​and SMPTE (the Society of Motion Picture & Television Engineers) 421M / VC-1, and JPEG (Joint Photographic Experts Group (JPEG)) formats such as JPEG and MJPEG (Motion JPEG).

[0064]

[0115] In some embodiments, the graphics processor 300 includes a block image transfer (BLIT) engine 304 to perform two-dimensional (2D) rasterizer operations, such as bit boundary block transfers. However, in one embodiment, 2D graphics operations are performed using one or more components of the graphics processing engine (GPE) 310. In some embodiments, the GPE 310 is a computing engine for performing graphics operations, including three-dimensional (3D) graphics operations and media operations.

[0065]

[0116] In some embodiments, the GPE310 includes a 3D pipeline 312 for performing 3D processing such as rendering 3D images and scenes using processing functions that act on 3D primitive shapes (e.g., rectangles, triangles, etc.). The 3D pipeline 312 includes programmable and fixed-function elements that perform various tasks within the element and / or generate execution threads for the 3D / media subsystem 315. While the 3D pipeline 312 can be used to perform media processing, embodiments of the GPE310 also include a media pipeline 316 which is specifically used to perform media processing such as video post-processing and image enhancement.

[0066]

[0117] In some embodiments, the media pipeline 316 includes fixed functions or programmable logic units for performing one or more specialized media operations, such as video decoding acceleration, video deinterlacing, and video encoding acceleration, on behalf of or in place of the video codec engine 306. In some embodiments, the media pipeline 316 additionally includes a thread generation unit that generates threads for execution in the 3D / media subsystem 315. The generated threads perform calculations for media processing on one or more graphics execution units included in the 3D / media subsystem 315.

[0067]

[0118] In some embodiments, the 3D / media subsystem 315 includes logic for executing threads generated by the 3D pipeline 312 and the media pipeline 316. In one embodiment, the pipelines send thread execution requests to the 3D / media subsystem 315, which includes thread dispatch logic for arbitrating various requests and dispatching them to available thread execution resources. The execution resources include an array of graphics execution units for processing 3D and media threads. In some embodiments, the 3D / media subsystem 315 includes one or more internal caches for thread instructions and data. In some embodiments, the subsystem also includes shared memory, including registers and addressable memory, for sharing data between threads and storing output data.

[0068]

[0119] Figure 3B shows a graphics processor 320 having a tiled architecture according to an embodiment described herein. In one embodiment, the graphics processor 320 includes a graphics processing engine cluster 322 having multiple instances of the graphics processing engine 310 of Figure 3A within graphics engine tiles 310A-310D. Each graphics engine tile 310A-310D can be interconnected via a set of tile interconnects 323A-323F. Each graphics engine tile 310A-310D can also be connected to a memory module or memory device 326A-326D via memory interconnects 325A-325D. The memory device 326A-326D can use any graphics memory technology. For example, the memory device 326A-326D may be graphics double data rate (GDDR) memory. In one embodiment, memory devices 326A-326D are high-bandwidth memory (HBM) modules that may reside on the die together with their respective graphics engine tiles 310A-310D. In one embodiment, memory devices 326A-326D are stackable memory devices that can be stacked on top of their respective graphics engine tiles 310A-310D. In one embodiment, each graphics engine tile 310A-310D and associated memory 326A-326D reside on a separate chiplet coupled to the base die or base substrate, as described in more detail in Figures 11B-11D.

[0069]

[0120] The graphics processor 320 can be configured with a non-uniform memory access (NUMA) system in which memory devices 326A-326D are coupled with associated graphics engine tiles 310A-310D. A given memory device may be accessed by graphics engine tiles other than the tile to which it is directly connected. However, the access latency to memory devices 326A-326D will be lowest when accessing local tiles. In one embodiment, a cache-coherent NUMA (ccNUMA) system uses tile interconnects 323A-323F to enable communication between cache controllers within graphics engine tiles 310A-310D to maintain a consistent memory image when multiple caches store the same memory location.

[0070]

[0121] The graphics processing engine cluster 322 can be connected to an on-chip or on-package fabric interconnect 324. The fabric interconnect 324 can enable communication between the graphics engine tiles 310A-310D and components such as the video codec 306 and one or more copy engines 304. The copy engines 304 can be used to move data to, from, and between memory devices 326A-326D and memory outside the graphics processor 320 (e.g., system memory). The fabric interconnect 324 can also be used to interconnect the graphics engine tiles 310A-310D. The graphics processor 320 may optionally include a display controller 302 to enable connection with an external display device 318. The graphics processor can also be configured as a graphics or arithmetic accelerator. In an accelerator configuration, the display controller 302 and display device 318 may be omitted.

[0071]

[0122] The graphics processor 320 can be connected to a host system via a host interface 328. The host interface 328 can enable communication between the graphics processor 320, system memory, and / or other system components. The host interface 328 can be, for example, a PCI Express bus or another type of host system interface.

[0072]

[0123] Figure 3C shows a computing accelerator 330 according to an embodiment described herein. The computing accelerator 330 may include an architecture similar to the graphics processor 320 in Figure 3B and is optimized for computing acceleration. The computing engine cluster 332 may include a set of computing engine tiles 340A-340D that include execution logic optimized for parallel or vector-based general-purpose computing. In some embodiments, the computing engine tiles 340A-340D do not include fixed-function graphics processing logic, but in one embodiment, one or more of the computing engine tiles 340A-340D may include logic for performing media acceleration. The computing engine tiles 340A-340D can be connected to memory 326A-326D via memory interconnects 325A-325D. Memory 326A-326D and memory interconnects 325A-325D may be of similar or different technology to the graphics processor 320. The graphics computing engine tiles 340A-340D can also be interconnected via a set of tile interconnects 323A-323F, and can be connected to and / or interconnected by the fabric interconnect 324. In one embodiment, the computing accelerator 330 includes a large L3 cache 336 which can be configured as a device-wide cache. The computing accelerator 330 can also be connected to the host processor and memory via the host interface 328 in a similar manner to the graphics processor 320 in Figure 3B.

[0073] Graphics processing engine

[0124] Figure 4 is a block diagram of the graphics processing engine 410 of a graphics processor according to several embodiments. In one embodiment, the graphics processing engine (GPE) 410 is a version of the GPE 310 shown in Figure 3A, and may also represent the graphics engine tiles 310A-310D in Figure 3B. Elements in Figure 4 having the same reference numeral (or name) as any other elements in the figures herein may, but are not limited to, operate or function in a similar manner to those described elsewhere in the Application. For example, the 3D pipeline 312 and media pipeline 316 are shown in Figure 3A. The media pipeline 316 is optional in some embodiments of the GPE 410 and may not be explicitly included within the GPE 410. For example, in at least one embodiment, a separate media and / or image processor is coupled to the GPE 410.

[0074]

[0125] In some embodiments, the GPE 410 is coupled to or includes a command streamer 403 that provides a command stream to the 3D pipeline 312 and / or the media pipeline 316. In some embodiments, the command streamer 403 is coupled to system memory, or memory which can be one or more of internal cache memory and shared cache memory. In some embodiments, the command streamer 403 receives commands from memory and sends commands to the 3D pipeline 312 and / or the media pipeline 316. Commands are directives fetched from a ring buffer that stores commands for the 3D pipeline 312 and the media pipeline 316. In one embodiment, the ring buffer may additionally include a batch command buffer that stores batches of multiple commands. Commands for the 3D pipeline 312 may also include, but are not limited to, references to data stored in memory, such as vertex and geometric data for the 3D pipeline 312 and / or image data and memory objects for the media pipeline 316. The 3D pipeline 312 and the media pipeline 316 process commands and data by performing operations through logic within their respective pipelines or by dispatching one or more execution threads to the graphics core array 414. In one embodiment, the graphics core array 414 includes one or more blocks of graphics cores (e.g., graphics core 415A, graphics core 415B), each block including one or more graphics cores. Each graphics core includes a set of graphics execution resources, including general-purpose and graphics-specific execution logic for performing graphics and arithmetic processing, as well as fixed-function texture processing and / or machine learning and artificial intelligence acceleration logic.

[0075]

[0126] In various embodiments, the 3D pipeline 312 may include fixed-function and programmable logic to process one or more shader programs, such as vertex shaders, geometry shaders, pixel shaders, fragment shaders, compute shaders, or other shader programs, by processing instructions and dispatching execution threads to the graphics core array 414. The graphics core array 414 provides a unified block of execution resources used when processing these shader programs. The multi-purpose execution logic (e.g., execution units) within the graphics cores 415A-414B of the graphics core array 414 may include support for various 3D API shader languages ​​and be capable of executing multiple concurrent execution threads related to multiple shaders.

[0076]

[0127] In some embodiments, the graphics core array 414 includes execution logic for performing media functions such as video and / or image processing. In one embodiment, the execution unit includes general-purpose logic that can be programmed to perform parallel general-purpose arithmetic processing in addition to graphics arithmetic processing. The general-purpose logic can perform arithmetic processing in parallel with or in conjunction with general-purpose logic in cores 202A-202N, such as the processor core 107 in Figure 1 or those in Figure 2A.

[0077]

[0128] Output data generated by threads running on the graphics core array 414 can be output to memory in the Unified Return Buffer (URB) 418. The URB 418 can store data from multiple threads. In some embodiments, the URB 418 may be used to transmit data between different threads running on the graphics core array 414. In some embodiments, the URB 418 may be additionally used for synchronization between threads on the graphics core array and fixed-function logic in the shared-function logic 420.

[0078]

[0129] In some embodiments, the graphics core array 414 is scalable so that the array includes a variable number of graphics cores, each of which has a variable number of execution units based on the target power and performance level of the GPE 410. In one embodiment, the execution resources are dynamically scalable, and as a result, the execution resources may be enabled or disabled.

[0079]

[0130] The graphics core array 414 is coupled with shared function logic 420, which includes multiple resources shared among the graphics cores within the graphics core array. The shared functions within the shared function logic 420 are hardware logic units that provide special supplemental functions to the graphics core array 414. In various embodiments, the shared function logic 420 includes, but is not limited to, sampler 421, math 422, and inter-thread communication (ITC) 423 logic. Furthermore, some embodiments implement one or more caches 425 within the shared function logic 420.

[0080]

[0131] Shared functions are implemented at least when the demand for a given special function is insufficient to be included within the graphics core array 414. Instead, a single instance of that special function is implemented as a standalone entity within the shared function logic 420 and shared among the execution resources within the graphics core array 414. The exact set of functions shared among and included within the graphics core array 414 varies by embodiment. In some embodiments, certain shared functions within the shared function logic 420, which are widely used by the graphics core array 414, may be included within the shared function logic 416 within the graphics core array 414. In various embodiments, the shared function logic 416 within the graphics core array 414 may contain some or all of the logic within the shared function logic 420. In one embodiment, all logic elements within the shared function logic 420 may overlap within the shared function logic 416 of the graphics core array 414. In one embodiment, the shared function logic 420 is excluded for the shared function logic 416 within the graphics core array 414.

[0081] Execution unit

[0132] Figures 5A–5B show thread execution logic 500, which includes an array of processing elements used in a graphics processor core, according to embodiments described herein. Elements in Figures 5A–5B having the same reference numerals (or names) as elements in other figures of this application may, but are not limited to, operate or function in the same manner as described elsewhere in this application. Figures 5A–5B provide an overview of thread execution logic 500 that can represent the hardware logic shown in each sub-core 221A–221F of Figure 2B. Figure 5A represents an execution unit in a general-purpose graphics processor, and Figure 5B represents an execution unit that may be used in a computer accelerator.

[0082]

[0133] As shown in Figure 5A, in some embodiments, the thread execution logic 500 includes a shader processor 502, a thread dispatcher 504, an instruction cache 506, a scalable execution unit including multiple execution units 508A-508N, a sampler 510, shared local memory 511, a data cache 512, and a data port 514. In one embodiment, the scalable execution unit array can be dynamically scaled by enabling or disabling one or more execution units (e.g., any of execution units 508A, 508B, 508C, 508D, or 508N-1 and 508N) based on the computational requirements of the workload. In one embodiment, the included components are interconnected via interconnection structures that link to each of the components. In some embodiments, the thread execution logic 500 includes one or more connections to memory, such as system memory or cache memory, via one or more of the instruction cache 506, data port 514, sampler 510, and execution units 508A-508N. In some embodiments, each execution unit (e.g., 508A) is a standalone programmable general-purpose arithmetic unit capable of executing multiple concurrent hardware / threads while processing multiple data elements in parallel for each thread. In various embodiments, the array of execution units 508A-508N is scalable to include any number of individual execution units.

[0083]

[0134] In some embodiments, execution units 508A-508N are primarily used to execute shader programs. The shader processor 502 can process various shader programs and dispatch execution threads associated with those shader programs via the thread dispatcher 504. In one embodiment, the thread dispatcher includes logic to mediate thread start requests from the graphics and media pipelines and instantiate the requested threads in one or more execution units within the execution units 508A-508N. For example, the geometry pipeline can dispatch vertex, tessellation, or geometry shaders to thread execution logic for processing. In some embodiments, the thread dispatcher 504 can also process runtime thread creation requests from running shader programs.

[0084]

[0135] In some embodiments, the execution units 508A-508N support an instruction set that includes native support for many standard 3D graphics shader instructions, resulting in shader programs from graphics libraries (e.g., Direct3D and OpenGL) being executed with minimal conversion. The execution units support vertex and geometric processing (e.g., vertex programs, geometric programs, vertex shaders), pixel processing (e.g., pixel shaders, fragment shaders), and general-purpose processing (e.g., computation and media shaders). Each of the execution units 508A-508N is capable of multi-issue single-instruction multiple-data (SIMD) execution, and multi-threaded operation enables an efficient execution environment when faced with higher latency memory access. Each hardware thread within each execution unit has its own dedicated high-bandwidth register file and associated independent thread state. Execution is multi-issue per clock to a pipeline capable of integer, single-precision and double-precision floating-point arithmetic, SIMD branching capability, logical operations, transcendental operations, and other operations. While waiting for data from memory or one of the shared functions, dependency logic within execution units 508A-508N puts the waiting thread to sleep until the requested data is returned. While the waiting thread is sleeping, hardware resources may be allocated to the processing of other threads. For example, during delays associated with vertex shader calculations, the execution unit can perform calculations for a pixel shader, a fragment shader, or another type of shader program (including a vertex shader). Various embodiments can be applied to the use of execution using single-instruction multiple-threaded (SIMT) as an alternative to or in addition to the use of SIMD. References to SIMD cores or calculations can also be applied to SIMT, or to SIMD in combination with SIMT.

[0085]

[0136] Each execution unit 508A-508N operates with respect to an array of data elements. The number of data elements is the "execution size," i.e., the number of channels in an instruction. An execution channel is a logical unit of execution for data element access, masking, and flow control within an instruction. The number of channels may be independent of the number of physical arithmetic logic units (ALUs) or floating-point units (FPUs) for a particular graphics processor. In some embodiments, execution units 508A-508N support integer and floating-point data types.

[0086]

[0137] The execution unit instruction set includes SIMD instructions. Various data elements can be stored in registers as packed data types, and the execution unit processes the elements based on their data size. For example, when acting on a 256-bit wide vector, the 256 bits of the vector are stored in registers, and the execution unit acts on the vector as four separate 54-bit packed data elements (Quad-Word (QW) size data elements), eight separate 32-bit packed data elements (Double-Word (DW) size data elements), sixteen separate 16-bit packed data elements (Word (W) size data elements), or thirty-two separate 8-bit data elements (Byte (B) size data elements). However, different vector widths and register sizes are possible.

[0087]

[0138] In one embodiment, one or more execution units can be combined into fused execution units 509A-509N having thread control logic (507A-507N) common to the fused EUs. Multiple EUs can be fused into an EU group. Each EU within a fused EU group can be configured to execute a separate SIMD hardware thread. The number of EUs within a fused EU group can vary depending on the embodiment. Furthermore, various SIMD widths, including SIMD8, SIMD16, and SIMD32, can be executed per EU, but are not limited to these. Each fused graphics execution unit 509A-509N includes at least two execution units. For example, fused execution unit 509A includes a first EU 508A, a second EU 508B, and thread control logic 507A common to the first EU 508A and the second EU 508B. The thread control logic 507A controls the threads executed in the fused graphics execution unit 509A, enabling each EU within the fused execution units 509A-509N to execute using a common instruction pointer register.

[0088]

[0139] One or more internal instruction caches (e.g., 506) are included in the thread execution logic 500 to cache thread instructions for the execution unit. In some embodiments, one or more data caches (e.g., 512) are included to cache thread data during thread execution. Threads running on the execution logic 500 may also store explicitly managed data in shared local memory 511. In some embodiments, a sampler 510 is included to provide texture sampling for 3D processing and media sampling for media processing. In some embodiments, the sampler 510 includes special texture or media sampling functions for processing texture or media data during the sampling process before providing the sampled data to the execution unit.

[0089]

[0140] During execution, the graphics and media pipeline sends a thread start request to the thread execution logic 500 via the thread creation and dispatch logic. Once a group of geometric objects has been processed and rasterized into pixel data, the pixel processor logic (e.g., pixel shader logic, fragment shader logic, etc.) in the shader processor 502 is invoked to further compute the output information and write the results to the output surface (e.g., color buffer, depth buffer, stencil buffer, etc.). In some embodiments, the pixel shader or fragment shader calculates the values ​​of various vertex attributes to be interpolated across the rasterized object. In some embodiments, the pixel processor logic in the shader processor 502 then executes the application programming interface (API) supplied pixel or fragment shader program. To execute the shader program, the shader processor 502 dispatches a thread to an execution unit (e.g., 508A) via the thread dispatcher 504. In some embodiments, the shader processor 502 uses texture sampling logic in the sampler 510 to access texture data in a texture map stored in memory. Arithmetic operations on the texture data and input geometry data either calculate pixel color data for each geometric segment or exclude one or more pixels from further processing.

[0090]

[0141] In some embodiments, the data port 514 provides a memory access mechanism to the thread execution logic 500, outputting processed data to memory for further processing in the graphics processor output pipeline. In some embodiments, the data port 514 includes or is coupled to one or more cache memories (e.g., data cache 512) for caching data for memory access via the data port.

[0091]

[0142] In one embodiment, the execution logic 500 may also include a ray tracer 505 capable of providing ray tracing acceleration functionality. The ray tracer 505 may support a ray tracing instruction set that includes instructions / functions for ray generation. The ray tracing instruction set may be similar to or different from the ray tracing instruction set supported by the ray tracing core 245 in Figure 2C.

[0092]

[0143] Figure 5B shows exemplary internal details of an execution unit 508 according to an embodiment. The graphics execution unit 508 may include an instruction fetch unit 537, a general-purpose register file array (GRF) 524, an architecture register file array (ARF) 526, a thread arbiter 522, a transmit unit 530, a branch unit 532, a set of SIMD floating-point units (FPUs) 534, and, in one embodiment, a set of dedicated integer SIMD ALUs 535. The GRF 524 and ARF 526 include sets of general-purpose register files and architecture register files associated with each concurrent hardware thread that may be active in the graphics execution unit 508. In one embodiment, per-thread architecture state is maintained in the ARF 526, and data used during thread execution is stored in the GRF 524. The execution state of each thread, including instruction pointers for each thread, may be held in thread-specific registers in the ARF 526.

[0093]

[0144] In one embodiment, the graphics execution unit 508 has an architecture that combines simultaneous multithreading (SMT) and fine interleaved multithreading (IMT). The architecture has a modular configuration that can be fine-tuned at design time based on the number of simultaneous thread targets and the number of registers per execution unit, where the execution unit resources are divided across the logic used to execute multiple simultaneous threads. The number of logical threads that can be executed by the graphics execution unit 508 is not limited to the number of hardware threads, and multiple logical threads can be assigned to each hardware thread.

[0094]

[0145] In one embodiment, the graphics execution unit 508 can issue multiple instructions together, which may each be a different instruction. The thread arbiter 522 of the graphics execution unit thread 508 can dispatch instructions to one of the following for execution: the transmit unit 530, the branch unit 532, or the SIMD FPU 534. Each execution thread can access 128 general-purpose registers in the GRF524, each register capable of storing 32 bytes and accessible as a SIMD8 element vector of 32-bit data elements. In one embodiment, each execution unit thread accesses 4K bytes in the GRF524, but embodiments are not limited to this, and other embodiments may provide larger or smaller register resources. In one embodiment, the graphics execution unit 508 is divided into seven hardware threads capable of independently executing arithmetic operations, but the number of threads per execution unit may also vary depending on the embodiment. For example, in one embodiment, up to 16 hardware threads are supported. In an embodiment where seven threads may access 4KB, the GRF524 can store a total of 28KB. If 16 threads can access 4KB, the GRF524 can store a total of 64KB. Flexible addressing mode allows registers to be addressed together, effectively constructing wider registers or representing strided rectangular block data structures.

[0095]

[0146] In one embodiment, memory operations, sampler operations, and other longer-latency system communications are dispatched by a “send” instruction executed by a message transfer unit 530. In one embodiment, branch instructions are dispatched to a dedicated branch unit 532 to facilitate SIMD diversity and eventual convergence.

[0096]

[0147] In one embodiment, the graphics execution unit 508 includes one or more SIMD floating-point units (FPUs) 534 for performing floating-point arithmetic. In one embodiment, the FPU(s) 534 also support integer arithmetic. In one embodiment, the FPU 534 can perform up to M 32-bit floating-point (or integer) SIMD arithmetic operations, or up to 2M 16-bit integer or 16-bit floating-point SIMD arithmetic operations. In one embodiment, at least one of the FPUs provides extended mathematical capabilities that support high-throughput transcendental mathematical functions and double-precision 54-bit floating-point. In some embodiments, a set of 8-bit integer SIMD ALUs 535 also exist and may be specifically optimized for performing operations related to machine learning computations.

[0097]

[0148] In one embodiment, an array of multiple instances of the graphics execution unit 508 can be instantiated in a graphics sub-core grouping (e.g., a sub-slice). With respect to scalability, the product architecture can select a precise number of execution units for each sub-core group. In one embodiment, the execution unit 508 can execute instructions across multiple execution channels. In a further embodiment, each thread executed by the graphics execution unit 508 runs on a different channel.

[0098]

[0149] Figure 6 shows an additional execution unit 600 according to one embodiment. The execution unit 600 may, but is not limited to, an execution unit optimized for computations to be used with computer engine tiles 340A-340D, for example, as shown in Figure 3C. Also, a variation of the execution unit 600 may be used in graphics engine tiles 310A-310D, as shown in Figure 3B. In one embodiment, the execution unit 600 includes a thread control unit 601, a thread state unit 602, an instruction fetch / prefetch unit 603, and an instruction decode unit 604 (also referred to here as a decoder). The execution unit 600 further includes a register file 606 that stores registers that can be assigned to hardware threads within the execution unit. The execution unit 600 additionally includes a transmit unit 607 and a branch unit 608. In one embodiment, the transmission unit 607 and the branching unit 608 can operate in the same manner as the transmission unit 530 and branching unit 532 of the graphics execution unit 508 in Figure 5B.

[0099]

[0150] The execution unit 600 also includes an arithmetic unit 610 which includes several different types of functional units. In one embodiment, the arithmetic unit 610 includes an ALU unit 611 which includes an array of arithmetic logic units. The ALU unit 611 can be configured to perform 64-bit, 32-bit, and 16-bit integer and floating-point operations. Integer and floating-point operations may be performed simultaneously. The arithmetic unit 610 may also include a systolic array 612 and a mathematical unit 613. The systolic array 612 includes a network of data processing units of width W and depth D which can be used to perform vector or other data parallel operations in a systolic manner. In one embodiment, the systolic array 612 can be configured to perform matrix operations such as matrix dot product operations. In one embodiment, the systolic array 612 supports 8-bit and 4-bit integer operations in addition to 16-bit floating-point operations. In one embodiment, the systolic array 612 can be configured to accelerate machine learning operations. In such embodiments, the systolic array 612 can be configured to support the bfloat 16-bit floating-point format. In one embodiment, a mathematical unit 613 can be included to perform a specific subset of mathematical operations in a more efficient and low-power manner than the ALU unit 611. The mathematical unit 613 can include a variation of the mathematical logic found in the shared function logic of the graphics processing engine provided by other embodiments (e.g., mathematical logic 422 of the shared function logic 420 in Figure 4). In one embodiment, the mathematical unit 613 can be configured to perform 32-bit and 64-bit floating-point operations.

[0100]

[0151] The thread control unit 601 includes logic to control the execution of threads within the execution unit. The thread control unit 601 may include thread arbitration logic to start, stop, and preempt threads within the execution unit 600. The thread state unit 602 can be used to store the thread state for threads assigned to run in the execution unit 600. Storing the thread state within the execution unit 600 allows for rapid preemption of threads if they become blocked or idle. The instruction fetch / prefetch unit 603 can fetch instructions from the instruction cache of a higher level of execution logic (e.g., instruction cache 506, as shown in Figure 5A). The instruction fetch / prefetch unit 603 can also issue prefetch requests for instructions to be loaded into the instruction cache based on an analysis of currently running threads. The instruction decode unit 604 can be used to decode instructions executed by the arithmetic unit. In one embodiment, the instruction decode unit 604 can be used as a secondary decoder to decode complex instructions into micro-operation components.

[0101]

[0152] The execution unit 600 additionally includes a register file 606 that can be used by hardware threads running on the execution unit 600. Registers in the register file 606 can be divided across logic used to execute multiple concurrent threads within the arithmetic unit 610 of the execution unit 600. The number of logical threads that may be executed by the graphics execution unit 600 is not limited to the number of hardware threads, and multiple logical threads can be assigned to each hardware thread. The size of the register file 606 may vary depending on the embodiment, based on the number of supported hardware threads. In one embodiment, register renaming can be used to dynamically assign registers to hardware threads.

[0102]

[0153] Figure 7 is a block diagram showing graphics processor instruction formats 700 according to several embodiments. In one or more embodiments, the graphics processor execution unit supports an instruction set having instructions in multiple formats. Solid boxes indicate components commonly included in execution unit instructions, while dashed lines include components that are optional or only included in a subset of instructions. In some embodiments, the instruction formats 700 described and illustrated are macro instructions, in that they are instructions supplied to the execution unit, as opposed to micro-operations resulting from instruction decoding when the instructions are processed.

[0103]

[0154] In some embodiments, the graphics processor execution unit natively supports instructions in the 128-bit instruction format 710. The 64-bit compact instruction format 730 is available for some instructions based on the selected instruction, instruction options, and number of operands. The native 128-bit instruction format 710 provides access to all instruction options, while the 64-bit format 730 restricts some options and processing. The native instructions available in the 64-bit format 730 vary by embodiment. In some embodiments, instructions are compacted using a set of index values ​​in the index field 713. The execution unit hardware refers to a set of compression tables based on the index values ​​and uses the output of the compression tables to reconstruct the native instructions in the 128-bit instruction format 710. Other sizes and formats of instructions are available.

[0104]

[0155] For each format, the instruction opcode 712 defines the operation performed by the execution unit. The execution unit executes each instruction in parallel across multiple data elements of each operand. For example, in response to an add instruction, the execution unit performs simultaneous addition across each color channel representing a texture or picture element. By default, the execution unit executes each instruction across all data channels of the operand. In some embodiments, the instruction control field 714 allows control over certain execution options, such as channel selection (e.g., prediction) and data channel ordering (e.g., swizzle). For instructions in the 128-bit instruction format 710, the exec-size field 716 limits the number of data channels executed in parallel. In some embodiments, the exec-size field 716 is not available for use with the 64-bit compact instruction format 730.

[0105]

[0156] Some execution unit instructions have up to three operands, including two source operands, src0 720, src1 722, and one destination 718. In some embodiments, the execution unit supports dual destination instructions in which one of the destinations is implied. Data processing instructions may have a third source operand (e.g., SRC2 724), and the instruction opcode 712 determines the number of source operands. The last source operand of an instruction may be a direct (e.g., hard-coded) value passed by the instruction.

[0106]

[0157] In some embodiments, the 128-bit instruction format 710 includes an access / address mode field 726 that specifies, for example, whether direct register addressing mode or indirect register addressing mode is used. When direct register addressing mode is used, the register addresses of one or more operands are directly provided by bits in the instruction.

[0107]

[0158] In some embodiments, the 128-bit instruction format 710 includes an access / address mode field 726 that specifies the access mode and / or address mode of the instruction. In one embodiment, the access mode is used to define the data access alignment for the instruction. Some embodiments support access modes including 16-byte aligned access mode and 1-byte aligned access mode, where the byte alignment of the access mode determines the access alignment of the instruction operands. For example, in the first mode, the instruction can use byte-aligned addressing for the source and destination operands, while in the second mode, the instruction can use 16-byte aligned addressing for all source and destination operands.

[0108]

[0159] In one embodiment, the address mode portion of the access / address mode field 726 determines whether the instruction uses direct or indirect addressing. When direct register addressing mode is used, the bits in the instruction directly provide the register addresses of one or more operands. When indirect register addressing mode is used, the register addresses of one or more operands can be calculated based on the address immediate field and address register values ​​in the instruction.

[0109]

[0160] In some embodiments, instructions are grouped based on the opcode 712 bit field to simplify opcode decoding 740. For 8-bit opcodes, bits 4, 5, and 6 allow the execution unit to determine the type of opcode. The detailed opcode groupings shown are merely examples. In some embodiments, the move and logic opcode group 742 includes data move and logic instructions (e.g., move (mov), compare (cmp)). In some embodiments, the move and logic group 742 shares five most significant bits (MSB), where move (mov) instructions are in the form of 0000xxxxb and logic instructions are in the form of 0001xxxb. The flow control instruction group 744 (e.g., call, jump (jmp)) includes instructions in the form of 0010xxxxb (e.g., 0x20). Other instruction groups 746 include a mix of instructions, including synchronous instructions (e.g., wait, send) in the form of 0011xxxxb (e.g., 0x30). Parallel mathematical instruction group 748 includes component-based arithmetic instructions (e.g., add, multiply) in the form of 0100xxxxb (e.g., 0x40). Parallel mathematical group 748 performs arithmetic operations in parallel across data channels. Vector mathematical group 750 includes arithmetic instructions (e.g., dp4) in the form of 0101xxxxb (e.g., 0x50). Vector mathematical groups perform operations such as dot product calculations of vector operands. The illustrated opcode decode 740 can, in one embodiment, be used to determine which part of the execution unit is used to execute the decoded instruction. For example, some instructions may be designated as systolic instructions executed by a systolic array. Other instructions, such as ray tracing instructions (not shown), can be routed to ray tracing cores or ray tracing logic within a slice or partition of execution logic.

[0110] Graphics pipeline

[0161] Figure 8 is a block diagram of another embodiment of the graphics processor 800. Elements in Figure 8 having the same reference numeral (or designation) as any other elements in the present application may, but are not limited to, operate or function in the same manner as those described elsewhere in the present application.

[0111]

[0162] In some embodiments, the graphics processor 800 includes a geometry pipeline 820, a media pipeline 830, a display engine 840, thread execution logic 850, and a rendering output pipeline 870. In some embodiments, the graphics processor 800 is a graphics processor in a multi-core processing system that includes one or more general-purpose processing cores. The graphics processor is controlled by register writes to one or more control registers (not shown) or by commands issued to the graphics processor 800 via a ring interconnect 802. In some embodiments, the ring interconnect 802 connects the graphics processor 800 to other processing components, such as other graphics processors or general-purpose processors. Commands from the ring interconnect 802 are interpreted by a command streamer 803 that supplies instructions to individual components of the geometry pipeline 820 or the media pipeline 830.

[0112]

[0163] In some embodiments, the command streamer 803 reads vertex data from memory and directs the operation of the vertex fetcher 805 to execute vertex processing commands provided by the command streamer 803. In some embodiments, the vertex fetcher 805 provides the vertex data to the vertex shader 807, which performs coordinate space transformations and lighting operations for each vertex. In some embodiments, the vertex fetcher 805 and the vertex shader 807 execute vertex processing instructions by dispatching execution threads to execution units 852A-852B via the thread dispatcher 831.

[0113]

[0164] In some embodiments, the execution units 852A-852B are arrays of vector processors having instruction sets for performing graphics and media operations. In some embodiments, the execution units 852A-852B have attached L1 caches 851 that are specific to each array or shared between arrays. The caches can be configured as data caches, instruction caches, or a single cache partitioned to contain data and instructions in different partitions.

[0114]

[0165] In some embodiments, the geometry pipeline 820 includes tessellation components for performing hardware-accelerated tessellation of 3D objects. In some embodiments, a programmable hull shader 811 sets the tessellation operation. A programmable domain shader 817 provides backend evaluation of the tessellation output. A tessellator 813 operates in the direction of the hull shader 811 and includes special-purpose logic for generating a set of detailed geometric objects based on a rough geometric model provided as input to the geometry pipeline 820. In some embodiments, the tessellation components (e.g., hull shader 811, tessellator 813, and domain shader 817) can be bypassed when tessellation is not used. The tessellation components can operate based on data received from the vertex shader 807.

[0115]

[0166] In some embodiments, a complete geometric object can be processed by the geometric shader 819 by one or more threads dispatched to execution units 852A-852B, or it can proceed directly to the clipper unit 829. In some embodiments, the geometric shader operates on the entire geometric object, rather than on vertices or vertex patches as in earlier stages of the graphics pipeline. When tessellation is disabled, the geometric shader 819 receives input from the vertex shader 807. In some embodiments, the geometric shader 819 can be programmed by the geometric shader program to perform geometric tessellation when the tessellation unit is disabled.

[0116]

[0167] Before rasterization, clipper 829 processes the vertex data. Clipper 829 may be a fixed-function clipper or a programmable clipper having clipping and geometric shader capabilities. In some embodiments, the rasterizer and depth test component 873 in the rendering output pipeline 870 dispatches a pixel shader to convert the geometric object into a pixel-level representation. In some embodiments, the pixel shader logic is contained within the thread execution logic 850. In some embodiments, the application can bypass the rasterizer and depth test component 873 and access the unrasterized vertex data via the stream output unit 823.

[0117]

[0168] The graphics processor 800 has an interconnection bus, interconnection fabric, or other interconnection mechanism that enables the transmission of data and messages between the main components of the processor. In some embodiments, the execution units 852A-852B and associated logical units (e.g., L1 cache 851, sampler 854, texture cache 858, etc.) are interconnected via a data port 856 to perform memory access and communicate using the processor's rendering output pipeline components. In some embodiments, each of the sampler 854, caches 851 and 858, and execution units 852A-852B has a separate memory access path. In one embodiment, the texture cache 858 can also be configured as a sampler cache.

[0118]

[0169] In some embodiments, the rendering output pipeline 870 includes a rasterizer and depth test component 873 that translates vertex-based objects into representations based on associated pixels. In some embodiments, the rasterizer logic includes a window / mask component for performing fixed-function triangle and line rasterization. Associated rendering caches 878 and depth caches 879 are also available in some embodiments. The pixel processing component 877 performs pixel-based processing on the data, although in some examples, pixel processing related to 2D processing (e.g., bit-block image transfer with blending) is performed by the 2D engine 841 or replaced by the display controller 843 using an overlay display plane at display time. In some embodiments, a shared L3 cache 875 is available to all graphics components, enabling data sharing without using main system memory.

[0119]

[0170] In some embodiments, the graphics processor media pipeline 830 includes a media engine 837 and a video front end 834. In some embodiments, the video front end 834 receives pipeline commands from a command streamer 803. In some embodiments, the media pipeline 830 includes individual command streamers. In some embodiments, the video front end 834 processes media commands before sending them to the media engine 837. In some embodiments, the media engine 837 includes a thread generation function that generates threads for dispatch to thread execution logic 850 by a thread dispatcher 831.

[0120]

[0171] In some embodiments, the graphics processor 800 includes a display engine 840. In some embodiments, the display engine 840 is external to the processor 800 and is coupled to the graphics processor via a ring interconnect 802 or some other interconnect bus or fabric. In some embodiments, the display engine 840 includes a 2D engine 841 and a display controller 843. In some embodiments, the display engine 840 includes dedicated logic that can operate independently of the 3D pipeline. In some embodiments, the display controller 843 is coupled to a display device (not shown), which may be a system-integrated display device, such as one in a laptop computer, or an external display device attached via a display device connector.

[0121]

[0172] In some embodiments, the geometric pipeline 820 and media pipeline 830 can be configured to perform operations based on multiple graphics and media programming interfaces and are not specific to any one application programming interface (API). In some embodiments, driver software for the graphics processor translates API calls specific to a particular graphics or media library into commands that can be processed by the graphics processor. In some embodiments, support for OpenGL (Open Graphics Library), OpenCL (Open Computing Language), and / or Vulkan graphics and computing APIs is provided by the Khronos Group. In some embodiments, support for the Direct3D library from Microsoft Corporation may also be provided. In some embodiments, combinations of these libraries may be supported. Support for OpenCV (Open Source Computer Vision Library) may also be provided. Future APIs with compatible 3D pipelines will also be supported if mapping from future API pipelines to graphics processor pipelines is possible.

[0122] Graphics Pipeline Programming

[0173] Figure 9A is a block diagram showing graphics processor command format 900 in several embodiments. Figure 9B is a block diagram showing graphics processor command sequence 910 in an embodiment. In Figure 9A, solid boxes indicate components commonly included in graphics commands, and dashed lines indicate components that are optional or included only in a subset of graphics commands. The exemplary graphics processor command format 900 in Figure 9A includes a data field for identifying client 902, a command operation code (opcode) 904, and data 906 for the command. Sub-opcodes 905 and command size 908 are also included in some commands.

[0123]

[0174] In some embodiments, client 902 specifies a client unit of the graphics device that processes the command data. In some embodiments, a graphics processor command parser examines the client field of each command to route the command data to the appropriate client unit, conditional on further processing of the command. In some embodiments, the graphics processor client unit includes a memory interface unit, a rendering unit, a 2D unit, a 3D unit, and a media unit. Each client unit has a corresponding processing pipeline for processing commands. When a command is received by a client unit, the client unit reads the opcode 904, and any sub-opcodes 905, and determines the action to perform. The client unit executes the command using the information in the data field 906. In some commands, an explicit command size 908 is expected to specify the size of the command. In some embodiments, the command parser automatically determines the size of at least some commands based on the command opcode. In some embodiments, commands are aligned in multiples of double words. Other command formats may also be used.

[0124]

[0175] The flowchart in Figure 9B shows an exemplary graphics processor command sequence 910. In some embodiments, the software or firmware of a data processing system characterizing an embodiment of the graphics processor uses a version of the command sequence that indicates how to set up, execute, and complete a set of graphics operations. Sample command sequences are illustrated and described for illustrative purposes only, as these specific commands or embodiments not limited to this command sequence are shown. Furthermore, commands may be issued as batches of commands in a command sequence so that the graphics processor processes the sequence of commands at least partially simultaneously.

[0125]

[0176] In some embodiments, the graphics processor command sequence 910 begins with a pipeline flush command 912, which causes any active graphics pipeline to complete any currently incomplete commands to the pipeline. In some embodiments, the 3D pipeline 922 and the media pipeline 924 do not operate simultaneously. The pipeline flush is performed to cause any active graphics pipeline to complete any incomplete commands. In response to the pipeline flush, the graphics processor's command parser pauses command processing until the active drawing engine completes any incomplete operations and the associated read cache is invalidated. Optionally, any data in the rendering cache marked as "dirty" can be flushed into memory. In some embodiments, the pipeline flush command 912 can be used for pipeline synchronization or before putting the graphics processor into a low-power state.

[0126]

[0177] In some embodiments, the pipeline selection command 913 is used when a command sequence explicitly switches between pipelines using a graphics processor. In some embodiments, the pipeline selection command 913 is used only once within the execution context before issuing pipeline commands, unless the context issues commands to both pipelines. In some embodiments, the pipeline flush command 912 is used immediately before pipeline switching via the pipeline selection command 913.

[0127]

[0178] In some embodiments, pipeline control commands 914 are used to construct a graphics pipeline for computation and to program the 3D pipeline 922 and media pipeline 924. In some embodiments, pipeline control commands 914 set the pipeline state for the active pipeline. In one embodiment, pipeline control commands 914 are used to clear data from one or more cache memories in the active pipeline and for pipeline synchronization before processing a batch of commands.

[0128]

[0179] In some embodiments, the return buffer state command 916 is used to configure a set of return buffers for each pipeline to write data to. Some pipeline operations use the allocation, selection, or configuration of one or more return buffers on which the operation writes intermediate data during processing. In some embodiments, the graphics processor also uses one or more return buffers to store output data and to perform cross-thread communication. In some embodiments, the return buffer state 916 includes selecting the size and number of return buffers to be used for a set of pipeline operations.

[0129]

[0180] The remaining commands in the command sequence differ based on the active pipeline for the calculation. Based on the pipeline decision 920, the command sequence is aligned to either the 3D pipeline 922, which begins in 3D pipeline state 930, or the media pipeline 924, which begins in media pipeline state 940.

[0130]

[0181] Commands for setting the 3D pipeline state 930 include 3D state setting commands for state variables that should be set before 3D primitive commands are processed, such as vertex buffer state, vertex element state, constant color state, depth buffer state, and other state variables. The values ​​of these commands are determined at least in part on the specific 3D API being used. In some embodiments, the 3D pipeline state 930 commands may also selectively disable or bypass specific pipeline elements if those elements are not being used.

[0131]

[0182] In some embodiments, the 3D primitive 932 command is used to submit 3D primitives to be processed by the 3D pipeline. The command and associated parameters passed to the graphics processor via the 3D primitive 932 command are forwarded to the vertex fetch function in the graphics pipeline. The vertex fetch function uses the 3D primitive 932 command data to generate a vertex data structure. The vertex data structure is stored in one or more return buffers. In some embodiments, the 3D primitive 932 command is used by a vertex shader to perform vertex operations on the 3D primitive. To process the vertex shader, the 3D pipeline 922 dispatches a shader execution thread to the graphics processor execution unit.

[0132]

[0183] In some embodiments, the 3D pipeline 922 is triggered by an execution command or event 934. In some embodiments, a register write triggers a command execution. In some embodiments, execution is triggered by a 'go' or 'kick' command in a command sequence. In one embodiment, command execution is triggered by a pipeline synchronization command, which flushes the command sequence via the graphics pipeline. The 3D pipeline performs geometric operations on 3D primitives. Once the operations are complete, the resulting geometric objects are rasterized, and the pixel engine colors the resulting pixels. Additional commands for controlling pixel shading and pixel backend operations may be included for these operations.

[0133]

[0184] In some embodiments, the graphics processor command sequence 910 follows the path of the media pipeline 924 when performing media operations. Generally, the specific uses and methods of programming the media pipeline 924 depend on the media or the operations being performed. Certain media decoding operations may be offloaded to the media pipeline during media decoding. In some embodiments, the media pipeline may also be bypassed, and media decoding may be performed entirely or partially using resources provided by one or more general-purpose processing cores. In one embodiment, the media pipeline also includes elements for general-purpose graphics processor unit (GPGPU) operations, where the graphics processor is used to perform SIMD vector operations using compute shader programs that are not explicitly related to rendering graphics primitives.

[0134]

[0185] In some embodiments, the media pipeline 924 is configured similarly to the 3D pipeline 922. A set of commands for setting the media pipeline state 940 is dispatched to or placed in the command queue before the media object command 942. In some embodiments, the command for the media pipeline state 940 includes data for configuring the media pipeline elements used to process media objects. This includes data for configuring the video decoding and video encoding logic within the media pipeline, such as the encoding or decoding format. In some embodiments, the command for the media pipeline state 940 also supports the use of one or more pointers to “indirect” state elements, which include a batch of state settings.

[0135]

[0186] In some embodiments, a media object command 942 supplies a pointer to a media object for processing by the media pipeline. The media object includes a memory buffer containing the video data to be processed. In some embodiments, all media pipeline states should be "active" before issuing the media object command 942. Once the pipeline states are set and the media object command 942 is queued, the media pipeline 924 is triggered by an execution command 944 or an equivalent execution event (e.g., a register write). The output from the media pipeline 924 can then be post-processed by operations provided by the 3D pipeline 922 or the media pipeline 924. In some embodiments, GPGPU operations are set up and executed in a similar manner to media operations.

[0136] Graphics Software Architecture

[0187] Figure 10 shows exemplary graphics software architectures for a data processing system 1000 according to several embodiments. In some embodiments, the software architecture includes a 3D graphics application 1010, an operating system 1020, and at least one processor 1030. In some embodiments, the processor 1030 includes a graphics processor 1032 and one or more general-purpose processor cores 1034. The graphics application 1010 and the operating system 1020 each run within the system memory 1050 of the data processing system.

[0137]

[0188] In some embodiments, the 3D graphics application 1010 includes one or more shader programs, including shader instructions 1012. The shader language instructions may be in a high-level shader language such as Direct3D's HLSL (High-level Shader Language) or GLSL (OpenGL Shader Language). The application also includes executable machine language instructions 1014 suitable for execution by a general-purpose processor core 1034. The application also includes graphics objects 1016 defined by vertex data.

[0138]

[0189] In some embodiments, the operating system 1020 is an operating system such as Microsoft®, Windows®, a proprietary UNIX®, or an open-source UNIX®, which uses a variant of the Linux® kernel. The operating system 1020 can support graphics APIs 1022 such as the Direct3D API, OpenGL API, or Vulkan API. When the Direct3D API is used, the operating system 1020 uses a front-end shader compiler 1024 to compile HLSL shader instructions 1012 into a lower-level shader language. Compilation may be just-in-time (JIT) compilation, or the application may perform pre-compilation of shaders. In some embodiments, high-level shaders are compiled into low-level shaders during the compilation of the 3D graphics application 1010. In some embodiments, shader instruction 1012 is provided in an intermediate form, such as a version of SPIR (Standard Portable Intermediate Representation) used by the Vulkan API.

[0139]

[0190] In some embodiments, the user-mode graphics driver 1026 includes a back-end shader compiler 1027 for translating shader instructions 1012 into hardware-specific representations. When the OpenGL API is used, the GLSL high-level language shader instructions 1012 are passed to the user-mode graphics driver 1026 for compilation. In some embodiments, the user-mode graphics driver 1026 communicates with the kernel-mode graphics driver 1029 using the operating system kernel-mode function 1028. In some embodiments, the kernel-mode graphics driver 1029 communicates with the graphics processor 1032 to dispatch commands and instructions.

[0140] IP core implementation

[0191] One or more aspects of at least one embodiment can be implemented by representative code stored in a machine-readable medium that represents and / or defines logic within an integrated circuit, such as a processor. For example, the machine-readable medium may include instructions that represent various logic within the processor. In some implementations, the machine-readable medium is also referred to here as a computer-readable medium or a non-temporary computer-readable medium. When read by a machine, the instructions allow the machine to construct logic to perform the techniques described herein. Such representations are known as “IP cores” and are reusable logic units for integrated circuits that can be stored in a tangible machine-readable medium as hardware models describing the structure of the integrated circuit. Hardware models can be supplied to various consumers or manufacturing facilities that load the hardware models into manufacturing machines that manufacture integrated circuits. Integrated circuits can be manufactured so that the circuits perform the operations described in relation to any of the embodiments described herein.

[0141]

[0192] Figure 11A is a block diagram showing an IP core development system 1100 that can be used to manufacture an integrated circuit to perform the operation according to an embodiment. The IP core development system 1100 may be used to make a modular, reusable design that can be incorporated into a larger design or used to build an entire integrated circuit (e.g., a System of Control (SOC) integrated circuit). The design facility 1130 can generate a software simulation 1110 of the IP core design in a high-level programming language (e.g., C / C++). The software simulation 1110 can be used to design, test, and verify the behavior of the IP core using a simulation model 1112. The simulation model 1112 may include functional simulation, behavioral simulation, and / or timing simulation. A register transfer level (RTL) design 1115 can then be created or synthesized from the simulation model 1112. The RTL design 1115 is an abstraction of the behavior of an integrated circuit that models the flow of digital signals between hardware registers, including the associated logic executed with the modeled digital signals. In addition to the RTL design 1115, lower-level designs at the logic or transistor level may be generated, designed, or synthesized. Therefore, specific details of the initial design and simulation may vary.

[0142]

[0193] The RTL design 1115 or equivalent may be further synthesized by the design facility into a hardware model 1120, which may be in a hardware description language (HDL), or any other representation of the physical design data. The HDL can be further simulated or tested to verify the IP core design. The IP core design can be stored using non-volatile memory 1140 (e.g., hard disk, flash memory, or any non-volatile storage medium) for delivery to a third-party manufacturing facility 1165. Alternatively, the IP core design may be transmitted via a wired connection 1150 or a wireless connection 1160 (e.g., via the Internet). The manufacturing facility 1165 can then manufacture an integrated circuit based at least in part on the IP core design. The manufactured integrated circuit can be configured to perform operation according to at least one embodiment described herein.

[0143]

[0194] Figure 11B shows a side section view of an integrated circuit package assembly 1170 according to several embodiments described herein. The integrated circuit package assembly 1170 represents the implementation of one or more processor or accelerator devices described herein. The package assembly 1170 includes multiple units of hardware logic 1172, 1174 connected to a substrate 1180. The logic 1172, 1174 may be implemented at least partially in hardware as configurable logic or fixed-function logic, and may include any one or more parts of a processor core, graphics processor, or other accelerator device described herein. Each unit of logic 1172, 1174 may be implemented in a semiconductor die and coupled to the substrate 1180 via an interconnection structure 1173. The interconnection structure 1173 may be configured to route electrical signals between the logic 1172, 1174 and the substrate 1180, and may include, but is not limited to, interconnections such as bumps or pillars. In some embodiments, the interconnect structure 1173 may be configured to route electrical signals, such as input / output (I / O) signals and / or power or ground signals, related to the operation of logic 1172, 1174, for example. In some embodiments, the substrate 1180 is an epoxy-based laminate. In other embodiments, the substrate 1180 may include other suitable types of substrates. The package assembly 1170 can be connected to other electrical devices via the package interconnect 1183. The package interconnect 1183 may be coupled to the surface of the substrate 1180 to route electrical signals to other electrical devices such as a motherboard, other chipsets, or multi-chip modules.

[0144]

[0195] In some embodiments, units of logic 1172 and 1174 are electrically coupled to a bridge 1182 configured to route electrical signals between logic 1172 and 1174. The bridge 1182 may be a high-density interconnect structure that provides a path for electrical signals. The bridge 1182 may include a bridge substrate made of glass or a suitable semiconductor material. To provide chip-to-chip connectivity between logic 1172 and 1174, electrical routing functions can be formed on the bridge substrate.

[0196] Although two logic units, 1172 and 1174, and a bridge, 1182, are shown, the embodiments described herein may include more or fewer logic units on one or more dies. Since the bridge 1182 may be omitted when the logic is contained on a single die, one or more dies can be connected by zero or more bridges. Alternatively, multiple dies or logic units can be connected by one or more bridges. Furthermore, multiple logic units, dies, and bridges can be connected to each other in other possible configurations, including a three-dimensional configuration.

[0145]

[0197] Figure 11C shows a package assembly 1190 containing multiple hardware logic chiplets connected to a substrate 1180 (e.g., a base die). Graphics processing units, parallel processors, and / or computing accelerators, as described herein, can be composed of a variety of separately manufactured silicon chiplets. In this context, a chiplet is at least partially packaged integrated circuit containing individual logic units that can be assembled together with other chiplets into a larger package. A variety of chiplets with different IP core logic can be assembled into a single device. Furthermore, chiplets can be integrated into a base die or base chiplet using active interposer technology. The concepts described herein enable interconnection and communication between various forms of IP within a GPU. IP cores can be manufactured using various process technologies and configured during manufacturing, thereby avoiding the complexity of concentrating on a single manufacturing process on a large SoC with multiple IPs, especially multiple flavor IPs. Enabling the use of multiple process technologies improves time to market and provides a cost-effective way to create multiple product SKUs. In addition, the decentralized IP is independently power-gated, and components not used in a given workload can be powered off, reducing overall power consumption.

[0146]

[0198] The hardware logic chiplets may include a special-purpose hardware logic chiplet 1172, a logic or I / O chiplet 1174, and / or a memory chiplet 1175. The hardware logic chiplets 1172 and 1174 may be implemented, at least in part, in configurable logic or fixed functional logic hardware, and may include any one or more of the processor cores, graphics processors, parallel processors, or other accelerator devices described herein. The memory chiplet 1175 may be DRAM (e.g., GDDR, HBM) memory or cache (SRAM) memory.

[0147]

[0199] Each chiplet can be manufactured as an individual semiconductor die and coupled to a substrate 1180 via an interconnection structure 1173. The interconnection structure 1173 may be configured to route electrical signals between various chiplets and logic within the substrate 1180. The interconnection structure 1173 may include, but is not limited to, bumps or pillars. In some embodiments, the interconnection structure 1173 may be configured to route electrical signals such as input / output (I / O) signals and / or power or ground signals related to the operation of logic, I / O, and memory chiplets.

[0148]

[0200] In some embodiments, the substrate 1180 is an epoxy-based laminate. In other embodiments, the substrate 1180 may include other suitable types of substrates. The package assembly 1190 can be connected to other electrical devices via the package interconnect 1183. The package interconnect 1183 may be bonded to the surface of the substrate 1180 to route electrical signals to other electrical devices such as a motherboard, other chipsets, or multi-chip modules.

[0149]

[0201] In some embodiments, the logic or I / O chiplet 1174 and the memory chiplet 1175 can be electrically coupled via a bridge 1187 configured to route electrical signals between the logic or I / O chiplet 1174 and the memory chiplet 1175. The bridge 1187 may be a high-density interconnect structure that provides the route for electrical signals. The bridge 1187 may include a bridge substrate made of glass or a suitable semiconductor material. To provide a chip-to-chip connection between the logic or I / O chiplet 1174 and the memory chiplet 1175, the electrical routing function can be formed on the bridge substrate. The bridge 1187 may also be referred to as a silicon bridge or interconnect bridge. For example, in some embodiments, the bridge 1187 is an embedded multi-die interconnect bridge (EMIB). In some embodiments, the bridge 1187 may simply be a direct connection from one chiplet to another.

[0150]

[0202] The board 1180 may include hardware components for I / O 1191, cache memory 1192, and other hardware logic 1193. To enable communication between various logic chiplets and logic 1191, 1193 within the board 1180, the fabric 1185 may be embedded within the board 1180. In one embodiment, the I / O 1191, fabric 1185, cache, bridge, and other hardware logic 1193 may be integrated into a base die stacked on top of the board 1180. The fabric 1185 may be another form of packet switching fabric that switches data packets between a network on chip interconnects or between components of a package assembly.

[0151]

[0203] In various embodiments, the package assembly 1190 may include fewer or more components and chiplets interconnected by the fabric 1185 or one or more bridges 1187. The chiplets within the package assembly 1190 may be arranged in 3D or 2.5D format. Generally, the bridge structure 1187 may be used to facilitate point-to-point interconnections between, for example, logic or I / O chiplets and memory chiplets. The fabric 1185 can be used to interconnect various logic and / or I / O chiplets (e.g., chiplets 1172, 1174, 1191, 1193) with other logic and / or I / O chiplets. In one embodiment, the onboard cache memory 1192 can function as a global cache for the package assembly 1190, part of a distributed global cache, or a dedicated cache for the fabric 1185.

[0152]

[0204] Figure 11D shows a package assembly 1194 including a replaceable chiplet 1195 according to one embodiment. The replaceable chiplet 1195 can be assembled into a standardized slot on one or more base chiplets 1196, 1198. The base chiplets 1196, 1198 may be coupled via a bridge interconnect 1197, which can be similar to other bridge interconnects described herein, such as EMIB. Memory chiplets can also be connected to logic or I / O chiplets via the bridge interconnect. I / O and logic chiplets can communicate via the interconnect fabric. Each base chiplet can support one or more slots in a standardized format for one of logic, I / O, or memory / cache.

[0153]

[0205] In one embodiment, the SRAM and power distribution circuit can be manufactured within one or more of the base chiplets 1196, 1198, which can be manufactured using different process technologies than the replaceable chiplet 1195 stacked on top of the base chiplets. For example, the base chiplets 1196, 1198 can be manufactured using a larger process technology, while the replaceable chiplet can be manufactured using a smaller process technology. One or more replaceable chiplets 1195 may be memory (e.g., DRAM) chiplets. Various memory densities can be selected for the package assembly 1194 based on the target power and / or performance for the product using the package assembly 1194. Furthermore, logic chiplets with a wide variety of functional units can be selected at assembly based on the target power and / or performance for the product. In addition, chiplets containing different types of IP logic cores can be inserted into the replaceable chiplet slots, enabling hybrid processor designs that can mix and match different technology IP blocks.

[0154] System examples in chip integrated circuits

[0206] Figure 12-13B shows an exemplary integrated circuit and associated graphics processor that can be manufactured using one or more IP cores according to the various embodiments described herein. In addition to those shown, other logic and circuitry may be included, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0155]

[0207] Figure 12 is a block diagram showing an exemplary system in a chip integrated circuit 1200 that can be manufactured using one or more IP cores according to one embodiment. The exemplary integrated circuit 1200 includes one or more application processors 1205 (e.g., CPUs) and at least one graphics processor 1210, and may additionally include an image processor 1215 and / or a video processor 1220, all of which may be modular IP cores from the same or multiple different design facilities. The integrated circuit 1200 includes a USB controller 1225, a UART controller 1230, an SPI / SDIO controller 1235, and I 2 S / I 2 The integrated circuit includes peripheral or bus logic, including a C controller 1240. Furthermore, the integrated circuit may include a display device 1245 coupled to one or more of the following: a High-Resolution Multimedia Interface (HDMI®) controller 1250 and a Mobile Industrial Processor Interface (MIPI) display interface 1255. Storage may be provided by a flash memory subsystem 1260, including flash memory and a flash memory controller. A memory interface may be provided via a memory controller 1265 for access to SDRAM or SRAM memory devices. Some integrated circuits further include an embedded security engine 1270.

[0156]

[0208] Figures 13A and 13B are block diagrams illustrating exemplary graphics processors for use within a SoC according to embodiments described herein. Figure 13A shows an exemplary graphics processor 1310 of a system in a chip integrated circuit that can be manufactured using one or more IP cores, according to embodiments. Figure 13B shows an additional exemplary graphics processor 1340 of a system in a chip integrated circuit that can be manufactured using one or more IP cores, according to embodiments. Graphics processor 1310 in Figure 13A is an example of a low-power graphics processor core. Graphics processor 1340 in Figure 13B is an example of a high-performance graphics processor core. Graphics processors 1310 and 1340 can each be a variation of graphics processor 1210 in Figure 12.

[0157]

[0209] As shown in Figure 13A, the graphics processor 1310 includes a vertex processor 1305 and one or more fragment processors (e.g., 1315A, 1315B, 1315C, 1315D, 1315N-1, and 1315N). The graphics processor 1310 is capable of executing different shader programs by separate logic, such that the vertex processor 1305 is optimized to perform calculations against vertex shader programs, while one or more fragment processors 1315A-1315N perform fragment (e.g., pixel) shader calculations against fragment or pixel shader programs. The vertex processor 1305 executes the vertex processing stage of the 3D graphics pipeline and generates primitive and vertex data. The fragment processors 1315A-1315N use the primitive and vertex data generated by the vertex processor 1305 to generate a frame buffer that will be displayed on the display device. In one embodiment, the fragment processors 1315A-1315N are optimized to execute a fragment shader program, as provided by the OpenGL API, which can be used to perform similar operations to a pixel shader program, as provided by the Direct3D API.

[0158]

[0210] The graphics processor 1310 further includes one or more memory management units (MMUs) 1320A-1320B, caches 1325A-1325B, and circuit interconnects 1330A-1330B. One or more MMUs 1320A-1320B provide virtual-to-physical address mapping for the graphics processor 1310, including vertex processors 1305 and / or fragment processors 1315A-1315N, which can reference vertex or image / texture data stored in memory, in addition to vertex or image / texture data stored in one or more caches 1325A-1325B. In one embodiment, one or more MMUs 1320A-1320B can synchronize with other MMUs in the system, including one or more MMUs associated with one or more application processors 1205, image processor 1215, and / or video processor 1220 in Figure 12, so that each processor 1205-1220 can participate in a shared or unified virtual memory system. One or more circuit interconnects 1330A-1330B, according to the embodiment, allow the graphics processor 1310 to interface with other IP cores in the SoC, either via the SoC's internal bus or via a direct connection.

[0159]

[0211] As shown in Figure 13B, the graphics processor 1340 includes one or more MMUs 1320A-1320B, caches 1325A-1325B, and circuit interconnects 1330A-1330B of the graphics processor 1310 in Figure 13A. The graphics processor 1340 includes one or more shader cores 1355A-1355N (e.g., 1355A, 1355B, 1355C, 1355D, 1355E, 1355F, or 1355N-1, and 1355N), and the one or more shader cores provide a unified shader core architecture in which a single core or type or core can execute all types of programmable shader code, including shader program code that implements vertex shaders, fragment shaders, and / or compute shaders. The exact number of shader cores presented may vary depending on the embodiment and implementation. Furthermore, the graphics processor 1340 includes an intercore task manager 1345 that functions as a thread dispatcher for dispatching execution threads to one or more shader cores 1355A-1355N, and a tile unit 1358 that accelerates tile processing for tile-based rendering, and the rendering operations of the scene are subdivided in image space, for example, to take advantage of local spatial coherence within the scene or to optimize the use of the internal cache.

[0160]

[0212] In some embodiments, processing resources represent processing elements (e.g., GPGPU cores, ray tracing cores, tensor cores, execution resources, execution units (EUs), stream processors, streaming multiprocessors (SMs), graphics multiprocessors) associated with graphics processors or graphics processor structures within a GPU as described herein (e.g., parallel processing units, graphics processing engines, multicore groups, arithmetic units, arithmetic units of subsequent graphics cores). For example, processing resources may be one of the GPGPGPU cores or tensor / ray tracing cores of a graphics multiprocessor; a ray tracing core, tensor core, or GPGPU core of a graphics multiprocessor; execution resources of a graphics multiprocessor; one of the GFX cores, tensor cores, or ray tracing cores of a multicore group; one of the vector logic units or scalar logic units of an arithmetic unit; an EU array or an execution unit having an EU array; an execution unit of execution logic; and / or an execution unit. Processing resources may also be, for example, a graphics processing engine, a processing cluster, a GPGPU, a GPGPU, a graphics processing engine, a graphics processing engine cluster, and / or execution resources within a graphics processing engine. Processing resources may also be processing resources within a graphics processor, a graphics processor, and / or a graphics processor.

[0161]

[0213] Support for 8-bit floating-point format operands in the arithmetic architecture. Parallel computing is a type of computation in which many calculations or processes are executed simultaneously. Parallel computing can come in various forms, including but not limited to SIMD or SIMT. SIMD describes a computer with multiple processing elements that simultaneously perform the same operation on multiple data points. In one example, Figures 5A-5B above refer to SIMD and its implementation in a typical processor in terms of EU, FPU, and ALU. In a typical SIMD machine, data is packaged into registers, each containing an array of channels. Instructions act on data found in channel n of a register, together with data found in the same channel of another register. SIMD machines have an advantage in areas where a single instruction sequence can be applied simultaneously to a large amount of data. For example, in one embodiment, a graphics processor (e.g., GPGPU, GPU, etc.) can be used to perform SIMD vector operations using computational shader programs.

[0162]

[0214] Furthermore, various embodiments can be applied to use cases of execution using single-instruction multiple-threading (SIMT) as an alternative to or in addition to the use of SIMD. References to SIMD cores or operations are also applicable to SIMT and to SIMD in combination with SIMT. The following description is based on SIMD machines. However, the embodiments described herein are not limited to applications in a SIMD context but may also be applied to other parallel computing paradigms such as SIMT. For the sake of ease of discussion and explanation, the following description generally focuses on SIMD implementations. However, the embodiments can be similarly applied to SIMT machines without modification of the techniques and methods described. With respect to SIMT machines, instructions can be provided to a systolic array and executed in the SIMT machine following similar patterns described below. Other types of parallel computers can also utilize the embodiments described herein.

[0163]

[0215] Various embodiments can implement a GPGPU with a matrix acceleration circuit. Such a matrix acceleration circuit can be used to accelerate machine learning (ML) operations.

[0164]

[0216] Figure 14 is a block diagram of a data processing system 1400 according to an embodiment. Various embodiments discussed herein may be implemented in a system such as data processing system 1400. Data processing system 1400 is a heterogeneous processing system having a processor 1402, a unified memory 1410, and a GPGPU 1420 including machine learning acceleration logic. The processor 1402 and GPGPU 1420 can be any processor and GPGPU / parallel processor described herein. The processor 1402 can execute instructions for a compiler 1415 stored in system memory 1412. The compiler 1415 operates on the processor 1402 to compile source code 1414A into compiled code 1414B. The compiled code 1414B may include instructions that can be executed by the processor 1402 and / or instructions that can be executed by the GPGPU 1420. During compilation, compiler 1415 may perform operations to insert metadata, including hints about the level of data parallelism present in the compiled code 1414B, and / or hints about data locality related to threads dispatched based on the compiled code 1414B. Compiler 1415 may include information used to perform such operations, or may perform such operations with the assistance of runtime library 1416. Runtime library 1416 may also assist compiler 1415 in compiling source code 1414A, and may include instructions that are linked at runtime with the compiled code 1414B to assist in the execution of compiled instructions on GPGPU 1420.

[0165]

[0217] Unified memory 1410 represents a unified address space that can be accessed by processor 1402 and GPGPU 1420. Unified memory may include system memory 1412 and GPGPU memory 1418. GPGPU memory 1418 is memory in the address space of GPGPU 1420 and may include part or all of system memory 1412. In one embodiment, GPGPU memory 1418 may also include at least part of any memory dedicated for use by GPGPU 1420. In one embodiment, compiled code 1414B stored in system memory 1412 can be mapped to GPGPU memory 1418 for access by GPGPU 1420.

[0166]

[0218] The GPGPU 1420 includes a plurality of arithmetic blocks 1424A-1424N, which may include one or more of the various arithmetic units or execution elements described herein. In one embodiment, the GPGPU 1420 further includes a matrix accelerator 1423 which may include one or more special function arithmetic units designed to accelerate a subset of matrix operations (e.g., dot product (or inner product)). The GPGPU 1420 may also include a set of resources that can be shared by the arithmetic blocks 1424A-1424N and the matrix accelerator 1423, which includes, but is not limited to, a set of registers 1425, a power and performance module 1426, and a cache 1427. In one embodiment, the registers 1425 include directly and indirectly accessible registers, where the indirectly accessible registers are optimized for use by the matrix accelerator 1423. The power and performance module 1426 can be configured to adjust the clock frequency and power distribution of the arithmetic blocks 1424A-1424N to the power gate idle components within the arithmetic blocks 1424A-1424N. In various embodiments, the cache 1427 may include an instruction cache and / or a lower-level data cache.

[0148] The GPGPU 1420 may further include an L3 data cache 1430, which can be used to cache data accessed from the unified memory 1410 by the matrix accelerator 1423 and / or the arithmetic elements in the arithmetic blocks 1424A-1424N. In one embodiment, the L3 data cache 1430 includes a shared local memory 1432 that can be shared by the arithmetic elements in the arithmetic blocks 1424A-1424N and the matrix accelerator 1423.

[0167]

[0219] In one embodiment, the GPGPU 1420 includes instruction handling logic such as a fetch and decode unit 1421 (also called a decoder, as in this case decoder 1421) and a scheduler controller 1422. The fetch and decode unit 1421 includes a fetch and decode unit that fetches and decodes instructions for execution by one or more of the computer blocks 1424A-1424N or matrix accelerators 1423. Instructions can be scheduled to appropriate functional units within the arithmetic blocks 1424A-1424N or to the matrix accelerators via the scheduler controller 1422. In one embodiment, the scheduler controller 1422 is an ASIC that can be configured to perform advanced scheduling operations. In one embodiment, the scheduler controller 1422 is a microcontroller or a low-energy-per-instruction processing core capable of executing scheduler instructions loaded from a firmware module.

[0220] In one embodiment, several functions performed by computer blocks 1424A-1424N can be directly scheduled or offloaded to matrix accelerator 1423. In various embodiments, matrix accelerator 1423 includes processing element logic configured to efficiently perform matrix operations such as multiplication and addition, and dot product, used by 3D graphics or compute shader programs. In one embodiment, matrix accelerator 1423 can be configured to accelerate operations used by machine learning frameworks. In one embodiment, matrix accelerator 1423 is an application-specific integrated circuit explicitly configured to perform a particular set of parallel matrix multiplication and / or addition operations. In one embodiment, matrix accelerator 1423 is a field-programmable gate array (FPGA) that provides fixed-function logic that can be updated between workloads. The set of matrix operations that can be performed by matrix accelerator 1423 can be limited in relation to the operations that can be performed by compute blocks 1424A-1424N. However, the matrix accelerator 1423 can perform these operations on the arithmetic blocks 1424A-1424N with considerably high throughput.

[0168]

[0221] In some embodiments, the data processing system 1400 in Figure 14 may be used for applications in the fields of artificial intelligence (AI) and machine learning (ML). Advances in these fields have enabled ML models to benefit from low-precision computation for training neural networks. Conventional training platforms support the IEEE-754 floating-point 16 (FP16) and Brain floating-point 16 (bfloat16 or BF16) data formats in high-performance systolic array implementations. However, recent advances have been made to support the training of deep neural networks using lower-precision data formats, such as 8-bit floating-point data formats. One such 8-bit floating-point data format is bfloat8 or BF8. BF8 has a binary format with one sign bit, five exponent bits, and two mantissa bits. In some cases, utilizing the BF8 format can provide up to a twofold improvement in neural network training throughput compared to FP16 or BF16 implementations. However, conventional systems do not provide hardware support for performing operations using 8-bit floating-point operands such as BF8 operands.

[0169]

[0222] The embodiments described herein address the aforementioned shortcomings by providing support for 8-bit floating-point format operands in the arithmetic architecture. In one embodiment, the 8-bit floating-point format described herein is the BF8 format. The embodiments introduce various techniques for supporting 8-bit floating-point format operands in the arithmetic architecture. One technique of the embodiments is systolic dot product accumulate with respect to 8-bit floating-point format input operands. Another technique of the embodiments is converting floating-point data to 8-bit floating-point format data, or converting floating-point data from 8-bit floating-point format data. Another technique of the embodiments is performing efficient stochastic rounding on floating-point format data values. Another technique of the embodiments is hybrid floating-point systolic arithmetic. A technique of further embodiments is performing mixed-mode arithmetic with 8-bit floating-point format operands. The technology of the embodiment described in this case will be explained in more detail below.

[0170] Systolic dot product storage for 8-bit floating-point input operands

[0223] The embodiment provides systolic dot product storage for an 8-bit floating-point format input operand.

[0171]

[0224] As mentioned above, conventional training platforms support the IEEE-754 FP16 and BFLOAT16 data formats in high-performance systolic array implementations. These data formats are also supported in systolic dot-product accumulate (DPAS) engines. As stated above, deep neural networks can be trained using an 8-bit floating-point data format (BFLOAT8 or BF8, binary format = 1s-5e-2m). BFLOAT8 can provide up to a twofold improvement in training throughput compared to FP16 and BFLOAT16 implementations. However, there are no existing solutions that support systolic dot product operations using the BFLOAT8 numeric format.

[0172]

[0225] The embodiment provides an extension to the DPAS (dot product storage systolic) engine to support the BF8 data format. The implementation provides an instruction for performing a matrix dot product on three input operands c += a*b, where the matrices a and b are of the BF data type. Furthermore, the embodiment provides hardware circuitry for fetching, decoding, and executing the instruction. In some implementations, the stored representation of the dot product can be returned in either a 32-bit (FP32) or 16-bit (FP16, BF16) floating-point scheme. The embodiment offers technical advantages such as increased systolic arithmetic density and throughput, reduced data movement costs (because BF8 utilizes half the bandwidth and cache / register space compared to the 16-bit data format), and accelerated training by enabling mixed-precision BFLOAT8 training.

[0173]

[0226] The embodiment provides DPAS instructions to support dot product and cumulative operations on input arguments presented in an 8-bit floating-point (e.g., BF8) data format. Figure 15 is a block diagram of the BFLOAT8 (BF8) binary format 1500 according to the embodiment. The BF8 binary format 1500 is represented by bits of sign 1510, exponent 1520, and mantissa 1530. The sign bit 1510 is 1 bit, the exponent 1520 is 5 bits, and the mantissa 1530 is 2 bits. The 5-bit exponent 1520 uses 15 offset values ​​which are capable of representing normal floating-point values ​​between 6.1e-05 and 5.7344e+04. The BF8 binary format 1500 also supports subnormal values ​​which extend the dynamic range down to a minimum representation value of 1.5e-05.

[0174]

[0227] Figure 16 is a block diagram showing a systolic DP 8-bit FP format operation 1610 performed by an instruction pipeline 1600 according to an embodiment. The instruction pipeline 1600 can, but is not limited to, be configured to perform a systolic DP 8-bit format operation 1610 such as a dot product operation. The dot product of two vectors is a scalar value equal to the sum of the products of the corresponding components of the vectors. The dot product can be calculated as shown in the following equation (1).

[0175]

number

[0228] The dot product may be used in convolution operations of neural networks such as convolutional neural networks (CNNs). The instruction pipeline 1600 used to accelerate hardware instructions may include an instruction fetch and decode unit 1421 that can fetch and decode hardware instructions, and a controller unit 1620 (such as a scheduler controller 1422) that can schedule the decoded instructions to one or more execution units and / or matrix accelerators 1423 of the arithmetic blocks 1424A-1424N (collectively referred to as arithmetic block 1424). The instruction pipeline 1600 may also include a selection circuit 1630, such as a collection of multiplexers (muxes), to route the input data to the arithmetic blocks 1424 and / or matrix accelerators 1423 according to the 8-bit FP format encoded with the hardware instructions of the systolic DP 8-bit format arithmetic 1610.

[0176]

[0229] In one embodiment, hardware instructions can be scheduled for arithmetic block 1424 and offloaded to matrix accelerator 1423. One or more hardware instructions and associated data for executing systolic DP 8-bit FP format arithmetic 1610 can be stored in memory 1650. The output of hardware instructions can also be stored in memory 1650. Memory 1650 can be any memory described herein, including system memory 1412, GPGPU memory 1418, or one or more cache memories 1427, 1430, as shown in Figure 14. In some embodiments, memory 1650 can be one or more register files.

[0177]

[0230] In one embodiment, the matrix accelerator 1423 can execute one or more hardware instructions to perform a systolic DP 8-bit format operation 1610 using a systolic array circuit 1640. The systolic array circuit 1640 may include a combination of programmable and fixed-function hardware that can be configured to perform dot product operations. The function units within the arithmetic block 1424 may also be configured to perform dot product operations. The systolic array circuit 1640 may be configured to perform a limited subset of dot product operations with considerably higher throughput than the arithmetic block 1424.

[0178]

[0231] In this embodiment, the DPAS instruction is provided to perform a systolic dot product and accumulate operation on an 8-bit floating-point format (e.g., BF8) source operand from a register file, accumulate the result with a selected precision (fp32, fp16, bf16), and return the final output written to a register file. This DPAS instruction for performing the systolic DP 8-bit format operation 1610 accepts three input operands to perform the operation c += a*b, where the 'a' and 'b' operands are of 8-bit FP type such as BF8. Some of the supported combinations of input and output operands are shown below.

[0179]

number

[0232] DPAS is a sum-of-products and cumulative operation in a systolic pipeline having BFLOAT8 input (src1 × src2). Each fused sum-of-products (FMA) stage of the systolic pipeline represents a 32-bit SIMD channel in the systolic array circuit 1640 and performs DPAS operations on four input elements from src1 and src2, respectively (e.g., dp4a operation). dst and src0 accept IEEE754 float or half-float operands, and src0 contains the cumulative output from preceding DPAS iterations in the systolic array. Embodiments can utilize, but are not limited to, any iteration of block normalization techniques, including dp4a, dp2a (block=2), dp8a (block=8), dp32a (block=32), etc. Each block normalization technique is associated with its own advantages (e.g., improved area efficiency) and disadvantages (e.g., loss of precision). The specific block normalization technique implemented may be based on the specific application in which it is used.

[0180]

[0233] The 'sdepth' parameter represents the systolic depth of the operation, meaning that these 'sdepth' operations are executed in preference to subsequent registers. The output of each stage is maintained with 32-bit precision, becoming the cumulative input to the next systolic stage. The dst and src0 arguments can accept IEEE-754 float, half-float, and bfloat16 data types, and previously accumulated results are passed to the instruction via the source register (src0). The final accumulated output is converted to the destination data format and written to the destination register (dst). The 'rcount' parameter is the number of iterations of the operation, meaning that the 'rcount' number of dpas instructions is generated, and dst and src0 are registers that advance sequentially, meaning src1 remains the same and src2 advances by 32 elements.

[0181]

[0234] In embodiments, the accumulator operand 'c' can be FP32, FP16, or BF16. The hardware of the systolic array circuit 1640 should support subnormal values ​​(i.e., DAZ=0) with respect to the input. In embodiments, the input subnormal values ​​can be up-converted and normalized on the grid before they are supplied to the first stage of the systolic array circuit 1640.

[0182]

[0235] In some implementations, the partial sum passed through the input argument 'c' can be accumulated at the end of the systolic chain to minimize precision losses resulting from internal normalization and addition. This accumulation of the accumulator input argument ('c') at the end of the systolic chain is called “late accumulate”. The internal sums at each stage of the systolic array are accumulated and rounded to the nearest FP32 value. In some embodiments, the accumulation of the accumulator input argument ('c') may occur at the first stage of the systolic chain or at any intermediate stage of the systolic chain.

[0183]

[0236] Figure 17A is a block diagram showing a systolic array circuit 1700 for performing systolic dot product storage with respect to an 8-bit floating-point format input operand according to an embodiment. In one embodiment, the systolic dot product storage with respect to an 8-bit floating-point format input operand shown in Figure 17A is an exemplary dp4a operation. In one implementation, the systolic array circuit 1700 is identical to the systolic array circuit 1640 described with respect to Figure 16. The systolic array circuit 1700 may include a combination of programmable and fixed-function hardware that can be configured to perform dot product operations. Other modifications and combinations of the circuits and elements of the systolic array circuit 1700 may be implemented, and are not limited to those described herein. Figure 17A provides an example architecture of the systolic array circuit 1700, and other architectures may be implemented to perform systolic dot product storage with respect to an 8-bit floating-point format input operand operation, as discussed herein.

[0184]

[0237] Each FMA unit within the systolic array circuit 1700 performs a vector-dot product (e.g., a four-element vector-dot product (dp4a)) on four pairs of BF8 input values ​​from the src1 and src2 registers. In one embodiment, each FMA unit includes a combination of multipliers 1710a-1710d and shifters 1715b-1715d, as well as an adder 1720. The third input register src0 contains a partial cumulative sum from the preceding dot product iterations. Multiple such FMA units linked together in a systolic array can perform DPAS operation, as will be further described below. The implementation of the systolic array can chain these individual FMA units in any possible order for efficient design, and the order of accumulation is not critical.

[0185]

[0238] In this embodiment, the systolic array circuit 1700 should support subnormal values ​​with respect to the BF8 input (e.g., DAZ=0). This can be achieved by expanding the input exponent and normalizing the subnormal input value on the grid. Multiplication can be performed, for example, using 4-bit multipliers 1710a-1710d and 1730a-1730d without loss of precision. The outputs of multipliers 1710a-1710d and 1730a-1730d can be normalized using shifters such as 32-bit shifters 1715a-1715e and 1735a-1735e after each multiplier. Although the shifters 1715a-1715e and 1735a-1735e are shown as 32-bit shifters, in this embodiment, the shifters 1715a-1715e and 1735a-1735e can have any precision. For example, in cases where block normalization operations with a large block size of 32 are used, the shifters 1715a-1715e and 1735a-1735e can be increased to as many as 48 bits. Thus, although the 32-bit shifters 1715a-1715e and 1735a-1735e are shown for illustrative purposes, the embodiment is not limited to a specific 32-bit shifter size, and the shifters 1715a-1715e and 1735a-1735e may have any precision.

[0186]

[0239] The normalized results output from shifters 1715a-1715e and 1735a-1735e are added together in adders such as 5-way FP32 adders 1720 and 1740, rounded by nearest neighbor rounding, and produce an FP32 output. In some embodiments, the 5-way FP32 adders may be an N-way adder tree (N is configurable) based on the block size selected for normalization. In embodiments, any subnormal values ​​in each subsequent FP32 intermediate result (e.g., in adders 1720 and 1740) are flushed to zero.

[0187]

[0240] As mentioned above, the systolic array circuit 1700 can perform post-accumulation. For post-accumulation, src0 is accumulated at the end of the systolic chain in a final adder such as the FP32 adder 1750. Thus, the 'c' value for the first stage of the systolic array circuit 1700 (e.g., 'depth 0') is zero. Post-accumulation can prevent loss of numerical precision of the accumulated output and provide improved performance with workload-level precision. As mentioned above, in some embodiments, the accumulation of the accumulator input argument ('c') can be performed at the first stage of the systolic chain or at any intermediate stage of the systolic chain.

[0188]

[0241] The final output after post-accumulation (e.g., dest(FP32)1752) is rounded to destination precision by adder 1750 using round to nearest even (RNE). Implementations of the systolic array circuit 1700 can support multiple output formats, including FP32, FP16, and BF16, to name a few. In some embodiments, the subnormal value at the final output of adder 1750 is flushed to zero if the output is FP32 or BF16. In some embodiments, the subnormal value is supported at the FP16 output.

[0189]

[0242] Figure 17B is a block diagram showing a systolic array circuit 1755 for performing a systolic dot product accumulation with respect to an 8-bit floating-point formatted input operand according to an embodiment. In one embodiment, the systolic dot product accumulation with respect to an 8-bit floating-point formatted input operand shown in Figure 17B is an exemplary dp2a operation, which is a two-element vector dot product operation. In one implementation, the systolic array circuit 1755 is identical to the systolic array circuit 1640 described with respect to Figure 16. The systolic array circuit 1755 may include a combination of programmable and fixed-function hardware that can be configured to perform dot product operations. Other modifications and combinations of the circuit and elements of the systolic array circuit 1755 may be implemented, and are not limited to those shown herein. Figure 17B provides an example architecture of the systolic array circuit 1755, and other architectures may be implemented to perform a systolic dot product accumulation with respect to an 8-bit floating-point formatted input operand operation, as discussed herein.

[0190]

[0243] Each FMA unit within the systolic array circuit 1755 performs a vector-dot product (e.g., a two-element vector-dot product (dp2a)) on four pairs of BF8 input values ​​from the src1 and src2 registers. In one embodiment, each FMA unit includes a combination of re-bias and normalization circuits 1760a-1760h, multipliers 1770a-1770d, and adders 1780a-b and 1785a-b. The third input register src0 contains a partially accumulated sum from the preceding dot product iterations. Multiple such FMA units linked together in the systolic array can perform DPAS processing, as will be further described below. The implementation of the systolic array can chain these individual FMA units in any possible order for efficient design, and the order of accumulation is not critical.

[0191]

[0244] In this embodiment, the systolic array circuit 1755 should support a subnormal value with respect to the BF8 input (e.g., DAZ=0). This can be achieved by expanding the input exponent and normalizing the subnormal input value on the grid. The rebiasing and normalization circuits 1760a-1760h can convert both the incoming operands (src1(BF8) and src2(BF8)) into a common binary format (e.g., FP32) capable of accommodating both the 8-bit FP format and its subnormal value (e.g., DAZ=0).

[0192]

[0245] Multiplication can be performed, for example, using FP32 multipliers 1770a-1770d without loss of precision. The outputs of multipliers 1710a-1710d can be added together in an addition tree (e.g., an N-way addition tree based on a selected block size), such as an addition tree provided by FP32 adders 1780a, 1780b and FP32 adders 1785a, 1785b, and rounded using rounding to nearest nearest (RNE) to generate an FP32 output. In the embodiment, any subnormal values ​​in each subsequent FP32 intermediate result (e.g., in adders 1780a-b, 1785a-b) are flushed to zero.

[0193]

[0246] As mentioned above, the systolic array circuit 1755 can perform post-accumulation. For post-accumulation, src0 is accumulated at the end of the systolic chain in a final addition tree, such as that provided by the FP32 adders 1790 and 1795. Thus, the 'c' value for the first stage of the systolic array circuit 1755 (e.g., 'depth 0') is zero. Post-accumulation can prevent loss of numerical precision of the accumulated output and provide improved performance with workload-level precision. As mentioned above, in some embodiments, the accumulation of the accumulator input argument ('c') can be performed at the first stage of the systolic chain or at any intermediate stage of the systolic chain.

[0194]

[0247] The final output after post-accumulation (e.g., dest(FP32)1792) is rounded to destination precision by adder 1795 using round to the nearest even number (RNE). Implementations of the systolic array circuit 1755 can support multiple output formats, including FP32, FP16, and BF16, to name a few. In some embodiments, the subnormal value at the final output of adder 1795 is flushed to zero if the output is FP32 or BF16. In some embodiments, the subnormal value is supported at the FP16 output.

[0195]

[0248] The following is an example of pseudocode for implementing systolic dot product storage for an 8-bit floating-point format input operand (e.g., a BF8 operand) according to an embodiment.

[0196]

number

[0249] Figure 18A shows a dot product by a cumulative instruction 1800 that can be executed by a systolic array circuit according to the embodiment described herein. Figure 18A shows the fields of a dot product by a cumulative instruction that can be executed by a systolic matrix logic provided by the embodiment, acting on an 8-bit floating-point format input operand. Figure 18A shows the fields of a dot product by a cumulative instruction 1800, which, when executed, causes a systolic matrix accelerator to perform a dot product with a cumulative with respect to an 8-bit floating-point format input operand (e.g., a BF8 operand). In one embodiment, the instruction 1800 includes an opcode field 1802, a systolic depth 1804 (sdepth), an iteration count 1806 (rcount), and operand fields specifying a destination 1808, a 0th source 1810 (src0), a 1st source 1812 (srcl), and a 2nd source 1814 (src2).

[0197]

[0250] The opcode field 1802 can specify an opcode that identifies the instruction 1800 for execution logic. In one embodiment, the opcode field 1802 includes one or more bits indicating that the instruction should be executed by a matrix accelerator (e.g., matrix accelerator 1423) if enabled. In one embodiment, the opcode field 1802 may also include one or more bits indicating that the instruction 1800 should be executed by application-specific dot product logic, such as dot product logic within the matrix accelerator 1423 (e.g., systolic array circuit 1640).

[0198]

[0251] The systolic depth 1804 (sdepth) can be used to specify the number of systolic layers to use for processing the input data. In one embodiment, the systolic depth 1804 can be provided as the most recent value. The iteration count 1806 (rcount) can be used to specify the number of dpas instructions generated with dst and src0 which advance consecutive registers, src1 which remains the same, and src2 which advances by N elements (where N is the destination format).

[0199]

[0252] Destination 1808, zero source 1810 (src0), first source 1812 (srcl), and second source 1814 (srcl) can be used to specify the destination to which the calculation will be written and the location from which the source data can be retrieved. In one embodiment, destination 1808 can specify the register to which the data should be written. In one embodiment, destination 1808 can be a scalar register, but in some embodiments, the destination can be a vector register that stores outputs from multiple channels. Zero source 1810, first source 1812, and second source 1814 can be registers containing one or more channels of source data or the nearest value, each channel having four elements to be processed by a systolic array circuit.

[0200]

[0253] In some embodiments, additional fields other than those described may exist. For example, in one embodiment, there is a source modifier field that specifies the numeric modifier of the source operand. The value of each data element of the source operand can optionally take its absolute value and / or its sign can be inverted before being sent to the execution pipeline. An absolute value modifier can be applied before a negate modifier so that it can produce guaranteed negative values. In one embodiment, a saturation field exists, which can be used to suppress destination saturation. If saturation is enabled, the output data to the destination register is saturated. The specific saturation operation depends on the destination data type. Saturation is an operation that converts any data outside the saturation target range of that data type to the closest representation within the target range.

[0201]

[0254] Figure 18B shows a program code compilation process 1815 according to one embodiment. In one embodiment, a source code-level description 1820 of a software program is compiled to a level having an operation 1840 that includes or specifies an 8-bit dot product, which is executed by processing logic, in a compiler 1830 that may include multiple levels of compilation. The operation 1840 may be an operation specified in an intermediate language, or it may be program code that references primitives of an operation framework, such as primitives provided by a machine learning framework. The operation 1840 that includes or specifies an 8-bit dot product may then be further compiled to machine-level object code 1860 by an additional compiler 1850, which may be a shader compiler, which object code includes an 8-bit dot product instruction executed by an accelerator for matrix operations such as those described herein.

[0202]

[0255] Figure 19 is a flowchart illustrating an embodiment of Method 1900 that executes instructions for systolic dot product storage with respect to 8-bit floating-point formatted input operands. Method 1900 may be executed by processing logic that may include hardware (e.g., circuits, dedicated logic, programmable logic, etc.), software (e.g., instructions executed on a processing device), or a combination thereof. The processes of Method 1900 are shown in a linear sequence for the sake of brevity and clarity in this description; however, it is assumed that any number of them may be executed in parallel, asynchronously, or in different orders. Furthermore, for the sake of brevity, clarity, and ease of understanding, many of the components and processes described with respect to Figure 1-18 may not be repeated or discussed below. In one implementation, a data processing system such as the data processing system 1400 in Figure 14 may execute Method 1900.

[0203]

[0256] Method 1900 begins in processing block 1910, where a single instruction is fetched and decoded for execution within the GPGPU. In one implementation, the single instruction is decoded into a matrix instruction, which acts on an 8-bit floating-point format operand to cause the GPGPU to perform a parallel dot product operation. In processing block 1920, a set of pipeline commands is determined using one or more 8-bit floating-point format operands (e.g., BF8 operands) to execute the decoded matrix instruction on a matrix accelerator.

[0204]

[0257] Next, in processing block 1930, a set of pipeline commands is scheduled to the systolic dot product pipeline to execute the decoded matrix instruction using one or more 8-bit floating-point format operands. Finally, in processing block 1940, the decoded matrix instruction is removed in response to the completion of the set of pipeline commands.

[0205]

[0258] Figure 20 is a flowchart illustrating an embodiment of Method 2000 for systolic dot product storage with respect to an 8-bit floating-point formatted input operand. Method 2000 may be executed by processing logic that may include hardware (e.g., circuits, dedicated logic, programmable logic, etc.), software (e.g., instructions executed on a processing device), or a combination thereof. The processes of Method 2000 are shown in a linear sequence for the sake of brevity and clarity in the description; however, it is assumed that any number of them may be executed in parallel, asynchronously, or in different orders. Furthermore, for the sake of brevity, clarity, and ease of understanding, many of the components and processes described with respect to Figure 1-19 may not be repeated or discussed below. In some implementations, a systolic array such as the systolic array circuit 1640 in Figure 16 or the systolic array circuit in Figure 17 may execute Method 2000.

[0206]

[0259] Method 2000 begins in processing block 2010, where source values ​​and computation depth for an instruction are fetched for execution by the GPGPU matrix operation accelerator. In one implementation, the source values ​​are 8-bit floating-point format operands (e.g., BF8 operands). In processing block 2020, a 4-bit multiplier is used to generate a set of products based on element-wise multiplication of the source input elements.

[0207]

[0260] In processing block 2030, the multiplier outputs are normalized using a 32-bit shifter for each multiplier. Then, in processing block 2040, the sum of the normalized set of multiplier outputs is calculated and rounded to the nearest even number. Finally, in processing block 2050, in the final depth layer of the matrix operation accelerator, the sum of the normalized set of multiplier outputs and the initial accumulator value is calculated. The grand total is then rounded to destination output precision using the nearest even number rounding.

[0208] Converting floating-point data to (or from) an 8-bit floating-point format.

[0261] The embodiment described herein is for converting floating-point data to (or from) an 8-bit floating-point format.

[0209]

[0262] As discussed earlier, advances in deep learning have enabled ML models to leverage low-precision computation to train neural networks. Conventional training platforms support IEEE-754 FP16 and BFLOAT16 data formats in high-performance systolic array implementations. These implementations use high-precision accumulators to prevent loss of precision between long chains of dot product operations. Within a neural network, these high-precision outputs should be rounded down to a low-precision format during post-processing of the layer before being sent to the next layer as input. For example, conventional hardware implementations for neural networks support rounding from FP32 to FP16 and BF16.

[0210]

[0263] As mentioned above, 8-bit FP format data (such as BFLOAT8, 1s-5e-2m) can improve training and inference performance. Hardware implementations of BFLOAT8 FMA can use either an FP32 or FP16 accumulator to maintain numerical precision. However, conventional systems do not have hardware support for rounding FP32 or FP16 FMA output to BFLOAT8 during post-processing. Conventional systems may offer slower software implementations that use sequence arithmetic and bitwise instructions to perform this rounding operation. For example, this function can be emulated in software using a sequence of arithmetic, bitwise, and compare instructions. Such slow software implementations result in a performance penalty for smaller, more irregular kernels, which are often used in deep neural network training.

[0211]

[0264] The embodiments propose instructions for converting floating-point data to 8-bit floating-point format data. In one implementation, the instructions of the embodiments perform a down-conversion from IEEE-754 FP32 or FP16 to BFLOAT8 by nearest-to-even rounding. In another implementation, the instructions of the embodiments perform an up-conversion from BFLOAT8 to FP32 or FP16 to facilitate mixed-precision arithmetic processing using the BFLOAT8 memory format.

[0212]

[0265] The embodiment provides instructions and hardware solutions for converting floating-point data to 8-bit floating-point format data. The instructions and hardware technology of the embodiment replaces long instruction sequences with single instructions that can be used by the programmer. This can result in improved performance for irregular kernel operations in neural networks. The embodiment also enables training in mixed-precision 8-bit floating-point formats (e.g., BFLOAT8), which can accelerate the training throughput of neural networks.

[0213]

[0266] Figure 21 is a block diagram showing an 8-bit FP format conversion process 2110 performed by an instruction pipeline 2100 according to an embodiment. The instruction pipeline 2100 can be configured to perform the 8-bit FP format conversion process 2110. The instruction pipeline 2100 can be used to accelerate hardware instructions and may include an instruction fetch and decode unit 1421 capable of fetching and decoding hardware instructions, and a controller unit 2120 (such as a scheduler controller 1422), the controller unit can schedule the decoded instructions to one or more execution units and / or matrix accelerators 1423 in arithmetic blocks 1424A-1424N (collectively referred to as arithmetic block 1424). The instruction pipeline 2100 may also include a selection circuit 2130, such as a collection of multiplexers (muxes), to route the input data to the arithmetic block 1424 and / or the matrix accelerator 1423, according to the 8-bit FP format encoded in the hardware instructions of the 8-bit FP format conversion process 2110.

[0214]

[0267] In one embodiment, hardware instructions are scheduled to the arithmetic block 1424 and / or can be offloaded to the matrix accelerator 1423 (for example, for calculations using the systolic array circuit 2140). One or more hardware instructions and associated data for executing the 8-bit FP format conversion process 2110 can be stored in memory 2150. The output of the hardware instructions can also be stored in memory 2150. Memory 2150 can be any memory described herein, including system memory 1412, GPGPU memory 1418, or one or more cache memories 1427, 1430, as shown in Figure 14.

[0215]

[0268] In one embodiment, the arithmetic block 1424 can execute one or more hardware instructions to perform an 8-bit FP format conversion process 2110 using the processing unit 2160. The processing unit 2160 may include a combination of programmable and fixed-function hardware that can be configured to perform the 8-bit FP format conversion process. In some implementations, the processing unit 2160 may be a vector processing unit (VPU). In some implementations, the processing unit 2160 may be a floating-point unit (FPU). The processing unit 2160 may include a conversion circuit 2162, a nearest nearest rounding (RNE) arithmetic circuit 2164, and a special processing circuit 2166.

[0216]

[0269] In the embodiment, a hardware instruction for performing an 8-bit FP format conversion process 2110 provides data conversion between IEEE-754 FP32 or FP16 data and the BFLOAT8 format. The data conversion can include down-conversion from FP32 / FP16 to an 8-bit FP format (e.g., BF8) or up-conversion from an 8-bit FP format (e.g., BF8) to FP32 / FP16. Figure 15 above shows an exemplary BF8 binary format that can be used as the 8-bit FP format in the embodiment. The BFLOAT8 binary format is represented as sign, exponent, and mantissa bits. The 5-bit exponent uses 15 offset values ​​capable of representing normal floating-point values ​​between 6.1e-05 and 5.7344e+04. The format also supports subnormal values ​​that extend the dynamic range down to a minimum representable value of 1.5e-05.

[0217]

[0270] When converting down from FP32 or FP16 to BF8, values ​​are rounded using the round-to-nearest-even (RTNE) process. Subnormals are supported in both conversions from FP32 and FP16. When upconverting from BF8 to either FP16 or FP32, the exponential values ​​of the 8-bit FP format (BF8) are appropriately scaled, and the mantissa is zero-extended.

[0218]

[0271] In the embodiment, the conversion circuit 2162 may include programmable and fixed-function hardware to perform the conversion process described above. The RNE rounding circuit 2164 may include programmable and fixed-function hardware to perform RNE rounding of the converted data. The special processing circuit 2166 may include programmable and fixed-function hardware to address corner cases encountered when converting and / or rounding the data, such as underflow, overflow, and non-normalization.

[0219]

[0272] In some implementations, the instructions for converting 8-bit FP format data described herein can take the following forms:

[0273] mov dst, src0

[0274] When the conversion circuit 2162 down-converts from FP32 / FP16 to BF8, the instructions should retain subnormal values ​​with respect to the output. In some embodiments, the special processing circuit 2166 may exhibit saturation behavior that leads to overflow (i.e., large values ​​do not saturate to BF8_MAX). The RNE rounding circuit 2164 should round the mantissa using the nearest even rounding process. Several exemplary implementations of instructions for converting 8-bit FP format data when performing down-conversion from FP32, FP16 to BF8 are detailed below:

[0275] mov <bf8> , <fp32>

[0276] rice <bf8> , <fp16>

[0277] When the conversion circuit 2162 upconverts from FP32 / FP16 to BF8, the exponential value is rescaled and the value is renormalized. The mantissa bit is extended with respect to the LSB bit by zero. Several exemplary implementations of the instructions for converting 8-bit FP format data when performing an upconversion from BF8 to FP32 or FP16 are detailed below:

[0278] mov <fp32> , <bf8>

[0279] rice <fp16> , <bf8>

[0280] FIG. 22A shows an instruction 2200 that can be executed by a processing unit according to an embodiment described herein. FIG. 22A shows the fields of a mov instruction that converts an 8-bit floating-point format input operand, which is executable by a processing unit such as a VPU or FPU provided by one embodiment. FIG. 22A shows the fields of the mov instruction 2200, which, when executed, causes the processing unit to convert the mov instruction to or from an 8-bit floating-point format input operand (e.g., a BF8 operand). The mov instruction copies a data item (i.e., the content of a register, the content of memory, or a constant value) referred to by its second operand to a location (i.e., a register or memory) referred to by its first operand.

[0220]

[0281] In one embodiment, the instruction 2200 includes an opcode field 2202 and an operand field for specifying a destination 2204 and a source 2206 (src).

[0221]

[0282] The opcode field 2202 can specify an opcode that identifies the instruction 2200 to the execution logic. In one embodiment, the opcode field 2202 includes one or more bits, which, when enabled, indicate that the instruction is to be executed by a processing unit of an arithmetic block (e.g., arithmetic block 1424).

[0222]

[0283] Destination 2204 and source 2206 (src) can be used to specify the destination to which the calculation will be written and the location from which the source data can be retrieved. In one embodiment, destination 2204 can specify a register to which the data will be written. In one embodiment, destination 2204 can be a scalar register, but in some embodiments, the destination can be a vector register that stores outputs from multiple channels. Source (src) 2206 can be a register or immediate value containing one or more channels of source data.

[0223]

[0284] In some embodiments, additional fields other than those illustrated may exist. For example, in one embodiment, there is a source modifier field that specifies a numerical modification of the source operand. The value of each data element of the source operand can optionally take its absolute value and / or its sign can be inverted before being sent to the execution pipeline. The absolute value modifier can be applied before the negate modifier so that guaranteed negative values ​​can be produced. In one embodiment, there is a saturation field, which can be used to suppress destination saturation. If saturation is enabled, the output data to the destination register is saturated. The specific saturation operation depends on the destination data type. Saturation is an operation that converts any data outside the saturation target range of the data type to the closest representation within the target range.

[0224]

[0285] Figure 22B shows a program code compilation process 2215 according to one embodiment. In one embodiment, a source code-level description 2220 of a software program is compiled to a level having an arithmetic operation 2240 that includes or specifies an 8-bit FP format conversion instruction to be executed by processing logic, in a compiler 2230 which may include multiple levels of compilation. The arithmetic operation 2240 may be an arithmetic operation specified in an intermediate language, or it may be program code that references a primitive of an arithmetic framework, such as a primitive provided by a machine learning framework. The arithmetic operation 2240 that includes or specifies an 8-bit FP format conversion instruction may then be further compiled by an additional compiler 2250 (which may be a shader compiler) into machine-level object code 2260, which includes an 8-bit FP format conversion instruction to be executed by a processing unit (e.g., VPU, FPU) of a computer block, as described herein.

[0225]

[0286] The following is an example of pseudocode for converting floating-point data to or from an 8-bit floating-point format data (e.g., BF8 operands) according to an embodiment.

[0226]

number

[0287] Figure 23 is a flowchart illustrating an embodiment of Method 2300, which executes an instruction to convert floating-point data to 8-bit floating-point format data. Method 2300 may be executed by processing logic that may include hardware (e.g., circuits, dedicated logic, programmable logic, etc.), software (e.g., instructions executed on a processing device), or a combination thereof. The process of Method 2300 is shown in a linear sequence for the sake of brevity and clarity in the description; however, it is assumed that any number of them may be executed in parallel, asynchronously, or in different orders. Furthermore, for the sake of brevity, clarity, and ease of understanding, many of the components and processes described with respect to Figure 1-22 may not be repeated or discussed below. In one implementation, a data processing system such as the data processing system 1400 in Figure 14 may execute Method 2300.

[0227]

[0288] Method 2300 begins in processing block 2310, where a single instruction is fetched and decoded for execution within the GPGPU. In one implementation, the single instruction is decoded into a decoded instruction, causing the GPGPU to perform a conversion of the operands to and from an 8-bit floating-point format. In processing block 2320, a set of commands is determined to execute the decoded vector instruction on the GPGPU's arithmetic block.

[0228]

[0289] In processing block 2330, a set of commands is scheduled to the GPGPU's arithmetic blocks to execute the decoded instructions and perform the conversion of the operands to and from an 8-bit floating-point format. Then, in processing block 2340, the decoded instructions are removed upon completion of the set of commands.

[0229]

[0290] Figure 24 is a flowchart illustrating an embodiment of Method 2400 for converting floating-point data to 8-bit floating-point format data. Method 2400 may be performed by processing logic that may include hardware (e.g., circuits, dedicated logic, programmable logic, etc.), software (e.g., instructions executed on a processing device), or a combination thereof. The processes of Method 2400 are shown in a linear sequence for the sake of brevity and clarity in the description; however, it is assumed that any number of them may be executed in parallel, asynchronously, or in different orders. Furthermore, for the sake of brevity, clarity, and ease of understanding, many of the components and processes described with respect to Figure 1-23 may not be repeated or discussed below. In one implementation, a processing unit such as the processing unit 2160 in Figure 21 is capable of performing Method 2400.

[0230]

[0291] Method 2400 begins with processing block 2410, where the source value of the instruction is fetched for execution by the GPGPU's arithmetic block. In some implementations, the source value is converted to a different data format, which is either at least one 8-bit floating-point operand or one that can be converted to an 8-bit floating-point operand. In determination block 2420, it is determined whether the source value is equal to 0, infinity, or not-a-number (NaN). If so, method 2400 proceeds to processing block 2425, where the source value is returned to the destination as a special use-case value (e.g., 0, infinity, etc.).

[0231]

[0292] In decision block 2420, if the source value is not equal to 0, infinity, or NaN, method 2400 proceeds to processing block 2430, where the source value is converted to the destination signed-size format by scaling, normalizing, and transforming the source value. Then, in processing block 2440, the nearest even rounding process is applied to the transformed source value.

[0232]

[0293] In the determination block 2450, it is determined whether an overflow, underflow, or abnormal condition has occurred. If so, method 2400 proceeds to processing block 2460, where the converted and rounded source value is returned as a special use-case value (e.g., 0, infinity, etc.). On the other hand, if no overflow, underflow, or abnormal condition has occurred, method 2400 proceeds to processing block 2470, where the converted and rounded source value is returned as the destination value.

[0233] Efficient stochastic rounding of floating-point format data values.

[0294] The embodiment in this case provides efficient probabilistic rounding for floating-point format data values.

[0234]

[0295] As deep learning training is moving towards 8-bit floating-point formats (e.g., BF8, 1s-5e-2m), numerical errors introduced due to loss of precision can significantly impact ML model convergence. One way to compensate for this loss of precision is to use 'rounding' when converting the cumulative FMA output of FP32 or FP16 to BF8 before passing it as input to the next layer of the neural network.

[0235]

[0296] However, rounding errors accumulated over long chains of dot product operations also raise concerns about the numerical stability of iterative solutions used in training deep neural networks. This problem worsens at lower precision in BF8 compared to FP16 (=4.88e-04) and BF16 (=3.90e-03) because the machine's 'ε' (=0.125) is larger.

[0236]

[0297] When using the BF8 data format across multiple workloads, stochastic rounding can reduce the accumulation of rounding errors and help achieve convergence. Stochastic rounding is a non-deterministic rounding process that rounds a real number to the next larger or smaller floating-point number with probability (1 minus the relative distance to that number). Full hardware support for stochastic rounding would involve a floating-point pseudorandom number generator, which would be costly to build and verify.

[0237]

[0298] However, in the context of deep neural network training, deep learning training has fewer constraints on random number generators, and random numbers can often be reused without affecting the numerical stability of the solver. Based on the reduced random number generator constraints, embodiments provide hardware and instruction combinations to accelerate probabilistic rounding using low-precision random bits generated and managed in software (e.g., 8 bits for FP16→BF8, 16 bits for FP32→FP16).

[0238]

[0299] The embodiments present invention provide one or more instructions for applying probabilistic rounding when the higher-precision output of an arithmetic operation is converted to a lower-precision format (e.g., BF8 (1s-5e-2m), HF8 (1s4e3m), FP16, and BF16 floating-point format). These instructions may include one or two higher-precision source operands and a third input operand, each containing a random integer generated by a software-based pseudo-random number generator (PRNG). In some implementations, the PRNG software may use an inexpensive PSNR algorithm such as xoroshiro128++ or an equivalent. The output is stored in the destination data format specified by the instruction.

[0239]

[0300] The instructions and hardware in this embodiment provide a technical advantage of replacing a wide range of instruction sequences with a single instruction that can be used by a programmer for improved speed and efficiency of neural network training. The embodiments also enable a programmer to use an algorithm for generating and managing (caching and reusing) random numbers while decoupling the PRNG from the rounding operation to reduce hardware complexity. Further, the embodiments accelerate the backpropagation of BFLOAT8 mixed-precision training to improve the speed and efficiency of neural network training.

[0240]

[0301] FIG. 25 is a block diagram showing 8-bit FP format conversion using a probabilistic rounding operation 2510 executed by an instruction pipeline 2500 according to an embodiment. The instruction pipeline 2500 can be configured to perform 8-bit FP format conversion using the probabilistic rounding operation 2510. The instruction pipeline 2500 can be used to accelerate hardware instructions and can include an instruction fetch & decode unit 1421 capable of fetching and decoding hardware instructions, and a controller unit 2520 (such as a scheduler controller 1422), where the controller unit can schedule the decoded instructions to one or more execution units and / or a matrix accelerator 1423 within arithmetic blocks 1424A-1424N (collectively referred to as arithmetic blocks 1424). The instruction pipeline 2500 can also include a selection circuit 2530, such as a collection of multiplexers (muxes), for routing input data to the arithmetic blocks 1424 and / or the matrix accelerator 1423 according to the 8-bit FP format encoded in the hardware instructions for 8-bit FP format conversion using the probabilistic rounding operation 2510.

[0241]

[0302] In one embodiment, hardware instructions are scheduled to the arithmetic block 1424 and / or can be offloaded to the matrix accelerator 1423 (for example, for operations using the systolic array circuit 2540). One or more hardware instructions and associated data for performing the 8-bit FP format conversion process 2110 using the probabilistic rounding operation 2510 can be stored in memory 2550. The output of the hardware instructions can also be stored in memory 2550. Memory 2550 can be any memory described herein, including system memory 1412, GPGPU memory 1418, or one or more cache memories 1427, 1430, as shown in Figure 14.

[0242]

[0303] In one embodiment, the arithmetic block 1424 can execute one or more hardware instructions using the processing unit 2560 to perform an 8-bit FP format conversion using a probabilistic rounding operation 2510. The processing unit 2560 may include a combination of programmable and fixed-function hardware that can be configured to perform an 8-bit FP format conversion using a probabilistic rounding operation. In some implementations, the processing unit 2560 may be a vector processing unit (VPU). In some implementations, the processing unit 2560 may be a floating-point unit (FPU). The processing unit 2560 may include a conversion circuit 2562, a probabilistic rounding circuit 2564, and a special processing circuit 2166.

[0243]

[0304] In this embodiment, an instruction that performs an 8-bit FP format conversion using probabilistic rounding can perform probabilistic rounding during the conversion from higher-precision floating-point to lower-precision floating-point. The instruction can take the following form:

[0305] srnd dest, src0, src1

[0306] In this instruction, src0 is the source operand containing a high-precision floating-point input, and src1 contains a random integer used by the rounding hardware. The random integer is generated in software using a PRNG algorithm such as xoroshiro128++. The output of the rounding operation is returned to dst in low-precision floating-point format as specified by the instruction opcode.

[0244]

[0307] During the conversion performed by the conversion circuit 2562, a normalized sign-size representation of src0 is generated. The conversion circuit 2562 may include programmable and fixed-function hardware to perform the conversion process. The stochastic rounding circuit 2564 then generates an intermediate result by adding a random integer from src1 to the normalized sign-size representation of src0 using a fixed-point adder 2565. The random integer is a PRNG 2570 generated by software using the PRNG algorithm. The stochastic rounding circuit 2564 then truncates the intermediate result to the size of the destination mantissa format after some exponential adjustment. The stochastic rounding circuit 2564 may include programmable and fixed-function hardware to perform the stochastic rounding process. Special processing circuits 2566 may include programmable and fixed-function hardware to address corner cases encountered when converting and / or rounding data, such as underflow, overflow, and denormalization.

[0245]

[0308] In some embodiments, the number of random bits used for rounding operations may depend on the input and output data formats defined by the instruction opcode. Table 1 below provides a list of exemplary supported input and output formats and the number of random bits used to perform rounding operations.

[0246]

number

[0309] In some embodiments, the width of the random number may vary depending on the source and destination data formats. Assuming the source data format has an N-bit mantissa and the destination data format has a K-bit mantissa, an (NK)-bit random number can be used to perform rounding in the stochastic rounding circuit 2564.

[0247]

[0310] Figure 26 is a block diagram illustrating a fixed-point addition 2600 of the sign-size representation of a mantissa and a random number according to an embodiment. A source mantissa 2601 (leading by 1) and a random number 2605 are shown to be added to produce an addition result 2610. The source mantissa contains an N-bit mantissa 2602, where K bits 2604 of the mantissa represent the number of mantissa bits used in the destination format. Before addition, the bits of the random number 2605 are aligned to the (NK) least significant bits of the source mantissa 2601. The addition result 2610 shows the addition result, which is the sum of the two leading bits (X) and the remaining mantissa bits (x).

[0248]

[0311] Figure 27A shows an instruction 2700 that can be executed by a processing unit according to the embodiments described herein. Figure 27A shows the fields of an instruction that converts a floating-point format input operand using probabilistic rounding. The instruction is executable by a processing unit such as a VPU or FPU provided by one embodiment. Figure 27A shows the fields of instruction 2700, which, when executed, causes a processing unit to execute an instruction that converts a floating-point format input operand using probabilistic rounding. In one embodiment, instruction 2700 includes an opcode field 2702 and operand fields for specifying a destination 2704, a 0th source (src0) 2706, and a 1st source (src1) 2708.

[0249]

[0312] The opcode field 2702 can specify an opcode to identify instruction 2700 to the execution logic. In one embodiment, the opcode field 2702 includes one or more bits that, when enabled, indicate that the instruction should be executed by the processing unit of an arithmetic block (e.g., arithmetic block 1424).

[0250]

[0313] Destination 2704, zero source 2706 (src0), and first source 2708 (src1) can be used to specify the destination to which the calculation is written and the location from which the source data can be retrieved. In one embodiment, destination 2704 can specify a register to which the data is written. In one embodiment, destination 2704 can be a scalar register, but in some embodiments, the destination can be a vector register that stores outputs from multiple channels. Zero source (src0) 2706 and first source (src1) 2708 can be registers or immediate values ​​containing one or more channels of source data.

[0251]

[0314] In some embodiments, additional fields other than those illustrated may exist. For example, in one embodiment, there is a source modifier field that specifies a numerical modification of the source operand. The value of each data element of the source operand can optionally take its absolute value and / or its sign can be inverted before being sent to the execution pipeline. The absolute value modifier can be applied before the negate modifier so that guaranteed negative values ​​can be produced. In one embodiment, there is a saturation field, which can be used to suppress destination saturation. If saturation is enabled, the output data to the destination register is saturated. The specific saturation operation depends on the destination data type. Saturation is an operation that converts any data outside the saturation target range of the data type to the closest representation within the target range.

[0252]

[0315] Figure 27B shows a program code compilation process 2715 according to one embodiment. In one embodiment, a source code-level description 2720 of a software program is compiled to a level having an operation 2740 that includes or specifies an FP format conversion instruction using probabilistic rounding, which is performed by processing logic, in a compiler 2730 that may include multiple levels of compilation. The operation 2740 may be an operation specified in an intermediate language, or it may be program code that references a primitive of an operation framework, such as a primitive provided by a machine learning framework. The operation 2740 that includes or specifies an FP format conversion using probabilistic rounding instructions may then be further compiled to machine-level object code 2760 by an additional compiler 2750, which may be a shader compiler, which object code includes an FP format conversion with probabilistic rounding instructions, which is performed by a processing unit (e.g., VPU, FPU) of a computer block, as described herein.

[0253]

[0316] The following is a first pseudocode example for achieving efficient probabilistic rounding of floating-point format data values ​​according to an embodiment.

[0254]

number

[0317] The following is a second simplified pseudocode example for achieving efficient stochastic rounding of floating-point data values ​​according to the embodiment.

[0255]

number

[0318] Figure 28 is a flowchart illustrating an embodiment of Method 2800 for executing instructions that perform efficient stochastic rounding on floating-point values. Method 2800 may be executed by processing logic that may include hardware (e.g., circuits, dedicated logic, programmable logic, etc.), software (e.g., instructions executed on a processing device), or a combination thereof. The processes of Method 2800 are shown in a linear sequence for the sake of brevity and clarity in the description; however, it is assumed that any number of them may be executed in parallel, asynchronously, or in different orders. Furthermore, for the sake of brevity, clarity, and ease of understanding, many of the components and processes described with respect to Figure 1-27 may not be repeated or discussed below. In one implementation, a data processing system such as the data processing system 1400 in Figure 14 may execute Method 2300.

[0256]

[0319] Method 2800 begins in processing block 2810, where a single instruction is fetched and decoded for execution within the GPGPU. In one implementation, the single instruction is decoded into a decoded instruction, causing the GPGPU to perform an 8-bit floating-point format conversion using probabilistic rounding. Then, in processing block 2820, a set of commands is determined to execute the decoded vector instruction on the GPGPU's arithmetic block.

[0257]

[0320] In processing block 2830, a set of commands is scheduled to the GPGPU's arithmetic blocks to execute the decoded instructions and perform a conversion to an 8-bit floating-point format using probabilistic rounding. Finally, in processing block 2840, the decoded instructions are removed upon completion of the set of commands.

[0258]

[0321] Figure 29 is a flowchart illustrating an embodiment of Method 2900 for performing efficient stochastic rounding on floating-point values. Method 2900 may be performed by processing logic that may include hardware (e.g., circuits, dedicated logic, programmable logic, etc.), software (e.g., instructions executed on a processing device), or a combination thereof. The processes of Method 2900 are shown in a linear sequence for the sake of brevity and clarity in this explanation; however, it is assumed that any number of them may be executed in parallel, asynchronously, or in different orders. Furthermore, for the sake of brevity, clarity, and ease of understanding, many of the components and processes described with respect to Figure 1-28 may not be repeated or discussed below. In one implementation, a processing unit such as processing unit 2560 in Figure 25 is capable of performing Method 2900.

[0259]

[0322] Method 2900 begins with processing block 2910, where the source value is fetched for instructions to be executed by the GPGPU's arithmetic blocks. In some implementations, the source value is converted from higher-precision floating-point to lower-precision floating-point. In decision block 2920, it is determined whether the source value is equal to 0, infinity, or NaN. If so, method 2900 proceeds to processing block 2925, where the source value is returned to the destination as a special use-case value. If, in decision block 2920, the source value is not equal to 0, infinity, or NaN, method 2900 proceeds to processing block 2930, where the source value is converted to the destination's sign-size format, and the converted source value is normalized.

[0260]

[0323] Next, in processing block 2940, random numbers are added to the transformed and normalized source values. In some implementations, the random numbers have a size determined based on the source and destination operands and the data format of the destination operand. In some implementations, the random numbers are obtained from PRNG software. In processing block 2950, ​​the sum of the results is exponentially adjusted, and the sum of the results is truncated to the size of the destination operand mantissa format to generate the resulting destination value.

[0261]

[0324] In decision block 2960, it is determined whether an overflow, underflow, or abnormal condition has occurred. If so, method 2900 proceeds to processing block 2970, where a special use case value is returned as the result destination value. On the other hand, if no overflow, underflow, or abnormal condition has occurred, method 2900 proceeds to processing block 2980, where the result destination value is returned.

[0262] Hybrid floating-point systolic arithmetic

[0325] The embodiment in this case provides hybrid floating-point systolic arithmetic.

[0263]

[0326] Advances in deep learning algorithms have enabled models to utilize low-precision computations in training neural networks. The noise resilience of deep neural networks has also allowed for experimentation with custom data formats that can be used for various deep learning tasks. One such custom data format, widely accepted within the deep learning community and applied by hardware manufacturers, is BFLOAT16.

[0264]

[0327] As smaller bit widths (8 bits or less) are used in deep learning, further customization of data formats may be implemented for efficient bit allocation. For example, it is known that during backpropagation, error gradients, which tend to have a wider distribution, can benefit from data formats with a higher dynamic range (i.e., larger exponents), while the forward (or inference) path can benefit from higher numerical precision (i.e., larger mantissa) to reduce numerical errors. This behavior is more evident in smaller models (fewer model parameters) optimized for edge devices. In smaller bit width data formats, this results in a trade-off between dynamic range and numerical precision.

[0265]

[0328] In addition to the bit allocation trade between the exponent and mantissa, floating-point formats can also customize the numerical distribution by selecting the appropriate exponential bias or zero point for the numerical distribution. Given a typical (near-zero) Gaussian data distribution for most tensors used in deep learning applications, an exponential bias is typically chosen to maximize the number of smaller values ​​that the format can represent. This can partially compensate for having a smaller dynamic range by prioritizing important parts of the numerical distribution.

[0266]

[0329] Two 8-bit floating-point representations have been introduced that can be used to train deep neural networks. One of these formats, BFLOAT8, uses the 's1.e5.m2' binary representation, which has a symmetric distribution of numbers. The other format, HFLOAT8, is represented in the 's1.e4.m3' format, which has a numerical distribution biased towards smaller numbers and an asymmetric exponential bias. Using a combination of BFLOAT8 and HFLOAT8 formats together to address different parts of the training pipeline can result in improved model accuracy. Mixing multiple data formats into a single training flow can result in hybrid floating-point arithmetic between input matrices represented in different binary formats. As the industry moves towards 8-bit and less than 8-bit data formats, this type of hybrid arithmetic will become more common. However, traditional systems with floating-point hardware do not support arithmetic operations between operands that use different binary encodings or non-traditional exponential biases.

[0267]

[0330] The embodiment addresses this technical problem by providing an extension to DPAS hardware to support custom binary coding for input operands and enable hybrid floating-point arithmetic. Binary format information of input operands, such as exponential size and / or exponential bias, can be embedded in the hardware or optionally represented as part of the instruction coding. The hardware extension of the embodiment can use this information to re-bias the input arguments and convert them to a common internal format before performing the requested arithmetic operation.

[0268]

[0331] Figure 30 is a block diagram showing two 8-bit floating-point formats using different binary encodings and exponential biases according to an embodiment. The BFLOAT8 (or Brain-Float8) format 3000 on the left shows a BFLOAT8 binary format using the s1.e5.m2 format. The s1.e5.m2 format includes one sign bit 3002, five exponential bits 3004, and two mantissa bits 3006. The HFLOAT8 (or Hybrid-Float8) format 3010 on the right shows an HFLOAT8 binary format using the s1.e4.m3 format. The s1.e4.m3 format includes one sign bit 3012, four exponential bits 3014, and three mantissa bits 3016. Furthermore, the HFLOAT8 format 3010 uses a larger exponential bias to shift the numerical distribution towards smaller numbers. The differences between these two formats are summarized in Table 2 below.

[0269]

number

[0332] The hybrid floating hardware of the embodiment present invention offers a technical advantage that overcomes the aforementioned drawbacks by allowing the application to select from a list of available floating-point formats best suited to various parts of the training pipeline in order to maximize accuracy. Furthermore, the embodiment can support multiple data formats with increasing hardware modifications. This improves processor performance and neural network training throughput.

[0270]

[0333] Figure 31 is a block diagram showing a hybrid 8-bit FP format systolic operation performed by the instruction pipeline 3100 according to an embodiment. The instruction pipeline 3100 can, but is not limited to, perform a hybrid 8-bit FP format systolic operation 3110 such as a dot product operation. The dot product of two vectors is a scalar value equal to the sum of the products of the corresponding components of the vectors. The dot product can be calculated as shown in the following equation (1).

[0271]

number

[0334] The dot product may be used in convolutional operations of neural networks such as convolutional neural networks (CNNs). The instruction pipeline 3100 used to accelerate hardware instructions may include an instruction fetch and decode unit 1421 that can fetch and decode hardware instructions, and a controller unit 3120 (such as a scheduler controller 1422) that can schedule the decoded instructions to one or more execution units and / or matrix accelerators 1423 of the arithmetic blocks 1424A-1424N (collectively referred to as arithmetic block 1424). The instruction pipeline 3100 may also include a selection circuit 1630, such as a collection of multiplexers (muxes), to route the input data to the arithmetic blocks 1424 and / or matrix accelerators 1423 according to a hybrid 8-bit FP format encoded with hardware instructions of the hybrid 8-bit FP format systolic arithmetic 3110.

[0272]

[0335] In one embodiment, hardware instructions can be scheduled for arithmetic block 1424 and offloaded to matrix accelerator 1423. One or more hardware instructions and associated data for executing the hybrid 8-bit FP format systolic arithmetic 3110 can be stored in memory 3150. The output of hardware instructions can also be stored in memory 3150. Memory 1650 can be any memory described herein, including system memory 1412, GPGPU memory 1418, or one or more cache memories 1427, 1430, as shown in Figure 14.

[0273]

[0336] In one embodiment, the matrix accelerator 1423 can execute one or more hardware instructions to perform a hybrid 8-bit FP format systolic operation 3110 using a systolic array circuit 3140. The systolic array circuit 3140 may include a combination of programmable and fixed-function hardware that can be configured to perform dot product operations. While the function units within the arithmetic block 1424 can also be configured to perform dot product operations, the systolic array circuit 3140 can be configured to perform a limited subset of dot product operations with considerably higher throughput than the arithmetic block 1424.

[0274]

[0337] In embodiments, the DPAS instruction is provided to perform a systolic dot product and store operation on hybrid 8-bit floating-point format data (e.g., BF8 and HF8) source operands from a register file, store the result at a selected precision (fp32, fp16, bf16), and write the final output to a register file for return. This DPAS instruction for performing the hybrid 8-bit FP format systolic operation 3110 accepts three input operands to perform the operation c += a*b, where the 'a' and 'b' operands are of hybrid 8-bit FP type, such as BF8 or HF8. Other combinations and variations of FP format types of the input operands are possible in embodiments and are not limited to the BF8 or HF8 format.

[0275]

[0338] Figure 32 is a block diagram showing a hybrid FMA unit 3200 of a systolic array circuit for performing hybrid floating-point systolic arithmetic according to an embodiment. In one embodiment, the hybrid FMA unit 3200 may be part of the systolic array circuit 3140 described with respect to Figure 31. In one embodiment, the hybrid FMA unit 3200 performs arithmetic operations on DPAS instructions having hybrid FP format operands. The hybrid FMA implementation of the hybrid FMA unit 3200 can accept custom floating-point formats and internally convert them to a more high-precision common format before performing arithmetic operations.

[0276]

[0339] In one embodiment, for example, information about a custom binary format such as the number of bits assigned to the exponent or the exponent offset to be used is provided by an integer bitmap (hereinafter "imm"),<imm.cbf> It can be passed according to the instruction as the fourth argument to the FMA instruction (as shown). Several examples of the hybrid DPAS instruction of the embodiment are shown below, using various combinations of input (e.g., BF8 and HF8) and output arguments.

[0277] hdpas_01. <sdepth> x <rcount> <f32> <f32> <hf8> <bf8><imm.cbf> hdpas_02. <sdepth> x <rcount> <f16> <f16> <bf8> <hf8><imm.cbf> hdpas_12. <sdepth> x <rcount> <f32> <f32> <hf8> <hf8><imm.cbf> dst src0 src1 src2.imm

[0340] The instruction encoding is,<hdpas_xx> It can be expressed as such, where 'xx' indicates which of the input arguments (src1, src2, or both) is allowed to use a custom input format. The implementation of the instruction encoding may vary depending on the encoding scheme used by the target architecture.

[0278]

[0341] Referring to Figure 32, the hybrid FMA calculation in the embodiment performed by the hybrid FMA unit 3200 is performed on the src1 and src2 operands, which are represented in HFLOAT8 and BFLOAT8 data formats, respectively. Both of these formats use different binary formats with different bit assignments for the exponent and mantissa, as well as different exponential biases (e.g., BFLOAT8 bias = 15, HFLOAT8 bias = 11).

[0279]

[0342] The hybrid FMA unit 3200 may include multiple re-bias and normalization units 3210a-h, multiple multipliers 3220a-d, multiple shifters 3230a-3230r, and an adder 3240. The details of the internal bit width may vary within the hybrid FMA unit 3200 depending on the input and output accuracy requirements.

[0280]

[0343] The first stage of the hybrid FMA unit 3200 includes rebiasing and normalization units 3210a-3210h. Rebiasing and normalization units 3210a-3210h can convert the incoming operands (src1 (HF8) and src2 (BF8)) into a common 's1.e8.m3' binary format, which is capable of accommodating both BFLOAT8 and HFLOAT8 formats and their subnormal values ​​(e.g., DAZ=0).

[0281]

[0344] The second stage of the hybrid FMA unit 3200 includes multipliers 3220a-3220d. Multipliers 3220a-3220d take the extended s1.e8.m3 format as input and generate an intermediate 17-bit coded size representation (s1.e8.m2.6).

[0282]

[0345] The third stage of the hybrid FMA unit 3200 includes shifters 3230a-3230e. Shifters 3230a-3230e can normalize the output of multipliers 3220a-3220d together with src0 (including the preceding cumulative sum) using, for example, a 32-bit shifter.

[0283]

[0346] The final stage of the hybrid FMA unit includes adder 3240. Adder 3240 contains an adder tree that generates a 27-bit mantissa, for example, as part of the result in s1.e8.m2.27 format. Adder 3240 rounds this result down to s1.e8.23m format using nearest even rounding.

[0284]

[0347] Figure 33A shows a hybrid dot product by a cumulative instruction 3300 that can be executed by a systolic array circuit according to the embodiment described herein. Figure 33A shows the field of a hybrid dot product by a cumulative instruction 3300 that can be executed by a systolic matrix logic provided by the embodiment acting on a hybrid 8-bit floating-point format input operand. Figure 33A shows the field of a hybrid dot product by a cumulative instruction 3300, which, when executed, causes a systolic matrix accelerator to perform a dot product with a cumulative operation with respect to a hybrid 8-bit floating-point format input operand (e.g., BF8 and HF8 operands). In one embodiment, instruction 3300 includes an opcode field 3302, a systolic depth 3304 (sdepth), an iteration count 3306 (rcount), and an operand field specifying a destination 3308, a first source 3310 (src0), a first source 3312 (srcl), a second source 3314 (src2), and an integer bitmap (imm) field 3316.

[0285]

[0348] The opcode field 3302 can specify an opcode that identifies the instruction 3300 for execution logic. In one embodiment, the opcode field 3302 includes one or more bits that, if enabled, indicate that the instruction should be executed by a matrix accelerator (e.g., matrix accelerator 1423). In one embodiment, the opcode field 3302 may also include one or more bits that indicate that the instruction 3300 should be executed by application-specific dot product logic, such as dot product logic within the matrix accelerator 1423 (e.g., systolic array circuit 3140).

[0286]

[0349] The systolic depth 3304 (sdepth) can be used to specify the number of systolic layers to use for processing the input data. In one embodiment, the systolic depth 3304 can be provided as the most recent value. The iteration count 3306 (rcount) can be used to specify the number of dpas instructions to be generated, along with dst and src0 which advance consecutive registers, src1 which remains the same, and src2 which advances by N elements (where N is the destination format).

[0287]

[0350] Destination 3308, zero source 3310 (src0), first source 3312 (srcl), and second source 3314 (srcl) can be used to specify the destination to which the calculation will be written and the location from which the source data can be retrieved. In one embodiment, destination 3308 can specify the register to which the data should be written. In one embodiment, destination 3308 can be a scalar register, but in some embodiments, the destination can be a vector register that stores outputs from multiple channels. Zero source 3310, first source 3312, and second source 3314 can be registers containing one or more channels of source data or the nearest value, each channel having four elements to be processed by a systolic array circuit.

[0288]

[0351] The integer bitmap (imm) field 3316 can be used to specify information about a custom binary format for at least one source operand (e.g., src1 3312 and / or src2 3314), such as the number of bits to be allocated for the exponent and the exponent offset to be used. This information can be passed in instruction 3300 as an integer bitmap in the imm field 3316.

[0289]

[0352] In some embodiments, additional fields other than those described may exist. For example, in one embodiment, there is a source modifier field that specifies the numeric modifier of the source operand. The value of each data element of the source operand can optionally take its absolute value and / or its sign can be inverted before being sent to the execution pipeline. The absolute value modifier can be applied before the negate modifier so that guaranteed negative values ​​can be produced. In one embodiment, there is a saturation field that can be used to suppress destination saturation. If saturation is enabled, the output data to the destination register is saturated. The specific saturation operation depends on the destination data type. Saturation is an operation that converts any data outside the saturation target range of that data type to the closest representation value within the target range.

[0290]

[0353] Figure 18B shows a program code compilation process 3315 according to one embodiment. In one embodiment, a source code-level description 3320 of a software program is compiled to a level having an operation 3340 that includes or specifies a hybrid 8-bit FP dot product, which is executed by processing logic, in a compiler 3330 that may include multiple levels of compilation. The operation 3340 may be an operation specified in an intermediate language, or it may be program code that references primitives of an operation framework, such as primitives provided by a machine learning framework. The operation 3340 that includes or specifies a hybrid 8-bit FP dot product may then be further compiled to machine-level object code 3360 by an additional compiler 1850, which may be a shader compiler, which object code may include a hybrid 8-bit FP dot product instruction executed by an accelerator for matrix operations such as those described herein.

[0291]

[0354] The following is an example of pseudocode for performing hybrid floating-point systolic arithmetic according to an embodiment.

[0292]

number

[0355] Figure 34 is a flowchart illustrating an embodiment of Method 3400 for executing instructions for hybrid floating-point systolic arithmetic. Method 3400 may be executed by processing logic that may include hardware (e.g., circuits, dedicated logic, programmable logic, etc.), software (e.g., instructions executed on a processing device), or a combination thereof. The processes of Method 3400 are shown in a linear sequence for the sake of brevity and clarity in the description; however, it is assumed that any number of them may be executed in parallel, asynchronously, or in different orders. Furthermore, for the sake of brevity, clarity, and ease of understanding, many of the components and processes described with respect to Figure 1-33 may not be repeated or discussed below. In one implementation, a data processing system such as the data processing system 1400 in Figure 14 may execute Method 3400.

[0293]

[0356] Method 3400 begins in processing block 3410, where a single instruction is fetched and decoded for execution within the GPGPU. In one implementation, the single instruction is decoded into a matrix instruction, which acts on a hybrid 8-bit floating-point format operand to cause the GPGPU to perform a parallel dot product operation. In processing block 3420, one or more 8-bit floating-point format operands are used to determine a set of pipeline commands to execute the decoded matrix instruction on a matrix accelerator.

[0294]

[0357] Next, in processing block 3430, a set of pipeline commands is scheduled to the systolic dot product pipeline to execute the decoded matrix instruction using one or more hybrid 8-bit floating-point format operands. Finally, in processing block 3440, the decoded matrix instruction is removed in response to the completion of the set of pipeline commands.

[0295]

[0358] Figure 35 is a flowchart illustrating an embodiment of Method 3500 for hybrid floating-point systolic arithmetic. Method 3500 may be performed by processing logic that may include hardware (e.g., circuits, dedicated logic, programmable logic, etc.), software (e.g., instructions executed on a processing device), or a combination thereof. The processes of Method 3500 are shown in a linear sequence for the sake of brevity and clarity in the description; however, it is assumed that any number of them may be executed in parallel, asynchronously, or in different orders. Furthermore, for the sake of brevity, clarity, and ease of understanding, many of the components and processes described with respect to Figures 1-34 may not be repeated or discussed below. In one implementation, a systolic array, such as the systolic array circuit 1640 in Figure 31, may perform Method 3500.

[0296]

[0359] Method 3500 begins in processing block 3510, where source values ​​and computation depth for an instruction are fetched for execution by the GPGPU matrix operation accelerator. In some implementations, the source values ​​are hybrid 8-bit floating-point format operands. In processing block 3520, the source value input is re-biased and normalized as part of a conversion to a common binary format.

[0297]

[0360] Next, in processing block 3530, a set of products is generated based on the element-wise multipliers of the source input elements in the common binary format. Then, in processing block 3540, the outputs of the multipliers and the inputs of the accumulators are normalized using shifters for each multiplier and for the inputs of the accumulators. In processing block 3550, the sum of the normalized set of multiplier outputs is calculated and the sum is rounded to the nearest even number. Finally, in processing block 3560, the sum is rounded to the destination output precision using the nearest even number rounding.

[0298] Execution of mixed-mode arithmetic using 8-bit floating-point operands

[0361] The embodiment results in performing mixed-mode arithmetic with 8-bit floating-point format operands.

[0299]

[0362] Advances in deep learning algorithms have enabled models to utilize low-precision computations in training neural networks. Conventional training platforms can support the IEEE-754 FP16 and BFLOAT16 data formats in high-performance systolic array implementations. However, 8-bit FP (such as BFLOAT8, 1s-5e-2m) may be used to improve training and inference performance.

[0300]

[0363] While much of the core computation of neural networks, such as convolutional and linear layers, may be able to utilize the 8-bit FP format data type, there are still parts of deep neural networks that operate under mixed-precision regimes (e.g., 8-bit FP format and 16-bit or 32-bit FP format). Some examples of parts of deep neural networks operating under mixed-precision regimes are batch normalization (BatchNorm) and layer normalization (LayerNorm) operations, which allow each layer to accept 8-bit FP format input (e.g., BFLOAT8) coming from the previous layer, while maintaining its own internal statistics (such as mean and variance) with higher precision.

[0301]

[0364] The current approach in conventional systems to address this mixed-precision problem is to upconvert the input tensor to a suitable higher-precision format before performing the operation, and then downconvert it to a lower precision for the systolic or output tensor. However, these conversion processes in conventional approaches introduce additional overhead for storing ultra-high-precision copies of the input tensor, increasing register bandwidth pressure and dependencies.

[0302]

[0365] The embodiments present address these technical issues by providing instructions for performing mixed-mode arithmetic on 8-bit FP format (e.g., BFLOAT8 and other IEEE-754 FP formats) input operands. Figure 15 above shows an exemplary BF8 binary format that can be used as the 8-bit FP format of the embodiments. The BFLOAT8 binary format is represented as sign, exponent, and mantissa bits. The 5-bit exponent uses an offset value of 15, which can represent normal floating-point values ​​between 6.1e-05 and 5.7344e+04. The format also supports subnormal values ​​that extend the dynamic range to a minimum representable value of 1.5e-05.

[0303]

[0366] These instructions for performing mixed-mode arithmetic can accept at least one input operand in 8-bit FP format (e.g., BFLOAT8), while the other input can be, for example, a standard floating-point or half-precision floating-point format. Embodiments provide a set of instructions for frequently occurring arithmetic operations that can operate on the aforementioned mixed-mode operands, such as multiplication (MUL), add, multiplication-cumulative (MAC), SEL, and subtraction (SUB).

[0304]

[0367] The embodiments described herein offer technical advantages in overcoming the aforementioned technical problems by reducing the footprint and bandwidth requirements for register files. Furthermore, the embodiments improve the end-to-end training performance of networks with a large percentage of BatchNorm and LayerNorm operations, for example. Moreover, enabling mixed-precision 8-bit FP format training may help accelerate training in neural networks in terms of training throughput.

[0305]

[0368] Figure 36 is a block diagram showing a mixed-mode 8-bit FP format arithmetic operation 3610 performed by an instruction pipeline 3600 according to an embodiment. The instruction pipeline 3600 can be configured to perform the mixed-mode 8-bit FP format arithmetic operation 3610. The instruction pipeline 3600 can be used to accelerate hardware instructions and may include an instruction fetch and decode unit 1421 capable of fetching and decoding hardware instructions, and a controller unit 3620 (such as a scheduler controller 1422), the controller unit can schedule the decoded instructions to one or more execution units and / or matrix accelerators 1423 in arithmetic blocks 1424A-1424N (collectively referred to as arithmetic block 1424). The instruction pipeline 3600 may also include a selection circuit 3630, such as a collection of multiplexers (muxes), to route input data to the arithmetic block 1424 and / or matrix accelerator 1423, according to the mixed-mode 8-bit FP format encoded in the hardware instructions of the mixed-mode 8-bit FP format arithmetic 3610.

[0306]

[0369] In one embodiment, hardware instructions are scheduled to the arithmetic block 1424 and / or can be offloaded to the matrix accelerator 1423 (for example, for calculations using the systolic array circuit 3640). One or more hardware instructions and associated data for executing the mixed-mode 8-bit FP format arithmetic 3610 can be stored in memory 3650. The output of the hardware instructions can also be stored in memory 3650. Memory 3650 can be any memory described herein, including system memory 1412, GPGPU memory 1418, or one or more cache memories 1427, 1430, as shown in Figure 14.

[0307]

[0370] In one embodiment, the arithmetic block 1424 can execute one or more hardware instructions to perform a mixed-mode 8-bit FP format arithmetic operation 3610 using the processing unit 3660. The processing unit 3660 may include a combination of programmable and fixed-function hardware that can be configured to perform a mixed-mode 8-bit FP format arithmetic operation. In some implementations, the processing unit 3660 may be a vector processing unit (VPU). In some implementations, the processing unit 3660 may be a floating-point unit (FPU). The processing unit 3660 may include a conversion circuit 3662, a nearest-neighbor rounding (RNE) arithmetic circuit 3664, and a special processing circuit 3666.

[0308]

[0371] In some embodiments, a hardware instruction for performing a mixed-mode 8-bit FP format arithmetic operation 3610 results in a mixed-mode operation for an 8-bit FP (e.g., BFLOAT8) input operand. This instruction accepts at least one 8-bit FP format (e.g., BFLOAT8) input operand, while the other input operands can be in an IEEE-754 floating-point or half-precision floating-point data format.

[0309]

[0372] The conversion circuit 3662 may include programmable and fixed-function hardware to perform the conversion process described above. The conversion circuit 3662 can internally upconvert an 8-bit FP format (e.g., BF8) operand to a higher-precision format to match the format of other input operands, and its operations are performed with higher precision. The data conversion of the conversion circuit 3662 renormalizes the 8-bit FP format input to match the dynamic range of the target precision and expands the mantissa with zeros in the least significant bit (LSB). The subnormal value for the BFLOAT8 input is preserved and normalized to the target precision. The RNE rounding circuit 3664 may include programmable and fixed-function hardware to perform RNE rounding operations on the converted data. The special processing circuit 3666 may include programmable and fixed-function hardware to handle corner cases encountered when converting and / or rounding data, such as underflow, overflow, and denormalization.

[0310]

[0373] In some implementations, the instructions for converting 8-bit FP format data as described here can take the following form: mac <f32> <f32> <f32> <bf8> mac <f16> <f16> <f16> <bf8> sub <f16> <f16> <bf8> add <f32> <f16> <bf8> I have <f16> <f16> <bf8> dst src0 src1 src2

[0374] Several examples of 8-bit FP format mixed modes are detailed below:

[0375] Instructions with two source operands (such as mov, add, cmp, sel, mul): One of the sources is in 8-bit FP format (e.g., BFLOAT8) and the other is a high-precision type. The destination is either in 8-bit FP format or a higher-precision type.

[0311]

[0376] Instructions with three source operands (such as mac): One or two of the sources are in 8-bit FP format (e.g., BFLOAT8), and the rest are of a higher precision type. The destination is either in 8-bit FP format or of a higher precision type.

[0312]

[0377] Figure 37 shows an exemplary schematic diagram of hardware circuitry 3700 for performing a mixed-mode MAC operation using at least one 8-bit FP format operand, according to an embodiment. In one implementation, the hardware circuitry 3700 may be implemented within the processing unit 3660 described with respect to Figure 36.

[0313]

[0378] As shown in the example in Figure 37, the hardware circuit 3700 for performing mixed-mode MAC operations accepts the input operands FP16(src1)3704 and BF8(src2)3706 and accumulates them together with the cumulative sum src0(F16)3702. The final output (dst(FP16)3750) is converted to the FP16 output. The conversion circuits 3710a, 3710b, and 3710c internally up-convert the src1 3704 and src2 3706 inputs to FP32. The conversion circuits 3710a-c may be the same as the conversion circuit 3662 described with respect to Figure 36. In the embodiment, the conversion circuits 3710a-c can maintain subnormal values ​​for all inputs (e.g., DAZ=0).

[0314]

[0379] The multiplier 3720 can generate an intermediate output by multiplying the FP32 inputs received from the conversion circuits 3710b and 3710c. The intermediate output from the multiplier 3720 is normalized and accumulated in the adder 3730 with the src0 input 3702 (which has been converted to FP32 format by the conversion circuit 3710a).

[0315]

[0380] Finally, another conversion circuit 3740 (which may be the same as the conversion circuit 3662 in Figure 36) converts the sum of FP32 to the output 3750 of FP16. In this embodiment, the conversion circuit 3740 maintains subnormal values ​​for all output (dst) data types (e.g., FTZ=0).

[0316]

[0381] Figure 38A shows a set of instructions 3800 that can be executed by the processing unit according to the embodiment described herein. Figure 38A shows the fields of instruction 3800 for performing mixed-mode operations using 8-bit FP-format operands. Instruction 3800 includes, but is not limited to, mixed-mode mac instructions 3812, mixed-mode sub instructions 3814, mixed-mode add instructions 3816, and mixed-mode mul instructions 3818. Other mixed-mode instructions for operations on 8-bit FP-format operands may be implemented by the embodiment.

[0317]

[0382] Instruction 3800 is executable by a processing unit such as a VPU or FPU, as provided by the embodiment. Figure 38A shows the fields of instruction 3800, which, when executed, causes the processing unit to execute instructions for performing mixed-mode arithmetic using 8-bit FP format operands. In one embodiment, instruction 3800 includes an opcode field 3802 and operand fields specifying a destination 3804, a 0th source (src0) 3806, a 1st source (src1) 3808, and / or a 2nd source (src2) 3810.

[0318]

[0383] The opcode field 3802 can specify an opcode that identifies the instruction 3800 to the execution logic. In one embodiment, the opcode field 3802 includes one or more bits that, when enabled, indicate that the instruction should be executed by a processing unit of an arithmetic block (e.g., arithmetic block 1424).

[0319]

[0384] Destination 3804, zero source 3806 (src0), first source 3808 (src1), and second source 3806 (src2) can be used to specify the destination to which the calculation will be written and the location from which the source data can be retrieved. In one embodiment, destination 3804 can specify the register to which the data will be written. In one embodiment, destination 3804 can be a scalar register, but in some embodiments, the destination can be a vector register that stores outputs from multiple channels. Zero source 3806 (src0), first source 3808 (src1), and second source 3806 (src2) can be registers or immediate values ​​containing one or more channels of source data.

[0320]

[0385] In some embodiments, additional fields other than those illustrated may exist. For example, in one embodiment, there is a source modifier field that specifies a numerical modification of the source operand. The value of each data element of the source operand can optionally take its absolute value and / or its sign can be inverted before being sent to the execution pipeline. The absolute value modifier can be applied before the negate modifier so that guaranteed negative values ​​can be produced. In one embodiment, there is a saturation field, which can be used to suppress destination saturation. If saturation is enabled, the output data to the destination register is saturated. The specific saturation operation depends on the destination data type. Saturation is an operation that converts any data outside the saturation target range of the data type to the closest representation within the target range.

[0321]

[0386] Figure 38B shows a program code compilation process 3815 according to one embodiment. In one embodiment, a source code-level description 3820 of a software program is compiled to a level having arithmetic operations 3840 that include or specify 8-bit FP mixed-mode instructions to be executed by processing logic, in a compiler 3830 which may include multiple levels of compilation. Arithmetic operations 3840 may be operations specified in an intermediate language, or they may be program code that references primitives of an arithmetic framework, such as primitives provided by a machine learning framework. Arithmetic operations 3840 that include or specify 8-bit FP mixed-mode instructions may then be further compiled to machine-level object code 3860 by an additional compiler 3850 (which may be a shader compiler), the object code which includes 8-bit FP mixed-mode instructions to be executed by processing units (e.g., VPU, FPU) of a computer block, as described herein.

[0322]

[0387] The following is an example of pseudocode for performing mixed-mode 8-bit FP format arithmetic according to the embodiment.

[0323]

number

[0388] Figure 39 is a flowchart illustrating an embodiment of Method 3900 for executing instructions that perform mixed-mode arithmetic with 8-bit floating-point format operands. Method 3900 may be executed by processing logic that may include hardware (e.g., circuits, dedicated logic, programmable logic, etc.), software (e.g., instructions executed on a processing device), or a combination thereof. The processes of Method 3900 are shown in a linear sequence for the sake of brevity and clarity in this explanation; however, it is assumed that any number of them may be executed in parallel, asynchronously, or in different orders. Furthermore, for the sake of brevity, clarity, and ease of understanding, many of the components and processes described with respect to Figure 1-38 may not be repeated or discussed below. In one implementation, a data processing system such as the data processing system 1400 in Figure 14 may execute Method 3900.

[0324]

[0389] Method 3900 begins with processing block 3910, where a single instruction is fetched and decoded for execution within the GPGPU. In one implementation, the single instruction may be decoded into a matrix instruction, causing the GPGPU to perform 8-bit floating-point format mixed-mode arithmetic. In processing block 3920, a set of commands is determined to execute the decoded vector instruction in the GPGPU's arithmetic block.

[0325]

[0390] Next, in processing block 3930, a set of commands is scheduled to the GPGPU's arithmetic blocks to execute the decoded instructions and perform 8-bit floating-point format mixed-mode arithmetic. Finally, in processing block 3940, the decoded instructions are removed in response to the completion of the set of commands.

[0326]

[0391] Figure 40 is a flowchart illustrating an embodiment of Method 4000 for performing mixed-mode arithmetic with 8-bit floating-point format operands. Method 4000 may be performed by processing logic that may include hardware (e.g., circuits, dedicated logic, programmable logic, etc.), software (e.g., instructions executed on a processing device), or a combination thereof. The processes of Method 4000 are shown in a linear sequence for the sake of brevity and clarity in the description; however, it is assumed that any number of them may be executed in parallel, asynchronously, or in different orders. Furthermore, for the sake of brevity, clarity, and ease of understanding, many of the components and processes described with respect to Figure 1-39 may not be repeated or discussed below. In one implementation, a processing unit such as processing unit 3660 in Figure 36 may perform Method 4000.

[0327]

[0392] Method 4000 begins in processing block 4010, where source values ​​for instructions are fetched for operations to be performed by the GPGPU arithmetic blocks. In some implementations, the source values ​​are mixed-mode 8-bit floating-point format operands. In processing block 4020, the source value inputs are re-biased and normalized as part of a conversion to a common binary format. Subsequently, in processing block 4030, the operations are performed on the source input elements in the common binary format.

[0328]

[0393] Next, in processing block 4040, the calculation output is normalized using a shifter. Then, in processing block 4050, the normalized output is converted to the destination format to generate the result value. Finally, in processing block 4060, the result value is returned to the destination operand.

[0329]

[0394] The following examples relate to further embodiments: Embodiment 1 is a device that provides support for operands in an 8-bit floating-point format in an arithmetic architecture. In one embodiment, Embodiment 1 brings about the accumulation of a systolic dot product with respect to input operands in an 8-bit floating-point format. The device of Embodiment 1 includes a processor, the processor comprising: a decoder that decodes an instruction fetched for execution into a decoded instruction, the decoded instruction being a matrix instruction that acts on an 8-bit floating-point operand to cause the processor to perform a parallel dot product operation; a controller that schedules the decoded instruction and provides input data to the 8-bit floating-point operand according to the 8-bit floating-point data format specified by the decoded instruction; and a systolic dot product circuit that executes the decoded instruction using a systolic layer, each systolic layer comprising one or more sets of interconnected multipliers, shifters, and adders, each set of multipliers, shifters, and adders generating a dot product of 8-bit floating-point operands, the systolic dot product circuit.

[0330]

[0395] In Example 2, the subject matter of Example 1 may optionally include the following: the shifter normalizes the output of the multiplier. In Example 3, any one subject matter from Examples 1-2 may optionally include the following: the multiplier includes at least one of a 4-bit multiplier, an 8-bit multiplier, a 16-bit multiplier, or a 32-bit multiplier. In Example 4, any one subject matter from Examples 1-3 may optionally include the following: the adder includes an addition tree that adds the product generated by the multiplier normalized by the shifter, and the adder rounds the result of the addition tree by rounding to the nearest even number.

[0331]

[0396] In Example 5, any one of Examples 1-4 may optionally include the following: the result is rounded to the precision of the destination specified by the decoded instruction. In Example 6, any one of Examples 1-5 may optionally include the following: the systolic dot product performs post-accumulation of the accumulator source operand, in which the accumulator source operand is accumulated following the generation of the dot product of the 8-bit floating-point operands. In Example 7, any one of Examples 1-6 may optionally include the following: the systolic dot product performs accumulation of the accumulator source operand, in which the accumulator source operand is accumulated in either the first stage of the systolic dot product or one of the intermediate stages of the systolic dot product.

[0332]

[0397] In Example 8, any one of Examples 1-7 may optionally include the following: the processor includes a graphics processing unit (GPU). In Example 8, any one of Examples 1-8 may optionally include the following: the device is at least one of a single-instruction multiplexed data (SIMD) machine or a single-instruction multiplexed threads (SIMT) machine.

[0333]

[0398] Example 10 is a method to help support operands in an 8-bit floating-point format in an arithmetic architecture, the method comprising: a step of the processor decoding an instruction fetched for execution into a decoded instruction, the decoded instruction being a matrix instruction that acts on an 8-bit floating-point operand to cause the processor to perform a parallel dot product operation; a step of the processor scheduling the decoded instruction, providing input data to an 8-bit floating-point operand according to an 8-bit floating-point data format specified by the decoded instruction; and a step of the processor's systolic dot product circuit executing the decoded instruction using a systolic layer, each systolic layer comprising one or more sets of interconnected multipliers, shifters, and adders, each set of multipliers, shifters, and adders producing a dot product of 8-bit floating-point operands.

[0334]

[0399] In Example 11, the subject of Example 10 may optionally include the following: the shifter normalizes the output of the multiplier, the adder includes an addition tree that adds the product produced by the multiplier normalized by the shifter, and the adder rounds the result of the addition tree by rounding to the nearest even number. In Example 12, any one subject of Examples 10-11 may optionally include the following: the result is rounded to the precision of the destination specified by the decoded instruction. In Example 13, any one subject of Examples 10-12 may optionally include the following: the multiplier includes at least one of a 4-bit multiplier, an 8-bit multiplier, a 16-bit multiplier, or a 32-bit multiplier.

[0335]

[0400] In Example 14, any one of Examples 10-13 may optionally include the following: the systolic dot product circuit further includes a step of performing post-accumulation of the accumulator source operand, in which the accumulator source operand is accumulated following the generation of the dot product of the 8-bit floating-point operands. In Example 15, any one of Examples 10-14 may optionally include the following: the systolic dot product circuit further includes a step of performing accumulation of the accumulator source operand, in which the accumulator source operand is accumulated in the first stage of the systolic dot product circuit or in one of the intermediate stages of the systolic dot product circuit.

[0336]

[0401] Example 16 is a non-temporary computer-readable medium that helps support operands in an 8-bit floating-point format in an arithmetic architecture. In Embodiment 16, a non-temporary computer-readable medium is capable of storing instructions, and when an instruction is executed by one or more processors, it causes the processors to perform the following methods: one or more processors decode an instruction fetched for execution into a decoded instruction, the decoded instruction being a matrix instruction acting on 8-bit floating-point operands to cause one or more processors to perform a parallel dot product operation; one or more processors schedule the decoded instruction, providing input data to 8-bit floating-point operands according to an 8-bit floating-point data format specified by the decoded instruction; and a systolic dot product circuit of one or more processors executes the decoded instruction using a systolic layer, each systolic layer comprising one or more sets of interconnected multipliers, shifters, and adders, each set of multipliers, shifters, and adders producing a dot product of 8-bit floating-point operands.

[0337]

[0402] In Example 17, the subject matter of Example 16 may optionally include the following: a shifter normalizes the output of a multiplier, an adder includes an addition tree that adds the product produced by the multiplier normalized by the shifter, and the adder rounds the result of the addition tree by rounding to the nearest even number. In Example 18, any one subject matter from Examples 16-17 may optionally include the following: the result is rounded to the precision of the destination specified by the decoded instruction.

[0338]

[0403] In Example 19, any one of the objects in Examples 16-18 may optionally include the following: the instruction causes one or more processors to perform post-accumulation of a systolic dot product circuit, where post-accumulation involves accumulating the accumulator source operand following the generation of the dot product of the 8-bit floating-point operands. In Example 20, any one of the objects in Examples 16-19 may optionally include the following: the instruction causes one or more processors to perform accumulation of a systolic dot product circuit, where accumulation involves accumulating the accumulator source operand in either the first stage of the systolic dot product circuit or one of the intermediate stages of the systolic dot product circuit.

[0339]

[0404] Embodiment 21 is a system that helps support operands in an 8-bit floating-point format in an arithmetic architecture. One or more processors in Embodiment 21 are communicably coupled to memory and include: a decoder that decodes an instruction fetched for execution into a decoded instruction, the decoded instruction being a matrix instruction that acts on an 8-bit floating-point operand to cause a graphics processing unit to perform a parallel dot product operation; a controller that schedules the decoded instruction and provides input data to an 8-bit floating-point operand according to an 8-bit floating-point data format specified by the decoded instruction; and a systric dot product circuit that executes the decoded instruction using a systric layer, each systric layer including one or more sets of interconnected multipliers, shifters, and adders, each set of multipliers, shifters, and adders producing a dot product of 8-bit floating-point operands.

[0340]

[0405] In Example 22, the subject matter of Example 21 may optionally include the following: the shifter normalizes the output of the multiplier. In Example 23, any one subject matter from Examples 21-22 may optionally include the following: the multiplier includes at least one of a 4-bit multiplier, an 8-bit multiplier, a 16-bit multiplier, or a 32-bit multiplier. In Example 24, any one subject matter from Examples 21-23 may optionally include the following: the adder includes an addition tree that adds the product generated by the multiplier normalized by the shifter, and the adder rounds the result of the addition tree by rounding to the nearest even number.

[0341]

[0406] In Example 25, any one of the objects in Examples 21-24 may optionally include the following: the result is rounded to the precision of the destination specified by the decoded instruction. In Example 26, any one of the objects in Examples 21-25 may optionally include the following: the systolic dot product performs post-accumulation of the accumulator source operand, in which the accumulator source operand is accumulated following the generation of the dot product of the 8-bit floating-point operands. In Example 27, any one of the objects in Examples 21-26 may optionally include the following: the systolic dot product performs accumulation of the accumulator source operand, in which the accumulator source operand is accumulated in either the first stage of the systolic dot product or one of the intermediate stages of the systolic dot product.

[0342]

[0407] In Example 28, any one of the subjects from Examples 21-27 may optionally include the following: the processor includes a graphics processing unit (GPU). In Example 28, any one of the subjects from Examples 21-28 may optionally include the following: the device is at least one of a single-instruction multiplexed data (SIMD) machine or a single-instruction multiplexed threads (SIMT) machine.

[0343]

[0408] Example 30 is a device that assists in supporting operands in an 8-bit floating-point format in an arithmetic architecture, the device comprising: means for decoding an instruction fetched for execution into a decoded instruction, the decoded instruction being a matrix instruction acting on an 8-bit floating-point operand to cause the processor to perform a parallel dot product operation; means for scheduling the decoded instruction, the means for providing input data to an 8-bit floating-point operand according to an 8-bit floating-point data format specified by the decoded instruction; and means for executing the decoded instruction using a systolic layer, each systolic layer comprising one or more sets of interconnected multipliers, shifters, and adders, each set of multipliers, shifters, and adders generating a dot product of 8-bit floating-point operands. In Example 31, the subject matter of Example 30 optionally further includes a device further configured to perform the method described in any one of Examples 11-15.

[0344]

[0409] Example 32 is at least one machine-readable medium containing a plurality of instructions that, in response to being executed on an arithmetic device, cause the arithmetic device to perform any one of the methods of Examples 10-15. Example 33 is a device that assists in supporting operands in an 8-bit floating-point format in an arithmetic architecture, configured to perform any one of the methods of Examples 10-15. Example 34 is a device that assists in supporting operands in an 8-bit floating-point format in an arithmetic architecture, having means for performing any one of the methods of Examples 10-15. Specific features in the examples may be used in any one or more embodiments.

[0345]

[0410] Example 35 is a device that assists in supporting operands in an 8-bit floating-point format in an arithmetic architecture, and in particular assists in converting floating-point data to or from 8-bit floating-point format data. The device of Example 35 includes a processor of a plurality of graphics processing units (GPUs) which: fetches a source value of an instruction executed by the arithmetic blocks of the processor (the source value is converted to a different data format, and the source value is at least one operand in an 8-bit floating-point format, or is converted to an 8-bit floating-point operand); converts the source value to a signed-size format of a destination by applying rescaling, normalization, and conversion, and rounding to the nearest even number of the converted source value; and returns the converted and rounded source value as the destination value.

[0346]

[0411] Example 36 is a device that helps support 8-bit floating-point format operands in an arithmetic architecture, and in particular assists in efficient probabilistic rounding of floating-point format data values. The device of Example 36 includes a processor of multiple graphics processing units (GPUs), the processors: fetch the source value of an instruction executed by the processor's arithmetic block (the source value is converted from higher precision floating-point to lower precision floating-point); convert the source value to the signed-size format of the destination, normalize the converted source value; add a random number to the converted and normalized source value (the random number has a size determined based on the data format of the source and destination operands, and the random number is obtained from a PRNG); exponentially adjust the sum of the results, truncate the sum of the results to the size of the mantissa format of the destination operand to generate the resulting destination value; and return the resulting destination value.

[0347]

[0412] Example 37 is a device that helps support 8-bit floating-point format operands in an arithmetic architecture, and in particular assists hybrid floating-point systolic arithmetic. The device of Example 37 includes a processor of multiple graphics processing units (GPUs) which: fetches the arithmetic depth and source values ​​for instructions executed by the processor's matrix arithmetic accelerator (the source values ​​include hybrid 8-bit floating-point format operands); rebias and normalizes the source values ​​as part of a conversion to a common binary format; generates a set of products based on the element-wise multiplication of the rebiased and normalized source values ​​in the common binary format; normalizes the multiplier outputs and accumulator inputs using shifters for each multiplier and for the accumulator inputs; calculates the sum of the set of normalized multiplier outputs and rounds the sum to the nearest even number; and rounds the calculated sum to destination output precision by rounding to the nearest even number.

[0348]

[0413] Example 38 is a device that helps support 8-bit floating-point format operands in an arithmetic architecture, and in particular supports mixed-mode arithmetic with 8-bit floating-point format operands. The device of Example 38 includes a processor of multiple graphics processing units (GPUs), the processors: fetch source values ​​for instructions for arithmetic operations to be performed by the processor's arithmetic blocks (the source values ​​include mixed-mode 8-bit floating-point format operands); re-bias and normalize the source values ​​as part of a conversion to a common binary format; perform operations on the re-biased and normalized source values ​​in the common binary format; normalize the output using a shifter; convert the normalized output to a destination format to generate a result value; and return the result value to the destination operand.

[0349]

[0414] The foregoing description and drawings should be considered illustrative rather than restrictive. A person skilled in the art will understand that various modifications and changes may be made to the embodiments described herein without departing from the broader spirit and scope of the features described in the attached claims. < / f16> < / f16> < / f16> < / f32> < / f16> < / f16> < / f16> < / f16> < / f16> < / f32> < / f32> < / f32> < / hf8> < / f32> < / f32> < / rcount> < / sdepth> < / bf8> < / f16> < / f16> < / rcount> < / sdepth> < / hf8> < / f32> < / f32> < / rcount> < / sdepth> < / fp16> < / fp32> < / bf8> < / bf8>

Claims

1. A device including an integrated circuit chip, wherein the integrated circuit chip is: Multiple registers that store multiple data elements, including 8-bit floating-point data elements and 32-bit floating-point data elements; A decoding circuit for decoding a single matrix instruction having fields indicating the location and opcode of a first source matrix containing a first plurality of 8-bit floating-point data elements encoded in a first 8-bit floating-point format, a second source matrix containing a second plurality of 8-bit floating-point data elements encoded in a second 8-bit floating-point format, and a third source matrix containing a plurality of 32-bit floating-point data elements, wherein the first 8-bit floating-point format includes a sign bit, a 5-bit exponent value, and a 2-bit mantissa value, and the second 8-bit floating-point format includes a sign bit, a 4-bit exponent value, and a 3-bit mantissa value; and An execution circuit including a matrix accelerator for accelerating matrix operations, wherein, in response to a single matrix instruction, the execution circuit generates a plurality of products based on a first plurality of 8-bit floating-point data elements of a first source matrix and a second plurality of 8-bit floating-point data elements of a second source matrix, and accumulates each of the plurality of products into a corresponding 32-bit floating-point data element of a third source matrix to generate a corresponding 32-bit floating-point result data element of a resulting matrix; A device that includes this.

2. The apparatus according to claim 1, further comprising a package assembly, wherein the package assembly is: The integrated circuit chip including a graphics processor chiplet; A first base chiplet comprising a first interconnect fabric and a first global cache coupled to the first interconnect fabric, wherein the graphics processor chiplet is stacked on the first base chiplet, and the first interconnect structure couples the graphics processor chiplet to the first interconnect fabric; A second base chiplet coupled to the first base chiplet by a second interconnection structure, the second base chiplet comprising a second interconnection fabric and a second global cache coupled to the second interconnection fabric; A processor core chiplet stacked on the second base chiplet, comprising a plurality of processor cores, wherein a third interconnection structure connects the processor core chiplet to the second interconnection fabric; A device including a device.

3. The apparatus according to claim 2, wherein the graphics processor chiplet is manufactured using a process technology different from the process technology used to manufacture the first and second base chiplets.

4. In the apparatus according to claim 2 or 3, further: A device comprising one or more memory controllers that couple the graphics processor chiplet and the processor core chiplet to an integrated memory, wherein the graphics processor chiplet and the processor core chiplet access the integrated memory, which shares an integrated virtual address space.

5. The apparatus according to any one of claims 1 to 4, further comprising a scheduler for scheduling a set of commands for execution by the execution circuit in response to the single matrix instruction.

6. An apparatus according to any one of claims 1 to 5, wherein the execution circuit is for executing the single matrix instruction via a plurality of single instruction multiplexed data channels.

7. The apparatus according to claim 6, wherein in each of the plurality of single-instruction multiplexed data channels, a group of 8-bit floating-point data elements from the first plurality of 8-bit floating-point data elements of the first source matrix is ​​multiplied by the corresponding group of 8-bit floating-point data elements from the second plurality of 8-bit floating-point data elements of the second source matrix.

8. The apparatus according to claim 6 or 7, wherein the single instruction multiplexing data channel includes a 32-bit single instruction multiplexing data channel.

9. The apparatus according to claim 8, wherein in one of the 32-bit single-instruction multiplexed data channels, four groups of the first plurality of 8-bit floating-point data elements of the first source matrix are multiplied by four corresponding groups of the second plurality of 8-bit floating-point data elements of the second source matrix.

10. The apparatus according to claim 4, further comprising a plurality of memory management units that provide virtual-physical address mapping.

11. The apparatus according to claim 10, wherein the plurality of memory management units include a first memory management unit associated with the processor core chiplet and a second memory management unit associated with the graphics processor chiplet.

12. The apparatus according to claim 11, wherein the first and second memory management units are synchronized according to the integrated virtual address space.

13. The apparatus according to any one of claims 10 to 12, wherein the plurality of memory management units include input / output memory management units for managing a plurality of sets of page tables that map virtual addresses to physical addresses, including virtual addresses of the integrated virtual address space shared by the graphics processor chiplet and the processor core chiplet.

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