Methods for forming oxide, nitride, and oxide stacks of non-volatile memory and their integration into CMOS process flows.

Abstract

A method for fabricating a semiconductor device is described. Generally, the method includes forming a customizable oxide-nitride (ONO) stack on a substrate in an in situ atomic layer deposition (ALD) tool or chamber. A radical oxidation or oxide deposition process step is performed to form a tunnel dielectric layer overlying the substrate. A silicon nitride deposition process step is also performed to form a multilayer charge trapping (CT) layer, and at least some of the process parameters of the silicon nitride deposition process step are adjusted in forming first and second CT sublayers of the multilayer CT layer. A subsequent radical oxidation or oxide deposition process step is performed in the ALD tool to form a blocking dielectric layer overlying the multilayer CT layer.

Description

[Technical Field]

[0001] Cross-reference of related applications This application is an international application, U.S. Provisional Patent Application No. 17 / 954141, filed on 27 September 2022, the contents of which are incorporated herein by reference.

[0002] Technical field This disclosure generally relates to non-volatile memory (NVM) cells or devices, and more specifically to NVM cells or devices based on silicon (semiconductor) oxide nitride oxide silicon (semiconductor) (SONOS), and methods for manufacturing the same. [Background technology]

[0003] NVMs are widely used in computer systems to store data, typically involving memory arrays with numerous NVM cells arranged in rows and columns, or other configurations. For the past several decades, scaling mechanisms in integrated circuits has been the driving force behind the ever-growing semiconductor industry. Scaling to increasingly smaller mechanisms allows for increased density of functional units within a limited area of ​​a semiconductor chip. However, the push for even greater capacity is not without its challenges. The need to optimize the performance of each device while scaling becomes increasingly important.

[0004] In some embodiments, the NVM cell may include at least a non-volatile element, such as a charge-trapping field-effect transistor (FET), a floating-gate transistor (programmed or erased by applying a voltage of appropriate polarity, magnitude, and duration between the control / memory gate and the substrate or drain / source region). For example, in an n-channel charge-trapping FET, a positive gate-to-substrate voltage is applied so that electrons tunnel out of the channel by Fowler-Nordheim (FN) tunneling and are trapped in the charge-trapping dielectric layer, thereby passing through the transistor's threshold voltage (V T ) increase or drain current (I D) which results in lowering. A negative gate-to-channel voltage causes holes to tunnel from the channel and be trapped in the charge-trapping dielectric layer, lowering the V of the SONOS transistor T or results in raising the I D . In some embodiments, a SONOS-based memory array is used and operated as a digital data storage device, where binary bits (0 and 1) of data are stored based on two separate V T or I D levels or values.

[0005] There is a need to use NVM technologies, such as SONOS, for analog memory and processing because they have multiple distinct V T and I D (more than 2) levels that can be set with achievable high precision. SONOS memory cells provide desirable low-latency, power, and noise operation for analog processing, including edge inference computing, such as neuromorphic computing in artificial intelligence (AI) applications. However, multi-level SONOS memory cells present more difficulties in scaling, such as charge retention in the ONO stack, degradation and / or shift of the V T .

Summary of the Invention

Problems to be Solved by the Invention

[0006] Therefore, an object of the present invention is to propose an improved manufacturing method for forming an ONO stack in a SONOS memory cell and to integrate such a process into a baseline complementary metal-oxide-semiconductor (CMOS) process flow.

Means for Solving the Problems

[0007] The present invention will be more fully understood from the following detailed description, and from the accompanying drawings and the claims provided below.

[0008] Detailed explanation The following description provides numerous specific details, such as examples of specific systems, elements, and methods, to give a good understanding of several embodiments of the subject matter. However, it will be apparent to those skilled in the art that at least some embodiments can be carried out without these specific details. In other examples, well-known elements or methods are not described in detail or are shown in the form of simple block diagrams, in order to avoid unnecessarily obscuring the art described herein. Accordingly, the specific details shown below are illustrative only. Specific implementations may differ from these illustrative details and are still to be interpreted as remaining within the spirit and scope of the subject matter.

[0009] Embodiments of memory cells including SONOS-based transistors, with or without metal-oxide-semiconductor (MOS) transistors or field-effect transistors (FETs), and methods for manufacturing the same, are described herein with reference to the drawings. However, certain embodiments may be carried out without one or more of their specific details, or in combination with other known methods, materials, and apparatus in the related art. In the following description, numerous specific details, such as specific materials, dimensions, concentrations, and process parameters, are given in order to thoroughly understand the subject matter. In other examples, well-known semiconductor design and manufacturing techniques are not described in particular detail in order to avoid unnecessarily obscuring the subject matter. References to “embodiments,” “one embodiment,” “an example embodiment,” “several embodiments,” and “various embodiments” in the description mean that a particular mechanism, structure, or feature described in relation to that embodiment is included in at least one embodiment of the subject matter. Furthermore, the terms “embodiments,” “one embodiment,” “an example embodiment,” “several embodiments,” and “various embodiments” appearing in various parts of the description do not necessarily all refer to the same embodiment.

[0010] The description includes references to the accompanying drawings, which form part of the detailed description. The drawings illustrate the description according to exemplary embodiments. Those embodiments, which may be shown herein as “examples,” are described in sufficient detail for a person skilled in the art to carry out embodiments of the claimed subject matter as described herein. Embodiments can be combined, other embodiments can be used, or structural, theoretical, and electrical modifications can be made without departing from the scope and spirit of the claimed subject matter. It should be understood that the embodiments described herein are not intended to limit the scope of the subject matter, but rather to enable a person skilled in the art to carry out, manufacture and / or use the subject matter.

[0011] The terms “over,” “below,” “between,” and “on” as used herein relate to the relative position of one layer to other layers. Therefore, for example, one layer deposited or positioned above or below other layers may be in direct contact with the other layers or may have one or more intervening layers. Furthermore, one layer deposited or positioned between layers may be in direct contact with those layers or may have one or more intervening layers. Moreover, the relative position of one layer to other layers is provided without considering the absolute orientation of the substrate, assuming operations of film deposition, modification, and removal on the starting substrate.

[0012] Unless otherwise stated, as will be apparent from the following discussion, discussions throughout the specification using terms such as “processing,” “computing,” “calculating,” and “determining” are understood to relate to the operation and / or processing of a computer or computing system, or similar electronic computing device, that manipulates and / or converts data represented as physical, for example, electronic quantities in the registers and / or memory of the computing system to other data represented as similar physical quantities in the memory, registers, or other storage, transmission, or display devices of such information of the computing system.

[0013] Summary of the subject According to one embodiment of a method for manufacturing a semiconductor device, the method may include the steps of: dividing a substrate into a first region and a second region; forming a customizable oxide-nitride-oxide (ONO) stack in the first region; performing at least one of a first radical oxidation and a first oxide deposition process step in an atomic layer deposition (ALD) tool to form a tunnel dielectric layer on the substrate; performing a plurality of silicon nitride deposition process steps in an ALD tool to form a multilayer charge trapping (CT) layer; determining process parameters of the first silicon nitride deposition process step of the plurality of silicon nitride deposition process steps to form a first CT sublayer; modifying at least one of the process parameters; performing a second silicon nitride deposition process step to form a second CT sublayer on top of the first CT sublayer; and performing at least one of a second radical oxidation and a second oxide deposition process step in an ALD tool to form a blocking dielectric layer on top of the multilayer CT layer in the first region.

[0014] In one embodiment, the silicon nitride formed may include silicon oxynitride containing oxygen.

[0015] In one embodiment, the customizable ONO stack formation process step is in situ and performed within the same ALD tool.

[0016] In one embodiment, the silicon nitride film composition of silicon, oxygen, and nitrogen in the first CT sublayer and the second CT sublayer is different. In one embodiment, the first CT sublayer is silicon nitride with a high oxygen content, so there is substantially no charge trapping, while the second CT sublayer is silicon nitride with a low oxygen content, so charge trapping is substantially concentrated.

[0017] According to one embodiment of a method of manufacturing a semiconductor device, the method includes performing a plurality of third silicon nitride deposition process steps to form a plurality of third CT sub-layers disposed between a first CT sub-layer and a second CT sub-layer, wherein the process parameters of the plurality of third silicon nitride deposition process steps may be further adjusted such that the oxygen level of the plurality of third CT sub-layers is between the oxygen levels of the first CT sub-layer and the second CT sub-layer. In one embodiment, the method includes performing at least one of a third radical oxidation and a third oxide deposition process step in the same ALD tool to form an oxide thin film overlying the first CT sub-layer and under the second CT sub-layer, wherein the oxide thin film is formed to reduce the electron charge accumulated at the boundary of the second CT sub-layer from tunneling into the first CT sub-layer.

[0018] In one embodiment, the process parameters of the first and second radical oxidation process steps can include the type of reaction gas containing O2 / H2 gas, the flow rate of the reaction gas into the ALD tool, the reaction time for each reaction gas, the sequence of reaction gases entering the ALD tool, and the repetition and the number of repetition sequences, and the process parameters are configured to control at least one of the thickness, density, and quality of the oxide formed in the tunnel dielectric layer.

[0019] In one embodiment, the process parameters of the first and second oxide deposition process steps can include the type of silicon source precursor gas containing HCD, the type of reaction gas containing O2 / H2 gas, the flow rates of the reaction gas and the silicon source precursor gas, the reaction time for each reaction gas and the silicon source precursor gas, and the sequence of the reaction gas and the silicon source precursor gas entering the ALD tool, and the process parameters are configured to control at least one of the thickness, density, and quality of the oxide formed in the blocking dielectric layer.

[0020] In one embodiment, the process parameters of the first and second silicon nitride deposition process steps can include the type of silicon source precursor gas including HCD, the type of reaction gas including NH3 / N2O , the flow rates of the reaction gas and the silicon source precursor gas, and the reaction time for each of the reaction gas and the silicon source precursor gas, the sequence of reaction gas and silicon source precursor gas entering the ALD tool, and repetition, and the number of repetition sequences.

[0021] In one embodiment, at least one of the plurality of silicon nitride deposition process steps can be plasma enhanced.

[0022] In one embodiment, the first radical oxidation and the first oxide deposition process steps can be repeated individually, alternately, or in combination thereof to form a tunnel dielectric layer, and the second radical oxidation and the second oxide deposition process steps can be repeated individually, alternately, or in combination thereof to form a blocking dielectric layer, and the process parameters of the first and second radical oxidation process steps and the first and second oxide deposition process steps are adjusted during the repetition of the process steps so that the tunnel dielectric layer and the blocking dielectric layer are customized.

[0023] According to one embodiment of a method of manufacturing a semiconductor device, the method includes forming a high voltage (HV) gate oxide layer, an input / output (I / O) gate oxide layer, and a low voltage (LV) gate oxide layer in a second region of a substrate, wherein at least one of the HV, I / O, and LV gate oxide layers is formed simultaneously with a blocking dielectric layer of a customizable O·N·O layer in a first region by at least one of the second radical oxidation and the second oxide deposition process steps.

[0024] In one embodiment, the multilayer CT layer may include at least three CT sublayers, and the process parameters of the multiple silicon nitride deposition process steps are modified such that, in the multilayer CT layer, the upper CT sublayer adjacent to the blocking dielectric layer is the least oxygen-rich, and the lower CT sublayer adjacent to the tunnel dielectric layer is the most oxygen-rich.

[0025] According to an embodiment of the method for manufacturing a memory device, the method may include the steps of: forming a tunnel oxide layer in a memory region and a logic region of a substrate; forming a customizable charge trapping (CT) layer and a cap layer on top of the tunnel oxide layer, wherein the customizable CT layer comprises a plurality of CT sublayers, and each CT sublayer is formed by one or more silicon nitride deposition process steps carried out in an atomic layer deposition (ALD) chamber; patterning the tunnel oxide layer, the customizable CT layer and the cap layer so that a memory stack is formed in the memory region while these layers are removed in the logic region; and carrying out at least one radical oxidation process step in the ALD chamber, simultaneously converting silicon nitride in at least the cap layer to form a blocking layer on top of the customizable CT layer, and converting silicon in the substrate to form a first gate oxide layer in the logic layer.

[0026] In one embodiment, the method may also include a step of performing at least one oxide deposition process step within the ALD chamber to simultaneously add thickness to the blocking oxide layer and the first gate oxide layer in the logic region.

[0027] In one embodiment, process parameters for one or more silicon nitride deposition process steps may include the type of silicon source precursor gas containing HCD, the type of reaction gas containing NH3 / N2O, the flow rates of the reaction gas and silicon source precursor gas, the reaction time for each reaction gas and silicon source precursor gas, and the sequence of reaction gas and silicon source precursor gas entering the ALD chamber.

[0028] In one embodiment, process parameters of one or more silicon nitride deposition process steps can be adjusted to produce CT sublayers having at least one of different thicknesses, densities, and film compositions of silicon nitride Si, O, and N in the CT sublayer.

[0029] According to one embodiment of a method for manufacturing a memory device based on SONOS, the method may include the steps of forming a memory cell including SONOS transistors and pass transistors in a memory region of a substrate, the steps of forming a tunnel oxide layer in the memory region and logic region of the substrate, forming a customizable charge trapping (CT) layer and a cap layer on top of the tunnel oxide layer, wherein the customizable CT layer includes a plurality of CT sublayers, and each CT sublayer is formed by one or more silicon nitride deposition process steps carried out in an atomic layer deposition (ALD) chamber, the steps of patterning the tunnel oxide layer, the customizable CT layer and the cap layer so that a memory stack is formed in the memory region while these layers are removed in the logic region, the steps of forming a blocking oxide layer on top of the customizable CT layer and forming a first gate oxide for the pass transistors in the memory region, and the steps of forming an HV gate oxide layer for a high-voltage (HV) transistor, an I / O gate oxide layer for an input / output (I / O) transistor and an LV gate oxide layer for a low-voltage (LV) transistor in the logic region. In one embodiment, at least one of the HV, I / O, and LV gate oxides is at least partially formed by carrying out at least one radical oxidation process step in an ALD chamber, simultaneously converting silicon nitride in at least the cap layer to form a blocking oxide layer, converting silicon to form a first gate oxide in the memory region, and converting silicon in the substrate to at least partially form at least one of the HV, I / O, and LV gate oxides in the logic region.

[0030] In one embodiment, the method may also include a step of performing at least one oxide deposition process step in the ALD chamber to simultaneously add thickness to the blocking oxide layer and the first gate oxide layer in the memory region.

[0031] In one embodiment, the pass transistor and the HV transistor can be of the same type, and the first gate oxide and the HV gate oxide are formed simultaneously and have substantially the same thickness.

[0032] In one embodiment, CT sublayers having different film compositions of silicon nitride Si, O, and N are produced in the CT sublayer, and in a customizable CT layer, process parameters of one or more silicon nitride deposition process steps can be adjusted such that the upper CT sublayer is the least oxygen-rich and the lower CT sublayer is the most oxygen-rich.

[0033] In one embodiment, the oxide deposition process, the radical oxidation process, and the silicon nitride deposition process are carried out in situ within an ALD chamber, and the process temperature is controlled to less than 650°C.

[0034] In one embodiment, the method may also include the step of forming a high-K metal gate (HKMG) on top of the blocking oxide of the SONOS transistor and the first gate oxide layer of the pass transistor. [Brief explanation of the drawing]

[0035] [Figure 1] Figure 1 is a block diagram showing a cross-sectional view of a non-volatile memory transistor or device based on SONOS. [Figure 2A] Figure 2A is a typical flowchart showing an embodiment of a method for manufacturing an oxide-nitride-oxide (ONO) stack in a SONOS-based non-volatile memory transistor according to an embodiment of the present disclosure. [Figure 2B] Figure 2B is a representative diagram showing an example of an atomic layer deposition (ALD) chamber or tool. [Figure 3A] Figure 3A is a representative cross-sectional view of the tunnel dielectric portion of a SONOS-based non-volatile memory transistor during manufacturing using the method shown in Figure 2A. [Figure 3B] Figure 3B is a representative cross-sectional view of the tunnel dielectric portion of a SONOS-based non-volatile memory transistor during manufacturing using the method shown in Figure 2A. [Figure 3C] Figure 3C is a representative cross-sectional view of the tunnel dielectric portion of a SONOS-based non-volatile memory transistor during manufacturing using the method shown in Figure 2A. [Figure 3D] Figure D is a representative cross-sectional view of the tunnel dielectric portion of a SONOS-based non-volatile memory transistor during manufacturing using the method shown in Figure 2A. [Figure 4A] Figure 4A is a representative cross-sectional view of the charge trapping dielectric portion of a SONOS-based non-volatile memory transistor during manufacturing using the method shown in Figure 2A. [Figure 4B] Figure 4B is a representative cross-sectional view of the charge trapping dielectric portion of a SONOS-based non-volatile memory transistor during manufacturing using the method shown in Figure 2A. [Figure 4C] Figure 4C is a representative cross-sectional view of the charge trapping dielectric portion of a SONOS-based non-volatile memory transistor during manufacturing using the method shown in Figure 2A. [Figure 4D] Figure 4D is a representative cross-sectional view of the charge trapping dielectric portion of a SONOS-based non-volatile memory transistor during manufacturing using the method shown in Figure 2A. [Figure 4E] Figure E is a representative cross-sectional view of the charge trapping dielectric portion of a SONOS-based non-volatile memory transistor during manufacturing using the method shown in Figure 2A. [Figure 5A] Figures 5A to 5D are representative cross-sectional views of the upper or blocking dielectric portion of a SONOS-based non-volatile memory transistor during manufacturing using the method shown in Figure 2A. [Figure 5B]Figure 5B is a typical cross-sectional view of the upper or blocking dielectric portion of a SONOS-based non-volatile memory transistor during manufacturing using the method shown in Figure 2A. [Figure 5C] Figure 5C is a representative diagram showing a cross-sectional view of the upper or blocking dielectric portion of a SONOS-based non-volatile memory transistor during manufacturing using the method shown in Figure 2A. [Figure 5D] Figure 5D is a representative diagram showing a cross-sectional view of the upper or blocking dielectric portion of a SONOS-based non-volatile memory transistor during manufacturing using the method shown in Figure 2A. [Figure 5E] Figure 5E is a typical cross-sectional view of a memory stack of a floating gate memory transistor including an ONO blocking dielectric stack according to an embodiment of the present disclosure. [Figure 6] Figure 6 is a block diagram showing a partial cross-sectional view of a non-volatile memory cell or device based on SONOS according to an embodiment of the present disclosure. [Figure 7] Figure 7 is a typical flowchart illustrating an embodiment of the integration of a SONOS-based memory transistor manufacturing method into a MOS transistor process flow according to the embodiments of this disclosure. [Figure 8A] Figure 8A is a representative diagram showing a partial cross-sectional view of a memory device based on SONOS using the method described in Figure 7. [Figure 8B] Figure 8B is a representative diagram showing a partial cross-sectional view of a memory device based on SONOS using the method described in Figure 7. [Figure 8C] Figure 8C is a representative diagram showing a partial cross-sectional view of a memory device based on SONOS using the method described in Figure 7. [Figure 8D] Figure 8D is a representative diagram showing a partial cross-sectional view of a memory device based on SONOS using the method described in Figure 7. [Figure 8E] Figure 8E is a representative diagram showing a partial cross-sectional view of a memory device based on SONOS using the method described in Figure 7. [Modes for carrying out the invention]

[0036] Description of the Embodiment Figure 1 is a block diagram showing a cross-sectional view of a SONOS-based NVM device. In one embodiment shown in Figure 1, the NVM transistor 100 is a SONOS-type charge-trapping NVM transistor, which, depending on the amount and polarity of the trapped charge it holds, can have a binary ("0" or "1") or multi-level analog value (e.g., 0 to 2) n -1) may be configured to store. Referring to Figure 1, the NVM cell 90 includes a memory gate (MG) stack 150 formed on a substrate 102. The NVM transistor 100 further includes a source / drain region 104 formed on or optionally in a shallow positive well (SPW (not shown)) on the substrate 102, on either side of the MG stack 150. The SPW may be enclosed in at least partially deep negative wells (DNW (not shown)). In one embodiment, the source / drain region 104 is connected by a channel region 116 located beneath the MG stack 150. The NVM transistor 100 includes a tunnel dielectric layer 106, a charge trapping layer 108, and a blocking dielectric layer 110 forming an ONO stack 120. In one embodiment, the charge trapping layer 108 may be multilayer and trap charges injected from the substrate 102 by FN tunneling or other mechanisms. T and I D The value may vary, at least partially, with the amount and polarity of the captured charge. In one embodiment, a high-K dielectric layer may form at least a portion of the blocking dielectric layer 110. A polysilicon (poly) or metal gate layer 112 is placed on top of the ONO stack 120, which can function as a control gate (CG) or memory gate. The NVM transistor 100 may also include a spacer 114 to provide electrical isolation from adjacent or other devices.

[0037] In various embodiments, the ONO stack 120 may be formed by a series of oxidation (thermal and / or radical and / or other), deposition (physical, chemical, etc.), etching, and / or cleaning process steps. These process steps may be carried out within a single process chamber and / or tool or multiple process chambers / tools. In some embodiments, current ONO processes limit the compositional variations that can be achieved in the thin layers of the ONO stack, which are essential in advanced technology nodes, for example, below 22 nm. Current ONO formation processes / tools may also suffer from limitations regarding the homogeneity of the film's stoichiometric composition and thickness, such as the thickness between wafers (WTW) and within wafers (WIW). This can negatively impact the quality and productivity of the ONO stack, limiting batch sizes to around 50 wafers and reducing the manufacturing plant's capacity for the relevant products. In advanced technology nodes, the thermal history of certain ONO processes may be too high, such as in-situ vapor generation (ISSG) oxidation, dry or wet furnace oxidation, and chemical vapor deposition of oxides and nitrides. The high thermal history associated with these processes can be so significant that it shifts the parameters of the baseline CMOS device, potentially requiring changes to the baseline FET model.

[0038] Figure 2A is a typical flowchart illustrating an embodiment of a method for manufacturing an oxide-nitride-oxide (ONO) stack in a SONOS-based non-volatile memory transistor, such as the NVM transistor in Figure 1, according to embodiments of the present disclosure. Referring to Figures 2A and 3A, the process can begin with a series of preliminary steps (step 202) including forming several isolation structures or shallow trench isolations (STIs) 301 within a wafer or substrate 302. In some embodiments, the preliminary steps may also include forming channels, such as channel 116 in Figure 1, source / drain 104 in Figure 1, and / or deep wells and / or wells. Various processes, including pad oxide formation, wet / dry etching or cleaning, tunnel mask application and dopant injection, may be carried out according to common practice in the art. It is understood that none of the above-described preliminary steps or other preliminary steps may be performed, or some may be performed, before the tunnel dielectric layer is formed. Subsequently, a pre-cleaning step is performed on the substrate surface 303 to remove pad oxide (if present) and / or other residual oxides, which may be a wet or dry process. In one embodiment, it can be a wet process using HF, followed by standard cleaning (SC1) and (SC2), which is highly selective for the material of the substrate 302.

[0039] Referring to Figures 2 and 3B, the ONO layer, e.g., the ONO stack 120 best shown in Figure 1, begins with the formation of the tunnel dielectric in step 204. The tunnel dielectric may be any material and may have any thickness suitable for maintaining a suitable barrier against leakage when the transistor is not biased, while allowing charge carriers to tunnel through the overlapping charge trapping layer under the application of a gate bias. In certain embodiments, the tunnel dielectric may be silicon dioxide, silicon nitride, e.g., oxynitrides, or a combination thereof, and may be deposited and / or grown by a thermal oxidation process in a furnace using ISSG or radical oxidation. As discussed earlier, forming very thin (e.g., less than 20 Å) tunnel dielectric layers with a homogeneous film stoichiometric composition and WTW / WIW thickness under a thermal history of less than 650°C using the processes described above is a challenge. In one embodiment that may be shown as a preferred embodiment, a multilayer silicon oxide tunnel dielectric layer 306 may be formed in a single in-situ atomic layer deposition (ALD) chamber capable of radical oxidation, thermal ALD, or plasma-enhanced ALD (PEALD) using either a batch or a single tool. In one embodiment, both the radical oxidation and ALD deposition processes may be carried out in the same ALD chamber. The sequential self-limiting surface reaction characteristics of ALD deposition and radical oxidation facilitate control of film thickness and homogeneity with atomic-scale precision at relatively low thermal histories (e.g., below 650°C). An example of an ALD chamber or tool 90 is shown with reference to Figure 2B. The ALD chamber 90 may be a batch-type tool in which multiple wafers (substrates) can be processed simultaneously. A precursor gas, such as HCD as a silicon source, may be introduced. Other reaction gases, such as ammonia or nitrous oxide, may be enhanced by a plasma source, such as inductively coupled plasma (ICP), before entering the chamber through a buffer nozzle with electrodes. Other reaction gases, such as H2 / O2, may be introduced by a cross-flow injector.The ALD chamber 90, best shown in Figure 2B, is merely one example of an ALD tool capable of radical oxidation, thermal ALD, and PEALD processes, and should not be interpreted as limiting. Depending on manufacturing requirements and other factors, other ALD tools capable of performing radical oxidation and ALD deposition as disclosed in this patent document may be used.

[0040] Referring to Figure 3B, in one embodiment, the tunnel dielectric sublayer 306a is formed by radical oxidation in an ALD chamber. The process involves flowing reaction gases of hydrogen (H2) and oxygen (O2) into the ALD chamber in a ratio of approximately 1:4 or other configurable ratios, without the formation of an external ignition event, such as a plasma. The H2 and O2 are reacted at a temperature in the range of approximately 300°C to 650°C and a pressure in the range of approximately 0.5 Torr to 10 Torr to form radicals, such as OH radicals, HO2 radicals, or O diradicals, at the interface of the substrate 302, and ultimately react and consume directly with the exposed surface portion of the silicon substrate 302. In one embodiment, an exemplary process / work table for carrying out radical oxidation in an ALD chamber is as follows: [Table 1]

[0041] The thickness, quality, and homogeneity of the formed tunnel dielectric sublayer 306a can be fine-tuned or adapted by modifying or adjusting the process gas sequence, flow rate, sequence duration, temperature, gas flow rate ratio, or other process parameters, depending on the requirements of the device being manufactured.

[0042] Referring to Figure 3C, the tunnel dielectric sublayer 306b can also be formed using a deposition workflow within the same or similar ALD chamber. In one embodiment, a chlorosilane, such as hexachlorodisilane Si2Cl6 (HCD), can be the precursor or silicon source gas. Hydrogen (H2) and oxygen (O2) gases are flowed into the ALD chamber in a ratio of approximately 1:4 without forming an external ignition event, such as a plasma. The H2 and O2 are reacted at a temperature in the range of approximately 300°C to 400°C and a pressure in the range of approximately 0.5 Torr to 10 Torr to form radicals, such as OH radicals, HO2 radicals, or O diradicals, which finally react with the HCD to form silicon oxide deposited on the surface of the substrate 302. During the same process, the generated radicals can also react directly with the silicon substrate 302 to form silicon oxide, as in the radical oxidation described above. In one embodiment, the following is a table of exemplary processes / work for carrying out silicon oxide deposition in an ALD chamber: [Table 2]

[0043] Similar to radical oxidation, the thickness, quality, and homogeneity of the formed tunnel dielectric sublayer 306b can be fine-tuned or adapted by modifying the process gas sequence, flow rate, duration, temperature, gas flow rate ratio, or other process parameters, depending on the requirements of the device being manufactured. In one embodiment, the radical oxidation process or ALD The tunnel dielectric layers 306a and 306b produced in the deposition process are denser and substantially less than the tunnel dielectric formed by wet oxidation techniques, even with reduced thickness. 3 It can be composed of hydrogen atoms per unit. The uniform thickness of the tunnel dielectric layer 306, especially around the STI corners, can reduce the heterogeneity of FN injection at the STI corners of the final SONOS device. D or V T This leads to lowering the sigma.

[0044] In this embodiment, multilayer tunnel dielectric sublayers 306a to 306d can be generated by individually repeating radical oxidation as described in Table 1 and ALD oxide deposition as described in Table 2, with or without modification of process parameters, by alternating between these, in combination, or in any designed sequence. Each sublayer can be formed by one or more radical oxidation process steps alone (e.g., Table 1 or a modification thereof), one or more ALD oxide deposition steps alone (e.g., Table 2 or a modification thereof), or a combination thereof, until it reaches a predetermined thickness, and each sublayer can be formed to a thickness of 2 Å or less. The final tunnel dielectric layer 306 is a laminate of multilayer tunnel dielectric sublayers 306a to 306d, as best shown in Figure 3D. By controlling and adjusting process parameters in the radical oxidation and ALD deposition stages, such as flow rate, reactants, duration, and temperature, a customizable tunnel dielectric layer 306 with desired thickness (WTW and WIW), homogeneity, interface conditions between the oxide and the silicon substrate, and stoichiometric composition of the film can be achieved. The tunnel dielectric layer 306 with four sublayers shown in Figure 3D is merely an example to illustrate the proposed ALD oxidation / deposition method and should not be interpreted as limiting. The tunnel dielectric layer 306 may have one or more sublayers, and each sublayer may have a different thickness, stoichiometric composition of the film, density, or other physical and chemical properties by fine-tuning the ALD radical oxidation and deposition process stages. In one embodiment, the tunnel dielectric layer 306 can be formed to a thickness in the approximate range of 5 Å to 30 Å.

[0045] Referring to Figure 2, in step 204, multilayer silicon nitride or silicon oxynitride (Si x O y N zA charge trapping layer can be formed in the same ALD chamber. In this embodiment, silicon nitride or silicon oxynitride may have various ratios of silicon (x), oxygen (y), and nitrogen (z) in the formed film. The charge trapping layer may be made of a suitable material and have a suitable thickness to accumulate charge and thereby change the threshold voltage of the subsequently formed SONOS device. Referring to Figure 4A, the charge trapping dielectric sublayer 308a is formed in the same or similar in-situ ALD chamber as the tunnel dielectric layer 306. In one embodiment, the process includes flowing a precursor gas HCD as a silicon source, ammonia (NH3) as a nitrogen source, and nitrous oxide (N2O) as an oxygen source. In other embodiments, other chlorosilane gases can be used as a silicon source, and other nitrogen or oxygen source gases can be used according to the practice of those skilled in the art. In yet another embodiment, for higher silicon nitride deposition rates and better homogeneity at lower temperatures, ammonia and nitrous oxide gases can be plasma-enhanced before introduction into the ALD chamber. In one embodiment, the silicon nitride ALD deposition process is carried out at a temperature below 650°C, which is lower than most thermal and chemical vapor deposition processes. In one embodiment, a silicon nitride layer up to 2 Å can be formed in the ALD chamber. The following is a table of exemplary processes / operations for carrying out silicon nitride deposition in the ALD chamber: [Table 3]

[0046] Similar to the silicon oxide ALD process described above, a customizable charge-trapping dielectric sublayer 308a can be produced by adjusting its thickness, homogeneity, and the ratio of oxygen, nitrogen, and / or silicon in the formed silicon nitride. In one embodiment, the silicon nitride ALD process may have little effect on the already formed tunnel dielectric layer 306. Referring to Figure 4B, another charge-trapping dielectric sublayer 308b may be formed on the charge-trapping dielectric sublayer 308a. In one embodiment, the charge-trapping dielectric sublayer 308b may be formed in the same ALD chamber using the process parameters listed in Table 3, or modified process parameters. For example, increasing the flow rate and / or flow time of N2O gas can produce an oxygen-rich nitride layer, or adjusting, increasing, or decreasing the HCD gas and ammonia gas can produce silicon-rich and nitrogen-rich nitride layers, respectively. Referring to Figure 4C, additional charge-trapping dielectric sublayers 308c may be formed on charge-trapping dielectric sublayer 308b using an ALD deposition process similar to those described in Table 3, with or without modification of process parameters. In one embodiment, charge-trapping dielectric sublayers 308a to 308c can collectively form a charge-trapping dielectric layer 308 for a finished SONOS device. It should be understood that the three-layer charge-trapping dielectric layer 308 shown in Figure 4C is merely an example to illustrate the proposed silicon nitride ALD deposition and should not be interpreted as limiting. The charge-trapping dielectric layer 308 may have one or more sublayers, and each sublayer may have different thicknesses, film compositions of Si, O, and N in silicon nitride, or other physical and chemical properties by fine-tuning the ALD deposition process. In one embodiment, the charge trapping dielectric layer 308 can be a multilayer silicon nitride with an oxygen content gradient increasing from top to bottom, where the upper sublayer 308c is the silicon nitride sublayer with the least oxygen, while the lower sublayer 308a contains the most oxygen.

[0047] As used in this application, the terms “high in oxygen” and “high in silicon” refer to stoichiometric silicon nitride having the composition (Si3N4) and a refractive index of approximately 2.0, as commonly used in the art. Therefore, “high in oxygen” silicon nitride involves a shift from stoichiometric silicon nitride (sometimes referred to as silicon nitride or oxynitride (oxygen-containing silicon nitride)) towards higher mass percentages of silicon and oxygen (i.e., a decrease in nitrogen). Consequently, oxygen-rich silicon nitride or oxynitride films are closer to silicon dioxide, and their RI decreases towards 1.45 RI for pure silicon dioxide. Similarly, films described in this application as “high in silicon” involve a shift from stoichiometric silicon nitride towards higher mass percentages of silicon and have less oxygen than “high in oxygen” films. Consequently, silicon-rich silicon nitride films are closer to silicon, and their RI increases towards 3.5 RI for pure silicon. Throughout this document, "silicon nitride" and "silicon oxynitride" are used interchangeably, and the formed film may or may not contain oxygen.

[0048] In one embodiment, it may be desirable to produce a charge-trapping dielectric film in which most of the charge trapping is distributed at the top of the film. This can minimize charge leakage through the underlying tunnel dielectric layer. For example, using the charge-trapping dielectric layer 308 in Figure 4C, the process parameters during ALD deposition of the charge-trapping dielectric sublayer 308a can be configured to produce an oxygen-rich, nitrogen-poor silicon nitride film. By adjusting the process parameters and using the same ALD chamber, the charge-trapping dielectric sublayer 308c can be formed as an oxygen-poor, nitrogen-rich silicon nitride film containing most of the charge trapping throughout the multilayer charge-trapping dielectric layer 308.

[0049] In some embodiments, a silicon oxide thin film may be formed within a charge-trapping nitride layer, sandwiched between two nitride layers. Referring to Figure 4D, a dielectric thin film 330 may be formed on a lower charge-trapping dielectric layer 308'. The lower charge-trapping dielectric 308' is one or more sublayers of silicon nitride formed similarly to the charge-trapping dielectric layer 308. The dielectric thin film 330 can be silicon oxide or very oxygen-rich silicon nitride and may be formed using ALD radical oxidation or ALD oxide deposition, similar to the formation of the tunnel dielectric sublayers 306a-306d described above. The silicon oxide may be deposited directly on the lower charge-trapping dielectric layer 308', or radicals may convert some of the silicon nitride in the lower charge-trapping dielectric layer 308' into silicon oxide or very oxygen-rich nitride. In embodiments, the dielectric thin film may be a single layer or have multiple sublayers, each sublayer formed in the same ALD chamber using the ALD radical oxidation or oxide deposition process steps described above.

[0050] Referring to Figure 4E, the upper charge-trapping dielectric layer 332 is subsequently formed on the dielectric thin film 330, and the finished charge-trapping dielectric layer 350 becomes a (N·O·N) stack 350 of nitride (332)·oxide (330)·nitride (308') (lower), having a layer thickness in the approximate range of 50 Å to 150 Å. In one embodiment, the upper charge-trapping dielectric layer 332, like the lower charge-trapping dielectric layer 308', includes one or more sublayers (not shown) of silicon nitride formed, similar to the charge-trapping dielectric sublayers 308a to 308c. The upper charge-trapping dielectric layer 332 is also customizable, and each of the silicon nitride sublayers therein may have different thicknesses, Si, O, and N film ratios in the formed silicon nitride, or other physical and chemical properties, by fine-tuning the ALD deposition process. In one embodiment, the dielectric thin film 330 inherently reduces the possibility of electron charge accumulating at the boundary of the upper charge trapping layer 332 from tunneling into the lower charge trapping layer 308' during programming, resulting in lower leakage current than conventional memory devices. In one preferred embodiment, the nitride sublayer in the upper charge trapping dielectric layer 332 may be customized to be oxygen-poor to contain most of the charge trapping, while the nitride sublayer in the lower charge trapping dielectric layer 308' may be customized to be oxygen-rich.

[0051] Referring to Figure 2, in step 208, a blocking dielectric layer 310 is formed on the charge-trapping dielectric layer 308 or a non-non In one embodiment, blocking dielectric sublayers 310b-310c are formed into silicon oxide films with customizable thickness, homogeneity, and quality by modifying the process carried out in the ALD chamber by similar radical oxidation or ALD oxide deposition. As a result, the blocking dielectric layer 332 can be a single-layer or multi-layer silicon oxide having a total thickness in the approximate range of 10 Å to 100 Å. Referring to Figure 5C, the ONO stack layer 320 is then formed on at least a portion of the substrate 302, all within the same in-situ ALD tool. Referring to Figure 5D, in one embodiment, the ONO stack layer 320 can be patterned to form one or more ONO stacks 320' for a SONOS-based transistor, similar to the ONO stack 120 of the NVM transistor 100 in Figure 1. A mask can be formed on or overlaid on the ONO stack layer 320, and the ONO stack layer 320 is etched to form one or more ONO stacks 320' overlaid on the substrate 320. The manufacturing method can then proceed to the remaining process in step 210. Process steps such as source / drain formation, spacer formation, and memory gate formation are carried out according to the practices of those skilled in the art.It is understood that the process steps described above can be performed before, during, or after the formation of the ONO stack layer 320 (in steps 204-208) without departing from the principles of this disclosure.

[0052] In one alternative embodiment, referring to Figure 5E, instead of being an ONO stack of a SONOS-based transistor and instead being formed directly on the substrate 302, the ONO stack layer 320 may be formed as part of the memory stack layer 540 of a floating-gate transistor 550. In one embodiment, the ONO stack layer 320, which functions as a blocking dielectric layer of the floating-gate transistor 550 as a whole, is formed on the tunnel oxide layer 502 and the floating-gate layer 504. The tunnel oxide layer 502, which is primarily silicon oxide, and the floating-gate layer 504, which can be polycrystalline silicon, may be formed in the same ALD chamber as the ONO stack layer 320 or may be formed using other techniques practiced by those skilled in the art.

[0053] Referring to Figure 6, a portion of a SONOS-based non-volatile memory (NVM) device 600 formed on a single substrate 102 is shown. In one embodiment, the substrate 102 is divided into a memory area where memory cells 620 are located and a logic area where HV MOS 604, I / O MOS 606, and LV MOS 608 are located. In one embodiment, only a single device of each type (i.e., memory cell 620, HV MOS 604, I / O MOS 606, and LV MOS 608) is shown for illustrative purposes only. Multiple devices of each type and other semiconductor devices can be located within the SONOS-based NVM device 600 and can be formed simultaneously or sequentially. As best shown in Figure 6, the NVM transistor 100 may have a polysilicon (Poly) or high-K metal gate (HKMG) layer 634 superimposed on the ONO stack 320', which can function as a control gate (CG) or memory gate (MG) of the memory cell 620.

[0054] As best illustrated in Figure 6, in a two-transistor (2T) configuration, the memory cell 620 further includes a pass transistor or select transistor 602 positioned adjacent to the SONOS-based NVM transistor 100 (referred to as the memory transistor). The pass transistor 602 is, for example, a conventional MOSFET that shares a common substrate connection or internal node with the NVM transistor 100. In one embodiment, the pass transistor 602 includes a high-K metal gate or polysilicon select gate (collectively, "SG") 632 positioned on top of an oxide or high-K dielectric gate dielectric layer 612. The SG 632 is appropriately biased to open or close the channel beneath the pass transistor 602. In other embodiments, the memory cell 620 employs a one-transistor (1T) configuration and may have only the NVM transistor 100.

[0055] Referring to Figure 6, in the logic region, the HV MOS, I / O MOS, and LV MOS transistors 604, 606, and 608 are field-effect transistors (FETs) having a logic gate 632, which is either an HKMG gate or a polysilicon gate, formed on top of the HV gate oxide 614, I / O gate oxide 616, and LV gate oxide 618, respectively. In one embodiment, the HV gate oxide 614 is the thickest, followed by the I / O gate oxide 616, and then the LV gate oxide 618. In one embodiment, the pass transistor 602 in the memory region may have a similar or identical structure and dimensions to one of the HV MOS, I / O MOS, and LV MOS transistors 604, 606, and 608.

[0056] Figure 7 is a process flowchart showing the main manufacturing steps for integrating a SONOS or NVM transistor (in the memory region) into a baseline complementary metal-oxide-semiconductor (CMOS) process flow (in the logic region) according to one embodiment of the present disclosure. Referring to Figure 7, the process begins with several preliminary steps, including the formation of several isolation structures or shallow trench isolations (STIs), the formation of pad oxides, the formation of sources / drains, the formation of wells, and pre-cleaning of the substrate in step 702. The pad oxide 870 can be formed on the surface of the substrate 102 in both the memory region and the logic region. In one embodiment, the pad oxide 860 can be silicon dioxide (SiO2) having a thickness of about 10 nanometers (nm) to about 20 nm, and ALD Within the chamber, the pad oxide 870 may be formed using the radical oxidation or oxide deposition process described above, or other oxidation or deposition processes known in the art. It is understood that in some embodiments, the pad oxide 870 may not be necessary or may not be formed. The dopant is injected into the substrate 102 through the pad oxide 870 (if present) to form wells (deep or shallow), source / drain, or channels for one or more NVM transistors 100 and pass transistors 602 in the memory region, and for MOS transistors 604, 606, and 608 in the logic region. It is understood that one or more prior steps may be performed later in the manufacturing process without departing from the principles of the present disclosure.

[0057] Next, referring to Figures 7 and 8A, the surface of the substrate 102 in the memory region is cleaned or pre-cleaned, and several dielectric layers are formed in steps 704 and 706. Subsequently, in step 706, a mask is formed on or overlaid on the dielectric layers, and the dielectric layers are etched to form the NV gate stack in the memory region. Pre-cleaning can be a wet or dry process to remove pad oxide 870 on the substrate 102 (at least in the memory region).

[0058] Referring to Figures 7 and 8A, in step 704, the process for the dielectric or NV gate stack layer may begin with the formation of a tunnel dielectric layer 306 in the memory region and extend over the logic region where the MOS transistors 604, 606, and 608 are to be formed. In one embodiment, the tunnel dielectric layer 306 may be made of any material and may have a suitable thickness to maintain a suitable barrier against leakage when the multilevel NVM transistor 926 is not biased, while allowing charge carriers to tunnel through the overlapping charge trapping layer under the application of a gate bias. In preferred embodiments, as described above at least in Figures 2 and 3A-3D and their corresponding descriptions, the tunnel dielectric layer 306 may include one or more sublayers of silicon oxide formed by a radical oxidation or ALD oxide deposition process step in an ALD chamber, e.g., the ALD chamber 90 in Figure 2B. By controlling and modifying process parameters in the radical oxidation process and ALD deposition process, such as flow rate, reactants, duration, and temperature, a customizable tunnel dielectric layer 306 with desired thickness (WTW and WIW), homogeneity, interface conditions between the oxide and the silicon substrate, and stoichiometric composition of the film can be achieved.

[0059] Referring again to Figure 8A, in step 704, a charge trapping layer 308 or 350 is formed on or overlaid on the tunnel dielectric 306. In one embodiment, the charge trapping layer 308 or 350 may be a multilayer silicon nitride (one or more sublayers) formed by the ALD deposition process steps, as previously described in Figures 4A-4E and their respective descriptions. In one embodiment, as best shown in Figure 4E, the charge trapping layer can be a multilayer charge trapping layer 308 having at least one sublayer (e.g., 308a-308c best shown in Figure 4C), and by fine-tuning the ALD deposition process steps, each sublayer may have a different thickness, Si, O, N film ratio, or physical and chemical properties.

[0060] In another embodiment, the charge-trapping dielectric layer 350 is a multi-layer N·O·N layer comprising at least a lower charge-trapping layer 308' that is physically closer to the tunnel dielectric layer 306, and an upper charge-trapping layer 332 that has one or more nitride sublayers and is oxygen-poor compared to the oxygen-rich lower charge-trapping layer 308', and contains most of the charge traps distributed within the multilayer charge-trapping layer 350. As best shown in Figure 4E, there may be an oxide thin film formed between the upper charge-trapping dielectric layer 332 and the lower charge-trapping dielectric layer 308', which during programming essentially reduces the possibility of electron charges accumulating at the boundary of the upper charge-trapping layer 332 from tunneling into the lower charge-trapping layer 308', resulting in lower leakage current than conventional memory devices. In one embodiment, all sublayers of the charge-trapping dielectric layer 308 or 350 may be formed in the same ALD chamber (in situ) by radical oxidation, oxide deposition, or nitride deposition process steps.

[0061] Referring again to Figures 7 and 8A, in step 706, the cap layer 802 is formed on or superimposed on the charge trapping layer 308 or 350. In some embodiments as shown, the cap layer 802 is a multilayer cap layer comprising at least an under or first cap layer 802a superimposed on the charge trapping layer 308 or 350 and a second cap layer 802b superimposed on the first cap layer 802a.

[0062] In one embodiment, the first cap layer 802a may include a high-temperature oxide (HTO), such as silicon oxide (SiO2), having a thickness of 2.0 nm to 4.0 nm, deposited using a low-pressure chemical vapor deposition (LPCVD) thermal oxidation process. In one embodiment, the second cap layer 802b may include a silicon nitride, silicon-rich silicon nitride, or silicon-rich silicon oxynitride layer having a thickness of 2.0 nm to 4.0 nm, formed by a CVD process using N2O / NH3 and DCS / NH3 gas mixtures. In other embodiments, the cap layer 802 may also be formed using radical oxidation or oxide or nitride deposition process steps within the ALD chamber, as described in the preceding paragraphs, for example, Tables 1-3 and their respective descriptions.

[0063] Referring further to Figures 7 and 8A, in step 706, the sacrificial oxide layer 806 is formed on or overlaid on the cap layer 802. In one embodiment, the sacrificial oxide layer 806 may include a high-temperature oxide (HTO) layer grown by a thermal oxidation process or radical oxidation and having a thickness of 2.0 nm to 4.0 nm. In other embodiments, the sacrificial oxide layer 806 may be formed using a radical oxidation or oxide deposition process step in the ALD chamber, as previously described.

[0064] Next, with further reference to Figures 7 and 8A, a patterned mask layer 850 is formed on or overlaid on the sacrificial oxide layer 806, and with reference to Figure 8B, the sacrificial oxide layer 806, the cap layer 802 and the charge trapping layer 308 or 350, and the tunnel dielectric layer 306 are etched or patterned to form the NV gate stack 860. In one embodiment, the NV gate stack 860 may be positioned substantially over the channel of the NVM transistor 100 in the memory region. The etching or patterning process can further remove various dielectric layers of the NV gate stack 860 from the logic region (step 706). The patterned mask layer 850 may include a photoresist layer patterned using standard lithography techniques, and the NV gate stack 860 layer in the logic region may be etched or removed using a dry etching process that includes one or more additional steps stopping on the surface of the substrate 102 or on the unremoved pad oxide 870 (if present). In one embodiment, a well (not shown) may be formed in the logic region. Figure 8B is a representative diagram, illustrating that one or more NV gate stacks 860 may be formed in the memory area or other areas on the substrate 102 during the same patterning process stage.

[0065] Referring to Figures 7 and 8C, in a highly selective cleaning process (step 708), the sacrificial oxide layer 806 and the upper or substantially all of the second cap layer 802b within the multilayer cap layer 802 are removed from the NV gate stack 860. This cleaning process further removes any oxides, such as oxides in the tunnel dielectric layer 306 and / or pad oxides 870 remaining in the memory region or logic region beyond the NV gate stack 860, to prepare the substrate 102 for oxide formation.

[0066] Next, with reference to Figures 7 and 8D, in step 710, the blocking dielectric layer 310 for the NVM transistor 100 in the memory region, the gate oxide 612 for the pass transistor (if present for a 2T configuration), and the LV gate oxide layer 618, the I / O gate oxide layer 616, and the HV gate oxide layer 614 are formed. In one embodiment, an oxidation process is carried out to oxidize the remaining portions of the second cap layer 802b and / or the first cap layer 802a of the multilayer cap layer 802, and optionally a portion of the charge trapping dielectric layer 308 or 350, thereby forming the blocking dielectric layer 310 on top of the charge trapping dielectric layer 308 or 350. In one embodiment, the oxidation process is adapted to oxidize or consume the remaining portion of the first cap layer 802a or the second cap layer 802b, or optionally a portion of the charge trapping dielectric layer 308 or 350, in the memory region to form the blocking dielectric layer 310 and the gate oxide layer 612 of the pass transistor 602 (if present), while simultaneously oxidizing at least the portion of the substrate 102 on which the I / O MOS 606 or LV MOS 608 or HV MOS 604 is to be placed, in the logic region to form the gate oxide layer. In one embodiment, the oxidation process may include in-situ radical oxidation carried out in an ALD chamber, e.g., ALD chamber 90. The in-situ radical oxidation process may be similar to the ALD radical oxidation process steps described in Table 1, Figures 5A-5C and their corresponding descriptions, where one or more silicon oxide sublayers (e.g., 310a-310c, best shown in Figure 5b) are formed on the NVM transistor 100 in the memory region. In one embodiment, silicon oxide in the blocking dielectric layer 310 is formed by radicals that react with or ultimately convert the nitride or oxynitride on top of the capping dielectric layer 802 or optionally the charge trapping dielectric layer 308 or 350.In one embodiment, radicals generated during the in-situ ALD radical oxidation process step, such as OH radicals, HO2 radicals, or O diradicals, can simultaneously react with the silicon substrate 102 and consume them, forming one or more sublayers in the gate oxide 612 of the pass transistor in the memory region and in the gate oxide layers 612, 614, and 616 in the logic region. By modifying the process parameters of the in-situ ALD radical oxidation process step (e.g., Table 1), oxide sublayers of varying thicknesses, qualities, homogeneity, stoichiometric composition, or other chemical and physical properties can be produced in both the memory and logic regions. The radical oxidation process step can also be repeatedly and alternately modified so that an ideal thickness T1 for the blocking dielectric layer 310, T2 for the gate oxide layer 612 of the pass transistor, and T3, T4, and T5 for the gate oxide layers 614, 616, and 618 of the HV MOS 604, I / O MOS 606, and LV MOS 608, respectively, are achieved. In one embodiment, T1 can be in the approximate range of 30-50 Å, T2 in the range of 50-150 Å, T3 in the range of 50-150 Å, T4 in the range of 50-150 Å, and T5 in the range of 10-30 Å.

[0067] Alternatively or additionally, in situ ALD oxide deposition (e.g., Table 2 or its modification) can be performed within the same ALD chamber to generate one or more oxide sublayers in at least one blocking dielectric layer 310 and gate oxides 612, 614, 616, 618. As previously described in Table 2, Figures 5A-5C, and their respective descriptions, radicals generated within the ALD chamber may react with a silicon source gas, e.g., HCD, or an oxynitride / nitride or silicon substrate to form one or more silicon oxide sublayers. In embodiments, the in situ ALD oxide deposition and radical oxidation process steps that can be performed within the same ALD chamber can be repeated, modified, alternated, and combined until predetermined thicknesses T1-T5 of the respective dielectric / oxide layers 310, 612, 614, 616, 618 are achieved. In alternative embodiments, the in situ ALD oxide deposition or radical oxidation process steps may not apply to all regions. A mask (not shown) can be applied to protect one or more regions from being affected by subsequent radical oxidation or ALD oxide deposition process steps in which the gate oxide layer therein is affected. In one embodiment, the gate oxide layer 618 of an LV MOS 608 in a logic region may be protected by a mask (not shown) to prevent further oxide from adding thickness in subsequent in-situ ALD process steps (radical oxidation, deposition, or both) after a thickness T5 has been achieved. In other examples, the gate oxide layer 612 of a pass transistor 602 and the gate oxide layer 614 of an HV MOS 604 may be substantially the same and formed simultaneously or sequentially in the same process steps.The primary objective and advantage of fabricating the blocking dielectric layer 310 of an NVM transistor and one or more gate oxides of MOS transistors 602, 604, 606, 608 in situ ALD process steps (both radical oxidation and oxide deposition) within the same or similar ALD chamber / tool ​​is that the oxide sublayers and layers are formed at relatively low thermal histories (below 650°C), thus not adversely impacting the CMOS process flow in the logic region. Another objective and advantage is that both the N·O·N stack 320 of the NVM transistor 100 and the gate oxide layers 612, 614, 616, 618 are highly customizable by changing the configuration of the in situ process steps in the ALD chamber or tool. In one embodiment, the ONO layer of the SONOS transistor and the gate oxide layers 612, 614, 616, 618 of all FETs are all formed in situ within the same ALD chamber or tool.

[0068] In one alternative embodiment, at least portions of the gate oxide layers 612, 614, 616, and 618 may be formed using RTO, furnace oxidation, radical oxidation, CVD, in-situ vapor generation (ISSG), or a combination thereof. These oxidation process steps can be carried out within separate process tools.

[0069] In this embodiment, the LV gate oxide layer 618, the I / O gate oxide layer 616, and the HV gate oxide layer 614 may be formed simultaneously or individually. Subsequently, in step 710, the LV gate oxide layer 618, the I / O gate oxide layer 616, and the HV gate oxide layer 614 are patterned, as best shown in Figure 8E. Although only one of each type of transistor (SONOS NVM, PATH, HV MOS, I / O MOS, LV MOS transistor) is shown, it will be understood that multiple transistors of each type (not shown in Figure 8D) may be manufactured simultaneously or subsequently using the methods and process steps described above.

[0070] Finally, a standard or baseline CMOS process flow follows, substantially completing the manufacturing of the front-end device (stage 712). The process flow may include the formation of HKMGs, spacers, channels, source / drain regions, etc., for each type of transistor. In one embodiment, the completed NVM transistor 100 and HV, I / O, or LV MOS transistors 604, 606, 608 may be configured to form an embodiment of an NVM cell 620. In an alternative embodiment, the pass transistor 602 may have a different structure from the HV, I / O, or LV MOS transistors 604, 606, 608, e.g., gate oxide thickness. In another alternative embodiment, the memory cell 620 may contain only the NVM transistor 100 in a single-transistor configuration.

[0071] Accordingly, embodiments of SONOS-based non-volatile memory and manufacturing methods, including a customizable O·N·O stack, and methods for integrating them into a baseline CMOS process flow are provided. While this disclosure has been described with reference to certain exemplary embodiments, it is evident that various modifications and changes can be made to those embodiments without departing from the broader spirit and scope of this disclosure. Accordingly, the specification and drawings should be considered illustrative rather than limiting.

[0072] The disclosure summary is provided in accordance with 37 CFR §1.72(b), which requires a summary that enables the reader to quickly confirm the nature of one or more embodiments of the technical disclosure. It is submitted with the understanding that it is not to be used to interpret or limit the scope and meaning of the claims. Furthermore, as can be seen in the prior detailed description, various features are grouped into a single embodiment in order to streamline the disclosure. This method of disclosure should not be interpreted as reflecting an intention that the claimed embodiments require more features than are expressly described in each claim. Rather, as reflected in the following claims, the subject matter of the invention lies in fewer features than all the features of a single disclosed embodiment combined. Accordingly, the following claims are incorporated into the detailed description, and each claim stands independently as a separate embodiment.

[0073] Any reference to an embodiment or embodiment in the description means that a particular mechanism, structure, or feature described in relation to that embodiment is included in at least one embodiment of the circuit or method. The phrase "an embodiment" appearing in various parts of the specification does not necessarily refer to the same embodiment.

Claims

1. A method for manufacturing semiconductor devices, Dividing the substrate into a first region and a second region, In the first region, a customizable oxide / nitride / oxide (ONO) stack is formed. Including, the formation is A tunnel dielectric layer is formed on the substrate by performing at least one of a first radical oxidation and a first oxide deposition process step within an atomic layer deposition (ALD) tool. Multiple silicon nitride deposition process steps are carried out within the ALD tool to form a multilayer charge trapping (CT) layer. The plurality of silicon nitride deposition process steps include, The process parameters of the first silicon nitride deposition process step of the plurality of silicon nitride deposition process steps are determined to form the first CT sublayer. Modifying at least one of the aforementioned process parameters, The process includes carrying out a second silicon nitride deposition step to form a second CT sublayer on top of the first CT sublayer, and Performing at least one of a second radical oxidation and a second oxide deposition process step within the ALD tool to form a blocking dielectric layer on top of the multilayer CT layer in the first region. Includes, The method wherein the multilayer CT layer comprises at least three CT sublayers, and the process parameters of a plurality of silicon nitride deposition process steps are modified such that, in the multilayer CT layer, the upper CT sublayer adjacent to the blocking dielectric layer is the least oxygen-rich, and the lower CT sublayer adjacent to the tunnel dielectric layer is the most oxygen-rich.

2. The method according to claim 1, wherein the silicon nitride deposited in the plurality of silicon nitride deposition process steps includes oxygen-containing silicon oxynitride.

3. The method according to claim 1, wherein the customizable ONO stack formation process step is performed in situ and within the same ALD tool.

4. The method according to claim 1, wherein the silicon nitride film composition of silicon, oxygen, and nitrogen in the first CT sublayer and the second CT sublayer are different.

5. The method according to claim 1, wherein the first CT sublayer is silicon nitride containing a large amount of oxygen, and therefore has virtually no charge trapping, and the second CT sublayer is silicon nitride with poor oxygen, and therefore has substantially dense charge trapping.

6. The method according to claim 5, further comprising carrying out a plurality of third silicon nitride deposition process steps to form a plurality of third CT sublayers positioned between the first CT sublayer and the second CT sublayer, wherein the process parameters of the plurality of third silicon nitride deposition process steps are adjusted such that the oxygen content level of the plurality of third CT sublayers is between the oxygen content level of the first CT sublayer and the second CT sublayer.

7. The method according to claim 5, further comprising performing at least one of a third radical oxidation and a third oxide deposition process step within the ALD tool to form an oxide thin film superimposed on and below the first CT sublayer, wherein the oxide thin film is formed to reduce the electron charge accumulating at the boundary of the second CT sublayer from tunneling into the first CT sublayer.

8. The process parameters of the first and second radical oxidation process steps are: O 2 / H 2 Types of reaction gases containing gases, Flow rate of reaction gas to ALD tool, Reaction time for each reaction gas, The sequence of reaction gases entering the ALD tool, and The number of repetitions and repeating sequences. The method according to claim 1, wherein the process parameter is configured to control at least one of the thickness, density, and quality of the oxide formed in the tunnel dielectric layer.

9. The process parameters of the first and second oxide deposition process steps are: Types of silicon source precursor gases containing hexachlorodisilane (HCD), O 2 / H 2 Types of reaction gases containing gases, Flow rates of reaction gas and silicon source precursor gas, The reaction time for each reaction gas and silicon source precursor gas, and Sequence of reaction gases and silicon source precursor gases entering the ALD tool The method according to claim 1, wherein the process parameter is configured to control at least one of the thickness, density, and quality of the oxide formed in the blocking dielectric layer.

10. The process parameters of the first and second silicon nitride deposition process steps are: Types of silicon source precursor gases containing hexachlorodisilane (HCD), NH 3 / N 2 Types of reaction gases containing O gas, Flow rates of reaction gas and silicon source precursor gas, and Reaction time for each reaction gas and silicon source precursor gas, Sequence of reaction gases and silicon source precursor gases entering the ALD tool, and The number of repetitions and repeating sequences. The method according to claim 1, including the method described in claim 1.

11. The method according to claim 1, wherein at least one of the plurality of silicon nitride deposition process steps is plasma-enhanced.

12. The first radical oxidation and the first oxide deposition process steps are repeated individually, alternately, or in combination thereof to form a tunnel dielectric layer, and The second radical oxidation and the second oxide deposition process steps are repeated individually, alternately, or in combination thereof to form a blocking dielectric layer. The method according to claim 1, wherein the process parameters of the first and second radical oxidation process steps and the first and second oxide deposition process steps are adjusted between iterations of the process steps to customize the tunnel dielectric layer and the blocking dielectric layer.

13. The method according to claim 1, further comprising the step of forming a high-voltage (HV) gate oxide layer, an input / output (I / O) gate oxide layer, and a low-voltage (LV) gate oxide layer in a second region of the substrate, wherein at least one of the HV, I / O, and LV gate oxide layers is formed simultaneously with a blocking dielectric layer of a customizable O-N-O layer in the first region by at least one of the second radical oxidation and second oxide deposition process steps.

14. A method for manufacturing a memory device, Forming tunnel oxide layers in the memory and logic regions of the substrate. A customizable charge-trapping (CT) layer and a capping layer are formed on top of the tunnel oxide layer, the customizable CT layer comprising a plurality of CT sublayers, and each CT sublayer being formed by one or more silicon nitride deposition process steps carried out in an atomic layer deposition (ALD) chamber. The tunnel oxide layer, the customizable CT layer, and the cap layer are patterned to form a memory stack in the memory region, while the tunnel oxide layer, the customizable CT layer, and the cap layer are removed in the logic region, and Performing at least one radical oxidation process step within the ALD chamber, simultaneously converting at least the silicon nitride in the cap layer to form a blocking oxide layer on top of the customizable CT layer, and converting the silicon in the substrate to form a first gate oxide layer in the logic region. Includes, The process parameters of the one or more silicon nitride deposition process steps are: Types of silicon source precursor gases containing hexachlorodisilane (HCD), NH 3 / N 2 Types of reaction gases containing O gas, Flow rates of reaction gas and silicon source precursor gas, The reaction time for each reaction gas and silicon source precursor gas, and Sequence of reaction gas and silicon source precursor gas entering the ALD chamber The method, including the method described above.

15. The method according to claim 14, further comprising performing at least one oxide deposition process step within the ALD chamber to simultaneously add thickness to the blocking oxide layer and the first gate oxide layer in the logic region.

16. The method according to claim 14, wherein process parameters of one or more silicon nitride deposition process steps are adjusted to produce a CT sublayer having at least one of different thicknesses, densities, and film compositions of silicon nitride Si, O, and N in the CT sublayer.

17. A method for manufacturing a memory device based on semiconductor oxide nitride oxide semiconductor (SONOS), comprising forming a memory cell including a SONOS transistor and a pass transistor in a memory region of a substrate, wherein the formation is Forming tunnel oxide layers in the memory and logic regions of the substrate. A customizable charge-trapping (CT) layer and a capping layer are formed on top of the tunnel oxide layer, the customizable CT layer comprising at least three CT sublayers, each CT sublayer being formed by one or more silicon nitride deposition process steps performed in an atomic layer deposition (ALD) chamber, the process parameters of the one or more silicon nitride deposition process steps being modified such that, in the customizable CT layer, the upper CT sublayer of the at least three CT sublayers is the least oxygen-poor, and the lower CT sublayer adjacent to the tunnel oxide layer is the most oxygen-rich. The tunnel oxide layer, the customizable CT layer, and the cap layer are patterned to form a memory stack in the memory region, while the tunnel oxide layer, the customizable CT layer, and the cap layer are removed in the logic region, and A blocking oxide layer is formed on top of the customizable CT layer, and the first gate oxide of the pass transistor in the memory region is formed. including, and The HV gate oxide layer of a high-voltage (HV) transistor, the I / O gate oxide layer of an input / output (I / O) transistor, and the LV gate oxide layer of a low-voltage (LV) transistor are formed in the logic region, and at least one of the HV, I / O, and LV gate oxides is at least partially formed by performing at least one radical oxidation process step in the ALD chamber, simultaneously converting silicon nitride in at least the cap layer to form a blocking oxide layer, converting silicon to form a first gate oxide in the memory region, and converting silicon in the substrate to at least partially form at least one of the HV, I / O, and LV gate oxides in the logic region. The method, including the method described above.

18. The method according to claim 17, further comprising performing at least one oxide deposition process step within the ALD chamber to simultaneously add thickness to the blocking oxide layer and the first gate oxide layer in the memory region.

19. The method according to claim 17, wherein the pass transistor and the HV transistor are of the same type, the first gate oxide and the HV gate oxide are formed simultaneously and have approximately the same thickness.

20. The method according to claim 17, wherein a CT sublayer having different film compositions of silicon nitride Si, O, and N in the CT sublayer is generated, and process parameters of one or more silicon nitride deposition process steps are adjusted such that in the customizable CT layer, the upper CT sublayer is the least oxygen-rich and the lower CT sublayer is the most oxygen-rich.

21. The method according to claim 18, wherein the oxide deposition process step, the radical oxidation process step, and the silicon nitride deposition process step are carried out in situ within the ALD chamber, and the process temperature is controlled to be less than 650°C.

22. The method according to claim 17, further comprising forming a high-K metal gate (HKMG) on top of the blocking oxide of the SONOS transistor and the first gate oxide layer of the pass transistor.

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