Device chip verification method

Abstract

To provide a verification method of a device chip that can avoid sacrificing good device chips.SOLUTION: A verification method of a device chip includes a preparation step of preparing a wafer having a plurality of devices formed on the surface of the wafer, which are divided by planned dividing lines, and whose electrical characteristics distinguish good devices and defective devices, a dividing step of dividing the wafer into individual device chips along the planned dividing lines, a defective product collection step of collecting a defective device chip, and a verification step of verifying the physical characteristics of the recovered defective device chip.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The present invention relates to a method for verifying device chips obtained by dividing a wafer.

Background Art

[0002] A wafer on which a plurality of devices such as ICs and LSIs are partitioned by a dividing line and formed on the surface is divided into individual device chips by a cutting device or a laser processing device, and is used in electric devices such as mobile phones and personal computers.

[0003] In recent years, with the miniaturization and thinning of electric devices, miniaturization and thinning are also required for device chips. When a wafer is processed using the above cutting device, laser device, etc., processing distortion may be formed in the wafer. If this processing distortion remains in the device chips obtained by dividing the wafer, the physical properties of the device chips will deteriorate, and there is a problem that the reliability of the electric device employing this device chip will decrease.

[0004] In order to address the above problems, before the device chips are incorporated into electric devices such as smartphones, physical properties such as flexural strength and impact strength are verified (see, for example, Patent Documents 1 and 2), and countermeasures are taken to prevent device chips divided from wafers containing device chips with problems in these physical properties from being adopted in products.

Prior Art Documents

Patent Documents

[0007] However, the verification method described above is uneconomical because it involves sacrificing multiple good device chips that are usable as products.

[0008] This invention has been made in view of the above facts, and its main technical problem is to provide a device chip verification method that can avoid sacrificing good device chips. [Means for solving the problem]

[0009] To solve the main technical problems mentioned above, the present invention provides a method for verifying a device chip, comprising: a preparation step of preparing a wafer on which multiple devices are formed on the surface, partitioned by division lines, and in which devices with good electrical characteristics are distinguished from devices with defects; a division step of dividing the wafer into individual device chips along the division lines; a defective product recovery step of recovering the defective device chips; and a verification step of verifying the physical characteristics of the recovered defective device chips. The process also includes a determination step based on the results of the verification step to determine whether or not to send a device chip with good electrical characteristics to a subsequent process, wherein the physical characteristics are those identified by verifying the defective device chip, such as bending strength, the state of chipping on the outer surface or back surface, the state of cracks on the surface or back surface, finished thickness, dimensional variation, warping, and drop strength, or a combination thereof. A method for verifying device chips is provided.

[0010] ApplicableThe wafer is preferably positioned in an opening in a frame having an opening capable of housing the wafer, and is integrally formed by a dicing tape. The dicing process may be any of the following: dicing with a cutting blade, dicing with a laser beam, dicing with plasma, dicing by pre-dicing, or dicing by SDBG (Stealth Dicing Before Grinding). [Effects of the Invention]

[0011] The present invention provides a method for verifying device chips, comprising: a preparation step of preparing a wafer on which multiple devices are formed on the surface, partitioned by division lines, and in which devices with good electrical characteristics are distinguished from devices with defects; a division step of dividing the wafer into individual device chips along the division lines; a defective product recovery step of recovering the defective device chips; and a verification step of verifying the physical characteristics of the recovered defective device chips. The process also includes a determination step based on the results of the verification step to determine whether or not to send a device chip with good electrical characteristics to a subsequent process, wherein the physical characteristics are those identified by verifying the defective device chip, such as bending strength, the state of chipping on the outer surface or back surface, the state of cracks on the surface or back surface, finished thickness, dimensional variation, warping, and drop strength, or a combination thereof. Therefore, even when verifying the physical properties such as bending strength and impact strength of device chips separated from a wafer before they are incorporated into electrical devices such as smartphones, it is possible to avoid sacrificing good device chips, thus resolving the problem of uneconomical practices. [Brief explanation of the drawing]

[0012] [Figure 1] This is a perspective view showing an embodiment of the preparation process. [Figure 2] This is a perspective view showing how the division process is carried out. [Figure 3] This is a perspective view of a pickup device suitable for implementing a defective product recovery process. [Figure 4] This is a perspective view showing the state after defective device chips have been recovered from the wafer. [Figure 5] This is a perspective view showing how the verification process is carried out. [Modes for carrying out the invention]

[0013] Hereinafter, embodiments relating to a verification method for a device chip configured according to the present invention will be described in detail with reference to the attached drawings.

[0014] In carrying out the device chip verification method of this embodiment, first, a preparation step is performed to prepare wafers in which devices with good electrical characteristics and devices with defects are distinguished. Figure 1 shows an unprocessed wafer 10 that is the subject of the device chip verification method of this embodiment. The wafer 10 is a wafer on which a plurality of devices 12 are formed on its surface 10a, partitioned by division lines 14. The wafer 10 is housed in an opening Fa of an annular frame F having an opening Fa capable of accommodating the wafer 10, and is attached by dicing tape T to form an integral structure.

[0015] An electrical characteristics test is performed on the wafer 10 described above to distinguish between devices with good electrical characteristics and devices with defective electrical characteristics. In this electrical characteristics test, for example, as shown in Figure 1, the terminals 22, 22 of the prober 20 that performs the electrical characteristics test are positioned on the devices 12 formed on the surface 10a of the wafer 10, and the tips 22a, 22a of each terminal 22 are brought into contact with a plurality of electrodes of the device 12 (not shown) to perform a continuity test of the device 12 and check whether the electrical characteristics of the device 12 under inspection are normal or not. As a result, it is checked whether it is a good device 12a with normal electrical characteristics or a defective device 12b with abnormal electrical characteristics. The above electrical characteristics test is performed on all devices 12 formed on the surface 10a of the wafer 10, and as shown in the lower part of Figure 1, in order to distinguish between good devices 12a and defective devices 12b, the surface of defective devices 12b is marked with ink of a predetermined color (for example, red). The wafer 10 shown in the figure contains a total of six defective devices 12b with faulty electrical characteristics, while the rest are good devices 12a with normal electrical characteristics. This will be explained below. With this, the preparation step for preparing a wafer 10 in which good devices 12a and defective devices 12b are distinguished is completed. The present invention is not limited to marking the defective devices 12b, and the coordinates on the wafer 10 that can identify the location of the defective devices 12b may be stored in a control means (not shown).

[0016] Once the above-described preparation steps are completed, a splitting step is then performed to split the devices 12 of the wafer 10 into individual device chips along the planned splitting line 14. When performing this splitting step, it is possible to select from various splitting methods, but in this embodiment, the wafer 10 prepared in the above-described preparation steps is transported to the cutting device 30 (only a portion is shown) shown in Figure 2, and the splitting step is performed.

[0017] The cutting device 30 includes a chuck table (not shown) that sucks and holds the wafer 10, and cutting means 31 that cuts the wafer 10 sucked and held by the chuck table. The chuck table is configured to be rotatable and includes X-axis feeding means (not shown) that feeds the chuck table in the X-axis direction indicated by the arrow X in the figure. The cutting means 31 includes a spindle housing 32 disposed in the Y-axis direction indicated by the arrow Y in the figure, a spindle 33 rotatably held by the spindle housing 32, and an annular cutting blade 34 held at the tip of the spindle 33, and further includes Y-axis feeding means (not shown) that index-feeds the cutting blade 34 in the Y-axis direction. The spindle 33 is rotationally driven by a spindle motor (not shown). At the tip of the spindle housing 32, a blade cover 35 that covers the spindle 33 is disposed. The blade cover 35 is provided with a cutting water inlet 36 for introducing cutting water, and a cutting water injection nozzle 37 for injecting the cutting water introduced from the cutting water inlet 36 to the location cut by the cutting blade 34.

[0018] In carrying out the splitting process, first, the wafer 10 is placed on the chuck table of the cutting device 30 with its surface 10a facing upwards and held in place by suction. An alignment means (not shown) is used to align the predetermined splitting line 14 of the wafer 10 in the X-axis direction and to align it with the cutting blade 34. Next, the cutting blade 34 is rotated at high speed in the direction indicated by arrow R1 and positioned on the predetermined splitting line 14 aligned in the X-axis direction. A cut is made from the surface 10a side in the Z-axis direction indicated by arrow Z, and the chuck table is machine-feeded in the X-axis direction to form a splitting groove 100 that divides the wafer 10. Furthermore, the Y-axis feed means is activated to index and feed the cutting blade 34 of the cutting means 31 onto an unprocessed splitting line 14 adjacent in the Y-axis direction to the splitting line 14 in which the splitting groove 100 has been formed, and a splitting groove 100 is formed in the same manner as above. By repeating these steps, splitting grooves 100 are formed along all the splitting lines 14 along the X-axis direction. Next, the chuck table is rotated 90 degrees to align the direction perpendicular to the direction in which the division groove 100 was previously formed with the X-axis direction, and the above-described cutting process is performed on all the division lines 14 that have been newly aligned with the X-axis direction, thereby completing the division process by forming division grooves 100 along all the division lines 14 formed on the wafer 10. By performing the division process in this way, as shown in the lower part of Figure 2, the wafer 10 is divided along the division lines 14 into good device chips 12a' with normal electrical characteristics and defective device chips 12b' with poor electrical characteristics. After performing the above division process, the wafer is transported to the pickup device 40 shown in Figure 3 in order to perform a defective product recovery process to recover the defective device chips 12b'.

[0019] The pickup device 40 shown in Fig. 3 includes a base 41, a first table 42 disposed on the base 41 so as to be movable in the Y-axis direction indicated by arrow Y, a second table 43 disposed on the first table 42 so as to be movable in the X-axis direction indicated by arrow X orthogonal to the Y-axis direction, a detection means 47, a pickup means 48, and an expansion means 50. The base 41 is formed in a rectangular shape, and two guide rails 411 and 412 along the Y-axis direction are disposed in parallel with each other on the upper surfaces of both side portions in the X-axis direction thereof. On one of the guide rails 412 on the base 41, a guide groove 412a having a V-shaped cross section is formed on its upper surface.

[0020] On the lower surface of one side portion in the X-axis direction of the first table 42, a guided rail 42a that is slidably fitted into the guide groove 412a formed in the one guide rail 412 described above is provided. Also, on the upper surfaces of both side portions in the Y-axis direction of the first table 42, two guide rails 421 and 422 along the X-axis direction are disposed in parallel with each other. On one of the guide rails 422 on the first table 42, a guide groove 422a having a V-shaped cross section is formed on its upper surface.

[0021] The first table 42 configured as described above fits the guided rail 42a into the guide groove 412a formed in one of the guide rails 412 of the base 41, and places the lower surface of the other side portion on the other guide rail 411 of the base 41. On the base 41, a first moving means 44 for moving the first table 42 in the direction indicated by arrow Y along the guide rails 411 and 412 provided on the base 41 is disposed. This first moving means 44 includes a male screw rod 44a disposed in parallel with the guide rail 411 provided on the base 41, and a pulse motor 44b connected to one end of the male screw rod 44a for rotationally driving the male screw rod 44a, and the male screw rod 44a is screwed into a female screw block (not shown) provided on the lower surface of the first table 42.

[0022] As shown in Figure 3, the second table 43 is formed in a rectangular shape and has an expansion means 50 in the center for expanding the wafer 10 held by the frame F. A guided rail 43a is provided on the lower surface of one side of the second table 43 in the Y-axis direction, which slidably fits into a guide groove 422a formed in one of the guide rails 422 provided on the first table 42. The second table 43 configured in this way has the guided rail 43a fitted into the guide groove 422a formed in one of the guide rails 422 of the first table 42, and the lower surface of the other side is placed on the other guide rail 421 provided on the first table 42. A second moving means 45 is provided on the first table 42 for moving the second table 43 in the X-axis direction along the guide rails 421 and 422 provided on the first table 42. As shown in Figure 3, the second moving means 45 includes a male screw rod 45a (shown by a dashed line) arranged parallel to the other guide rail 421 provided on the first table 42, and a pulse motor 45b connected to the other end of the male screw rod 45a for rotational driving of the male screw rod 45a, and the male screw rod 45a is screwed into a female screw block 46 (shown by a dashed line) provided on the lower surface of the second table 43.

[0023] The expansion means 50 is a means of expanding the dicing tape T located between the wafer 10 held in the frame F and the frame F, thereby widening the spacing between adjacent good devices 12a and defective devices 12b, making it suitable for picking up individual device chips from the wafer 10. The expansion means 50 comprises a frame holding means 51 for holding the frame F that supports the wafer 10, and a tape expansion means 52 for expanding the dicing tape T attached to the frame F held in the frame holding means 51.

[0024] The frame holding means 51 includes a frame holding member 51a formed in an annular shape to hold the frame F described above, and a plurality of clamps 51b (four in the illustrated embodiment) arranged at equal intervals around the outer circumference of the frame holding member 51a as fixing means. The upper surface of the frame holding member 51a is formed flat, and the frame F placed on the upper surface of the frame holding member 51a is gripped by the plurality of clamps 51b and fixed to the upper surface of the frame holding member 51a.

[0025] Inside the frame holding member 51a, a cylindrical expansion drum 54 fixed to a circular base 53 is provided. The diameter of the expansion drum 54 is smaller than the inner diameter of the opening Fa of the frame F described above, and larger than the outer diameter of the wafer 10 attached to the dicing tape T, in a plan view. The tape expansion means 52 in the illustrated embodiment comprises a plurality (for example, four) of air cylinders 52a fixed to the circular base 53 and arranged around the expansion drum 54, and a piston rod 52b extending upward from the air cylinder 52a, with its upper end connected to the lower surface of the frame holding member 51a. Control air is supplied to the air cylinder 52a via a connecting passage (not shown), and the action of the air cylinder 52a causes the piston rod 52b to move up and down, thereby moving the frame holding means 51 in the vertical direction.

[0026] Furthermore, the expansion means 50 in the illustrated embodiment includes a rotating means 55 that rotates the frame holding means 51 together with the expansion drum 54, as shown in Figure 3. This rotating means 55 consists of a pulse motor 55a (shown by a dashed line) disposed on the lower side of the second table 43, a rotating pulley 55b mounted on the rotation shaft of the pulse motor 55a, and an endless belt 56 wound around the rotating pulley 552 and the circular base 53. By driving the pulse motor 55a of the rotating means 55 configured in this way, the expansion means 50 can be rotated by any angle θ in the direction indicated by arrow R2 via the rotating pulley 55b and the endless belt 56.

[0027] The pickup device 40 described above is equipped with position detection means (not shown) that detects the Y-axis position of the first table 42, the X-axis position of the second table 43, and the rotational angular position of the extension means 50. Based on the position information detected by the position detection means, the first moving means 44, the second moving means 45, and the rotating means 55 are activated to position the extension means 50 at any XY coordinate position and rotational angular position.

[0028] The detection means 47 is a means for detecting and distinguishing good device chips 12a' and defective device chips 12b' that have been individually separated from a wafer 10 which is supported via a dicing tape T on an annular frame F that is disposed on a base 41 and held by a frame holding means 51. The detection means 47 comprises an L-shaped support column 47a disposed on the base 41 and an imaging means 47b disposed at the tip of the support column 47a. The detection means 47 configured in this way images the good device chips 12a' and defective device chips 12b' that are supported on the annular frame F held by the frame holding means 51, and the imaged information is sent to a control means (not shown).

[0029] Furthermore, as shown in Figure 3, the pickup means 48 is disposed on the base 41 and is a means for sucking up and recovering the individually separated good device chips 12a' and defective device chips 12b' from the dicing tape T. This pickup means 48 comprises a swivel arm 48a disposed on the base 41 and a pickup collet 48b attached to the tip of the swivel arm 48a. The swivel arm 48a is swiveled in the direction indicated by arrow R3 by a driving means (not shown) and is also configured to move in the vertical direction indicated by arrow R4. A suction means (not shown) is connected to the pickup collet 48b, and once a defective device chip 12b' is sucked up by the tip of the pickup collet 48b, it can be stored in a storage container 49 prepared for storing the defective device chip 12b'.

[0030] The pickup device 40 has a configuration that is generally as described above, and the procedure for carrying out the defective product recovery process described above using this pickup device 40 will be explained below.

[0031] First, the annular frame F supporting the wafer 10, which has undergone the preparation and splitting processes described above, is placed on the frame holding member 51a and secured by the clamp 51b. At this time, the frame holding member 51a is raised by the action of the tape expansion means 52, and the upper surface of the frame holding member 51a on which the frame F is placed is positioned at approximately the same height as the upper edge of the expansion drum 54.

[0032] Next, the first moving means 44 and the second moving means 45 are activated to move the first table 42 in the Y-axis direction and adjust the position of the second table 43 in the X-axis direction, positioning the wafer 10 directly below the imaging means 47b of the detection means 47. Then, the tape expansion means 52 is activated to descend in the direction indicated by arrow R5, lowering the upper surface of the frame holding member 51a to a position lower than the upper edge of the expansion drum 54. As a result, the dicing tape T comes into contact with the upper edge of the expansion drum 54 and expands radially, widening the spacing between the good device chips 12a' and the defective device chips 12b'.

[0033] The good device chips 12a' and defective device chips 12b' described above are imaged by the imaging means 47b, and the defective device chips 12b' with poor electrical characteristics are identified based on the markers attached to them, their position information is obtained and stored in a control means (not shown). Next, based on this position information, the first moving means 44 and the second moving means 45 are activated, and the pick-up means 48 is activated to pick up only the defective device chips 12b', and as shown in Figure 4, all the defective device chips 12b' (6 in this embodiment) are stored in the storage container 49. Alternatively, the good device chips 12a' may also be collected and stored in a separate storage container at the same time as the defective device chips 12b' are stored. The defective product recovery process is not limited to the method described above. For example, the good device chip 12a' may be picked up and recovered from the wafer 10 first, and the defective device chip 12b' may be recovered by leaving it on the dicing tape T.

[0034] As described above, once the defective device chip 12b' with poor electrical characteristics has been recovered through the defective product recovery process, a verification process is carried out to verify the physical characteristics of the recovered defective device chip 12b'. The number of samples required to verify the physical characteristics of the device chips separated from the wafer 10 is determined in advance through experiments, etc., and varies depending on the type of wafer and device, but in this embodiment, it will be explained assuming that six samples are required.

[0035] The specific method for verifying the physical properties described above can be selected from various methods as needed, but typically, a three-point bending test is performed by applying a load to a defective device chip 12b' using a physical strength measuring device 60, which is simplified as shown in Figure 5, to verify the bending strength of the defective device chip 12b'. The physical strength measuring device 60 includes a pair of support bases 62 arranged with a predetermined gap S between them, and an indenter 64 that is inserted from above into the center of the gap S formed by the pair of support bases 62. The indenter 64 has a tapered cross-section, with its thickness decreasing towards the lower end tip, and the tip is formed in a rounded R shape. The device includes an indenter moving means (not shown) for moving the indenter 64 in the direction indicated by the arrow R6 in the figure, and a load measuring device (not shown) for measuring the load applied to the indenter 64.

[0036] In carrying out the verification process, the defective device chip 12b' is transported to the physical strength measuring device 60 described above and placed on a pair of support bases 62, as shown on the right side of Figure 5. At this time, whether the front or back surface of the defective device chip 12b' faces upward is determined based on the experimental conditions set in advance when establishing the flexural strength standard. Next, the indenter 64 is gradually lowered from above until it contacts the defective device chip 12b', and the load applied to the indenter 64 is measured using the load measuring device described above. When the indenter 64 is lowered further, it deforms and bends downward. Then, when the indenter 64 is lowered further and the pressing force exceeds a predetermined limit value, the defective device chip 12b' is destroyed. When the defective device chip 12b' is destroyed, the load measured by the load measuring device decreases sharply from its maximum value to zero. Therefore, the timing at which the defective device chip 12b' was destroyed and the maximum value of the load applied to the defective device chip 12b' are measured from the changes in the load measuring device. Based on the maximum value of the load, the distance of the gap S between the pair of support bases 62, the dimensions of the defective device chip 12b', etc., a bending stress value corresponding to the flexural strength of the defective device chip 12b' is calculated. Such physical strength measurements are performed on all six recovered defective device chips 12b', and a decision process is carried out to determine whether or not to send the good device chip 12a', which has normal electrical characteristics, to the next process based on the results of this verification process.

[0037] In this determination step, for example, the decision is made based on whether the flexural strength (bending stress value) of all six defective device chips 12b' meets a predetermined standard value. If the flexural strength of all defective device chips 12b' meets the standard value, it is determined that all good device chips 12a' with normal electrical characteristics may be sent to the next process. Furthermore, if, as a result of the above verification step, even one defective device chip 12b' does not meet the standard value for flexural strength, it is determined that even if the good device chips 12a' have normal electrical characteristics, a certain percentage of them do not meet the physical characteristic standards, and therefore they are not to be transported to the next process.

[0038] According to the embodiment described above, the verification of the physical characteristics of the device chips separated from wafer 10 is performed only on defective device chips 12b' that have been determined to have poor electrical characteristics. This avoids sacrificing good device chips 12a', thus resolving the problem of uneconomical practices. The number of defective device chips 12b' with poor electrical characteristics varies depending on the wafer being manufactured. If the number of defective device chips 12b' is less than the required number of samples (e.g., 6), the verification of the physical characteristics of the defective device chips 12b' with poor electrical characteristics is prioritized, and the physical characteristics of only the remaining number of good device chips 12a' are verified. Even in this case, the sacrificial number of good device chips 12a' is minimized.

[0039] In the embodiment described above, when performing the splitting process, the wafer 10 is transported to the cutting device 30 and the wafer 10 is split into individual device chips by the cutting blade 34. However, the present invention is not limited to this, and various splitting methods can be employed. For example, splitting may be performed by laser processing, by etching using plasma, by so-called pre-dicing in which a groove with a depth corresponding to the finished thickness is formed along the planned splitting line on the surface of the wafer with a cutting blade and the groove is exposed by grinding from the back side, or by so-called SDBG (Stealth Dicing Before Grinding) in which a modified layer is formed inside the wafer with a laser beam, and then the wafer is split into individual device chips while grinding from the back side.

[0040] Furthermore, while the above-described embodiment explained a case where the physical characteristic verified in the verification process is the flexural strength (bending stress value) of the device chip, the present invention is not limited thereto. For example, the verification may involve any one of the following, or a combination thereof: the state of chipping on the outer surface or back surface, the state of cracks on the surface or back surface, the finished thickness, dimensional variation, warping, or drop strength. [Explanation of symbols]

[0041] 10: Wafer 12: Devices 12a: Good quality devices 12a': Good quality device chip 12b: Defective device 12b': Defective device chip 14: Planned division line 20: Prova 22: Terminals 22a:Tip 30: Cutting equipment 31: Cutting means 32: Spindle Housing 33: Spindle 34: Cutting blade 35: Blade cover 36: Cutting water inlet 37: Cutting fluid spray nozzle 40: Pickup device 41: Base 411: Guide rail 412: Guide rail 412a: Guide groove 42: First Table 421: Guide rail 422: Guide rail 422a: Guide groove 43: The second table 44: The first means of transportation 44a: Male threaded rod 44b: Pulse motor 45: Second means of transportation 45a: Male threaded rod 45b: Pulse motor 47: Detection methods 47a: Support pillar 47b: Imaging means 48: Pickup method 48a: Swivel arm 48b: Pickup Collet 50: Expansion methods 51: Frame holding means 52: Tape expansion means 53: Circular base 54: Expansion Drum 55: Rotating means 55a: Pulse motor 55b: Rotating pulley 60:Physical strength measuring device 62: Support stand 64: Indenter F: Frame T: Dicing Tape

Claims

1. A method for verifying a device chip, A preparation step to prepare a wafer in which multiple devices are formed on the surface by partitioning lines, and in which devices with good electrical characteristics are distinguished from devices with defects, A splitting process in which the wafer is divided into individual device chips along the planned splitting line, A defective product recovery process for recovering the defective device chip, A verification process to verify the physical characteristics of the recovered defective device chips, Including, The verification process includes a determination step to determine whether or not to send a device chip with good electrical characteristics to the next process, based on the results of the verification process. A method for verifying a device chip, wherein the physical characteristics are those identified by verifying the defective device chip, such as bending strength, the state of chipping on the outer surface or back surface, the state of cracks on the surface or back surface, finished thickness, dimensional variation, warping, and drop strength, or a combination thereof.

2. The method for verifying a device chip according to claim 1, wherein the wafer is positioned in an opening of a frame having an opening capable of housing the wafer and is integrally formed by a dicing tape.

3. The method for verifying a device chip according to Claim 1, wherein the division step is any of division by a cutting blade, division by a laser beam, division by plasma, division by pre-dicing, or division by SDBG.

Images