Semiconductor memory device and method for manufacturing a semiconductor memory device

Abstract

To form a memory hole with a wide bottom diameter under a high etching rate condition.SOLUTION: A semiconductor storage device of an embodiment comprises a lower layer film, a first laminate which is arranged above the lower layer film and in which a plurality of first conductive layers and a plurality of first insulation layers are alternately laminated layer by layer, and a first pillar which reaches the lower layer film through the first laminate and in which each memory cell is formed in an intersection between the pillar and the plurality of first conductive layers. At least one first insulation layer located in a first region in a lamination direction of the first laminate among the plurality of first insulation layers except the first insulation layer of the lowest layer of the first laminate is thicker than the first insulation layer located in a second region of a higher layer than the first region of the first laminate among the plurality of first insulation layers. The first pillar has a first bowing shape in a height position of at least one first insulation layer of the first laminate, and has a second bowing shape in a height position of the first insulation layer of the second region of the first laminate.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor memory device and a method for manufacturing a semiconductor memory device.

Background Art

[0002] In the manufacturing process of a semiconductor memory device such as a 3D non-volatile memory, memory holes are formed that penetrate a stacked body in which a plurality of different insulating layers are alternately stacked. In recent years, the number of stacked insulating layers has increased, and it has been required to form memory holes with a wide bottom diameter under conditions of high etching rate.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0004] One embodiment aims to provide a semiconductor memory device and a method for manufacturing a semiconductor memory device that can form a memory hole with a wide bottom diameter under conditions of high etching rate.

Means for Solving the Problems

[0005] The semiconductor memory device of the embodiment includes a lower layer film, a first stacked body disposed above the lower layer film, in which a plurality of first conductive layers and a plurality of first insulating layers are alternately stacked one by one, and a first pillar that penetrates the first stacked body to reach the lower layer film and in which memory cells are respectively formed at intersections with the plurality of first conductive layers. The aforementioned plurality of first insulating layers are oxide layers,Of the plurality of first insulating layers, at least one first insulating layer located in a first region in the stacking direction of the first laminate, excluding the bottommost first insulating layer of the first laminate, is thicker than the first insulating layer located in a second region above the first region. The thickened first insulating layer is positioned in the first laminate at a height of 20% to 50% of the height of the top surface relative to the bottom surface of the first laminate, with the top surface being 100% of the height of the bottom surface of the first laminate. The first pillar is the first laminate , increased the thickness before Record number The first insulating layer has a first bowing shape at a height position, and the second bowing shape has a second bowing shape at a height position of the first insulating layer in the second region of the first laminate. [Brief explanation of the drawing]

[0006] [Figure 1] A diagram showing a schematic configuration example of a semiconductor memory device according to Embodiment 1. [Figure 2] A cross-sectional view along the Y direction showing an example of the configuration of a semiconductor memory device according to Embodiment 1. [Figure 3] A diagram illustrating, in order, a part of the procedure for manufacturing a semiconductor memory device according to Embodiment 1. [Figure 4] A diagram illustrating, in order, a part of the procedure for manufacturing a semiconductor memory device according to Embodiment 1. [Figure 5] A diagram illustrating, in order, a part of the procedure for manufacturing a semiconductor memory device according to Embodiment 1. [Figure 6] A diagram illustrating, in order, a part of the procedure for manufacturing a semiconductor memory device according to Embodiment 1. [Figure 7] A diagram illustrating, in order, a part of the procedure for manufacturing a semiconductor memory device according to Embodiment 1. [Figure 8] A diagram illustrating, in order, a part of the procedure for manufacturing a semiconductor memory device according to Embodiment 1. [Figure 9] A diagram illustrating, in order, a part of the procedure for manufacturing a semiconductor memory device according to Embodiment 1. [Figure 10] A diagram illustrating, in order, a part of the procedure for manufacturing a semiconductor memory device according to Embodiment 1. [Figure 11] A diagram illustrating, in order, a part of the procedure for manufacturing a semiconductor memory device according to Embodiment 1. [Figure 12] Schematic diagram showing the etching mechanism of the memory hole according to Embodiment 1 and the comparative example. [Figure 13] Cross-sectional view along the X direction showing an example of the configuration of the semiconductor memory device according to a modification of Embodiment 1. [Figure 14] Cross-sectional view along the X direction showing an example of the configuration of the semiconductor memory device according to Embodiment 2. [Figure 15] Cross-sectional view along the X direction showing an example of the configuration of the semiconductor memory device according to a modification of Embodiment 2. [Figure 16] Cross-sectional view along the X direction showing an example of the configuration of the semiconductor memory device according to Embodiment 3. [Figure 17] Cross-sectional view along the X direction showing an example of the configuration of the semiconductor memory device according to Modification 1 of Embodiment 3. [Figure 18] Cross-sectional view along the X direction showing an example of the configuration of the semiconductor memory device according to Modification 2 of Embodiment 3. [Figure 19] Cross-sectional view along the X direction showing an example of the configuration of the semiconductor memory device according to Modification 3 of Embodiment 3.

Mode for Carrying Out the Invention

[0007] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that the present invention is not limited by the following embodiments. Also, the constituent elements in the following embodiments include those that can be easily assumed by those skilled in the art or those that are substantially the same.

[0008] [Embodiment 1] Hereinafter, Embodiment 1 will be described in detail with reference to the drawings.

[0009] (Example of Configuration of Semiconductor Memory Device) FIG. 1 is a diagram showing a schematic configuration example of a semiconductor memory device 1 according to Embodiment 1. FIG. 1(a) is a cross-sectional view along the X direction of the semiconductor memory device 1, and FIG. 1(b) is a schematic plan view of the semiconductor memory device 1. However, in FIG. 1(a), hatching is omitted for the sake of clarity of the drawing.

[0010] In this specification, both the X and Y directions are directions along the orientation of the surface of the word line WL, which will be described later, and the X and Y directions are orthogonal to each other. Furthermore, the direction of electrical extraction of the word line WL, which will be described later, is defined as the direction along the X direction. Furthermore, the direction in which the bit line BL extends, which will be described later, is defined as the direction along the Y direction.

[0011] As shown in Figure 1, the semiconductor memory device 1 is configured, for example, in the shape of a roughly rectangular chip, and comprises, in order from the bottom of the paper, an electrode film 20, a source line SL, and a plurality of word lines WL. Above the plurality of word lines WL, the semiconductor memory device 1 also includes peripheral circuits CBA provided on the semiconductor substrate SB. In the description of the semiconductor memory device 1, the side on which the semiconductor substrate SB is placed will be referred to as the upper side of the semiconductor memory device 1.

[0012] A source wire SL is placed on the electrode film 20 via an insulating layer 60. Multiple plugs PG are arranged in the insulating layer 60, and electrical conductivity is maintained between the source wire SL and the electrode film 20 via the plugs PG. As a result, a source potential can be applied to the source wire SL from outside the semiconductor memory device 1 via the electrode film 20 and the plugs PG.

[0013] Multiple word lines WL are stacked on the source line SL. In the semiconductor memory device 1, the region where the multiple word lines WL are arranged corresponds to the element region ER. The memory region MR is located in the center of the multiple word lines WL, and the step region SR is located at both ends in the X direction.

[0014] Multiple pillars PL are arranged in the memory region MR, penetrating the word line WL in the stacking direction. Multiple memory cells are formed at the intersections of the pillars PL and the word line WL. As a result, the semiconductor memory device 1 is configured as a three-dimensional non-volatile memory, for example, in which memory cells are arranged three-dimensionally in the memory region MR.

[0015] In the staircase area SR, multiple word lines WL are processed into a staircase shape and terminated. Contact CCs are placed on each terrace section of each level, which is formed by multiple word lines WL, and these CCs are connected to the word lines WL of each level.

[0016] These contact CCs allow individual stacked word lines WLs to be drawn out. From these contact CCs, write voltages and read voltages are applied to memory cells contained in the memory region MR in the center of multiple word lines WLs, via word lines WLs at the same height as the memory cells.

[0017] Multiple word lines WL, pillars PL, and contacts CC are covered by an insulating layer 50. The insulating layer 50 also extends around the multiple word lines WL. Both ends of the insulating layer 50 in the X direction and both ends in the Y direction correspond to the end faces of the semiconductor memory device 1.

[0018] Near the edge face of the semiconductor memory device 1, an outer peripheral region OR is arranged along the edge face of the semiconductor memory device 1. That is, the outer peripheral region OR surrounds the element region ER at a predetermined distance from it. Multiple insulating layers NL are stacked in the outer peripheral region OR, each corresponding to the height position of multiple word lines WL.

[0019] A chip-shaped semiconductor memory device 1 can be obtained, for example, by segmenting a substrate that supports the semiconductor memory device 1. On the substrate before segmentation, multiple semiconductor memory devices 1 are arranged, for example, in a matrix, and scribe lines are provided between each semiconductor memory device 1 for cutting out the semiconductor memory device 1 into a chip shape.

[0020] Most of the scribe lines are removed when cutting out the semiconductor memory device 1, but some of the scribe lines may remain on the end face of the semiconductor memory device 1. The outer peripheral region OR shown above is the portion where such scribe lines remain.

[0021] In the example shown in Figure 1, the semiconductor memory device 1 has only one stacked word line WL structure in the device region ER, but the configuration of the semiconductor memory device 1 is not limited to this. The semiconductor memory device 1 may have multiple stacked word line WL structures in the device region ER.

[0022] Above the insulating layer 50, the peripheral circuit CBA provided on the semiconductor substrate SB is arranged.

[0023] The semiconductor substrate SB is, for example, a silicon substrate. Peripheral circuits CBA, including transistors TR and wiring, are arranged on the surface of the semiconductor substrate SB. Various voltages applied to the memory cell from contacts CC are controlled by the peripheral circuits CBA, which are electrically connected to these contacts CC. In this way, the peripheral circuits CBA control the electrical operation of the memory cell.

[0024] The peripheral circuit CBA is covered with an insulating layer 40, and by joining this insulating layer 40 with the insulating layer 50 covering the laminate LM, a semiconductor memory device 1 is formed that includes multiple word lines WL, pillars PL, contacts CC, etc., and the peripheral circuit CBA.

[0025] Next, a detailed example of the configuration of the semiconductor memory device 1 will be described using Figure 2. Figure 2 is a cross-sectional view showing an example of the configuration of the semiconductor memory device 1 according to Embodiment 1.

[0026] Figure 2(a) is a cross-sectional view along the Y direction including the memory region MR. Figure 2(b) is a partially enlarged view showing a cross-section of the pillar PL located in the memory region MR. Figure 2(c) is a cross-sectional view along the X direction including the stepped region SR and the outer peripheral region OR.

[0027] Note that in Figures 2(a) and (c), the structure above the insulating layer 40, such as the semiconductor substrate SB and peripheral circuit CBA, and the structure below the insulating layer 60, such as the electrode film 20, are omitted.

[0028] As shown in Figures 2(a) and 2(c), the source wire SL is arranged on the insulating layer 60 on which the plug PG is provided. The source wire SL, as the lower layer, has a multilayer structure in which, for example, the source wire DSLa, the intermediate source wire BSL or the intermediate insulating layer SCO, and the source wire DSLb are stacked in this order from the insulating layer 60 side.

[0029] The source line DSLa, intermediate source line BSL, and source line DSLb are, for example, polysilicon layers. Of these, at least the intermediate source line BSL may be a conductive polysilicon layer with diffused impurities. The intermediate source line BSL is located below the memory region MR of the laminate LM. The intermediate insulating layer SCO is, for example, a silicon oxide layer. The intermediate insulating layer SCO is located below the step region SR of the laminate LM.

[0030] A laminated structure LM is positioned above the source wire SL. Insulating layers 52, 53, and 54 are arranged on the laminated structure LM in that order. Furthermore, as shown in Figure 2(c), an insulating layer 51 is interposed between these insulating layers 52-54 and the laminated structure LM in the stepped region SR. These insulating layers 51-54 constitute a part of the insulating layer 50 in Figure 1.

[0031] The laminate LM consists of multiple word lines WL and multiple insulating layers OL, each layered alternately. The word lines WL are, for example, tungsten layers or molybdenum layers. The insulating layers OL are, for example, silicon oxide layers.

[0032] The laminate LM comprises, more specifically, a laminate LMa as a first laminate and a laminate LMb as a second laminate. Laminate LMa has a configuration in which multiple word lines WL as first conductive layers and multiple insulating layers OL as first insulating layers are alternately laminated one layer at a time on a source line SL. Laminate LMb has a configuration in which multiple word lines WL as second conductive layers and multiple insulating layers OL as second insulating layers are alternately laminated one layer at a time on laminate LMa.

[0033] Furthermore, one or more select gate lines may be laminated via an insulating layer OL below the bottommost word line WL of the laminate LMa, and above the topmost word line WL of the laminate LMb. The number of layers of these word lines WL and select gate lines in the laminate LM is arbitrary. The number of word line WL layers may be, for example, several tens to several hundreds of layers.

[0034] The aforementioned laminate LMa comprises several insulating layers OLt that are thicker than the other insulating layers OL contained within the LMa. These insulating layers OLt are located, for example, on the lower side of the LMa laminate, excluding the bottommost layer.

[0035] More specifically, these insulating layers OLt are positioned at at least one of the height positions within the range of 20% to 50%, where the height of the top surface of the laminate LMa is considered 100% of the height of the bottom surface of the laminate LMa.

[0036] The aforementioned laminate LMb comprises several insulating layers OLt that are thicker than the other insulating layers OL included in the laminate LMb. These insulating layers OLt are located, for example, on the lower side of the laminate LMb, excluding the bottommost layer of the laminate LMb.

[0037] More specifically, these insulating layers OLt are positioned at at least one of the height positions within the range of 20% to 50%, where the height of the top surface of the laminate LMb is 100% of the height of the bottom surface of the laminate LMb.

[0038] Furthermore, the insulating layers OL included in the laminates LMa and LMb, excluding these insulating layers OLt, have a thickness approximately equal to that of the word wire WL, for example. Therefore, the thickness of insulating layer Ot is set to be thicker than that of the other insulating layers OL and the word wire WL.

[0039] From this point forward, when we do not distinguish between the insulating layer OLt contained in the laminates LMa and LMb, respectively, and other insulating layers OL, we may collectively refer to them as the insulating layer OL.

[0040] Multiple plate-shaped contacts LI divide the laminate LM in the Y direction.

[0041] These plate-like contacts LI are aligned with each other in the Y direction and extend along the stacking direction and the X direction of the laminate LM. In other words, the plate-like contacts LI extend continuously within the laminate LM from one end in the X direction to the other. This divides the laminate LM in the Y direction.

[0042] More specifically, in the memory region MR, the plate-shaped contact LI penetrates the insulating layer 52, the laminate LM, and the source line DSLb to reach the intermediate source line BSL. In the stepped region SR, the plate-shaped contact LI penetrates the insulating layers 52, 51, at least a portion of the laminate LM, and the source line DSLb to reach the intermediate insulating layer SCO.

[0043] Furthermore, each plate-shaped contact LI includes an insulating layer 55 and a conductive layer 21. The insulating layer 55 is, for example, a silicon oxide layer. The conductive layer 21 is, for example, a tungsten layer or a conductive polysilicon layer.

[0044] The insulating layer 55 covers the side walls of the plate-shaped contact LI facing in the Y direction. The conductive layer 21 is filled inside the insulating layer 55 and is electrically connected to the source wire SL, including the intermediate source wire BSL, as shown in Figure 2(a). The conductive layer 21 is also connected to the upper wiring via a plug (not shown).

[0045] With this configuration, the plate-shaped contact LI functions as a source wire contact. However, instead of the plate-shaped contact LI, the laminate LM may be divided in the Y direction by a plate-shaped member made of, for example, an insulating layer. In such a case, the plate-shaped member does not function as a source wire contact.

[0046] As shown in Figure 2(a), multiple pillars PL are distributed between individual plate-shaped contacts LI of the memory region MR, extending within the laminate LM in the stacking direction of the laminate LM. The multiple pillars PL are arranged, for example, in a staggered pattern when viewed from the stacking direction of the laminate LM.

[0047] Furthermore, pillar PL penetrates the insulating layer 52, the laminate LM, the source wire DSLb, and the intermediate source wire BSL to reach the source wire DSLa. More specifically, pillar PL includes pillar PLa as a first pillar extending within the laminate LMa and pillar PLb as a second pillar extending within the laminate LMb.

[0048] In other words, the pillar PLa penetrates the laminate LMa, the source line DSLb, and the intermediate source line BSL to reach the source line DSLa. Each pillar PLa has a cross-sectional shape such as a circle, ellipse, or oval shape in the direction along the layer direction of the laminate LMa, that is, along the XY plane.

[0049] Furthermore, each pillar PLa has a Boeing shape at its lower and upper sections. A Boeing shape is a shape in which the diameter of the pillar PLa is larger than the surrounding area. In other words, the cross-sectional area of ​​the Boeing shape in the direction along the XY plane is larger than the cross-sectional area of ​​the surrounding area in the direction along the XY plane.

[0050] The first Boeing shape at the bottom of pillar PLa is located at the same height as the thicker insulating layer OLt of the laminate LMa. Furthermore, the diameter and cross-sectional area in the XY plane of the Boeing shape at the bottom of pillar PLa increase as it is located at the height of the insulating layer OLt, which is closer to the center of the laminate LMa in the stacking direction. Therefore, the diameter and cross-sectional area in the XY plane of the Boeing shape at the bottom of pillar PLa may be maximized at the height of the insulating layer OLt in the center of the laminate LMa in the stacking direction.

[0051] The second Boeing shape at the top of pillar PLa is located above the Boeing shape at the bottom of pillar PLa, for example, closer to the top edge of pillar PLa.

[0052] Furthermore, the pillar PLb penetrates the insulating layer 52 and the laminate LMb, and is connected to the upper end of the pillar PLa in the laminate LMa. Each pillar PLb also has a cross-sectional shape such as a circle, ellipse, or oval shape in the direction along the layer direction of the laminate LMb, that is, in the direction along the XY plane.

[0053] Furthermore, each pillar PLb has a Boeing shape at its lower and upper sections. In other words, these Boeing shapes also have larger diameters and cross-sectional areas than the surrounding pillar PLb diameters and cross-sectional areas in the XY plane.

[0054] The third Boeing shape at the bottom of pillar PLb is located at the same height as the thicker insulating layer OLt of the laminate LMb. Furthermore, the diameter and cross-sectional area in the XY plane of the Boeing shape at the bottom of pillar PLb increase as it is located at the height of the insulating layer OLt, which is closer to the center of the laminate LMb in the stacking direction. Therefore, the diameter and cross-sectional area in the XY plane of the Boeing shape at the bottom of pillar PLb may be maximized at the height of the insulating layer OLt in the center of the laminate LMb in the stacking direction.

[0055] The fourth Boeing shape at the top of pillar PLb is located above the Boeing shape at the bottom of pillar PLb, and is positioned, for example, closer to the top edge of pillar PLb.

[0056] These pillars PLa and PLb, which have Boeing shapes at their upper and lower sections respectively, may hereafter be referred to as a two-stage Boeing shape.

[0057] Each pillar PL, including pillars PLa and PLb respectively, has a memory layer ME located on its outer periphery, a channel layer CN that penetrates the laminate LM and connects to the intermediate source line BSL, and a core layer CR that serves as the core material of the pillar PL. However, the memory layer ME is not located at the depth position of the intermediate source line BSL. The memory layer ME and channel layer CN also cover the end of the pillar PL on the source line SL side.

[0058] As shown in Figure 2(b), the memory layer ME has a multilayer structure in which a block insulating layer BK, a charge storage layer CT, and a tunnel insulating layer TN are stacked in this order from the outer periphery side of the pillar PL.

[0059] The channel layer CN is in contact with the intermediate source line BSL on its side, thereby electrically connecting to the source line SL, which includes the intermediate source line BSL. The channel layer CN is connected to the bit line BL, which extends along the Y direction through the insulating layer 54, via plug CH located in the insulating layers 52, 53.

[0060] The bit line BL is connected to the electrode pad PDc located in the insulating layer 40 via the electrode pad PDb located in the insulating layer 54. The electrode pad PDc is electrically connected to the peripheral circuit CBA (see Figure 1), which is covered by the insulating layer 40. This connects the channel layer CN of the pillar PL to the peripheral circuit CBA.

[0061] The block insulating layer BK and tunnel insulating layer TN of the memory layer ME, as well as the core layer CR, are, for example, silicon oxide layers. The charge storage layer CT of the memory layer ME is, for example, a silicon nitride layer. The channel layer CN is a semiconductor layer, for example, a polysilicon layer or an amorphous silicon layer.

[0062] With the above configuration, memory cells MC are formed in the portions of the pillar PL side surface that face each word line WL. Data is written to and read from the memory cells MC by applying a predetermined voltage from the word line WL.

[0063] As shown in Figure 2(c), the stepped region SR has a stepped section SP. The stepped section SP has a stepped shape in which multiple word lines WL and multiple insulating layers OL are processed in a stepped manner. As described above, the stepped section SP extends in the X direction at both ends of the laminate LM (see Figure 1(a)), and as it moves away from the memory region MR in the center of the laminate LM, it descends toward the source line SL. Also, as described above, an insulating layer 51 is placed between the stepped section SP and the insulating layer 52, covering the stepped section SP and extending outwards to its periphery.

[0064] Each step of the staircase section SP is connected to a word wire WL, which has contacts CC that penetrate the insulating layers 51 and 52.

[0065] The contact CC has an insulating layer 56 covering the outer circumference of the contact CC and a conductive layer 22, such as a tungsten layer or a copper layer, filled inside the insulating layer 56. The conductive layer 22 is connected to the wiring MX located in the insulating layer 54 via a plug V0 located in the insulating layer 53. The wiring MX is electrically connected to the peripheral circuit CBA (see Figure 1) via electrode pads PDb, PCc, etc.

[0066] This configuration allows the word lines WL of each layer to be electrically extracted. In other words, with the above configuration, a predetermined voltage can be applied from the peripheral circuit CBA to the memory cell MC via the electrode pads PDc, PCb, contact CC, and word lines WL, thereby enabling the memory cell MC to operate as a memory element.

[0067] Furthermore, within the stepped region SR, multiple columnar sections (not shown) extending in the stacking direction of the laminate LM are dispersed, along with the insulating layers 52 and 51 and the laminate LM. As will be described later, these columnar sections play a role in supporting these components when forming the laminate LM from a laminate in which the sacrificial layer and the insulating layer are stacked.

[0068] Furthermore, in the outer peripheral region OR (see Figure 1) of the laminate LM, laminate LMs are arranged at a distance from the laminate LM, surrounding it. The laminate LMs have a structure in which multiple insulating layers NL and multiple insulating layers OL are alternately stacked one layer at a time. The multiple insulating layers NL are made of different materials from the insulating layers OL, such as silicon nitride layers.

[0069] The laminated LMs comprises, more specifically, a laminated LMsa and a laminated LMsb. Laminated LMsa includes several insulating layers OLt positioned at the same height as the insulating layers OLt of laminated LMa described above. Laminated LMsb also includes several insulating layers OLt positioned at the same height as the insulating layers OLt of laminated LMb described above.

[0070] (Method of manufacturing semiconductor memory devices) Next, the method for manufacturing the semiconductor memory device 1 according to Embodiment 1 will be described using Figures 3 to 11. Figures 3 to 11 are diagrams illustrating, in order, some of the steps of the method for manufacturing the semiconductor memory device 1 according to Embodiment 1.

[0071] First, Figures 3 and 4 show how the pillar PL is formed. Figures 3 and 4 show a cross-section of the memory region MR along the Y direction during manufacturing.

[0072] As shown in Figure 3(a), a source wire DSLa, an intermediate sacrificial layer SCN, and a source wire DSLb are formed on a support substrate SS in this order. The support substrate SS may be, for example, a semiconductor substrate such as a silicon substrate, an insulating substrate such as a ceramic substrate or a quartz substrate, or a conductive substrate such as a sapphire substrate. The source wires DSLa and DSLb are, for example, polysilicon layers. The intermediate sacrificial layer SCN is, for example, a silicon nitride layer, which is later replaced with conductive polysilicon to become the intermediate source wire BSL.

[0073] Furthermore, a second laminate, LMsa, is formed on the source line DSLb by alternately stacking multiple first insulating layers NL and multiple second insulating layers OL one layer at a time. The insulating layers NL are, for example, silicon nitride layers and function as sacrificial layers that will later be replaced by conductive materials to become the word line WL. The laminate LMsa is the portion that will later become the laminate LMa through this replacement process.

[0074] Such laminated structures (LMsa) are formed using methods such as plasma CVD (Chemical Vapor Deposition). When forming the insulating layer (OL), silane-based gases such as monosilane (SiH4) and oxidizing gases such as oxygen (O2) are used. When forming the insulating layer (NL), silane-based gases such as monosilane (SiH4) and nitriding gases such as ammonia (NH3) are used.

[0075] Furthermore, at this time, the laminate LMa is formed to have the aforementioned insulating layer OLt, which is thicker than the other insulating layers OL, at a predetermined position. To form the insulating layer OLt thicker, for example, the processing time by plasma CVD or the like can be increased compared to the other insulating layers OL.

[0076] When forming the source line DSLa, intermediate sacrificial layer SCN, and source line DSLb in the region that will become the memory region MR, the intermediate insulating layer SCO (see Figure 2(c)) is formed in place of the intermediate sacrificial layer SCN in the region that will later become the step region SR, although this is not shown in the diagram.

[0077] Furthermore, although not shown in the diagram, portions of the stepped section SP that are positioned on the laminated LMa are formed at both ends of the laminated LMsa in the X direction. The stepped shape at the ends of the laminated LMsa can be obtained, for example, by forming a resist layer (not shown) on the upper surface of the laminated LMsa, and then processing the laminated LMsa from the upper side while slimming the resist layer using oxygen plasma or the like.

[0078] Furthermore, in the memory region MR, multiple memory holes MHa are formed from the top surface of the stacked LMsa, penetrating the stacked LMsa, source line DSLb, and intermediate sacrificial layer SCN, and reaching the source line DSLa.

[0079] Multiple memory holes MHa are formed, for example, by plasma etching at low temperatures. Specifically, for example, a support substrate SS is placed on a stage cooled to 0°C or below, more preferably -10°C or below, and a laminate LMSsa, on which a resist layer (not shown) having a hole pattern is formed on its upper surface, is etched using a plasma such as a hydrofluorocarbon (CxHyFz) gas.

[0080] Under these conditions, for example, the reaction of fluorocarbon gases and hydrogen gases with the insulating layers NL and OL in the plasma causes etching to proceed while deposits are attached to the processed surfaces of the laminate LMsa, such as the sides of memory holes MHa in the process of formation. As an example, the deposits may include (NH4)xSiFy, etc. The nitrogen and silicon as the first element contained in the deposits such as (NH4)xSiFy originate from the insulating layer NL, which is, for example, a silicon nitride layer.

[0081] The deposits adhering to the side surface of the memory hole MHa have the function of protecting the memory hole MHa side surface from the plasma. Therefore, by adjusting the plasma conditions in various ways, the amount of deposits can also be adjusted, making it possible to form memory holes MHa with desired shapes such as straight, tapered, or bowed shapes. Under the above conditions, deposits are more likely to be generated during etching of the insulating layer NL, of the insulating layers NL and OL.

[0082] At the beginning of etching, while processing the upper layer of the LMa laminate, there is relatively little deposit, so the sides of the memory holes MHa are not protected from the plasma, and the memory holes MHa have a bowed shape at the top. Furthermore, as etching progresses to a certain extent, the deposits on the sides cause the memory holes MHa to gradually become tapered.

[0083] However, a thicker insulating layer OLt is formed on the lower side of the laminate LMsa. As mentioned above, when etching the insulating layers OL and OLt, the amount of deposits generated decreases compared to when etching the insulating layer NL. Therefore, the memory hole MHa also has a bowing shape at the bottom.

[0084] Thus, similar to the pillar PLa described above, a two-stage Boeing shape is formed, meaning that memory holes MHa with Boeing shapes are formed in the upper and lower parts.

[0085] As shown in Figure 3(b), the memory holes MHa are filled with a sacrificial layer, such as an amorphous silicon layer, to form multiple pillars PLs.

[0086] As shown in Figure 3(c), a laminate LMsb is formed on a laminate LMsa on which multiple pillars PLs are formed, with multiple insulating layers NL and multiple insulating layers OL alternately stacked one layer at a time. The laminate LMsb is the portion that will later become the laminate LMb. Such a laminate LMsb can also be formed, like the laminate LMsa described above, by changing the gas type as appropriate, for example, by plasma CVD.

[0087] Furthermore, the aforementioned insulating layer OLt, which is thicker than the other insulating layers OL, is formed on the laminate LMb at predetermined positions. An insulating layer 52 is formed on the laminate LMsb.

[0088] For example, after the laminate LMsb is formed, although not shown in the diagram, portions of the stepped section SP that are placed on the laminate LMsb are formed at both ends of the laminate LMsb in the X direction. The stepped shape at the ends of the laminate LMsb is obtained by processing the laminate LMsb from the top side while slimming, for example, the resist layer, similar to the stepped shape formed on the laminate LMsa described above.

[0089] Although not shown in the diagram, the stepped shape formed on the laminates LMsa and LMsb is covered by the insulating layer 51 (see Figure 2) described above. Subsequently, the entire upper surface of the laminate, including the stepped region SR, is covered with the insulating layer 52.

[0090] Furthermore, in the memory region MR, multiple memory holes MHb are formed, each reaching a pillar PLs formed in the laminate LMsa. These multiple memory holes MHb are also formed, like the memory holes MHa described above, for example, by plasma etching at low temperatures.

[0091] Specifically, for example, a support substrate SS is placed on a stage cooled to 0°C or below, more preferably to -10°C or below, and a laminate LMSsb having a hole pattern formed on its upper surface (not shown) is etched using a plasma such as a hydrofluorocarbon (CxHyFz) gas.

[0092] Through this process, deposits corresponding to the depth of the memory hole MHb in the process of formation are attached to the sides of the memory hole MHb, and the memory hole MHb ends up having a bowing shape located on the upper side of the laminate LMb and a bowing shape located on the lower side of the laminate LMsb at the height of the thicker insulating layer OLt.

[0093] Thus, similar to the pillar PLb described above, a two-stage Boeing shape is formed, meaning that memory holes MHb with Boeing shapes are formed in the upper and lower parts.

[0094] As shown in Figure 4(a), the sacrificial layer filling the memory hole MHa is removed through the memory hole MHb. This creates multiple memory holes MH that penetrate the insulating layer 52, the laminate LMsb, LMsa, the source wire DSLb, and the intermediate sacrificial layer SCN, reaching the source wire DSLa.

[0095] As shown in Figure 4(b), a memory layer ME is formed within the memory hole MH, with a block insulating layer BK, a charge storage layer CT, and a tunnel insulating layer TN stacked in that order from the outer periphery of the memory hole MH. The memory layer ME is also formed on the bottom surface of the memory hole MH. As described above, the block insulating layer BK and the tunnel insulating layer TN are, for example, silicon oxide layers, and the charge storage layer CT is, for example, a silicon nitride layer.

[0096] Furthermore, a channel layer CN, such as a polysilicon layer or amorphous silicon layer, is formed inside the memory layer ME. The channel layer CN is also formed on the bottom surface of the memory holes MH via the memory layer ME. In addition, a core layer CR, such as a silicon oxide layer, is filled further inside the channel layer CN.

[0097] As a result, multiple pillars PL are formed. However, at this stage, the memory layer ME is also formed at the height of the intermediate sacrificial layer SCN, covering the entire side surface of the channel layer CN.

[0098] Next, Figures 5 and 6 show the formation of the intermediate source line (BSL). Similar to Figures 3 and 4 described above, Figures 5 and 6 show a cross-section of the memory region MR along the Y direction during manufacturing.

[0099] As shown in Figure 5(a), multiple slits ST are formed at the location where the plate-shaped contact LI of the memory region MR is formed, penetrating the laminates LMsa, LMsb and the source line DSLa to reach the intermediate sacrificial layer SCN. These slits ST also extend in the X direction, dividing the laminates LMsa, LMsb in the Y direction.

[0100] Furthermore, an insulating layer 55s is formed on the side walls of these slits ST facing each other in the Y direction. The insulating layer 55s is, for example, a silicon oxide layer and functions as a protective layer for the laminates LMsa and LMsb when forming the intermediate source wire BSL.

[0101] As shown in Figure 5(b), a removal solution for the intermediate sacrificial layer SCN, such as thermal phosphoric acid, is introduced through multiple slits ST to remove the intermediate sacrificial layer SCN. This forms a gap layer GPs between the source lines DSLa and DSLb. In addition, a portion of the memory layer ME on the outer periphery of the pillar PL is exposed within the gap layer GPs.

[0102] In this case, since an insulating layer 55s is formed on the side wall of the slit ST that penetrates the laminates LMsa and LMsb, the removal of the insulating layer NL contained in the laminates LMsa and LMsb is suppressed.

[0103] As shown in Figure 6(a), different chemical solutions are appropriately introduced into the gap layer GPs through multiple slits ST to sequentially remove the block insulating layer BK, charge storage layer CT, and tunnel insulating layer TN exposed within the gap layer GPs. As a result, the memory layer ME is removed from a portion of the pillar PL's sidewall, and a portion of the inner channel layer CN's sidewall is exposed within the gap layer GPs.

[0104] As shown in Figure 6(b), a raw material gas for forming amorphous silicon, for example, is injected through multiple slits ST, and the gap layers GPs are filled with amorphous silicon, etc. Furthermore, the support substrate SS is heat-treated to polycrystallize the amorphous silicon filled in the gap layers GPs, forming an intermediate source wire BSL containing polysilicon, etc.

[0105] As a result, a portion of the channel layer CN of the pillar PL is connected to the source line SL on the side via the intermediate source line BSL.

[0106] The intermediate source line (BSL) formation process shown in Figures 5 and 6 is also referred to as the intermediate source line (BSL) replacement process.

[0107] Next, the insulating layer 55s on the side wall of the slit ST is removed.

[0108] Next, Figures 7 and 8 show how the laminates LMa and LMb are formed. Figures 7 and 8(a) show a cross-section along the Y direction of the memory region MR during manufacturing, similar to Figures 3 to 6 described above. Figures 7 and 8(b) show a cross-section along the X direction of the step region SR during manufacturing.

[0109] In this step region SR, a step structure is formed in which the ends of the laminates LMsa and LMsb are processed into a step shape. This step structure is entirely covered by an insulating layer 51, and further covered by an insulating layer 52 that covers the entire laminates LMa and LMb. In addition, in parallel with the formation of the pillar PL described above, multiple columnar parts (not shown) are formed in the step region SR.

[0110] Furthermore, in the stepped region SR, an intermediate insulating layer SCO is formed in place of the intermediate sacrificial layer SCN. Since this intermediate insulating layer SCO is, for example, a silicon oxide layer, it remains without being removed by the aforementioned replacement process of the intermediate source wire BSL.

[0111] Furthermore, in the outer peripheral region OR (see Figure 1) on the X-direction outside the stair region SR and on the Y-direction outside the laminates LMsa and LMsb (not shown), there are laminates LMsa and LMsb that have been separated from the laminates LMsa and LMsb on which pillars PL and stair structures are formed.

[0112] As described above, the outer region OR is a region included in the scribe line and is located outside the element region ER (see Figure 1). The various processes described above are performed on the element region ER, and the outer region OR is not subject to these processes.

[0113] Therefore, due to processes such as forming a step structure on the laminates LMa and LMb on which pillars PL, etc., are formed, the aforementioned laminates LMa and LMb that have been separated from the laminates LMa and LMb on which pillars PL, etc., are formed may remain in the outer peripheral region OR.

[0114] As shown in Figure 7(a), a removal solution for the insulating layer NL, such as thermal phosphoric acid, is introduced into the interior of the laminates LMsa and LMsb through a slit ST that penetrates the laminates LMsa and LMsb, thereby removing the insulating layer NL of the laminates LMsa and LMsb. This forms laminates LMga and LMgb having multiple gap layers GP from which the insulating layer NL between insulating layers OL has been removed.

[0115] As shown in Figure 7(b), the removal of the insulating layer NL of the laminates LMsa and LMsb through the slit ST extends to the stepped region SR. As described above, the slit ST is formed to divide the laminates LMsa and LMsb in the Y direction and extends to the outside of the stepped region SR, as shown by the dashed line in Figure 7(b). Through such a slit ST, the insulating layer NL in the stepped region SR is also removed.

[0116] However, the slit ST does not reach, for example, the outer peripheral region OR beyond the staircase region SR. Therefore, the insulating layer NL of the laminates LMsa and LMsb remaining in the outer peripheral region OR is not removed.

[0117] Furthermore, laminates LMga and LMgb containing multiple gap layers GP have a fragile structure. In the memory region MR, multiple pillars PL support these fragile laminates LMga and LMgb. In the stepped region SR, multiple columnar parts (not shown) support the laminates LMga and LMgb. This support structure of pillars PL and columnar parts prevents the remaining insulating layer OL from bending, and prevents the laminates LMga and LMgb from becoming distorted or collapsing.

[0118] As shown in Figures 8(a) and 8(b), a conductive material gas, such as tungsten or molybdenum, is injected into the laminates LMga and LMgb through the slit ST, filling the gap layer GP of the laminates LMga and LMgb with the conductive material to form multiple word lines WL. This forms a laminate LM in which multiple word lines WL and multiple insulating layers OL are alternately stacked one layer at a time.

[0119] In this case, as described above, no slit ST is formed in the outer peripheral region OR, and the laminates LMsa and LMsb in the outer peripheral region OR still contain the insulating layer NL. In other words, the laminates LMsa and LMsb formed by the processes shown in Figures 3(a) and 3(c) above are maintained in the outer peripheral region OR.

[0120] The word line WL formation process shown in Figures 7 and 8 is also referred to as the word line WL replacement process.

[0121] Next, Figures 9 and 10 show how the plate-shaped contact LI, contact CC, and various upper layer wiring are formed. Figures 9 and 10(a) show a cross-section along the Y direction of the memory region MR during manufacturing, similar to Figures 7 and 8(a) described above. Figures 9 and 10(b) show a cross-section along the X direction of the step region SR during manufacturing, similar to Figures 7 and 8(b).

[0122] As shown in Figure 9(a), an insulating layer 55 is formed on the side walls of the slit ST facing in the Y direction, and a conductive layer 21 is filled inside the insulating layer 55. This forms a plate-shaped contact LI. However, as described above, an insulating layer 55 or the like may be filled inside the slit ST to form a plate-shaped member that does not function as a source wire contact. In this case, the slit ST is formed solely for the purpose of replacing the word wire WL.

[0123] As shown in Figure 9(b), multiple contact CCs are formed that penetrate the insulating layers 52 and 51 and reach the upper surface of each word wire WL of the stepped section SP. These contact CCs are formed by forming multiple contact holes (not shown) that penetrate the insulating layers 52 and 51 and reach the word wire WL, forming an insulating layer 56 that covers the side walls of the contact holes, and forming a conductive layer 22 that fills the inside of the insulating layer 56.

[0124] As shown in Figures 10(a) and 10(b), an additional insulating layer 53 is formed on the insulating layer 52 that covers the laminate LM.

[0125] As shown in Figure 10(a), a plug CH is formed that penetrates the insulating layer 53 and is connected to the channel layer CN of the pillar PL. A bit wire BL is also formed on the insulating layer 53 and connected to the plug CH. An insulating layer 54 is also formed to cover the insulating layer 53 and the bit wire BL, and multiple electrode pads PDb are formed in the insulating layer 54 that are connected to the bit wire BL and exposed on the upper surface of the insulating layer 54.

[0126] As shown in Figure 10(b), in the stepped region SR, in parallel with the process in Figure 10(a), a plug V0 is formed that penetrates the insulating layer 53 and connects to each of the multiple contacts CC. Although not shown, the plug V0 is also connected to the plate-shaped contact LI.

[0127] Furthermore, an upper wiring MX connected to the plug V0 is formed on the insulating layer 53. In addition, an insulating layer 54 is formed to cover the insulating layer 53 and the upper wiring MX, and a plurality of electrode pads PDb connected to the upper wiring MX and exposed on the upper surface of the insulating layer 54 are formed in the insulating layer 54.

[0128] Next, Figure 11 shows how peripheral circuits CBA are formed on the laminate LM. Figure 11(a) shows a cross-section along the Y direction of the semiconductor substrate SB on which the peripheral circuits CBA are formed. Figure 11(b) shows a cross-section along the Y direction of the memory region MR during manufacturing, similar to Figures 9 and 10(a) described above.

[0129] As shown in Figure 11(a), a peripheral circuit CBA including a transistor TR is formed separately on the surface of a semiconductor substrate SB such as a silicon substrate. An insulating layer 40 is also formed to cover the peripheral circuit CBA. Contacts, vias, and wiring connected to the peripheral circuit CBA are formed in the insulating layer 40. In addition, multiple electrode pads PDc are formed in the insulating layer 40 that are electrically connected to the peripheral circuit CBA via these components and are exposed on the surface of the insulating layer 40.

[0130] The semiconductor substrate SB on which the peripheral circuit CBA is formed is positioned facing the side of the support substrate SS on which the laminate LM, etc., is formed, as shown in Figure 11(b).

[0131] Next, the insulating layer 54 on the support substrate SS and the insulating layer 40 on the semiconductor substrate SB are joined. These insulating layers 54 and 40 can be joined by activating them beforehand, for example, by plasma treatment. When joining the insulating layers 54 and 40, the support substrate SS and the semiconductor substrate SB are aligned so that the electrode pad PDb formed on the insulating layer 54 and the electrode pad PDc formed on the insulating layer 40 overlap.

[0132] After bonding the insulating layers 54 and 40, an annealing process is performed to bond the electrode pads PDb and PDc, for example, by Cu-Cu bonding. As a result, a bonded substrate is obtained in which the support substrate SS and the semiconductor substrate SB are bonded together.

[0133] Subsequently, the support substrate SS is removed from the bonded substrate by CMP (Chemical Mechanical Polishing) or similar methods to expose the source wire DSLa.

[0134] Furthermore, an insulating layer 60 is formed on the underside of the source wire DSLa, and a plug PG (see Figure 1) is formed that penetrates the insulating layer 60. In addition, an electrode film 20 (see Figure 1) is formed on the insulating layer 60. As a result, the source wire SL and the electrode film 20 are electrically connected via the plug PG.

[0135] Furthermore, peripheral circuits PER are provided, and the semiconductor substrate SB, to which the laminated LM and other components are bonded together, is cut by a dicing blade or the like, and a fragmentation process is performed to cut out individual semiconductor memory devices 1. At this time, the scribe lines that were provided on the outer periphery of the laminated LM disappear almost completely, but in some cases, a portion of the scribe lines may remain as an outer peripheral region OR including the laminated LMs that have been separated from the laminated LM.

[0136] The semiconductor memory device 1 of Embodiment 1 is manufactured as described above.

[0137] (Overview) In semiconductor memory devices such as 3D non-volatile memory, multiple silicon nitride layers, which will later be replaced by word lines, and multiple silicon oxide layers, which will insulate the spaces between the multiple word lines, are stacked, and a memory structure is formed within memory holes that penetrate these layers.

[0138] With the increasing integration of semiconductor memory devices, the number of layers of silicon nitride and silicon oxide is increasing, and there is a need to improve the throughput of memory hole formation by etching. By replacing the plasma etching at temperatures above 0°C, which has been used for memory hole formation until now, with plasma etching using fluorocarbon gas and hydrogen gas at temperatures below 0°C, the etching rate of the silicon nitride layer can be dramatically increased.

[0139] On the other hand, under these low-temperature etching conditions, the deposits generated during the etching of the silicon nitride layer cause the memory holes to become tapered, resulting in a problem where sufficient conductivity cannot be obtained between the memory structure formed within the memory holes and the source wires in the underlying layer.

[0140] The etching mechanism of memory holes in this type of low-temperature etching will be explained using Figure 12.

[0141] Figure 12 is a schematic diagram showing the etching mechanism of memory holes MHa and MHx in Embodiment 1 and the Comparative Example. Figures 12(a) and 12(b) show how the memory hole MHx of the Comparative Example is formed by etching. Figure 12(c) shows how the memory hole MHa of Embodiment 1 is formed by etching.

[0142] As shown in Figure 12(a), in the comparative example, all insulating layers OLx included in the laminate have the same thickness. A resist layer 70 having a hole pattern is formed on such a laminate, and the laminate is etched through the resist layer 70 by plasma etching using a fluorocarbon gas and hydrogen gas at a low temperature, for example, to form the memory holes MHx of the comparative example.

[0143] In such etching processes, for example, a deposit Dsh, which is a reaction mixture of silicon and nitrogen derived from the insulating layer NL, fluorine derived from fluorocarbon gases, and hydrogen derived from hydrogen gas, is deposited onto the etched surface such as the side of the memory hole MHx, while fluorocarbon ions (CFx) are deposited. + Memory holes MHx are formed by ion shocks such as those described above.

[0144] The deposits Dsh that adhere to the sides of memory holes MHx are formed containing, for example, (NH4)xSiFy, SiOxFy, NH4F, HCN, etc. As a result, the protective effect of the deposits Dsh on the side walls of the memory holes MHx is enhanced, and the memory holes MHx, which were bowed at the top, gradually take on a tapered shape.

[0145] During this etching process, the resist layer 70, which acts as an etching mask, also undergoes fluorocarbon radical (CFx) * ), and fluorine radicals (F) in fluorocarbons * The material is gradually etched by etchants such as ).

[0146] As a result, deposits Dcf, which are reaction mixtures of carbon derived from the resist layer 70, carbon derived from fluorocarbon gases, and fluorine, adhere to the side walls of the hole pattern openings in the resist layer 70. Such deposits Dcf are formed, for example, containing CFx.

[0147] As shown in Figure 12(b), after the memory hole MHx penetrates the stack and reaches the source line DSLb of the lower layer, further over-etching occurs. By the time the memory hole MHx reaches the stack on the lower side, the memory hole MHx becomes more tapered, and the aspect ratio of the memory hole MHx increases, resulting in the formation of fluorocarbon ions (CFx). + ) etc. make it difficult for them to reach the bottom of the memory hole MHx. For this reason, the memory hole MHx has an even more tapered shape.

[0148] Furthermore, when the memory hole MHx reaches the source line DSLb, in order to maintain a selectivity ratio with the source line DSLb so that the source line DSLb is not etched, conditions are set to facilitate the deposition of CFx and the like on the source line DSLb surface at the bottom of the memory hole MHx, for example, by switching the stage on which the support substrate is placed to a high temperature of 50°C or higher. At this time, the mixture containing CFx deposited on the source line DSLb surface at the bottom of the memory hole MHx and silicon derived from the source line DSLb is composed of fluorocarbon ions (CFx + It is sputtered by the impact of the ) and added as a component of the sediment Dsh.

[0149] These deposits, Dsh and CFx, also contribute to the tapering shape of the memory holes MHx. When forming memory holes that penetrate the upper layer of the laminate, over-etching occurs on the lower memory holes, which are filled with amorphous silicon layers. Therefore, deposits containing silicon derived from the amorphous silicon layer, such as Dsh and CFx, are deposited on the bottom surface of the upper memory holes, which is thought to contribute to their tapering shape.

[0150] As shown in Figure 12(c), in the configuration of Embodiment 1, several insulating layers OLt, which are thicker than other insulating layers OL, are arranged on the lower side of the laminate LMa, which tends to become tapered. As a result, the amount of deposit Dsh generated from the insulating layer NL, such as a silicon nitride layer, is reduced at the height of these insulating layers OLt, thereby suppressing the tapered shape of the memory holes MHa.

[0151] Furthermore, by adjusting the thickness and number of insulating layers OLt, it is possible to form memory holes MHa with a bowing shape at the height of these insulating layers OLt. In this way, by making the memory holes MHa bowing-shaped on the lower side, the bottom area of ​​the memory holes MHa can be effectively increased.

[0152] Here, it is conceivable to place an insulating layer OLt, which is thicker than the other insulating layers OL, at the bottom layer of the laminate LMa. However, the inventors have found that the bottom area of ​​the memory hole MHa is largely determined by the upper layers up to the bottom insulating layer OL. During over-etching, deposits Dsh from the source line DSLb and CFx are deposited at the bottom of the memory hole MHa. * This is presumably because deposits such as DCF are more likely to adhere to the surface.

[0153] According to the present inventors, a bowing shape for memory holes MHa can be easily obtained within a height range of 20% to 50%, where the height of the top surface of the laminated LMa is set to 100% relative to the height of the bottom surface of the laminated LMa, and such a bowing shape makes it possible to increase the bottom area of ​​the memory holes MHa.

[0154] According to the manufacturing method of the semiconductor memory device 1 of Embodiment 1, several insulating layers OLt on the lower side of the laminated LMa, excluding the bottom insulating layer OL of the laminated LMa, are formed to be thicker than the insulating layer OL on the upper side of the laminated LMa. Furthermore, when forming memory holes MHa, the laminated LMa is etched while deposits Dsh containing silicon and nitrogen are attached to the side walls of the memory holes MHa. This makes it possible to form memory holes MHa with a wide bottom diameter under high etching rate conditions.

[0155] According to the manufacturing method of the semiconductor memory device 1 of Embodiment 1, several insulating layers OLt are arranged in the laminate LMa at a height of 20% to 50% of the height of the top surface relative to the bottom surface of the laminate LMa, where 100% is the height of the top surface.

[0156] In this way, by placing several insulating layers OLt at an appropriate height position before the memory hole MHa reaches the underlying source line DSLb and over-etching begins, the memory hole MHa will have a two-stage bowing shape, which can effectively widen the bottom diameter.

[0157] (modified version) Next, a modified semiconductor memory device 1a of Embodiment 1 will be described using Figure 13. The modified semiconductor memory device 1a differs from Embodiment 1 in that the insulating layers OLt and OLm, which are thicker than the other insulating layers OL, have different thicknesses.

[0158] Figure 13 is a cross-sectional view along the X direction showing an example of the configuration of a semiconductor memory device 1a according to a modified embodiment of Embodiment 1. Figure 13 shows cross-sections of a pillar PL arranged in the memory region MR and an untreated laminate LMas arranged in the outer peripheral region OR.

[0159] In Figure 13, components similar to those in Embodiment 1 described above are denoted by the same reference numerals, and their descriptions are omitted.

[0160] As shown in Figure 13, the modified semiconductor memory device 1a comprises a laminate LMaa as a first laminate arranged on a source line SL, and a laminate LMm including a laminate LMab arranged on the laminate LMaa.

[0161] The laminate LMaa has a structure in which multiple word lines WL and multiple insulating layers OL, which serve as first insulating layers, are alternately stacked one layer at a time. Of the multiple insulating layers OL, some insulating layers OLt and OLm on the lower side of the laminate LMaa, excluding the bottom insulating layer OL, are thicker than the insulating layers OL on the upper side of the laminate LMm. Furthermore, of these insulating layers OLt and OLm, insulating layer OLt is even thicker than insulating layer OLm.

[0162] More specifically, several insulating layers OLt and OLm are positioned in the laminate LMaa at at least one of the height positions within a range of 20% to 50% of the height of the top surface relative to the bottom surface of the laminate LMaa, with the top surface being 100% of the bottom surface of the laminate LMaa. Furthermore, within the range in which these insulating layers OLt and OLm are positioned, insulating layer OLt is positioned near the center in the stacking direction of the laminate LMaa. Insulating layer OLm is positioned above and below insulating layer OLt, respectively.

[0163] In the example shown in Figure 13, two types of insulating layers OLt and OLm with two different layer thicknesses are shown. However, there may be three or more types of insulating layers OL (OLt, OLm...) that are thicker than the other insulating layers OL, each having three or more different layer thicknesses.

[0164] Thus, in the modified laminate LMaa, the thickness of the insulating layer OL (OLt, OLm...) increases towards the center of the laminate LMaa in the stacking direction.

[0165] The laminate LMab has a structure in which multiple word lines WL and multiple insulating layers OL are alternately stacked one layer at a time. Of the multiple insulating layers OL, some insulating layers OLt and OLm on the lower side of the laminate LMab, excluding the bottom insulating layer OL, are thicker than the insulating layers OL on the upper side of the laminate LMm. Furthermore, of these insulating layers OLt and OLm, insulating layer OLt is even thicker than insulating layer OLm.

[0166] More specifically, several insulating layers OLt and OLm are positioned in the laminated LMab at at least one of the height positions within a range of 20% to 50% of the height of the top surface relative to the bottom surface of the laminated LMab, with the top surface being 100% of the bottom surface of the laminated LMab. Furthermore, within the range in which these insulating layers OLt and OLm are positioned, insulating layer OLt is positioned near the center in the stacking direction of the laminated LMab. Insulating layer OLm is positioned above and below insulating layer OLt, respectively.

[0167] In the example shown in Figure 13, two types of insulating layers OLt and OLm with two different layer thicknesses are shown. However, there may be three or more types of insulating layers OL (OLt, OLm...) that are thicker than the other insulating layers OL, each having three or more different layer thicknesses.

[0168] Thus, in the modified laminate LMab, the thickness of the insulating layer OL (OLt, OLm...) increases towards the center of the laminate in the stacking direction of the LMab in several insulating layers OL.

[0169] With the laminated LMm configured as described above, in the modified semiconductor memory device 1a, the pillar PLa placed in the laminated LMaa and the pillar PLb placed in the laminated LMab both have a two-stage bowing shape.

[0170] In other words, pillar PLa has a bowing shape at its upper and lower parts, and the lower bowing shape is positioned at the height of the insulating layers OLt and OLm. Furthermore, the diameter of the bowing shape at the bottom of pillar PLa and the cross-sectional area in the XY plane may be maximized at the height of insulating layer OLt in the center of the stacking direction of the laminate LMaa.

[0171] Furthermore, the pillar PLb has a bowing shape at its upper and lower parts, with the lower bowing shape positioned at the height of the insulating layers OLt and OLm. In addition, the diameter of the bowing shape at the bottom of the pillar PLb and the cross-sectional area in the XY plane may be maximized at the height of the insulating layer OLt in the center of the stacking direction of the laminate LMab.

[0172] Thus, even when the thicknesses of the insulating layers OLt and OLm, which are thicker than the other insulating layer OL, are different, pillars PLa and PLb having a two-stage bowing shape can be formed.

[0173] The laminate LMas, located in the outer peripheral region OR of the semiconductor memory device 1a, maintains the state it was in before the laminate LMm underwent replacement processing. Therefore, the laminate LMas comprises laminates LMasa and LMasub, in which multiple word lines WL and multiple insulating layers OL are alternately stacked one layer at a time. Furthermore, the laminates LMasa and LMasub each have several insulating layers OLt and OLm that are thicker than the other insulating layers OL and have different thicknesses from each other, at positions corresponding to the insulating layers OLt and OLm of the aforementioned laminates LMaa and LMab.

[0174] In the manufacturing method of the modified semiconductor memory device 1a, in several insulating layers OLt and OLm aligned in the stacking direction of the laminate LMaa, the thickness of the insulating layers OLt and OLm increases as you move towards the center of the stacking direction of the laminate LMaa.

[0175] In this way, by making the insulating layers OLm above and below the insulating layer OLt slightly thinner than the insulating layer OLt, the total thickness of several insulating layers OLt and OLm can be reduced to, for example, the total thickness of several insulating layers OLt in Embodiment 1 described above. On the other hand, an insulating layer OLt that is even thicker than the insulating layer OLm is placed near the center of a height position where a bowing shape is easily obtained. This makes it possible to form a two-stage bowing-shaped memory hole MHa while suppressing a decrease in the etching rate.

[0176] Furthermore, by varying the thickness of the insulating layers OLt and OLm as described above, and by positioning the thicker insulating layer OLt closer to the center in the stacking direction than the insulating layer OLm, the bowing shape of the lower part of the memory hole MHa can be controlled with even greater precision.

[0177] The method for manufacturing the modified semiconductor memory device 1a also provides the same effects as the method for manufacturing the semiconductor memory device 1 of Embodiment 1 described above.

[0178] [Embodiment 2] Embodiment 2 will now be described in detail with reference to the drawings. Embodiment 2 differs from Embodiment 1 described above in that the proportion of oxygen contained in the insulating layer NL is increased.

[0179] Figure 14 is a cross-sectional view along the X direction showing an example of the configuration of the semiconductor memory device 2 according to Embodiment 2. Figure 14 shows cross-sections of the pillar PL arranged in the memory region MR and the untreated laminate LMbs arranged in the outer peripheral region OR.

[0180] In Figure 14, components similar to those in Embodiment 1 described above are denoted by the same reference numerals, and their descriptions are omitted.

[0181] As shown in Figure 14, the semiconductor memory device 2 of Embodiment 2 includes a laminate LMn which comprises a first laminate LMba arranged on a source line SL and a third laminate LMbb arranged on the laminate LMba.

[0182] The laminate LMba has a structure in which multiple word wires WL, which serve as first conductive layers, and multiple insulating layers OL, which serve as first insulating layers, are alternately laminated one layer at a time. All of the insulating layers OL of the laminate LMba have substantially equal thickness.

[0183] The laminate LMbb has a structure in which multiple word wires WL, which serve as a second conductive layer, and multiple insulating layers OL, which serve as a third insulating layer, are alternately laminated one layer at a time. All of the insulating layers OL in the laminate LMbb have substantially equal thickness.

[0184] Furthermore, the laminate LMbs, which is located in the outer peripheral region OR of the semiconductor memory device 2, comprises a laminate LMbsa located on the source line SL and a laminate LMbsb located on the laminate LMbsa. In addition, the multiple insulating layers OL, which serve as second insulating layers, provided in the laminates LMbsa and LMbsb, all have substantially equal thickness, similar to the laminates LMba and LMbb described above.

[0185] On the other hand, the laminated LMbsa comprises several insulating layers NL, which are first insulating layers such as silicon nitride layers, and several insulating layers NOL, which are first insulating layers that contain oxygen at a higher ratio than the insulating layers NL on the upper side of the laminated bsa, in place of several insulating layers NL, excluding the bottom insulating layer NL of the laminated LMbsa.

[0186] More specifically, the insulating layer NOL is, for example, a silicon oxynitride layer, and has a thickness approximately equal to that of the other insulating layer NL. Furthermore, in the laminate LMba, the insulating layer NOL is positioned at at least one of the height positions within the range of 20% to 50% of the height of the top surface relative to the bottom surface of the laminate LMbsa, with the top surface being 100%.

[0187] The insulating layer NOL, such as a silicon oxynitride layer, is formed by adding an oxidizing gas such as oxygen (O2) to a silane-based gas such as monosilane (SiH4) and a nitriding gas such as ammonia (NH3), using methods such as plasma CVD.

[0188] Similarly, the laminate LMbsb as a fourth laminate comprises several insulating layers NL as fourth insulating layers, and several insulating layers NOL as fourth insulating layers, which are the lower insulating layers NL of the laminate LMbsb, and which replace some insulating layers NL other than the bottom insulating layer NL of the laminate LMbsb with oxygen in a higher proportion than the insulating layers NL on the upper side of the laminate bsb.

[0189] More specifically, the insulating layer NOL is positioned in the laminate LMbsb at at least one of the height positions within the range of 20% to 50% of the height of the top surface relative to the bottom surface of the laminate LMbsb, with the top surface being 100% of the height of the bottom surface of the laminate LMbsb.

[0190] Here, the laminate LMbs represents the state of the laminate LMn before it undergoes replacement processing. The laminate LMn before replacement processing has several insulating layers NOL containing oxygen on the lower layer side, and when memory holes MHa and MHb are formed by low-temperature plasma etching, the deposit Dsh generated from these insulating layers NOL is less than the deposit Dsh generated from other insulating layers NL.

[0191] Therefore, in the semiconductor memory device 2 of Embodiment 2, both the pillar PLa arranged in the stacked LMba and the pillar PLb arranged in the stacked LMbb have a two-stage bowing shape.

[0192] Specifically, pillar PLa has a first and second Boeing shape at its lower and upper sections, respectively, with the lower Boeing shape positioned at the height of the insulating layer NOL. Pillar PLb also has a third and fourth Boeing shape at its lower and upper sections, respectively, with the lower Boeing shape positioned at the height of the insulating layer NOL.

[0193] Thus, even when the insulating layer NOL, such as a silicon oxynitride layer, is placed in an appropriate position on the laminate LMbs, pillars PLa and PLb having a two-stage bowing shape can be formed.

[0194] At this time, by adjusting the degree of oxidation and the number of layers of the insulating layer NOL included in the laminate LMbs, the bowing shape formed on each pillar PLa, PLb can also be adjusted, and the diameter and bottom area of ​​these pillars PLa, PLb can be widened to the desired size.

[0195] More preferably, the composition of the insulating layer NOL can be adjusted to, for example, a ratio of 30 atm% to 45 atm% silicon, 35 atm% to 55 atm% nitrogen, 20 atm% to 30 atm% hydrogen, and 10 atm% to 20 atm% oxygen.

[0196] According to the manufacturing method of the semiconductor memory device 2 of Embodiment 2, among the plurality of insulating layers NL, some insulating layers NOL on the lower side of the laminated LMbsa, excluding the bottom insulating layer NL of the laminated LMbsa, contain oxygen at a higher ratio than the insulating layers NL on the upper side of the laminated bsa. When forming memory holes MHa, the laminated LMa is etched while depositing a deposit Dsh containing silicon and nitrogen onto the side walls of the memory holes MHa. This makes it possible to form memory holes MHa with a wide bottom diameter under high etching rate conditions.

[0197] According to the manufacturing method of the semiconductor memory device 2 of Embodiment 2, several insulating layers NOL are formed in the laminated LMbsa at a height of 20% to 50% of the height of the uppermost surface relative to the bottommost surface of the laminated LMbsa, with the uppermost surface being 100%.

[0198] In this way, by placing several insulating layers NOL at an appropriate height position before the memory hole MHa reaches the underlying source line DSLb and over-etching begins, the memory hole MHa will have a two-stage bowing shape, which can effectively widen the bottom diameter.

[0199] According to the manufacturing method of the semiconductor memory device 2 of Embodiment 2, several insulating layers NOL are formed so as to contain 30 atm% to 45 atm% silicon, 35 atm% to 55 atm% nitrogen, and 10 atm% to 20 atm% oxygen, respectively.

[0200] In this way, by appropriately adjusting the ratio of nitrogen to oxygen contained in the insulating layer NOL, it is possible to form memory holes MHa with a desired bottom diameter and bottom area.

[0201] The method for manufacturing the semiconductor memory device 2 of Embodiment 2 also provides the same effects as the method for manufacturing the semiconductor memory device 1 of Embodiment 1 described above.

[0202] (modified version) Next, a modified semiconductor memory device 2a of Embodiment 2 will be described using Figure 15. The modified semiconductor memory device 2a differs from Embodiment 2 in that the oxygen ratios of the insulating layers NOL and NOLc are different.

[0203] Figure 15 is a cross-sectional view along the X direction showing an example of the configuration of a semiconductor memory device 2a according to a modified embodiment of Embodiment 2. Figure 15 shows cross-sections of a pillar PL arranged in the memory region MR and an untreated laminate LMcs arranged in the outer peripheral region OR.

[0204] In Figure 15, components similar to those in Embodiment 2 described above are denoted by the same reference numerals, and their descriptions are omitted.

[0205] As shown in Figure 15, the modified semiconductor memory device 2a also comprises a laminate LMn in which the thickness of all insulating layers OL is substantially equal, similar to the embodiment 2 described above. This is also true for the laminate LMcs, which comprises a laminate LMcsa arranged in the outer peripheral region OR and positioned on the source line SL, and a laminate LMcsb positioned on the laminate LMcsa.

[0206] On the other hand, in the laminate LMcsa, some of the insulating layer NOL of the laminate LMbsa of Embodiment 2 described above is an insulating layer NOLc, which is an insulating layer such as a silicon oxynitride layer with a lower oxygen ratio than the insulating layer NOL. More specifically, for example, among the insulating layers NOL and NOLc, which are both silicon oxynitride layers, the degree of oxidation of the insulating layer NOLc is lower than that of the insulating layer NOL.

[0207] More specifically, several insulating layers NOL and NOLc have approximately the same thickness as other insulating layers NL, and in the laminate LMcsa, with the height of the top surface relative to the bottom surface of the laminate LMcsa being 100%, the layers are positioned at at least one of these height positions within the range of 20% to 50%.

[0208] Even in this case, the composition of either the insulating layer NOL or NOLc can be adjusted by varying the oxygen ratio of these insulating layers NOL and NOLc, for example, so that silicon is 30 atm% to 45 atm%, nitrogen is 35 atm% to 55 atm%, hydrogen is 20 atm% to 30 atm%, and oxygen is 10 atm% to 20 atm%.

[0209] Furthermore, within the range where these insulating layers NOL and NOLc are arranged, the insulating layer NOL, which has a high degree of oxidation, is located near the center of the stacking direction of the laminate LMcsa. The insulating layer NOLc, which has a low degree of oxidation, is located above and below the insulating layer NOL, respectively.

[0210] Similarly, in the laminated LMcsb, some of the insulating NOL layers of the laminated LMbsb of Embodiment 2 described above are replaced by insulating NOLc, which is an insulating layer such as a silicon oxynitride layer with a lower oxygen ratio than the insulating NOL layer.

[0211] More specifically, several insulating layers NOL and NOLc are positioned in the laminate LMcsb at at least one of the height positions within a range of 20% to 50% of the height of the top surface relative to the bottom surface of the laminate LMcsb, with the top surface being 100% of the bottom surface of the laminate LMcsb. Furthermore, within the range in which these insulating layers NOL and NOLc are positioned, the insulating layer NOL with a high degree of oxidation is positioned near the center in the lamination direction of the laminate LMcsb. The insulating layer NOLc with a low degree of oxidation is positioned above and below the insulating layer NOL, respectively.

[0212] In the example shown in Figure 15, two types of insulating layers NOL and NOLc, each containing two different oxygen ratios, are shown in the laminates LMcsa and LMcsb, respectively. However, the oxygen-containing insulating layer NOL may be three or more types of insulating layers NOL, each containing three or more different oxygen ratios.

[0213] Thus, in the modified laminates LMcsa and LMcsb, the oxygen ratio of the insulating NOL layer increases towards the center of the laminate in the stacking direction of each of the NOL layers (NOL, NOLc...) in several insulating layers.

[0214] Here, the laminate LMcs represents the state of the laminate LMn before it undergoes replacement processing. By configuring the laminate LMn before replacement processing to have several insulating layers NOL and NOLc with different oxygen ratios on the lower layer side, memory holes MHa and MHb with a two-stage bowing shape can be obtained when forming memory holes MHa and MHb by low-temperature plasma etching.

[0215] In other words, the pillar PLa placed in the laminate LMba has a bowing shape at its lower and upper parts, and the lower bowing shape is positioned at the height of the insulating layers NOL and NOLc. Furthermore, the diameter of the bowing shape at the bottom of the pillar PLa and the cross-sectional area in the XY plane may be maximized at the height of the insulating layer NOL in the center of the laminate direction of the laminate LMba.

[0216] Similarly, the pillar PLb placed in the laminate LMbb has a bowing shape at its lower and upper parts, with the lower bowing shape positioned at the height of the insulating layers NOL and NOLc. Furthermore, the diameter of the bowing shape at the bottom of the pillar PLb and the cross-sectional area in the XY plane may be maximized at the height of the insulating layer NOL in the center of the laminate direction of the laminate LMbb.

[0217] In the manufacturing method of the modified semiconductor memory device 2a, several insulating layers NOL,NOLc are formed such that the proportion of oxygen contained in the NOL,NOLc layers arranged in the stacking direction of the laminate LMcsa increases towards the center of the stacking direction of the laminate LMcsa.

[0218] The insulating layer NOL, which contains oxygen in a predetermined ratio, exhibits a lower etching rate in low-temperature plasma etching compared to the insulating layer NL, which is a silicon nitride layer or the like. On the other hand, as mentioned above, it has been found that the bowing shape of the memory holes MHa is easily obtained at a height position between 20% and 50%, for example, when the height of the top surface of the laminated LMcsa is taken as 100% of the height of the bottom surface of the laminated LMcsa.

[0219] Therefore, by placing a high-oxygen-ratio insulating layer NOL near the center of a height position where a Boeing shape is easily obtained, and by lowering the oxygen ratio of the insulating layers NOLc placed above and below the insulating layer NOL, it is possible to form a two-stage Boeing-shaped memory hole MHa while suppressing a decrease in the etching rate.

[0220] Furthermore, by differentiating the oxygen ratios of the insulating layers NOL and NOLc as described above, and by positioning the insulating layer NOL, which has a higher oxygen ratio, closer to the center in the stacking direction than the insulating layer NOLc, the bowing shape of the lower part of the memory hole MHa can be controlled with even greater precision.

[0221] The method for manufacturing the modified semiconductor memory device 2a also provides the same effects as the method for manufacturing the semiconductor memory device 2 of Embodiment 2 described above.

[0222] [Embodiment 3] Embodiment 3 will now be described in detail with reference to the drawings. Embodiment 3 differs from Embodiment 2 described above in that one insulating layer NOL is composed of different layers.

[0223] As explained below, instead of replacing some insulating layers NL with insulating layers NOL such as a silicon oxynitride layer as in Embodiment 2 described above, it is possible to increase the oxygen ratio in some insulating layers NL by, for example, creating a laminated structure of insulating layers NL and insulating layers NOL.

[0224] Figure 16 is a cross-sectional view along the X direction showing an example of the configuration of the semiconductor memory device 3 according to Embodiment 3. Figure 16 shows cross-sections of the pillar PL arranged in the memory region MR and the untreated laminated LMds arranged in the outer peripheral region OR.

[0225] In Figure 16, components similar to those in Embodiments 1 and 2 described above are denoted by the same reference numerals, and their descriptions are omitted.

[0226] As shown in Figure 16, the semiconductor memory device 3 of Embodiment 3 also comprises a laminate LMn in which the thickness of all insulating layers OL is substantially equal, similar to Embodiment 2 described above. This is also true for the laminate LMds, which comprises a laminate LMdsa arranged in the outer peripheral region OR and positioned on the source line SL, and a laminate LMdsb positioned on the laminate LMdsa.

[0227] On the other hand, the laminate LMdsa has several insulating layers NL / NOL / NL, each consisting of different layers, instead of some insulating layers NOL in the laminate LMbsa of Embodiment 2 described above. That is, each of the several insulating layers NL / NOL / NL has a configuration in which insulating layer NL and insulating layer NOL are laminated, and has a layer thickness approximately equal to that of the other insulating layers NL which consist of only one type of layer.

[0228] More specifically, in each individual insulating layer NL / NOL / NL, insulating layer NOL is positioned in the center of the stacking direction of insulating layer NL / NOL / NL, and insulating layers NL are positioned above and below insulating layer NOL, respectively.

[0229] Furthermore, several insulating layers NL / NOL / NL are positioned in the laminate LMcsa at at least one of the height positions within the range of 20% to 50%, with the height of the top surface relative to the bottom surface of the laminate LMcsa being 100%.

[0230] Similarly, the laminate LMdsb includes several insulating layers NL / NOL / NL, each consisting of different layers, instead of some insulating layers NOL in the laminate LMbsb of Embodiment 2 described above. Furthermore, the several insulating layers NL / NOL / NL are arranged in the laminate LMcsa at at least one of the height positions within the range of 20% to 50% of the height of the top surface relative to the bottom surface of the laminate LMcsa, with the top surface being 100%.

[0231] Here, the laminated LMds represent the state of the laminated LMn before it undergoes replacement processing. Even if the laminated LMn before replacement processing is configured to have several insulating layers NL / NOL / NL with different layers stacked on the lower side, memory holes MHa and MHb having a two-stage bowing shape can be obtained when forming memory holes MHa and MHb by low-temperature plasma etching.

[0232] In other words, the pillar PLa placed in the laminate LMba has a bowing shape at its lower and upper parts, and the lower bowing shape is positioned at the height of the insulating layer NL / NOL / NL. Similarly, the pillar PLb placed in the laminate LMbb has a bowing shape at its lower and upper parts, and the lower bowing shape is positioned at the height of the insulating layer NL / NOL / NL.

[0233] At this time, by adjusting the thickness of each insulating layer NL and NOL contained in the insulating layer NL / NOL / NL, and the oxygen ratio of the insulating layer NOL, the bowing shape formed on each pillar PLa and PLb can also be adjusted, and the diameter and bottom area of ​​these pillars PLa and PLb can be expanded to the desired size.

[0234] In this case, the composition of the insulating layer NOL can also be adjusted, for example, to a ratio of 30 atm% to 45 atm% of silicon, 35 atm% to 55 atm% of nitrogen, 20 atm% to 30 atm% of hydrogen, and 10 atm% to 20 atm% of oxygen.

[0235] According to the manufacturing method of the semiconductor memory device 3 of Embodiment 3, several insulating layers NL / NOL / NL are formed such that each of the several insulating layers NL / NOL / NL has a laminated structure of insulating layer NL and insulating layer NOL. When forming memory holes MHa, the laminate LMa is etched while depositing a silicon and nitrogen-containing deposit Dsh onto the sidewall of the memory hole MHa. This makes it possible to form memory holes MHa with a wide bottom diameter under high etching rate conditions.

[0236] According to the manufacturing method of the semiconductor memory device 3 of Embodiment 3, several insulating layers NL / NOL / NL are formed such that each insulating layer NOL is sandwiched between insulating layers NL in the stacking direction of the laminate LMcsa.

[0237] This makes it possible to reduce the total thickness of the insulating layer NOL included in several insulating layers NL / NOL / NL compared to, for example, the total thickness of several insulating layer NOL in Embodiment 2 described above. Therefore, it is possible to suppress the increase in the thickness of the insulating layer NOL, which has a lower etching rate than the insulating layer NL, and to form memory holes MHa with high throughput.

[0238] The method for manufacturing the semiconductor memory device 3 of Embodiment 3 also provides the same effects as the methods for manufacturing the semiconductor memory devices 1 and 2 of Embodiments 1 and 2 described above.

[0239] (Variation 1) Next, a semiconductor memory device 3a of Modification 1 of Embodiment 3 will be described using Figure 17. The semiconductor memory device 3a of Modification 1 differs from Embodiment 3 in that the thicknesses of the insulating layers NOL and NOLe inserted into the insulating layers NL / NOL / NL and NL / NOLe / NL are different from those of the semiconductor memory device 3a of Modification 1 described above.

[0240] Figure 17 is a cross-sectional view along the X direction showing an example of the configuration of a semiconductor memory device 3a according to a modified example 1 of Embodiment 3. Figure 17 shows cross-sections of a pillar PL arranged in the memory region MR and an untreated laminate LMes arranged in the outer peripheral region OR.

[0241] In Figure 17, components similar to those in Embodiment 3 described above are denoted by the same reference numerals, and their descriptions are omitted.

[0242] As shown in Figure 17, the semiconductor memory device 3a of the modified example 1 also comprises a laminate LMn in which the thickness of all insulating layers OL is substantially equal, similar to the embodiment 3 described above. This is also true for the laminate LMes, which comprises a laminate LMesa arranged in the outer peripheral region OR and positioned on the source line SL, and a laminate LMesub positioned on the laminate LMesa.

[0243] On the other hand, in the LMesa laminate, among several insulating layers NL / NOL / NL and NL / NOLe / NL, the insulating layer NOLe included in insulating layer NL / NOLe / NL is thinner than the insulating layer NOL included in insulating layer NL / NOL / NL. Also, the insulating layer NL included in insulating layer NL / NOLe / NL is thicker than the insulating layer NL included in insulating layer NL / NOL / NL.

[0244] In other words, each insulating layer NL / NOL / NL and NL / NOLe / NL has approximately the same thickness as the other insulating layers NL, and the ratio of the thickness of insulating layer NOL to insulating layer NL in insulating layer NL / NOL / NL is different from the ratio of the thickness of insulating layer NOLe to insulating layer NL in insulating layer NL / NOLe / NL.

[0245] In this case, the composition of both the insulating layer NOL and NOLe can be adjusted, for example, to a ratio of 30 atm% to 45 atm% silicon, 35 atm% to 55 atm% nitrogen, 20 atm% to 30 atm% hydrogen, and 10 atm% to 20 atm% oxygen.

[0246] Thus, in the modified example 1, the laminated LMesa is configured such that, in several insulating layers NL / NOL / NL (NL / NOL / NL, NL / NOLe / NL...), the thickness of the inserted insulating layer NOL increases as you move towards the center of the laminated LMesa in the stacking direction, while the thickness of the insulating layer NL sandwiching the insulating layer NOL above and below decreases.

[0247] Similarly, in the LMeSb laminate, among several insulating layers NL / NOL / NL and NL / NOLe / NL, the insulating layer NOLe included in insulating layer NL / NOLe / NL is thinner than the insulating layer NOL included in insulating layer NL / NOL / NL. Also, the insulating layer NL included in insulating layer NL / NOLe / NL is thicker than the insulating layer NL included in insulating layer NL / NOL / NL.

[0248] In the example shown in Figure 17, two types of insulating layers NL / NOL / NL and NL / NOLe / NL, each with two different layer thickness ratios, are shown in the laminates LMesa and LMeb, ​​respectively. However, the insulating layer NOL inserted into these layers may have three or more different layer thicknesses, resulting in three or more types of insulating layers NL / NOL / NL.

[0249] Thus, in the modified example 1, the laminates LMesa and LMeb are configured such that, in several insulating layers NL / NOL / NL (NL / NOL / NL, NL / NOLe / NL...), the thickness of the inserted insulating layer NOL increases as you move towards the center of each layer in the stacking direction of the laminates LMesa and LMeb, ​​while the thickness of the insulating layer NL sandwiching the insulating layer NOL above and below decreases.

[0250] Here, the laminate LMes represents the state of the laminate LMn before it undergoes replacement processing. By configuring the laminate LMn before replacement processing to include several insulating layers NL / NOL / NL, NL / NOLe / NL with different layer thicknesses of the inserted insulating layers NOL and NOLe, memory holes MHa and MHb with a two-stage bowing shape can be obtained when forming memory holes MHa and MHb by low-temperature plasma etching.

[0251] In other words, the pillars PLa placed in the laminate LMba have bowing shapes at the bottom and top, respectively, and the lower bowing shape is positioned at the height of the insulating layers NL / NOL / NL, NL / NOLe / NL. Furthermore, the diameter of the bowing shape at the bottom of pillars PLa and the cross-sectional area in the XY plane may be maximized at the height of the insulating layer NL / NOL / NL, NL / NOLe / NL.

[0252] Similarly, the pillar PLb placed in the laminate LMbb has a bowing shape at its lower and upper parts, with the lower bowing shape positioned at the height of the insulating layers NL / NOL / NL and NL / NOLe / NL. Furthermore, the diameter of the bowing shape at the bottom of the pillar PLb and the cross-sectional area in the XY plane may be maximized at the height of the insulating layer NL / NOL / NL.

[0253] According to the semiconductor memory device 3a of the modified example 1, in several insulating layers NL / NOL / NL,NL / NOLe / N arranged in the stacking direction of the stacked LMesa, several insulating layers NL / NOL / NL,NL / NOLe / N are formed such that the thickness of the insulating layer NOL increases towards the center in the stacking direction.

[0254] Thus, by making the insulating layer NOL inserted into the insulating layer NL / NOL / NL near the center of the height position where the Boeing shape is easily obtained thicker, and by making the insulating layer NOLe of the upper and lower insulating layers NL / NOLe / NL thinner, it is possible to form a two-stage Boeing-shaped memory hole MHa while suppressing a decrease in etching rate, similar to the modified example of Embodiment 2 described above.

[0255] Furthermore, as described above, by varying the thickness of the insulating layers NOL and NOLe inserted into the insulating layers NL / NOL / NL and NL / NOLe / NL, and by positioning the thicker insulating layer NOL closer to the center in the stacking direction than the insulating layer NOLe, the bowing shape of the lower part of the memory hole MHa can be controlled with even greater precision.

[0256] The method for manufacturing the semiconductor memory device 3a of the modified example 1 also provides the same effects as the method for manufacturing the semiconductor memory device 3 of the embodiment 3 described above.

[0257] (Modification 2) Next, a semiconductor memory device 3b of modified embodiment 3, part 2, will be described using Figure 18. The semiconductor memory device 3b of modified embodiment 2 differs from embodiment 3 in that it has an insulating layer NOLm formed by stacking multiple insulating layers NL and multiple insulating layers NOL.

[0258] Figure 18 is a cross-sectional view along the X direction showing an example of the configuration of a semiconductor memory device 3b according to a modified example 2 of Embodiment 3. Figure 18(a) shows a cross-section of a pillar PL arranged in the memory region MR and an untreated laminate LMfs arranged in the outer peripheral region OR. Figure 18(b) shows a partially enlarged view of the insulating layer NOLm provided by the laminate LMfs.

[0259] In Figure 18, components similar to those in Embodiment 3 described above are denoted by the same reference numerals, and their descriptions are omitted.

[0260] As shown in Figure 18, the semiconductor memory device 3b of the modified example 2 also comprises a laminate LMn in which the thickness of all insulating layers OL is substantially equal, similar to the embodiment 3 described above. This is also true for the laminate LMfs, which comprises a laminate LMfsa arranged in the outer peripheral region OR and positioned on the source line SL, and a laminate LMfsb positioned on the laminate LMfsa.

[0261] On the other hand, the laminate LMfsa has several insulating layers NOLm instead of several insulating layers NL / NOL / NL in the laminate LMdsa of Embodiment 3 described above. Similarly, the laminate LMfsb has several insulating layers NOLm instead of several insulating layers NL / NOL / NL in the laminate LMdsb of Embodiment 3 described above.

[0262] Each of these insulating layers NOLm has a structure in which multiple insulating layers NL and multiple insulating layers NOL are alternately stacked one layer at a time. The bottom layer and bottom layer of each insulating layer NOLm are insulated with insulating layers NL.

[0263] Such a laminated insulating layer NOLm can be formed, for example, by using plasma CVD, to intermittently add an oxidizing gas such as oxygen (O2) to a silane-based gas such as monosilane (SiH4) and a nitriding gas such as ammonia (NH3).

[0264] Here, the laminate LMfs represents the state of the laminate LMn before it undergoes replacement processing. By configuring the laminate LMn before replacement processing to include several insulating layers NOLm, memory holes MHa and MHb with a two-stage bowing shape can be obtained when memory holes MHa and MHb are formed by low-temperature plasma etching.

[0265] In other words, the pillar PLa placed in the laminate LMba has a bowing shape at its upper and lower ends, with the lower bowing shape positioned at the height of the insulating layer NOLm. Similarly, the pillar PLb placed in the laminate LMbb has a bowing shape at its upper and lower ends, with the lower bowing shape positioned at the height of the insulating layer NOLm.

[0266] According to the manufacturing method of the semiconductor memory device 3b of the modified example 2, several insulating layers NOLm are formed such that a structure is formed in which multiple insulating layers NL and multiple insulating layers NOL are alternately stacked one layer at a time. This allows for more precise adjustment of the oxygen ratio in the insulating layer NOLm, and enables more precise control of the bowing shape below the memory hole MHa.

[0267] The method for manufacturing the semiconductor memory device 3b of the modified example 2 also provides the same effects as the method for manufacturing the semiconductor memory device 3 of the embodiment 3 described above.

[0268] (Variation 3) Next, the semiconductor memory device 3c of Modification 3 of Embodiment 3 will be described using FIG. 19. The semiconductor memory device 3c of Modification 3 is different from Embodiment 3 described above in that it has an insulating layer NOLg in which a plurality of insulating layers NL and a plurality of insulating layers NOL are laminated at different intervals.

[0269] FIG. 19 is a cross-sectional view along the X direction showing an example of the configuration of the semiconductor memory device 3c according to Modification 3 of Embodiment 3. FIG. 19(a) shows a cross-section of a pillar PL disposed in the memory region MR and an unprocessed laminate LMgs disposed in the outer peripheral region OR. FIG. 19(b) shows a partially enlarged view of the insulating layer NOLg included in the laminate LMgs.

[0270] In FIG. 19, the same components as those in Embodiment 3 described above are denoted by the same reference numerals, and the description thereof is omitted.

[0271] As shown in FIG. 19, the semiconductor memory device 3c of Modification 3 also includes a laminate LMn in which the thicknesses of all the insulating layers OL are substantially equal, similar to Embodiment 3 described above. This also applies to the laminate LMgs including a laminate LMgsa disposed in the outer peripheral region OR and on the source line SL, and a laminate LMgsb disposed on the laminate LMgsa.

[0272] On the other hand, the laminate LMgsa includes some insulating layers NOLg each having a structure in which a plurality of insulating layers NL and a plurality of insulating layers NOL are alternately laminated one by one, instead of some of the insulating layers NL / NOL / NL of the laminate LMdsa of Embodiment 3 described above.

[0273] Similarly, the laminate LMgsb includes some insulating layers NOLg each having a structure in which a plurality of insulating layers NL and a plurality of insulating layers NOL are alternately laminated one by one, instead of some of the insulating layers NL / NOL / NL of the laminate LMdsb of Embodiment 3 described above.

[0274] In each of these insulating layers NOLg, a plurality of insulating layers NL have different layer thicknesses within one insulating layer NOLg, and the insulating layer NL becomes thinner toward the center in the stacking direction of the insulating layer NOLg. That is, the distance between the insulating layers NOL becomes narrower toward the center in the stacking direction of the insulating layer NOLg.

[0275] Here, the laminate LMgs shows the state before the laminate LMn undergoes the replacement process. Even when the laminate LMn before the replacement process is configured to include several insulating layers NOLg, when forming the memory holes MHa and MHb by low-temperature plasma etching, memory holes MHa and MHb having a two-stage bowing shape can be obtained.

[0276] That is, the pillar PLa disposed in the laminate LMba has a bowing shape at both the upper and lower portions, and among these, the lower bowing shape is disposed at the height position of the insulating layer NOLg. Similarly, the pillar PLb disposed in the laminate LMbb has a bowing shape at both the upper and lower portions, and among these, the lower bowing shape is disposed at the height position of the insulating layer NOLg.

[0277] According to the manufacturing method of the semiconductor memory device 3c of Modification 3, several insulating layers NOLg are formed such that the ratio of the insulating layer NOL among the plurality of insulating layers NL and the plurality of insulating layers NOL increases toward the central portion in the layer thickness direction of several insulating layers NOLg.

[0278] Thereby, in the thickness direction of one insulating layer NOLg, the oxygen ratio of the insulating layer NOLg can be increased in the central portion where the deposit Dsh is more likely to adhere, and the deposit Dsh can be reduced.

[0279] According to the manufacturing method of the semiconductor memory device 3c of Modification 3, among others, the same effects as those of the manufacturing method of the semiconductor memory device 3 of Embodiment 3 described above are achieved.

[0280] [Other Embodiments] In the embodiments 1 to 3 described above and their variations, the pillar PL is connected to the source line SL on the side of the channel layer CN, but this is not limited to this configuration. For example, the pillar may be configured such that the memory layer on the bottom surface of the pillar is removed and the source line is connected at the lower end of the channel layer.

[0281] Furthermore, in the embodiments 1 to 3 described above and their variations, the laminate LM etc. is laminated in two stages, resulting in a laminate LM with a 2-tier structure including laminates LMa, LMb, etc. However, the laminate may have a 1-tier structure, or a structure with 3 or more tiers. By increasing the number of tiers, the number of laminated word lines WL can be further increased.

[0282] When the laminate has a 1-tier structure, any of the configurations described in embodiments 1 to 3 and their variations can be applied to the lower layer of the entire laminate. This results in the formation of a pillar that penetrates the entire laminate and has a two-stage bowing shape on the upper and lower layers.

[0283] When the laminate has a multi-tier structure of 3 tiers or more, any of the configurations of embodiments 1 to 3 described above and their variations can be applied to each laminate constituting an individual tier. As a result, a pillar having a two-stage bowing shape is formed at the bottom and top for each laminate constituting an individual tier.

[0284] Furthermore, in the embodiments 1 to 3 described above and their variations, the configuration including the laminated LM and the peripheral circuit PER are formed on separate substrates and then bonded together. However, the configuration of the semiconductor memory device is not limited to this, and the configuration including the laminated LM and the peripheral circuit PER may be directly formed on the semiconductor substrate SB on which the peripheral circuit PER is formed.

[0285] In this case, the laminated structure LM, etc., can be formed on a semiconductor substrate SB away from the area where the peripheral circuit PER is formed. Alternatively, the laminated structure LM, etc., can be formed on the insulating layer 40 shown in Figure 11, so that the configuration including the laminated structure LM, etc., is positioned above the peripheral circuit PER. The methods of embodiments 1 to 3 described above and their modified forms are also applicable to semiconductor memory devices having these configurations.

[0286] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of symbols]

[0287] 1,1a,2,2a,3,3a,3b,3c... Semiconductor memory devices, LM,LMa,LMas,LMb,LMbs,LMcs,LMds,LMes,LMfs,LMgs,LMm,LMn,LMsa,LMsb... Stacked structures, MC... Memory cells, NL,NOL,NOLc,NOLm,NOLe,OL,OLm,OLt... Insulating layers, OR... Peripheral regions, PL,PLa,PLb... Pillars, WL... Word lines.

Claims

1. The lower layer membrane, A first laminate is disposed above the aforementioned lower layer film, and is formed by alternately stacking a plurality of first conductive layers and a plurality of first insulating layers one layer at a time. The first pillar penetrates the first laminate and reaches the lower layer, with memory cells formed at the intersections with the plurality of first conductive layers, The plurality of first insulating layers are oxide layers, Of the plurality of first insulating layers, at least one first insulating layer located in a first region in the stacking direction of the first laminate, excluding the bottommost first insulating layer of the first laminate, is thicker than the first insulating layer located in a second region above the first region. The first insulating layer, which has been made thicker, In the first laminate, the uppermost surface is positioned at a height of 20% to 50% of the lowermost surface of the first laminate, with the uppermost surface being 100% of the lowermost surface. The first pillar is, The first laminate has a first bowing shape at a height position of the first insulating layer with increased thickness, The first laminate has a second bowing shape at the height position of the first insulating layer in the second region of the first laminate, Semiconductor memory device.

2. The lower layer film and A first laminate is disposed above the aforementioned lower layer film, and is formed by alternately stacking a plurality of first conductive layers and a plurality of first insulating layers one layer at a time. The first pillar penetrates the first laminate and reaches the lower layer, with memory cells formed at the intersections with the plurality of first conductive layers, Of the plurality of first insulating layers, at least one first insulating layer located in a first region in the stacking direction of the first laminate, excluding the bottommost first insulating layer of the first laminate, is thicker than the first insulating layer located in a second region above the first region. The increased thickness of the first insulating layer is a number of first insulating layers arranged in the stacking direction of the first laminate, In the aforementioned several first insulating layers, the thickness of the first insulating layer increases towards the center in the lamination direction. The first pillar is, The first laminate has a first bowing shape at a height position of the first insulating layer with increased thickness, The first laminate has a second bowing shape at the height position of the first insulating layer in the second region of the first laminate, Semiconductor memory device.

3. The underlying membrane, A first laminate is disposed above the aforementioned lower layer film, and is formed by alternately stacking a plurality of first conductive layers and a plurality of first insulating layers one layer at a time. A first pillar that penetrates the first laminate and reaches the lower layer, with memory cells formed at each intersection with the plurality of first conductive layers, The present invention comprises a second laminate positioned above the lower layer film at a distance from the first laminate, in which a plurality of second insulating layers and the plurality of first insulating layers are alternately laminated one layer at a time, The plurality of second insulating layers contain at least nitrogen, Among the plurality of second insulating layers, a second insulating layer located in a first region in the stacking direction of the second laminate contains oxygen at a higher ratio than a second insulating layer located in a second region above the first region, excluding the second insulating layer at the bottom of the second laminate. In the second insulating layer, which has an increased oxygen ratio and is aligned in the stacking direction of the second laminate, the proportion of oxygen contained increases towards the center in the stacking direction. The first pillar is, Among the plurality of first conductive layers, the first conductive layer that is positioned at the same height as the second insulating layer with a higher oxygen ratio has a first bowing shape at the height position, Among the plurality of first conductive layers, the other first conductive layer, which is positioned at the same height as the second insulating layer in the second region, has a second bowing shape at the height of the other first conductive layer. Semiconductor memory device.

4. The lower layer film and A first laminate is disposed above the aforementioned lower layer film, and is formed by alternately stacking a plurality of first conductive layers and a plurality of first insulating layers one layer at a time. A first pillar that penetrates the first laminate and reaches the lower layer, with memory cells formed at each intersection with the plurality of first conductive layers, The present invention comprises a second laminate positioned above the lower layer film at a distance from the first laminate, in which a plurality of second insulating layers and the plurality of first insulating layers are alternately laminated one layer at a time, The plurality of second insulating layers contain at least nitrogen, Among the plurality of second insulating layers, a second insulating layer located in a first region in the stacking direction of the second laminate contains oxygen at a higher ratio than a second insulating layer located in a second region above the first region, excluding the second insulating layer at the bottom of the second laminate. Each of the second insulating layers with an increased oxygen ratio has a laminated structure of a nitrided layer and an oxynitride layer. The first pillar is, Among the plurality of first conductive layers, the first conductive layer that is positioned at the same height as the second insulating layer with a higher oxygen ratio has a first bowing shape at the height position, Among the plurality of first conductive layers, the other first conductive layer, which is positioned at the same height as the second insulating layer in the second region, has a second bowing shape at the height of the other first conductive layer. Semiconductor memory device.

5. A laminate is formed in which multiple first insulating layers and multiple second insulating layers are stacked alternately, one layer at a time. A method for manufacturing a semiconductor memory device, comprising forming a pillar in which a plurality of memory cells are formed within a hole penetrating the aforementioned stack, Each of the aforementioned plurality of first insulating layers is a layer in which the first element has been nitrided. Each of the plurality of second insulating layers is a layer in which the first element has been oxidized. When forming the aforementioned laminate, Among the plurality of second insulating layers, a second insulating layer located in a first region in the stacking direction of the laminate, wherein at least one second insulating layer, excluding the second insulating layer of the lowest layer of the laminate, is formed to be thicker than the second insulating layer in a second region located above the first region among the plurality of second insulating layers. The first insulating layer, which has been made thicker, In the laminate, with the height of the top surface relative to the bottom surface of the laminate being 100%, the components are positioned at a height of 20% to 50%. When forming the aforementioned hole, The laminate is etched while depositing a deposit containing the first element and nitrogen onto the side walls of the holes. A method for manufacturing semiconductor memory devices.

6. A laminate is formed in which multiple first insulating layers and multiple second insulating layers are stacked alternately, one layer at a time. A method for manufacturing a semiconductor memory device, comprising forming a pillar in which a plurality of memory cells are formed within a hole penetrating the aforementioned stack, Each of the aforementioned plurality of first insulating layers is a layer in which the first element has been nitrided. Each of the plurality of second insulating layers is a layer in which the first element has been oxidized. When forming the aforementioned laminate, A first insulating layer among the plurality of first insulating layers located in a first region in the stacking direction of the laminate, wherein at least one of the first insulating layers, excluding the bottommost first insulating layer of the laminate, contains oxygen at a higher ratio than the first insulating layer in a second region located above the first region among the plurality of first insulating layers. In the first insulating layer with an increased oxygen ratio, which is arranged in the stacking direction of the laminate, the first insulating layer with an increased oxygen ratio is formed such that the proportion of oxygen contained increases towards the center in the stacking direction. When forming the aforementioned hole, The laminate is etched while depositing a deposit containing the first element and nitrogen onto the side walls of the holes. A method for manufacturing semiconductor memory devices.

7. Each of the first insulating layers with an increased oxygen ratio, The first element in an amount of 30 atm% or more and 45 atm% or less, Nitrogen in concentrations of 35 atm% to 55 atm%, The first insulating layer is formed with an increased oxygen ratio, containing 10 atm% to 20 atm% of oxygen. The method for manufacturing a semiconductor memory device according to claim 6.

8. Each of the first insulating layers with an increased oxygen ratio is an oxynitride layer. The method for manufacturing a semiconductor memory device according to claim 6.

9. A laminate is formed in which a plurality of first insulating layers and a plurality of second insulating layers are alternately stacked one layer at a time. A method for manufacturing a semiconductor memory device, comprising forming a pillar in which a plurality of memory cells are formed within a hole penetrating the aforementioned stack, Each of the aforementioned plurality of first insulating layers is a layer in which the first element has been nitrided. Each of the plurality of second insulating layers is a layer in which the first element has been oxidized. When forming the aforementioned laminate, A first insulating layer among the plurality of first insulating layers located in a first region in the stacking direction of the laminate, wherein at least one of the first insulating layers, excluding the bottommost first insulating layer of the laminate, contains oxygen at a higher ratio than the first insulating layer in a second region located above the first region among the plurality of first insulating layers. Each of the first insulating layers with an increased oxygen ratio is formed such that it has a laminated structure of a nitrided layer and an oxynitrided layer. When forming the aforementioned hole, The laminate is etched while depositing a deposit containing the first element and nitrogen onto the side walls of the holes. A method for manufacturing semiconductor memory devices.

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