Method for manufacturing a semiconductor light-emitting element and semiconductor light-emitting element

Abstract

The present invention provides a semiconductor light-emitting element and a method for manufacturing a semiconductor light-emitting element that suppresses the generation of leakage current in the reverse bias direction. [Solution] A method for manufacturing a semiconductor light-emitting element, comprising: a bonding step of bonding a support substrate to an intermediate electrode layer having a dielectric portion and a semiconductor laminate via a metal bonding layer; a mesa formation step of etching the semiconductor laminate to form a street region on the intermediate electrode layer where the dielectric portion is exposed on the surface; and a dicing step of cutting the support, which comprises a support substrate, a metal bonding layer and an intermediate electrode layer, by irradiating the street region with a laser, wherein, in a top view, the average value of the distance L between the outer edge of the mesa-shaped upper surface after the dicing step and the outer edge of the upper surface of the support is 14 μm or more and 20 μm or less.

Description

[Technical Field]

[0001] This invention relates to a method for manufacturing a semiconductor light-emitting element and a semiconductor light-emitting element. [Background technology]

[0002] In semiconductor manufacturing, blade dicing has traditionally been widely used in the dicing process. However, because blade dicing physically cuts the workpiece, it is prone to chipping, where the chip end face breaks off, and can also negatively affect device characteristics and cause appearance defects. In recent years, laser dicing has been proposed as an alternative to blade dicing. Laser dicing does not involve physical dicing with a blade, so it is expected to improve the incidence of chipping and appearance defects. It is also expected to suppress the negative effects on device characteristics caused by mechanical damage.

[0003] For example, Patent Document 1 discloses a method for manufacturing a device chip by irradiating a pulsed laser beam from the side of a wafer substrate that is covered with a film. Patent Document 1 also discloses a step for removing the film, taking into account the thermal effects when the laser beam is irradiated, and mentions design guidelines for the street region, which is the line to be divided. [Prior art documents] [Patent Documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2022-054232 [Overview of the Initiative] [Problems that the invention aims to solve]

[0005] Patent Document 1 discloses design guidelines for cases where a single material such as silicon or sapphire is used as the support substrate, but it does not disclose the case where the laser dicing method is applied to a support substrate junction type semiconductor light-emitting element that includes a metal junction layer. The inventors of the present invention considered that when laser dicing a support substrate junction type semiconductor light-emitting element, the heat generated during dicing of the metal portion may affect the element characteristics. In fact, the inventors of the present invention experimentally confirmed that when laser dicing is used in a support substrate junction type semiconductor light-emitting element, leakage current may occur in the reverse bias direction.

[0006] Therefore, the present invention aims to provide a method for manufacturing a semiconductor light-emitting element and a semiconductor light-emitting element that can suppress the generation of leakage current in the reverse bias direction in a support substrate junction type semiconductor light-emitting element that includes a metal junction layer in between. [Means for solving the problem]

[0007] The inventors of the present invention have conducted extensive research to achieve the above-mentioned objectives and have found that in devices with low leakage current, when the semiconductor light-emitting element is viewed from above, the distance between the outer edge of the semiconductor laminate top surface (described later) and the corresponding outer edge of the support top surface is above a certain level. Therefore, they have found that by ensuring a sufficient street region (described later) during the manufacturing process of the semiconductor light-emitting element, and by ensuring that the distance between the outer edge of the mesa-shaped top surface (described later) and the outer edge of the support top surface is above a certain level when the semiconductor light-emitting element is viewed from above, it is possible to obtain a semiconductor light-emitting element that suppresses the generation of leakage current in the reverse bias direction during dicing.

[0008] In other words, the gist of the present invention is as follows: (1) A bonding step of bonding a support substrate to an intermediate electrode layer having a dielectric portion and a semiconductor laminate through a metal bonding layer; a mesa forming step of forming a mesa shape by etching the semiconductor laminate while forming a street region on the intermediate electrode layer where the dielectric portion is exposed on the surface; and a dicing step of cutting the support by irradiating a laser into the street region with respect to the support including the support substrate, the metal bonding layer, and the intermediate electrode layer. In a top view, an average value of a distance L between an outer edge of an upper surface of the mesa shape after the dicing step and an outer edge of the upper surface of the support is 14 μm or more and 20 μm or less. A method for manufacturing a semiconductor light-emitting device, characterized by this.

[0009] (2) The method for manufacturing a semiconductor light-emitting device according to (1) above, further including a step of forming a protective film on the upper surface of the mesa shape excluding the central portion of the upper surface of the upper surface electrode provided on the upper portion of the semiconductor laminate and the side surface of the mesa shape between the mesa forming step and the dicing step.

[0010] (3) The method for manufacturing a semiconductor light-emitting device according to (1) or (2) above, wherein a minimum value of the distance L between the outer edge of the upper surface of the mesa shape and the outer edge of the upper surface of the support is 11.5 μm or more.

[0011] (4) The method for manufacturing a semiconductor light-emitting device according to (1) to (3) above, wherein a light emission wavelength of the semiconductor laminate is 1000 nm or more and 2400 nm or less.

[0012] (5) The method for manufacturing a semiconductor light-emitting device according to (1) to (4) above, wherein a thickness of the metal bonding layer in the support is 1500 nm or more and 4000 nm or less.

[0013] (6) A semiconductor light-emitting device including a support in which an intermediate electrode layer having a dielectric portion is laminated on a support substrate through a metal bonding layer, and a semiconductor laminate formed on the support. The semiconductor laminate has a mesa shape. In a top view, the upper surface of the support is present around the mesa shape, and an average value of a distance L between an outer edge of the upper surface of the mesa shape and an outer edge of the upper surface of the support is 14 μm or more and 20 μm or less.

[0014] (7) A protective film is formed on the mesa-shaped upper surface and the side surface of the mesa shape excluding the central portion of the upper surface of the upper surface electrode provided on the upper portion of the semiconductor laminate, and the protective film is exposed on the upper surface of the support, or the dielectric portion is exposed. The semiconductor light-emitting device according to (6) above.

[0015] (8) The minimum value of the distance L between the outer edge of the mesa-shaped upper surface and the outer edge of the upper surface of the support is 11.5 μm or more. The semiconductor light-emitting device according to (6) or (7) above.

[0016] (9) The emission wavelength of the semiconductor laminate is 1000 nm or more and 2400 nm or less. The semiconductor light-emitting device according to (6) to (8) above.

[0017] (10) The thickness of the metal bonding layer in the support is 1500 nm or more and 4000 nm or less. The semiconductor light-emitting device according to (6) to (9) above. <D [Effect of the Invention]

[0018] According to the present invention, it is possible to provide a method for manufacturing a semiconductor light-emitting device and a semiconductor light-emitting device that can suppress the generation of leakage current in the reverse bias direction. [Brief Description of the Drawings]

[0019] [Figure 1] It is a top view of a semiconductor light-emitting device according to an embodiment of the present invention. [Figure 2A] It is a schematic cross-sectional view for explaining a method for manufacturing a semiconductor light-emitting device according to an embodiment of the present invention. [Figure 2B] It is a schematic cross-sectional view for explaining a method for manufacturing a semiconductor light-emitting device following FIG. 2A. [Figure 2C] It is a schematic cross-sectional view for explaining a method for manufacturing a semiconductor light-emitting device following FIG. 2B. [Figure 2D] It is a schematic cross-sectional view for explaining a method for manufacturing a semiconductor light-emitting device following FIG. 2C. [Figure 2E]This is a schematic cross-sectional diagram illustrating the manufacturing method of a semiconductor light-emitting element, following Figure 2D. [Figure 2F] Figure 2E is a schematic cross-sectional diagram illustrating the manufacturing method of a semiconductor light-emitting element. [Figure 2G] Figure 2F is a schematic cross-sectional diagram illustrating the manufacturing method of a semiconductor light-emitting element. [Figure 3] This is a schematic cross-sectional view showing the structure of a semiconductor light-emitting element according to one embodiment of the present invention. [Modes for carrying out the invention]

[0020] Prior to describing embodiments according to the present invention, the following points will be explained.

[0021] Referring to Figure 1, the "distance L between the outer edge of the mesa-shaped upper surface and the outer edge of the support upper surface in a top view after the dicing process" in this embodiment will be explained.

[0022] First, in this embodiment, the mesa shape refers to a plateau-like shape with exposed top and side surfaces. The top surface of the mesa shape (also referred to as the mesa shape top surface) is substantially flat and may have rough surface areas. The side surfaces of the mesa shape (also referred to as the mesa shape side surfaces) may be vertical or inclined. Furthermore, the side surfaces may be a forward mesa that widens downward from the top surface, or a reverse mesa that narrows downward from the top surface. Below the mesa shape is a support structure, and the top surface of the support structure surrounds the mesa shape. As shown in Figure 1, in a top view, the top surface of the mesa shape is enclosed within the top surface of the support structure surrounding the mesa shape. Note that, as will be described later, if a protective film is formed, the mesa shape after the dicing process will include the protective film.

[0023] Next, the "distance L" in this embodiment will be explained with reference to Figure 1. In this embodiment, "distance L" is the shortest distance between any point on the outer edge of the mesa-shaped upper surface enclosed within the upper surface of the support 300 when the semiconductor light-emitting element 1 is viewed from above, and any point on the outer edge of the upper surface of the support 300. If the shape of the outer edge of the support 300 or the mesa-shaped upper surface is not rectangular, the shortest distance over the entire outer edge of the mesa shape is taken as "distance L," and the average and minimum values ​​are calculated. If the shape of the outer edges of both the support 300 and the mesa-shaped upper surface is rectangular, and the sides of the outer edge of the mesa-shaped upper surface and the sides of the outer edge of the support upper surface are parallel, the average and minimum values ​​can be calculated based on the representative values ​​of each of the four sides as shown in Figure 1. Specifically, the average and minimum values ​​of the measured distances between each of the four sides of the mesa-shaped upper surface and each of the corresponding parallel sides of the four sides of the support upper surface are determined. The average value is, for example, the arithmetic mean of distances A, B, C, and D in Figure 1. If the outer edges of both sides are parallel, then any one measurement point is sufficient on each side. Also, in a top view, a portion of the dielectric part 82 (or protective film 70) of the exposed intermediate electrode layer 80 is observed as the top surface of the support 300.

[0024] In this embodiment, the reverse bias current (Ir) and reverse bias voltage (Vr) can be measured using a constant current voltage device after removing the semiconductor element after dicing, mounting it on a transistor outline header (e.g., TO-18) using silver paste, and bonding the top electrode with gold wire. The number of measurement points is, for example, 10.

[0025] In this embodiment, "InGaAlAsPSb" is defined as follows, where the composition ratios of In, Ga, and Al are a, b, and 1-a-b, respectively, and the composition ratios of As, P, and Sb are x, y, and 1-xy, respectively, In a Ga b Al 1-a―b As x P y S 1-x-yThis means that. In this embodiment, the In composition ratio a and Ga composition ratio b, as well as the Al composition ratio x and P composition ratio y of the InGaAlAsPSb composition ratio, are determined from the wavelengths observed by photoluminescence measurements performed on the surface of each layer when each layer was grown. Unless otherwise specified, the In composition ratio a and Ga composition ratio b are between 0 and 1 and between 0 and 0 ≤ 1-a-b ≤ 1. Similarly, unless otherwise specified, the Al composition ratio x and Sb composition ratio y are between 0 and 1 and between 0 and 0 ≤ 1-x-y ≤ 1.

[0026] In this specification, "undoped" refers to a state in which specific dopants such as Si, S, and Zn are not intentionally added. Unavoidable dopant contamination during the manufacturing process is acceptable in the undoped layer.

[0027] The following describes one embodiment of the present invention.

[0028] (Method of manufacturing semiconductor hibi) A method for manufacturing a semiconductor light-emitting element according to this embodiment will be described.

[0029] Figures 2A to 2G are process diagrams of the manufacturing method of a semiconductor light-emitting element according to this embodiment. These schematically illustrate a part of the cross-section of the growth substrate, and for the sake of explanation, the intermediate electrode layer and electrodes are simplified in the illustration, and the aspect ratio of the substrate and each layer is also exaggerated from reality. The semiconductor light-emitting element according to this embodiment includes at least a bonding step (Figures 2A to 2C) in which a support substrate 190 is bonded to an intermediate electrode layer 80 having a dielectric portion 82 and a semiconductor laminate 200 via a metal bonding layer 90; a mesa formation step (Figure 2F) in which the semiconductor laminate 200 is etched to form a mesa shape while street regions on the surface of the intermediate electrode layer 80 are formed; and a dicing step (Figure 3) in which the support 300, which comprises the support substrate 190, the metal bonding layer 90 and the intermediate electrode layer 80, is cut by irradiating the street regions with a laser. This manufacturing method may further include a step between the mesa formation step and the dicing step of forming a protective film 70 on the mesa-shaped upper surface and mesa-shaped side surfaces of the upper electrode 170 provided on the upper part of the semiconductor laminate 200, excluding the central part of the upper surface (Figure 2F). In addition, in the manufacturing method of the semiconductor light-emitting element 1 according to this embodiment, first, a semiconductor layer including the semiconductor laminate 200 may be formed by epitaxial growth (Figure 2A). The details of the embodiment, including optional steps, will be described below.

[0030] <Joining process> <<Semiconductor Laminate>> As shown in Figure 2A, a semiconductor layer including a semiconductor laminate 200 is formed on a growth substrate 10. In the example in Figure 2A, a buffer layer 20 and an etching stop layer 30 are provided on the growth substrate 10. After the bonding process, it is preferable to etch the semiconductor layers other than the semiconductor laminate 200, namely the growth substrate 10, buffer layer 20, and etching stop layer 30, leaving only the semiconductor laminate 200 (Figure 2C). However, the etching stop layer 30 may also be left and used as a layer constituting the semiconductor laminate 200. In the figure, for simplicity, the etching stop layer 30 is also removed. As the growth substrate 10, a compound substrate such as GaAs, InP, or InAs can be used, and the growth substrate 10 can be manufactured according to a conventional method. The conductivity type of the growth substrate 10 can be n-type, p-type, or undoped, and each semiconductor layer can be appropriately provided according to each conductivity type. For simplicity of explanation, the growth substrate 10 will be described below as being n-type doped. The thickness of the growth substrate 10 is preferably 200 μm or more and 900 μm or less. Below, each semiconductor layer when the growth substrate 10 is n-type doped will be briefly described as an example.

[0031] It is preferable to epitaxially grow a buffer layer 20 on the growth substrate 10. The buffer layer 20 plays a role in mitigating lattice mismatch between the growth substrate 10 and the etching stop layer 30, which will be described later. The buffer layer 20 can be formed, for example, by metal-organic chemical vapor deposition (MOCVD). The thickness of the buffer layer 20 is preferably 0.01 μm or more and 0.5 μm or less, and it is preferably n-type doped. Here, the element to be doped into the buffer layer 20 is Si, etc. Next, the etching stop layer 30 is laminated on the buffer layer 20. It is preferable that the etching stop layer 30 is not etched under conditions that etch the growth substrate 10 and the buffer layer 20, and has a composition that is lattice-matched with the second conductivity type layer 40. The thickness of the etching stop layer 30 is preferably 0.01 μm or more and 0.1 μm or less, and more preferably 0.02 μm or more and 0.05 μm or less. Furthermore, the etching stop layer 30 is preferably n-type doped, and the elements used for doping here include Si. Next, a second conductivity layer 40 is laminated on the etching stop layer 30. The thickness of the second conductivity layer 40 should be sufficient to supply carriers, and is preferably, for example, 2 μm or more and 10 μm or less. The second conductivity layer 40 can be an n-type doped semiconductor layer, and the elements used for doping here include Si.

[0032] Furthermore, an active layer 50 is laminated on the second conductive layer 40. The active layer 50 preferably contains one or more of Al, Ga, and In as Group III elements, and one or more of As, Sb, and P as Group V elements. The active layer 50 may be a single layer structure, a double hetero (DH) structure, or a multiple quantum well structure in which multiple barrier layers and well layers are alternately laminated.

[0033] Next, a first conductivity layer 60 is laminated on the active layer 50. The first conductivity layer 60 may have an electron blocking layer on the active layer 50 side. The first conductivity layer 60 preferably contains one or more of Al, Ga, and In as Group III elements, and one or more of As, Sb, and P as Group V elements. The thickness of the first conductivity layer 60 is preferably 0.4 μm to 5 μm, and more preferably 1 μm to 3 μm. Furthermore, the first conductivity layer 60 is preferably p-type doped, and the element used for doping here may be Zn, etc. In this example, the semiconductor layers (second conductivity layer 40 to first conductivity layer 60) laminated above the etching stop layer 30 on the growth substrate 10 constitute the semiconductor laminate 200. The emission wavelength of the semiconductor laminate 200 is preferably between 1000 nm and 2400 nm, more preferably between 1200 nm and 2000 nm, and even more preferably between 1300 nm and 1600 nm.

[0034] <<Intermediate electrode layer>> Next, an intermediate electrode layer 80 is formed on the first conductivity type layer 60. First, it is preferable to coat the entire surface of the first conductivity type layer 60 with a resist. The resist is patterned in a predetermined shape by photolithography, and the semiconductor layer of the first conductivity type layer 60 is exposed only in the area where the conductive portion 81 described later is to be formed. Next, it is preferable to deposit a metal film on the first conductivity type layer 60, including the patterned resist. Examples of metals used here include AuZn. By removing the resist and the metal film on the resist by lift-off, a conductive portion 81 with a desired pattern can be formed on the first conductivity type layer 60. It is also preferable to perform heat treatment on the conductive portion 81 by RTA (high-temperature short-time annealing). Note that a contact layer, which is highly doped in the first conductivity type layer 60, may be patterned and arranged on the first conductivity type layer 60 side of the conductive portion 81.

[0035] Next, a dielectric portion 82 can be formed on the outer periphery of the conductive portion 81 on the first conductivity type layer 60. It is preferable to deposit an insulating film on the first conductivity type layer 60 including the conductive portion 81. The insulating film used here is preferably SiO2 or SiN. After the insulating film is formed, the insulating film on the conductive portion 81 can be removed by etching using a mask pattern made of resist, and then the remaining resist can be removed by lift-off to form the dielectric portion 82. Known methods such as sputtering or plasma CVD can be applied as the method for forming the metal film and insulating film. The thickness of the intermediate electrode layer 80 is not limited, but for example it can be 300 nm or more and 1300 nm or less, more preferably 350 nm or more and 800 nm or less, and even more preferably 430 nm or more and 640 nm or less.

[0036] <<Metal bonding layer>> As shown in Figure 2B, it is preferable to form a reflective layer 91 on the intermediate electrode layer 80. The reflective layer 91 may include multiple metal layers, but in addition to Au, Al, Pt, Ti, Ag, etc. can be used as the metal constituting the reflective layer 91. For example, the reflective layer 91 may be a single layer made only of Au, or it may contain two or more Au metal layers. It is preferable that the composition of the reflective layer 91 contains 50% by mass or more of Au, and furthermore, in order to ensure bonding with the metal bonding layer 92 in a subsequent process, it is preferable that the outermost layer of the reflective layer 91 (the side opposite to the intermediate electrode layer 80) be an Au metal layer.

[0037] For example, a reflective layer 91 can be formed by depositing each metal in the order of Al, Au, Pt, and Au on the intermediate electrode layer 80. The thickness of the Au on the outermost surface of the reflective layer 91 can be, for example, 400 nm to 2000 nm, and the thickness of the metal layer made of metals other than Au can be, for example, 5 nm to 200 nm. The reflective layer 91 can be formed by depositing a film using general means such as vapor deposition.

[0038] Alternatively, a bonding layer 92 may be formed on the support substrate 190 by laminating metals such as Ti, Pt, and Au, or metals that form a eutectic alloy with Au (such as Sn), or solder. For example, the bonding layer 92 can be formed by laminating Ti with a thickness of 400 nm to 800 nm, Pt with a thickness of 5 nm to 20 nm, and Au with a thickness of 700 nm to 1200 nm in order from the surface of the support substrate 190. In order to ensure bonding with the reflective layer 91 described above, it is preferable that the outermost surface of the bonding layer 92 (the surface opposite to the support substrate) is also an Au metal layer. In this case, bonding between Au particles by Au-Au diffusion can be performed (Figure 2C).

[0039] <<Support substrate>> Referring to Figure 2C, the bonding of the semiconductor laminate 200 and the support substrate 190 will be specifically described. The semiconductor laminate 200 and the intermediate electrode layer 80 are bonded to the support substrate 190 via the reflective layer 91 and the bonding layer 92. The bonding layer 92 and the reflective layer 91 are placed facing each other and bonded together, and the two can be bonded by performing heat compression bonding at a temperature of 250°C to 500°C and a surface pressure of 5kN to 15kN for 20 minutes to 40 minutes. The metal layer formed by bonding the reflective layer 91 and the bonding layer 92 together is referred to as the metal bonding layer 90. The thickness of the metal bonding layer is preferably 1500nm to 4500nm, more preferably 2500nm to 4000nm, and even more preferably 3000nm to 3500nm.

[0040] The support substrate 190 can be any substrate different from the growth substrate 10, and can be a semiconductor substrate such as Si, Ge, GaAs, GaP, InP, InAs, a metal substrate such as Al, Cu, Mo alloy, W alloy, Fe-Ni-Co alloy, or a submount substrate based on a ceramic substrate. Because the bonding method described above is used, the support substrate 190 may have lattice mismatch with each semiconductor layer formed in this embodiment. Although the support substrate 190 may be insulating depending on the application, it is preferable that it be a conductive substrate. By using a Si substrate, the thickness of the support substrate 190 can be significantly reduced compared to conventional methods, making it suitable for mounting in combination with various semiconductor devices. Furthermore, high heat dissipation is also preferable, and Si substrates are advantageous in terms of cost.

[0041] After bonding the support substrate 190, the growth substrate 10 is removed. If the growth substrate 10 is an InP substrate, it can be wet-etched using, for example, diluted hydrochloric acid. Alternatively, a portion of the growth substrate 10 and buffer layer 20 may be removed by polishing. The etching stop layer 30 is wet-etched with a different chemical solution than that used for the growth substrate 10 and buffer layer 20. Although not shown in Figure 2C, the etching stop layer 30 may be left only in the position where the ohmic electrode 100 described later is to be formed, and the ohmic electrode 100 may be formed on the etching stop layer 30, using the etching stop layer 30 as a layer to reduce contact resistance with the electrode (contact layer).

[0042] Referring to Figure 2D, the illustrated ohmic electrode 100 and top electrode 170 will be described. After removing the growth substrate 10, it is preferable to form the ohmic electrode 100 on the top surface of the semiconductor layer (the surface opposite to the support substrate 190). The ohmic electrode 100 can be formed using metals such as Au, Ge, Ni, and Ti. The ohmic electrode 100 can be formed by depositing a film using general means such as vapor deposition. The thickness of the ohmic electrode 100 is not limited, but for example, it can be 300 nm to 1300 nm, more preferably 350 nm to 800 nm.

[0043] It is preferable to form an upper electrode 170 on the ohmic electrode 100 after the ohmic electrode 100 has been formed. The upper electrode 170 may be formed over the entire upper part of the ohmic electrode 100, or it may be formed only on a part of the ohmic electrode 100. The upper electrode 170 can be formed using a metal such as Ti or Au, a metal that forms a eutectic alloy with Au (such as Sn), or solder. The upper electrode 170 can be formed using general means such as vapor deposition.

[0044] As shown in Figure 2E, after the formation of the upper electrode 170, at least a portion of the surface of the second conductivity layer 40, excluding the upper electrode 170 and the ohmic electrode 100, is roughened. This roughening improves the light extraction efficiency. The roughening of the surface of the second conductivity layer 40 can be carried out using common methods such as wet etching or selective etching using a mask.

[0045] <Mesa formation process> As shown in Figure 2F, a portion of the semiconductor stack 200 is removed by dry etching. The side surface of the semiconductor stack 200 is processed in the inter-element region after division, which is demarcated by the chip separation line. At this time, a mesa is formed in the semiconductor stack 200 while a street region is formed on the surface of the intermediate electrode layer 80 where the dielectric portion 82 is exposed, by removal using a dry etching method with an adjusted etching rate, for example. Reactive ion etching (RIE) is preferred as the dry etching method, and inductively coupled plasma (ICP) can be used as the plasma source. Dry etching is performed by forming a mask in the area that is not to be etched, and then drilling through the opening in the mask so that a street region with a certain width is formed along the chip separation line when viewed from above. The width of the opening in the mask for forming this street region is called the "street width".

[0046] The street width is preferably the width necessary to obtain a sufficient distance L (corresponding to the distance L in Figure 3) between the outer edge of the mesa-shaped upper surface and the outer edge of the upper surface of the support 300, as shown in the cross-section after the dicing process described later (Figure 3), and the width necessary to perform laser dicing without adversely affecting the element characteristics due to heat generation. The street width is preferably, for example, 40 μm or more and 100 μm or less, more preferably 50 μm or more and 80 μm or less, and even more preferably 50 μm or more and 70 μm or less. The street region can be lattice-shaped, and the areas that are not street regions when viewed from above are arranged with the upper electrode 100 formed above, or the conductive portion 81 of the intermediate electrode layer 80. The surface of the support exposed in the street region includes a dielectric portion 82, and the exposed upper surface is preferably the dielectric portion 82 or the protective film 70 described later. To expose the sides of the mesa shape in the street region described above, a mask (e.g., an SiO2 mask) is formed on the semiconductor laminate 200 (on the second conductivity layer 40) with a thickness such that the etching rate during dry etching is smaller than that of the semiconductor laminate 200 and that it does not disappear until the etching of the street region is complete (Figure 2F), and then dry etching of the street region is performed. It is preferable to remove all of the semiconductor laminate 200 on the street region by the above dry etching. As for the etching conditions for dry etching, the sides of the mesa shape may be forward mesa, perpendicular, or reverse mesa, but etching is performed until the dielectric portion 82 of the intermediate electrode layer 80, which is the street region, is exposed (Figure 2F).

[0047] Furthermore, as shown in Figure 2G, it is preferable to perform a step of forming a protective film 70 using plasma CVD or the like after the mesa formation step and before the dicing step described later. Examples of protective films used at this time include SiO2 or SiN. The SiO2 of the mask in the above mesa formation step may also be used as part of the protective film 70. It is preferable that the protective film 70 is formed on the mesa-shaped upper surface and the mesa-shaped side surface, excluding the central part of the upper surface of the upper electrode 170. It is preferable that the protective film 70 is not formed on the central part of the upper surface of the upper electrode 170 because it is used for electrical connection with the outside. As shown in Figure 2G, the protective film 70 can be made to cover the side and upper surface of the mesa shape and the peripheral part of the upper side surface of the upper electrode 170. If there is a step of forming this protective film 70, the protective film 70 is included in the term "mesa-shaped side surface" or "mesa-shaped upper surface". The protective film 70 may also be formed on the exposed part of the support 300 in the street region, but it is not necessary to form it there because the dielectric part 82 is already there. The protective film 70 is formed to secure a part through which current flows from outside the element. The thickness of the protective film 70 is preferably 50 nm or more and 500 nm or less. By forming the protective film 70, the semiconductor laminate 200 can be protected from the laser dicing protective film described later, debris generated during the dicing process, and the liquid used to wash them away.

[0048] Subsequently, to adjust the overall thickness of the semiconductor light-emitting element 1, it is preferable to adjust the thickness by polishing or etching the support substrate 190. In this embodiment, there is no limit to the overall thickness of the semiconductor light-emitting element including the support substrate 190, but it is preferably 80 μm or more and 500 μm or less, and more preferably 120 μm or more and 180 μm or less.

[0049] Next, it is preferable to form a back-side ohmic electrode 160 on the back surface of the support substrate 190. The back-side ohmic electrode 160 can be formed using a metal such as Ti, Pt, or Au, or a metal that forms a eutectic alloy with Au (such as Sn), or solder. The back-side ohmic electrode 160 can be formed by depositing a film using general means such as vapor deposition. The thickness of the back-side ohmic electrode 160 is not limited, but for example, it can be 300 nm or more and 1300 nm or less, more preferably 350 nm or more and 800 nm or less. It is preferable to heat-treat the formed back-side ohmic electrode 160 by RTA.

[0050] <Dicing Process> A dicing process is performed on a support 300 comprising a support substrate 190, a metal bonding layer 90, and an intermediate electrode layer 80, by irradiating the street area (particularly the chip separation line) with a laser to cut the support 300 and the back surface ohmic electrode 160. The thermal effect of heat generated during cutting through the metal bonding layer 90 is likely to occur when the laser is irradiated from the semiconductor laminate 200 side, but it will also occur when the laser is irradiated from the back surface of the support substrate 190 if the cutting position is close to the metal bonding layer 90. Therefore, when performing a full cut using laser ablation, the laser irradiation can be from either side, and when performing a half cut, it is preferable to irradiate from the semiconductor laminate 200 side. The laser is irradiated multiple times, but the incident surface and scanning conditions (output, frequency, scanning speed, defocus, beam diameter and number of beams, etc.) of these lasers are arbitrary and known methods can be used. In this embodiment, the case in which the laser is irradiated from the semiconductor laminate 200 side will be described. First, it is preferable to apply a laser dicing protective film (not shown) to the entire surface of the semiconductor light-emitting element, including the protective film 70 and the upper electrode 170. The laser dicing protective film is an organic protective film, preferably with a composition of 50% or more H2O, and the remaining composition may include propylene glycol monomethyl ether (PGME), polyvinyl alcohol (PVA), methanol (MeOH), etc. It is preferable that the laser dicing protective film is water-soluble. The laser dicing protective film has the effect of suppressing the adhesion of debris generated during the dicing process to the surface of the semiconductor light-emitting element. As a laser dicing process, it is preferable to apply the laser protective film, perform laser dicing, and finally perform water washing (washing off the laser dicing protective film and debris). Figure 3 shows the semiconductor light-emitting element 1 after the dicing process. After a dicing process in which the chip separation line located approximately in the center of the street area is cut with a specific width of cutting margin, the average value of the distance L in Figure 3, measured by the method described above, is preferably 14 μm or more and 20 μm or less, preferably 14.1 μm or more and 19.8 μm or less, and more preferably 14.2 μm or more and 19.5 μm or less.The minimum value of distance L is preferably 11.5 μm or more, more preferably 11.6 μm or more, and even more preferably 11.7 μm or more. The average width of the cut during laser dicing, obtained by subtracting twice the average value of distance L from the street width, can be, for example, 10 μm to 30 μm, or 18 μm to 25 μm. The semiconductor light-emitting element 1 obtained in this way suppresses the generation of leakage current in the reverse bias direction. Furthermore, by setting the average value of distance L to 20 μm or less, an excessive reduction in the number of chips per wafer can be suppressed.

[0051] (Semiconductor light-emitting device) The semiconductor light-emitting element 1 in this embodiment, which was manufactured based on the semiconductor light-emitting element manufacturing method described above, will now be described.

[0052] As shown in Figure 3, the semiconductor light-emitting element 1 according to this embodiment comprises a support 300 on which an intermediate electrode layer 80 having a dielectric portion 82 is laminated via a metal junction layer 90 on a support 190, and a semiconductor laminate 200 formed on the support 300. The semiconductor laminate 200 has a mesa shape, and in a top view, the top surface of the support 300 is located around the periphery of the mesa shape.

[0053] The semiconductor light-emitting element 1 shown in Figure 3 will be described. In a top view of the semiconductor light-emitting element 1, the average value of the distance (distance L in Figure 3) between the outer edge of the mesa-shaped top surface and the outer edge of the top surface of the support 300 is preferably 14 μm or more and 20 μm or less, preferably 14.1 μm or more and 19.8 μm or less, and more preferably 14.2 μm or more and 19.5 μm or less. The minimum value of distance L is preferably 11.5 μm or more, more preferably 11.6 μm or more, and even more preferably 11.7 μm or more. Furthermore, the thickness of the metal junction layer is preferably 1500 nm or more and 4500 nm or less, more preferably 2500 nm or more and 4000 nm or less, and even more preferably 3000 nm or more and 3500 nm or less.

[0054] Preferably, the semiconductor light-emitting element 1 has a protective film 70 formed on the mesa-shaped upper surface and mesa-shaped side surfaces of the upper electrode 170, which is located on the upper part of the semiconductor laminate 200, excluding the central part of the upper surface. The upper surface of the support 300 may have the protective film 70 exposed, or the dielectric portion 82 may be exposed. The protective film 70 may be formed on the exposed portion of the support 300 in the street region, but it may not be formed if the dielectric portion 82 is already present. Preferably, the semiconductor laminate 200 is not placed in the portion where the dielectric portion 82 or the protective film 70 is exposed. This semiconductor light-emitting element 1 can suppress the generation of leakage current in the reverse bias direction. The reason for not providing the protective film 70 on the central part of the upper surface of the upper electrode 170 is to make a connection for supplying current to the semiconductor light-emitting element 1 from the outside.

[0055] The first conductivity layer 60 of the semiconductor laminate 200 may have a first conductivity semiconductor layer such as an electron blocking layer, a cladding layer, or a contact layer. Similarly, the second conductivity layer 40 may have a second conductivity semiconductor layer such as a cladding layer or a contact layer. Furthermore, an undoped layer called a spacer layer may be provided between the active layer 50 and the first conductivity layer 60, or between the active layer 50 and the second conductivity layer 40. Preferably, the first conductivity layer 60 and the second conductivity layer 40 are layers having a larger band gap than the active layer 50.

[0056] The active layer 50 preferably contains one or more of Al, Ga, and In as Group III elements, and one or more of As, Sb, and P as Group V elements. The first conductive layer 60 preferably contains one or more of Al, Ga, and In as Group III elements, and one or more of As, Sb, and P as Group V elements. The emission wavelength of the semiconductor laminate 200 is preferably between 1000 nm and 2400 nm, more preferably between 1200 nm and 2000 nm, and even more preferably between 1300 nm and 1600 nm.

[0057] Hereinafter, the present invention will be described in more detail with reference to examples, but the present invention is not limited to the following examples in any way.

Example

[0058] (Example 1) On a substrate 10 for growing n-type InP (thickness: 600 μm, S-doped, dopant concentration: 2.0×10 18 / cm 3 ), using the MOCVD method, an n-type InP buffer layer 20 (thickness: 0.1 μm, Si-doped, dopant concentration: 5.0×10 17 / cm 3 ), an n-type In 0.57 Ga 0.43 As etching stop layer 30 (thickness: 0.02 μm, Si-doped, dopant concentration: 5.0×10 17 / cm 3 ), and an n-type InP cladding layer 40 (thickness: 3.5 μm, Si-doped, dopant concentration: 5.0×10 17 / cm 3 ) were formed in sequence. Next, as the active layer 50, a multiple quantum well structure composed of an undoped In 0.42 Ga 0.42 Al 0.16 As barrier layer and an undoped InGa 0.195 Al 0.04 As well layer was formed. After depositing an In 0.42 Ga 0.42 Al 0.16 As barrier layer with a thickness of 8 nm, an InGa 0.195 Al 0.04 As well layer with a thickness of 10 nm and an In 0.42 Ga 0.42 Al 0.16 As barrier layer with a thickness of 8 nm were alternately formed 10 layers each, resulting in 10.5 sets of multiple quantum well structures including the first barrier layer. An undoped In 0.522 Al 0.478 As electron blocking layer (thickness: 0.02 μm), a p-type InP cladding layer 60 (thickness 2.4 μm, Zn-doped, dopant concentration: 7.0×10 17 / cm 3) is formed. The thickness and dopant concentration of each semiconductor layer described here are the design values ​​for each layer growth.

[0059] Next, a resist was applied to the entire surface of the p-type InP cladding layer 60. The resist was patterned in a predetermined shape by photolithography, and the resist was removed from the area where the conductive portion 81 was to be formed, exposing the p-type InP cladding layer 60. AuZn (thickness: 550 nm) was deposited onto the p-type InP cladding layer 60, including the resist, by sputtering. Subsequently, the resist and the AuZn on the resist were removed by lift-off. Furthermore, heat treatment by RTA (condition: 300°C) was performed. As a result, the conductive portion 81 of the intermediate electrode layer 80 was formed.

[0060] Next, an insulating film made of SiO2 (thickness: 700 nm) was deposited on the p-type InP cladding layer 60, including the conductive portion 81, by plasma CVD. A resist was applied to the deposited SiO2 insulating film, and the SiO2 insulating film on the conductive portion was removed by etching using a mask pattern made of the resist. Then, the remaining resist was removed by lift-off, thereby forming the dielectric portion 82. As a result, an intermediate electrode layer 80 was formed, which is composed of the dielectric portion 82 and the conductive portion 81, with the outer periphery being the dielectric portion 82. A gap of a certain interval is created between the dielectric portion 82 and the conductive portion 81, and the thickness of the dielectric portion 82 is greater than the thickness of the conductive portion 81.

[0061] A reflective layer 91 (Ti (thickness: 2 nm) / Au (thickness: 650 nm) / Pt (thickness: 100 nm) / Au (thickness: 900 nm)) was formed on the above-mentioned intermediate electrode layer 80 by vapor deposition, and further, a bonding layer 92 (Ti (thickness: 650 nm) / Pt (thickness: 20 nm) / Au (thickness: 900 nm)) was formed on the support substrate 190 (Si substrate) by vapor deposition. The reflective layer 91 and the bonding layer 92 were placed facing each other, and heat compression bonding was performed at a surface pressure of 10 kN and 350°C for 30 minutes. Although not shown in the figures, at this time, because the gap between the dielectric part 82 and the conductive part 81 and the thickness of the dielectric part 82 are greater than the thickness of the conductive part 81, a void was created at the interface between the reflective layer 91 and the bonding layer 92 due to a recess in the reflective layer 91 that was formed in a position corresponding to the conductive part 81 and its surroundings. As a result, a metal bonding layer 90 was formed.

[0062] Next, the growth substrate 10 and buffer layer 20 were removed by wet etching with diluted hydrochloric acid, exposing the etching stop layer 30. Then, to leave the areas where the upper surface ohmic electrode and upper electrode 170 described later would be formed as contact layers, a mask was formed in those areas using a photolithograph, and the remaining areas were removed by wet etching with a tartaric acid-hydrogen peroxide solution.

[0063] On the etching stop layer 30, which was exposed after removing the mask, Au (thickness: 10 nm) / Ge (thickness: 30 nm) / Au (thickness: 60 nm) / Ni (thickness: 30 nm) / Au (thickness: 800 nm) / Ti (thickness: 100 nm) / Au (thickness: 1000 nm) were formed by vapor deposition to form the upper ohmic electrode 100. Next, an upper electrode 170 (Ti (thickness: 150 nm) / Pt (thickness: 100 nm) / Au (thickness: 2500 nm)) was formed on the upper ohmic electrode by vapor deposition. A lift-off method using resist was used to form the electrode pattern.

[0064] Next, a resist mask was formed by photolithography to cover the entire street width, the outer edge of the mesa-shaped upper surface, and the upper ohmic electrode 100 and upper electrode 170. Then, the light extraction surface of the n-type InP cladding layer 40 outside the masked area was roughened by wet etching.

[0065] Next, SiO2 was formed over the entire surface by plasma CVD, followed by the formation of a mask pattern using a resist and an etched SiO2 mask. The street width of the mask openings exposed by the mask pattern is 55 μm. Dry etching (ICP-RIE) exposed the dielectric portion 82 on the outer periphery of the intermediate electrode layer 80 in the street region, and also exposed the side surfaces from the p-type InP cladding layer 60 to the n-type InP cladding layer 40.

[0066] After mesa formation, the SiO2 mask present on the upper ohmic electrode and upper electrode 170 was removed, and then SiN was deposited as a protective film 70 on the entire surface (including the upper surface of the remaining SiO2 mask and the exposed sides and street areas of the semiconductor laminate 200) by plasma CVD. Subsequently, the SiN in the central upper surface region of the central circular part of the upper electrode 170 (corresponding to the connection area with the outside) was removed by etching using a mask pattern made of resist, and then the resist was removed. The thickness of the SiN was 190 μm. Next, the back surface of the support substrate 190 was polished or etched to make the overall thickness of the semiconductor light-emitting element 1 150 μm. Next, a back surface ohmic electrode 160 (Ti (thickness: 10 nm) / Pt (thickness: 50 nm) / Au (thickness: 200 nm)) was formed on the back surface of the support substrate 190 by vapor deposition, and heat treatment was performed at 300°C for 60 seconds by RTA.

[0067] Finally, laser dicing was performed on the street region. In the street region, the back surface ohmic electrode 160, support substrate 190, metal bonding layer 90, dielectric portion 82 of the intermediate electrode layer 80, and protective film 70 (SiN) were formed in order, and the laser was irradiated from the protective film side. Laser dicing was performed after attaching adhesive tape to the back surface of the back surface ohmic electrode 160, and then applying a water-soluble protective film (Hogomax 102 manufactured by DISCO) to the entire surface, including on the protective film 70. Using a laser dicer manufactured by DISCO, the street region was fully cut by ablation by laser scanning six times from the semiconductor laminate 200 side. After that, it was washed with water to remove the water-soluble protective film and debris generated by the laser scanning. After drying, the spacing between individual chips was increased by expanding the adhesive tape with an expander. In this way, the chips were separated into rectangular individual elements with a chip size of 250 μm × 250 μm, and the semiconductor light-emitting element according to Example 1 was fabricated.

[0068] (Example 2) A semiconductor light-emitting element 1 according to Example 2 was obtained in the same manner as in Example 1, except that the street width was set to 50 μm.

[0069] (Example 3) A semiconductor light-emitting element 1 according to Example 3 was obtained in the same manner as in Example 1, except that the street width was set to 60 μm.

[0070] (Comparative Example 1) A semiconductor light-emitting element 1 according to Comparative Example 1 was obtained in the same manner as in Example 1, except that the street width was set to 40 μm.

[0071] (Comparative Example 2) A semiconductor light-emitting element 1 according to Comparative Example 2 was obtained in the same manner as in Example 1, except that the street width was set to 45 μm.

[0072] Ten semiconductor light-emitting elements were selected from each of the examples 1 to 3 and comparative examples 1 to 2. For the distance L, the distance L was calculated for each element and the average value of the four sides was calculated. Furthermore, the average value of these 10 elements was calculated as L.AVE Let L be the smallest L among the 10 elements. MIN The following was done. In addition, 10 semiconductor light-emitting elements were extracted from the extraction positions used for the distance measurement described above, and 10 semiconductor light-emitting elements adjacent to them were extracted. These were mounted on a transistor outline header (TO-18) using silver paste, and the top electrodes were bonded using gold wire. The reverse bias current (Ir) and reverse bias voltage (Vr) were then measured. A constant current voltage device (ADC Corporation: model number 6243) was used for the measurements. The average value [A] and standard deviation [A] of the reverse bias current for 10 elements when a voltage of 10V was applied in the reverse direction, the average value [V] and standard deviation [V] of the reverse bias voltage for 10 elements when a current of 0.1μA was applied in the reverse direction, and the average value [V] and standard deviation [V] of the reverse bias voltage for 10 elements when a current of 1μA was applied in the reverse direction were measured. The above values ​​are listed in Table 1 below.

[0073] [Table 1]

[0074] Table 1 shows that when the street width is 50 μm or more, the average leakage current (reverse bias current) value decreases when a reverse bias voltage of 10 V is applied. Furthermore, the variation (standard deviation) of the average reverse bias voltage when reverse bias currents of 0.1 μA and 1 μA are applied also decreases. This is thought to be because the lateral influence on the metal junction layer 90 heated during laser dicing is suppressed by sufficiently widening the street width and sufficiently increasing the distance L. In other words, Table 1 shows that semiconductor light-emitting elements that satisfy the conditions of the present invention have a sufficiently small leakage current value. From these results, it was confirmed that even if the number of chips that can be obtained decreases by widening the street width, in order to obtain a semiconductor light-emitting element that can suppress leakage current, it is necessary to widen the street width and make the distance L long enough to satisfy the conditions of the present invention. [Explanation of symbols]

[0075] 1. Semiconductor light-emitting element 10 Growth substrate 20 buffer layers 30 Etching stop layer 40 Second conductive layer 50 active layer 60 First conductive layer 70 Protective film 80 Intermediate electrode layer 81 Conductive part 82 Dielectric part 90 Metal bonding layer 91 Reflective layer 92 Bonding layer 100 ohmic electrodes 160 Backside ohmic electrode 170 Top electrode 190 Support substrate 200 Semiconductor Stack 300 Support

Claims

1. A bonding step in which a support substrate is bonded to an intermediate electrode layer having a dielectric portion and a semiconductor laminate via a metal bonding layer, A mesa formation step is performed in which the semiconductor laminate is etched to form a mesa shape, and street regions on the surface where the dielectric portion is exposed are formed in the intermediate electrode layer. The process includes a dicing step of cutting the support, which comprises the support substrate, the metal bonding layer, and the intermediate electrode layer, by irradiating the street region with a laser, A method for manufacturing a semiconductor light-emitting element, characterized in that, in a top view, the average value of the distance L between the outer edge of the mesa-shaped upper surface after the dicing process and the outer edge of the upper surface of the support is 14 μm or more and 20 μm or less.

2. Between the mesa formation step and the dicing step, the step further includes forming a protective film on the upper surface of the mesa shape and the side surfaces of the mesa shape, excluding the central portion of the upper surface of the upper electrode provided on the upper part of the semiconductor laminate. A method for manufacturing a semiconductor light-emitting element according to claim 1.

3. The method for manufacturing a semiconductor light-emitting element according to claim 1 or 2, wherein the minimum value of the distance L between the outer edge of the mesa-shaped upper surface and the outer edge of the upper surface of the support is 11.5 μm or more.

4. The method for manufacturing a semiconductor light-emitting element according to claim 1 or 2, wherein the emission wavelength of the semiconductor laminate is 1000 nm or more and 2400 nm or less.

5. The method for manufacturing a semiconductor light-emitting element according to claim 1 or 2, wherein the thickness of the metal junction layer in the support is 1500 nm or more and 4000 nm or less.

6. A support comprising a support substrate on which an intermediate electrode layer having a dielectric portion is laminated via a metal bonding layer, The system comprises a semiconductor laminate formed on the support, The semiconductor laminate has a mesa shape, In a top view, the upper surface of the support is located around the mesa shape. A semiconductor light-emitting element characterized in that the average value of the distance L between the outer edge of the mesa-shaped upper surface and the outer edge of the upper surface of the support is 14 μm or more and 20 μm or less.

7. A protective film is formed on the upper surface of the mesa-shaped upper surface and the side surface of the mesa-shaped upper surface, excluding the central part of the upper surface of the upper electrode provided on the upper part of the semiconductor laminate. The semiconductor light-emitting element according to claim 6, wherein the protective film is exposed on the upper surface of the support, or the dielectric portion is exposed.

8. The semiconductor light-emitting element according to claim 6 or 7, wherein the minimum value of the distance L between the outer edge of the mesa-shaped upper surface and the outer edge of the upper surface of the support is 11.5 μm or more.

9. The semiconductor light-emitting element according to claim 6 or 7, wherein the emission wavelength of the semiconductor laminate is 1000 nm or more and 2400 nm or less.

10. The semiconductor light-emitting element according to claim 6 or 7, wherein the thickness of the metal bonding layer in the support is 1500 nm or more and 4000 nm or less.

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