Pulse generation circuit and pulse generation device

Abstract

The pulse generation circuit according to the present disclosure comprises: a switch which is capable of delivering a first current discharged from a first capacitor, which has been charged, to the primary-side winding of a saturable transformer; a second capacitor connected in series with the secondary-side winding of the saturable transformer; a first diode connected in parallel with the serial connection of the secondary-side winding and the second capacitor such that a second current generated in the secondary-side winding becomes a forward current; a second diode connected in parallel with the first diode such that a third current discharged by the second capacitor, which has been charged by the second current, becomes a forward current; and a third capacitor connected in series with the second diode and in parallel with the first diode.

Description

Technical Field

[0001] The present disclosure relates to a pulse generation circuit and a pulse generation device that generate a high-voltage pulse with a short rise time.

Background Art

[0002] As a pulse generation circuit for generating a high-voltage pulse with a short rise time, for example, as shown in FIG. 6 of Non-Patent Document 1, a circuit using a magnetic compression circuit (MPC) is known. The magnetic compression circuit shown in FIG. 6 of Non-Patent Document 1 is a general two-stage magnetic compression circuit composed of a capacitor (C0) charged to a certain voltage by a charger, a discharge semiconductor element (IGBT), a step-up pulse transformer (PT), charge / discharge capacitors (C1, C2, CP), and saturable inductors (SI1, SI2).

Prior Art Documents

Patent Documents

[0003]

Non-Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] A general two-stage magnetic compression circuit composed of a first circuit region and a second circuit region shown in FIG. 6 of Non-Patent Document 1 operates as follows.

[0005] The charge of the capacitor (C0) charged to a predetermined voltage by the charger flows to the primary winding of the step-up pulse transformer (PT) when the discharge semiconductor element (IGBT) switch is turned on.

[0006] The current flowing through the primary winding of the pulse transformer (PT) generates a boosted current in the secondary winding, and this generated current charges the charge / discharge capacitor (C1).

[0007] The charge / discharge capacitor (C1) is charged by the current generated in the secondary winding of the step-up pulse transformer (PT), and the saturable inductor (SI1) reaches a magnetic saturation state when the charging voltage is at its maximum. As a result, the charge stored in the charge / discharge capacitor (C1), when the charging voltage is at its maximum, flows into the charge / discharge capacitor (C2). As described above, the timing of magnetic saturation of the saturable inductor (SI1) must coincide with the timing when the charging voltage of the charge / discharge capacitor (C1) is at its maximum, so the core material, core shape, number of windings, etc. must be considered.

[0008] If the timing of magnetic saturation of the saturable inductor (SI1) is earlier than the timing of maximum charging voltage of the charge / discharge capacitor (C1), then current will start flowing to the charge / discharge capacitor (C2) before the charge / discharge capacitor (C1) is fully charged, which creates a problem where the charge / discharge capacitor (C2) cannot be charged at a high voltage.

[0009] On the other hand, if the timing of magnetic saturation of the saturable inductor (SI1) is later than the timing of the charging voltage of the charge / discharge capacitor (C1) reaching its maximum, the charge stored in the charge / discharge capacitor (C1) flows out into the secondary winding of the boost pulse transformer (PT), resulting in a current being generated in the primary winding of the boost pulse transformer (PT), and energy flowing back into the first circuit region.

[0010] The same applies to the timing of magnetic saturation of the saturable inductor (SI2); the timing of magnetic saturation must coincide with the timing when the charging voltage of the charge / discharge capacitor (C2) reaches its maximum. Generally, the product of the time it takes for a saturable inductor to reach magnetic saturation and the applied voltage (voltage-time product) depends on the core material, core shape, and number of windings. Therefore, designing a saturable inductor to magnetically saturate in sync with the charging / discharging capacitor reaching its maximum voltage has presented a challenge.

[0011] Furthermore, if the time it takes for a saturable inductor to reach magnetic saturation is timed to coincide with the timing when the charging voltage of the charge / discharge capacitor reaches its maximum, the voltage applied to the saturable inductor becomes a predetermined design voltage. As a result, there is a problem in that the output voltage of the magnetic compression circuit cannot be freely changed. The objective of this disclosure is to provide a pulse generation circuit and pulse generation device that are easy to design and allow for free adjustment of the output voltage. [Means for solving the problem]

[0012] The pulse generation circuit disclosed herein is In a pulse generation circuit that magnetically compresses a first current discharged from a first capacitor connected in series with the primary winding of a saturable transformer using the magnetic saturation of the saturable transformer, A switch that can be controlled to turn on and off based on a control signal, and that can send the first current discharged from the charged first capacitor to the primary winding of the saturable transformer, A second capacitor connected in series with the secondary winding of the aforementioned saturable transformer, A first diode is connected in parallel to the series connection of the secondary winding and the second capacitor, such that the second current generated in the secondary winding by the first current becomes a forward current. A second diode is connected in parallel to the first diode such that the third current discharged from the second capacitor, which is charged by the second current, is a forward current. A third capacitor connected in series with the second diode and in parallel with the first diode, Equipped with, The switch is controlled to turn on and send the first current to the primary winding of the saturable transformer, and then is controlled to turn off at the timing when the charging voltage of the second capacitor reaches its maximum. The saturable transformer operates as a saturable inductor that saturates magnetically at any time after the switch turns off. It is a pulse generation circuit characterized by this.

Advantages of the Invention

[0013] It becomes possible to provide a pulse generation circuit and a pulse generation device that are easy to design and can freely change the output voltage.

Brief Description of the Drawings

[0014] [Figure 1] It is a diagram showing an example of a first pulse generation circuit according to a first embodiment of the present disclosure. [Figure 2] It is a diagram showing the state of step 1 in an example of the operation of the first pulse generation circuit according to the first embodiment of the present disclosure. [Figure 3] It is a diagram showing the state of step 2 in an example of the operation of the first pulse generation circuit according to the first embodiment of the present disclosure. [Figure 4] It is a diagram showing the state of step 4 in an example of the operation of the first pulse generation circuit according to the first embodiment of the present disclosure. [Figure 5] It is a diagram showing the state of step 5 in an example of the operation of the first pulse generation circuit according to the first embodiment of the present disclosure. [Figure 6] It is a diagram showing the state of step 7 in an example of the operation of the first pulse generation circuit according to the first embodiment of the present disclosure. [Figure 7] It is a diagram showing an example of the temporal transition of voltage due to the operation of the first pulse generation circuit according to the first embodiment of the present disclosure. [Figure 8] It is a diagram showing an example of a second pulse generation circuit according to a second embodiment of the present disclosure. [Figure 9] It is a diagram showing an example of the flow of current due to the operation of the second pulse generation circuit according to the second embodiment of the present disclosure.

Best Mode for Carrying Out the Invention

[0015] Hereinafter, embodiments of a pulse generation circuit and a pulse generation device according to the present disclosure will be described with reference to the drawings. [[ID=********]] [[ID=********]]

[0016] [[ID=********]] (First Embodiment of the Present Disclosure)[[ID=********]] FIG. 1 shows an example of a first pulse generation circuit 10 according to the first embodiment of the present disclosure. [[ID=********]] [[ID=********]]

[0017] [[ID=********]] The first pulse generation circuit 10 according to the first embodiment of the present disclosure includes a first circuit region 11 and a second circuit region 12, and the first circuit region 11 and the second circuit region 12 are electrically connected to each other via a first saturable transformer (ST1) 4. [[ID=********]] [[ID=********]]

[0018] [[ID=********]] The first circuit region 11 of the first pulse generation circuit 10 is a circuit that generates a pulse current. On the other hand, the second circuit region 12 of the first pulse generation circuit 10 is a circuit that compresses the pulse width of the pulse current generated in the first circuit region 11 and supplies the compressed narrow-width pulse current to the load 9. [[ID=********]] [[ID=********]]

[0019] [[ID=********]] The first circuit region 11 of the first pulse generation circuit 10 is configured by connecting a first semiconductor switch (SW1) 1, a first capacitor (C1) 3, and a primary winding 4-1 of a first saturable transformer (ST1) 4 in series to a charging circuit, and connecting a second semiconductor switch (SW2) 2 in parallel. The first semiconductor switch (SW1) 1 and the second semiconductor switch (SW2) 2 can be controlled to be turned on and off based on a control signal from a control unit not shown. The control unit has a control signal generation circuit that generates a control signal, and by applying the generated control signal to the first semiconductor switch (SW1) and the second semiconductor switch (SW2), controls the first semiconductor switch (SW1) and the second semiconductor switch (SW2) to be turned on and off. [[ID=********]] [[ID=********]]

[0020] [[ID=********]] The second circuit region 12 of the first pulse generation circuit 10 is configured by connecting the second capacitor (C2) 5 in series with the secondary winding 4-2 of the first saturable transformer (ST1) 4, connecting the first fast recovery diode (FRD1) 6 in parallel with the series connection between the secondary winding 4-2 of the first saturable transformer (ST1) 4 and the second capacitor (C2) 5, and further connecting the second fast recovery diode (FRD2) 7 and the third capacitor (C3) 8 in series with the second capacitor (C2) 5 and in parallel with the first fast recovery diode (FRD1) 6.

[0021] The first fast recovery diode (FRD1) 6 is connected in a direction that causes the pulse current generated in the secondary winding 4-2 of the first saturable transformer (ST1) 4 to be a forward current, and the second fast recovery diode (FRD2) 7 is connected in a direction that causes the pulse current discharged from the second capacitor (C2) 5 to be a forward current.

[0022] The first saturable transformer (ST1) 4 functions as a pulse transformer while transferring energy from the first capacitor (C1) 3 to the second capacitor (C2) 5. After the primary winding 4-1 of the first circuit region 11 is opened by controlling the first semiconductor switch (SW1) 1 and the second semiconductor switch (SW2) 2 to the OFF state, it functions as a saturable inductor in the secondary winding 4-2 of the second circuit region 12. As a result, the second circuit region 12 of the first pulse generation circuit 10 is configured as a single-stage magnetic compression circuit with the first saturable transformer (ST1) 4, the second capacitor (C2) 5, and the third capacitor (C3) 8.

[0023] The turns ratio of the primary winding 4-1 and the secondary winding 4-2 of the first saturable transformer (ST1) 4 can be any turns ratio as long as the number of turns of the primary winding 4-1 is less than the number of turns of the secondary winding 4-2. The first circuit region 11 of the first pulse generation circuit 10 controls the first semiconductor switch (SW1) 1 to ON and the second semiconductor switch (SW2) 2 to OFF by a control signal, so that the first capacitor (C1) 3 is initially charged to a predetermined voltage by the charging circuit. After the initial charging is complete, the first semiconductor switch (SW1) 1 is turned OFF and the second semiconductor switch (SW2) 2 is turned ON by a control signal, so that the initially charged first capacitor (C1) 3 starts to discharge, and a pulse current is supplied to the primary winding 4-1 of the first saturable transformer (ST1) 4.

[0024] The first saturable transformer (ST1) 4 is designed to be in a desaturated state while a pulsed current is supplied from the initially charged first capacitor (C1) 3 to the primary winding 4-1 of the first saturable transformer (ST1) 4.

[0025] In the second circuit region 12 of the first pulse generation circuit 10, a pulse current is induced in the secondary winding 4-2 by the pulse current supplied from the first capacitor (C1) 3 to the primary winding 4-1 of the first saturable transformer (ST1) 4 via the first saturable transformer (ST1) 4, which functions as a pulse transformer, and the second capacitor (C2) 5 is charged.

[0026] The first saturable transformer (ST1) 4 functions as being in a non-saturated state while the pulse current in the primary winding 4-1 induces a pulse current in the secondary winding 4-2, charging the second capacitor (C2) 5.

[0027] Furthermore, in the second circuit region 12 of the first pulse generation circuit 10, when the first saturable transformer (ST1) 4 transitions from a non-saturated state to a magnetically saturated state at a timing after the second capacitor (C2) 5 has been fully charged by the pulse current induced in the secondary winding 4-2 of the first saturable transformer (ST1) 4, the inductance of the secondary winding 4-2 of the first saturable transformer (ST1) 4 decreases sharply. As a result, the charge that was stored in the second capacitor (C2) moves rapidly to the third capacitor (C3), causing the voltage of the third capacitor (C3) to rise sharply, and consequently, a voltage with a steep rise is applied to the load 9.

[0028] The first fast recovery diode (FRD1) 6 and the second fast recovery diode (FRD) 7 of the first pulse generation circuit 10 should preferably have a withstand voltage that is sufficiently higher than the charging voltage of the second capacitor (C2) 5 and the third capacitor (C3) 8, and a short reverse recovery time.

[0029] Next, the operation of the first pulse generation circuit 10 according to the first embodiment of this disclosure will be described with reference to Figures 2 to 6. Figures 2 to 6 show an example of the operation of the first pulse generation circuit 10 according to the first embodiment of the present disclosure.

[0030] (Step 1) As shown in Figure 2, in the first circuit region 11, the control unit controls the first semiconductor switch (SW1) 1 to be turned ON and the second semiconductor switch (SW2) 2 to be turned OFF by a control signal, thereby initially charging the first capacitor (C1) 3 to a predetermined voltage using a charging circuit.

[0031] (Step 2) Once the first capacitor (C1) 3 is fully charged, the control unit controls the first semiconductor switch (SW1) 1 to turn off and the second semiconductor switch (SW2) 2 to turn on using a control signal, as shown in Figure 3. This causes the first capacitor (C1) 3 to begin a rapid discharge and the first current I1 is supplied to the primary winding 4-1 of the first saturable transformer (ST1) 4.

[0032] (Step 3) When the first current I1 is supplied to the primary winding 4-1, the first saturable transformer (ST1) 4, in its function as a pulse transformer, generates a voltage in the secondary winding 4-2 according to the turns ratio of the primary winding 4-1 and the secondary winding 4-2.

[0033] (Step 4) The voltage generated in the secondary winding 4-2 of the first saturable transformer (ST1) 4 generates a second current I2 in the second circuit region 12, as shown in Figure 4, and charges the second capacitor (C2) 5. The first fast recovery diode (FRD1) 6 is connected in a direction that makes the second current I2 a forward current.

[0034] (Step 5) Once the charging of the second capacitor (C2) 5 is complete, the control unit controls the second semiconductor switch (SW2) 2 to turn off using a control signal, as shown in Figure 5. As a result, no current flows through the primary winding 4-1 of the first saturable transformer (ST1) 4 thereafter, preventing energy from flowing back into the first circuit region 11.

[0035] (Step 6) The second capacitor (C2) 5, once fully charged, discharges a small amount of current to the third capacitor (C3) 8 through the secondary winding 4-2 of the saturable transformer (ST) 4. Due to this small discharge current in the secondary winding 4-2, the first saturable transformer (ST1) 4 becomes magnetically saturated after a certain period of time has elapsed since the first semiconductor switch (SW2) 2 was controlled to be turned off.

[0036] (Step 7) When the first saturable transformer (ST1) 4 becomes magnetically saturated, the second capacitor (C2) 5 begins to discharge rapidly, as shown in Figure 6, and a third current I3 is supplied to the third capacitor (C3) 8. The second fast recovery diode (FRD2) 7 is connected in a direction that makes the third current I3 a forward current.

[0037] As a result of the above operation, a pulse voltage is output across the third capacitor (C3) by the third current I3 and applied to the load 9.

[0038] The time it takes for the first saturable transformer (ST1) 4 to become magnetically saturated by the minute discharge current of the secondary winding 4-2 varies depending on the charging voltage of the secondary winding 4-2 of the first saturable transformer (ST1) 4 and the second capacitor (C2), but this has no effect whatsoever on the magnetic compression operation itself. Therefore, the charging voltage of the second capacitor (C2) can be freely changed, and the output voltage applied to the load 9 can be freely changed.

[0039] Next, in the operation flow of the first pulse generation circuit 10 from (step 1) to (step 7), an example of the temporal transition of voltage at points A and B shown in Figures 2 to 6 is presented.

[0040] Figure 7 shows an example of the temporal transition of voltage at points A and B due to the operation of the first pulse generation circuit 10 according to the first embodiment of the present disclosure. Figure 7(a) shows the temporal transition of voltage at point A in the operation flow of the first pulse generation circuit 10 from (step 1) to (step 6), and Figure 7(b) shows the temporal transition of voltage at point B. The time on the horizontal axis is set to 0 when the first semiconductor switch (SW1) 1 is controlled to ON and the second semiconductor switch (SW2) 2 is controlled to OFF by the control signal, as shown in step 1.

[0041] As shown in step 1, the first capacitor (C1) 3 is initially charged to a predetermined voltage by time T0. At time T0, as shown in (Step 2), the control signal turns the first semiconductor switch (SW1) 1 off and the second semiconductor switch (SW2) 2 on, supplying the first current I1 to the primary winding 4-1 of the first saturable transformer (ST1) 4. As a result, a voltage is generated in the secondary winding 4-2, as shown in (Step 3), and the voltage at point A begins to change (charging of the second capacitor (C2) 5 begins). At time T1, when the second capacitor (C2) 5 is fully charged, the voltage at point A reaches its maximum (maximum voltage Vt1).

[0042] As shown in step 6, the second capacitor (C2) 5 then discharges a small amount through the secondary winding 4-2 of the saturating transformer (ST) 4, so that the voltage at point A gradually begins to decrease and the voltage at point B gradually begins to increase. Due to this minute discharge current, when the first saturable transformer (ST1) 4 becomes magnetically saturated at time T2, the second capacitor (C2) 5 begins to discharge rapidly, and a third current I3 is supplied to the third capacitor (C3) 8. As a result, the voltage at point A drops sharply, while the voltage at point B rises sharply.

[0043] When the third current I3 completes the charging of the third capacitor (C3) 8 from the second capacitor (C2) 5, the voltage at point A becomes 0 and the voltage at point B becomes maximum (maximum voltage Vt3).

[0044] As described above, in the first pulse generation circuit 10 according to the first embodiment of this disclosure, the control unit controls the second semiconductor switch (SW2) 2 to turn off at the timing when the energy transfer from the first capacitor (C1) 3 to the second capacitor (C2) 5 is completed. After it is turned off, no current flows into the first circuit region 11, and the first circuit region 11 and the second circuit region 12 can be electrically completely separated and isolated. As a result, the first pulse generation circuit 10 can prevent the energy of the second capacitor (C2) 5 from flowing back into the first circuit region 11 after the energy transfer from the first capacitor (C1) 3 to the second capacitor (C2) 5 is completed.

[0045] Furthermore, the first saturable transformer (ST1) 4 of the first pulse generation circuit 10 only needs to be in a non-saturated state until the energy transfer from the first capacitor (C1) 3 to the second capacitor (C2) 5 is completed, and the time from the completion of energy transfer until magnetic saturation does not need to be considered.

[0046] As shown in Figure 1, in addition to the first pulse generation circuit 10, a charging circuit connected to the first semiconductor switch (SW1) 1 may also be included to configure the pulse generator as one that supplies high-voltage pulses with a short rise time to the load 9. Based on the above, the first pulse generation circuit 10 and pulse generation device according to the first embodiment of this disclosure are easy to design and allow the output voltage to be freely changed.

[0047] (Second Embodiment of the Disclosure) Figure 8 shows an example of a second pulse generation circuit 20 according to the second embodiment of the present disclosure.

[0048] The second pulse generation circuit 20 according to the second embodiment of this disclosure has the output across the third capacitor (C3) reversed in polarity compared to the first pulse generation circuit 10 according to the first embodiment. Therefore, the second pulse generation circuit 20 according to the second embodiment is configured by replacing the first saturable transformer (ST1) 4, the first fast recovery diode (FRD1) 6, and the second fast recovery diode (FRD2) 7 of the first pulse generation circuit 10 according to the first embodiment with a second saturable transformer (ST2) 24, a third fast recovery diode (FRD3) 26, and a fourth fast recovery diode (FRD4) 27, respectively, while remaining identical to the first pulse generation circuit 10.

[0049] The second saturable transformer (ST2) 24 has the input voltage / output voltage relationship of the first saturable transformer (ST1) 4 reversed, the third fast recovery diode (FRD3) 26 has the direction of the forward current of the first fast recovery diode (FRD1) 6 reversed, and the fourth fast recovery diode (FRD4) 27 has the direction of the forward current of the second fast recovery diode (FRD2) 7 reversed.

[0050] Figure 9 shows an example of the current flow due to the operation of the second pulse generation circuit 20 according to the second embodiment of this disclosure. Note that the operating states of the first semiconductor switch (SW1) 1 and the second semiconductor switch (SW2) 2 are omitted in Figure 9.

[0051] The operation of the second pulse generation circuit 20 will be explained below, focusing on the differences from the operation of the first pulse generation circuit 10 from (step 1) to (step 7).

[0052] The second pulse generation circuit 20 performs an operation corresponding to (step 2), causing the first capacitor (C1) 3 to rapidly discharge, and the first current I1 is supplied to the primary winding 24-1 of the second saturable transformer (ST2) 24.

[0053] As a result, the second pulse generation circuit 20 performs an operation corresponding to (step 3), causing the second saturable transformer (ST2) 24 to function as a transformer and generate a voltage on the secondary winding 24-2 according to the turns ratio of the primary winding 24-1 and the secondary winding 24-2.

[0054] However, the direction of the voltage generated in the secondary winding 24-2 of the second saturable transformer (ST2) 24 is opposite to the direction of the voltage generated in the secondary winding 4-2 of the first saturable transformer (ST1) 4. Therefore, in the operation corresponding to (step 4), the second pulse generation circuit 20 generates a fourth current I4 that is opposite to the second current I2, and the second capacitor (C2) 5 is charged. The third fast recovery diode (FRD3) 26 is connected in a direction that makes the fourth current I4 a forward current.

[0055] Similarly, in the operation corresponding to step 6, the second pulse generation circuit 20 generates a fifth current I5 in the opposite direction to the third current I3, and charges the third capacitor (C3) 8. The fourth fast recovery diode (FRD4) 27 is connected in a direction such that the fifth current I5 is a forward current.

[0056] Through the above operation, the second pulse generation circuit 20 can reverse the polarity of the output across the third capacitor (C3) 8 with respect to the first pulse generation circuit 10. The second pulse generation circuit 20 may also be configured, similar to the first pulse generation circuit 10, to include a charging circuit connected to the first semiconductor switch (SW1) 1, thereby supplying a high-voltage pulse with a short rise time to the load 9.

[0057] Based on the above, the second pulse generation circuit 20 of the second embodiment of this disclosure can achieve the same effect as the first pulse generation circuit 10 of the first embodiment by reversing its polarity.

[0058] While several embodiments of this disclosure have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be implemented in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. [Explanation of symbols]

[0059] 1: First semiconductor switch (SW1) 2: Second semiconductor switch (SW2) 3: First capacitor (C1) 4: First saturable transformer (ST1) 4-1: Primary winding 4-2: Secondary winding 5: Second capacitor (C2) 6: First Fast Recovery Diode (FRD1) 7: Second Fast Recovery Diode (FRD2) 8: Third capacitor (C3) 9: Load 10: First pulse generation circuit 11: First circuit region 12: Second circuit region 20: Second pulse generation circuit 24: Second saturable transformer (ST2) 24-1: Primary winding 24-2: Secondary winding 26: Third Fast Recovery Diode (FRD3) 27: The fourth fast recovery diode (FRD4)

Claims

1. In a pulse generation circuit that magnetically compresses a first current discharged from a first capacitor connected in series with the primary winding of a saturable transformer using the magnetic saturation of the saturable transformer, A switch that can be controlled to turn on and off based on a control signal, and can send the first current discharged from the charged first capacitor to the primary winding of the saturable transformer, A second capacitor connected in series with the secondary winding of the aforementioned saturable transformer, A first diode is connected in parallel to the series connection of the secondary winding and the second capacitor, such that the second current generated in the secondary winding by the first current becomes a forward current. A second diode is connected in parallel to the first diode such that the third current discharged from the second capacitor, which is charged by the second current, is a forward current. A third capacitor connected in series with the second diode and in parallel with the first diode, Equipped with, The pulse generation circuit is characterized in that the switch is controlled to turn on to send the first current to the primary winding of the saturable transformer, and then controlled to turn off when the charging voltage of the second capacitor reaches its maximum, and the saturable transformer operates as a saturable inductor that magnetically saturates at any time after the switch is turned off, thereby outputting a pulse voltage across the third capacitor by the third current.

2. The pulse generation circuit according to claim 1, wherein the switch is controlled to the OFF position to charge the first capacitor, and after the charging of the first capacitor is complete, the switch is controlled to the ON position to send the first current to the primary winding of the saturable transformer.

3. The pulse generating circuit according to claim 1 or 2, wherein the withstand voltage of the first diode and the second diode is higher than the charging voltage of the second capacitor and the third capacitor.

4. A pulse generator for applying a pulse voltage to a load, A first capacitor that is charged by a charging circuit, A pulse generation circuit that magnetically compresses a first current discharged from a first capacitor connected in series with the primary winding of a saturable transformer, using the magnetic saturation of the saturable transformer, Equipped with, The pulse generation circuit is A switch that can be controlled to turn on and off based on a control signal, and can send the first current discharged from the charged first capacitor to the primary winding of the saturable transformer, A second capacitor connected in series with the secondary winding of the aforementioned saturable transformer, A first diode is connected in parallel to the series connection of the secondary winding and the second capacitor, such that the second current generated in the secondary winding by the first current becomes a forward current. A second diode is connected in parallel to the first diode such that the third current discharged from the second capacitor, which is charged by the second current, is a forward current. A third capacitor connected in series with the second diode and in parallel with the first diode, Equipped with, The third capacitor can be connected in parallel with the load via both ends of the third capacitor. The switch is controlled to turn on to send the first current to the primary winding of the saturable transformer, and then controlled to turn off when the charging voltage of the second capacitor reaches its maximum. The saturable transformer operates as a saturable inductor that magnetically saturates at any time after the switch is turned off, so that a pulse voltage is output across the third capacitor by the third current. A pulse generator characterized by applying the output pulse voltage to the load.

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