Parallel video encoder device, parallel video encoder processing method, and parallel video encoder processing program

Abstract

To reduce a transfer amount between chips while maintaining performance.SOLUTION: A parallel video encoding device divides an input image and transfers a reference image mutually among a plurality of encoder modules. In the parallel video encoding device, each of the encoder modules has a management table, and the encoder module manages transfer states of the reference image generated by an adjacent encoder module are managed by block units in the management table. The parallel video encoding device is configured to: refer to the management table for each block included in a reference area when requesting the reference image needed for motion search or motion compensation in encoding processing for a frame; generate a read request to a memory of a self chip if the block is in a transfer competition state; wait for the reception of the block without generating a transfer request to an adjacent chip if the block is in a transfer progression state; and store the reference image in the memory of the self chip after generating the transfer request to the adjacent chip and receiving the block if the block is in a non-transfer state, and update a state of the management table.SELECTED DRAWING: Figure 5

Description

Technical Field

[0001] The disclosed technology relates to a parallel video encoder device, a parallel video encoder processing method, and a parallel video encoder processing program.

Background Art

[0002] In order to meet the demand for higher resolution of video encoders such as HEVC (High Efficiency Video Codec), VVC (Versatile Video Coding), and H.26x, a screen-splitting type parallel processing architecture using a plurality of encoder modules is often used. This method has multiple prior examples, ranging from the HDTV encoder in MPEG-2 in the past to the 8K encoder in recent HEVC.

Prior Art Documents

Non-Patent Documents

[0003]

Non-Patent Document 1

Non-Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0004] In video encoding, the locally decoded image generated in each frame is used as a reference image when encoding subsequent frames. To avoid efficiency degradation due to screen splitting, it is necessary to share the reference image between chips in order to perform motion search / motion compensation across the split boundary, as shown in Figure 1 (" / " means "or"). Conventional methods generally involve transferring all areas of the locally decoded image that may be referenced in subsequent frames to adjacent chips immediately after generation (see, for example, Non-Patent Document 1).

[0005] Conventional methods that transfer reference images in advance are not always efficient, as some videos have little movement across segmentation boundaries, resulting in a large portion of the transferred reference image being discarded without being referenced. There are also methods that predict the required range of the reference image and transfer it in advance (see, for example, Non-Patent Document 2). However, when the prediction is wrong, the reference image cannot be used, leading to a decrease in encoding efficiency.

[0006] The disclosed technology was developed in view of the above points, and aims to provide a parallel video encoder device, a parallel video encoder processing method, and a parallel video encoder processing program that can reduce the amount of data transferred between chips while maintaining performance. [Means for solving the problem]

[0007] A first aspect of this disclosure is a parallel video encoder device that divides an input image and transfers reference images between a plurality of encoder modules, wherein each encoder module has a management table, which manages the transfer status of reference images generated by adjacent encoder modules on a block basis, and the encoding processing unit, when requesting a reference image necessary for motion detection or motion compensation during frame encoding processing, refers to the management table for each block included in the reference range, requests a read from its own chip's memory if the image has already been transferred, waits for reception without requesting a transfer from an adjacent chip if the image is being transferred, and if the image has not yet been transferred, requests a transfer from an adjacent chip, stores the image in its own chip's memory after reception, and updates the state of the management table.

[0008] A second aspect of this disclosure is a parallel video encoder processing method for dividing an input image and mutually transferring reference images between multiple encoder modules, wherein each encoder module has a management table, and in the management table manages the transfer status of reference images generated by adjacent encoder modules on a block basis, and in the frame encoding process, when a reference image necessary for motion detection or motion compensation is requested, the computer is instructed to refer to the management table for each block included in the reference range, and if the image has been transferred, a read request is made to the memory of the chip itself, if the image is being transferred, the computer waits for reception without making a transfer request to the adjacent chip, and if the image has not been transferred, a transfer request is made to the adjacent chip, and after receiving the image, it is stored in the memory of the chip itself, and the state of the management table is updated.

[0009] A third aspect of this disclosure is a parallel video encoder processing program that divides an input image and transfers reference images between multiple encoder modules, wherein each encoder module has a management table, which manages the transfer status of reference images generated by neighboring encoder modules on a block basis, and in the frame encoding process, when a reference image necessary for motion detection or motion compensation is requested, the computer is instructed to refer to the management table for each block included in the reference range, and if the image has been transferred, it makes a read request to the memory of its own chip, if the image is being transferred, it waits for reception without making a transfer request to the neighboring chip, and if the image has not been transferred, it makes a transfer request to the neighboring chip, stores the image in the memory of its own chip after receiving it, and updates the state of the management table. [Effects of the Invention]

[0010] According to the disclosed technology, it is possible to reduce the amount of data transferred between chips while maintaining performance. [Brief explanation of the drawing]

[0011] [Figure 1] This diagram schematically shows the inter-chip systems that perform motion search / motion compensation across partition boundaries. [Figure 2] This diagram schematically illustrates instantaneous data transfer between chips. [Figure 3] This figure shows an example of a management table used by an encoder module. [Figure 4] This is a block diagram showing the hardware configuration of a parallel video encoder device. [Figure 5] This is a block diagram showing the functional configuration of the parallel video encoder device of this embodiment. [Figure 6] This flowchart shows the processing flow of flowchart 1 by the parallel video encoder device according to the first embodiment. [Figure 7] This flowchart shows the processing flow of flowchart 2 by the parallel video encoder device according to the first embodiment. [Figure 8] This diagram illustrates the pre-transfer range of frames. [Figure 9] This flowchart shows the processing flow of flowchart 3 by the parallel video encoder device according to the second embodiment. [Modes for carrying out the invention]

[0012] An example of an embodiment of the disclosed technology will be described below with reference to the drawings. In each drawing, identical or equivalent components and parts are given the same reference numerals. Furthermore, the dimensional ratios in the drawings are exaggerated for illustrative purposes and may differ from actual ratios.

[0013] First, an overview of the technology of each embodiment of this disclosure will be described (hereinafter, matters common to each embodiment will be referred to as "this embodiment"). In this embodiment, the encoder module is defined as a chip unit, and each encoder module has a management table. In this embodiment, by efficiently performing immediate transfers to request the necessary reference images from adjacent chips using the management table, the amount of data transferred between chips is efficiently reduced while maintaining performance. Figure 2 is a schematic diagram of immediate transfer between chips. In Figure 2, the chip in question shows the encoder module of interest, and the chip above shows the adjacent encoder module. In this embodiment, the management table is used when performing motion detection / motion compensation (table 25E in Figure 2 (hereinafter, the reference numeral is omitted)). Motion detection / motion compensation is denoted as ME / MC (Motion Estimation / Motion Compensation). The chip is equipped with a CPU (Central Processing Unit) 21E for executing various processes as an encoder module. Processing related to ME / MC is executed using a CODEC 22E. The reference image data itself is stored in the Cache 23E or DRAM (Dynamic Random Access Memory) 24E of each chip (indicated by (R) in Figure 2). (a1) to (a3) ​​in Figure 2 represent block units managed by the management table, with (a1) representing the upper area, (a2) representing the local area, and (a3) ​​representing the lower area, corresponding to the upper chip, local chip, and lower chip, respectively. It is assumed that the memory storage address of each block of the reference image is uniquely determined from the block's coordinates and frame number, including data transferred from adjacent chips and data originally located on the local chip. Information on whether a particular 8x8 pixel block has been transferred can be managed within each chip by determining whether or not the chip has received the block in question. Therefore, there is no need to exchange management table information between chips (modules).

[0014] In this embodiment, as shown in FIG. 3, the encoder module has a management table that manages the transfer state of the reference image (such as whether it has been transferred to its own chip, etc.) in units of blocks such as 8x8 pixels, and performs processing according to the state of the blocks. (a1) The shaded part in the upper region is a block that has been transferred to its own chip. In the case of transfer completed, a read request is made to the memory of its own chip. The chip memory mentioned here is Cache 23E or DRAM 24E (the same applies hereinafter). In the case of untransferred, a transfer request is made to an adjacent chip, and after the transfer is completed, the data is stored in the memory of its own chip. Also, in the case of waiting for transfer, control is performed so as not to make duplicate transfer requests. Thereby, the data amount of inter-chip transfer with a small bandwidth can be suppressed, and the delay due to waiting for transfer can be suppressed.

[0015] Also, in the first embodiment, for the reference image in the region with a high probability of being referenced, by pre-transferring it in the same manner as the prior art, an increase in bursty inter-chip transfer can be suppressed, and the transfer delay can be made smaller.

[0016] The bandwidth freed up by the technology of this embodiment can be allocated to other data transfers, enabling reduction of the bandwidth of the inter-chip interface and reduction of the hardware cost. Also, the technology of this embodiment exhibits more effects in a video encoder, but it can also be applied to a video decoder device.

[0017] Hereinafter, the configuration of this embodiment will be described.

[0018] FIG. 4 is a block diagram showing the hardware configuration of the parallel video encoder device 100.

[0019] As shown in Figure 4, the parallel video encoder device 100 includes a CPU (Central Processing Unit) 11, a ROM (Read Only Memory) 12, a RAM (Random Access Memory) 13, storage 14, an input unit 15, a display unit 16, a communication interface (I / F) 17, and multiple encoder module chips 18 (hereinafter simply referred to as "chips"). Each component is connected to the others via a bus 19 so as to be able to communicate with each other.

[0020] The CPU 11 is a central processing unit that executes various programs and controls various components. Specifically, the CPU 11 reads a program from the ROM 12 or storage 14 and executes the program using the RAM 13 as a working area. The CPU 11 controls each of the above components and performs various calculations according to the program stored in the ROM 12 or storage 14. In this embodiment, the ROM 12 or storage 14 stores a parallel video encoder processing program.

[0021] ROM12 stores various programs and data. RAM13 temporarily stores programs or data as a working area. Storage14 consists of a storage device such as an HDD (Hard Disk Drive) or SSD (Solid State Drive) and stores various programs, including the operating system, and various data.

[0022] The input unit 15 includes a pointing device such as a mouse and a keyboard, and is used for various types of input.

[0023] The display unit 16 is, for example, a liquid crystal display and displays various information. The display unit 16 may also function as an input unit 15 by employing a touch panel system.

[0024] The communication interface 17 is an interface for communicating with other devices such as terminals. For such communication, a wired communication standard such as Ethernet® or FDDI, or a wireless communication standard such as 4G, 5G, or Wi-Fi® may be used.

[0025] [First Embodiment] Next, the functional configurations of the parallel video encoder device 100 according to the first embodiment will be described. Figure 5 is a block diagram showing the functional configuration of the parallel video encoder device of this embodiment. Each functional configuration is realized by the CPU 11 reading the parallel video encoder processing program stored in the ROM 12 or storage 14, expanding it into the RAM 13, and executing it.

[0026] As shown in Figure 5, the parallel video encoder device 100 is functionally configured to include a pre-transfer unit 102 and an encoding processing unit 110. The parallel video encoder device 100 has these functional processing units for each encoder module. In the parallel video encoder device 100, each encoder module has a management table, in which the transfer status of the reference image generated by the adjacent encoder module is managed in block units.

[0027] The pre-transfer unit 102 pre-transfers a portion of the reference image according to the pre-transfer range before the encoding process of the current frame begins. The processing of the pre-transfer unit 102 will be explained in flowchart 1 below.

[0028] When the encoding processing unit 110 requests a reference image necessary for motion detection or motion compensation during frame encoding, it refers to a management table for each block included in the reference range and performs processing according to the transfer status. If the transfer has already been completed, it requests a read from its own chip's memory. If the transfer is in progress, it waits for reception without requesting a transfer from an adjacent chip. If the transfer has not yet been completed, it requests a transfer from an adjacent chip, stores the received image in its own chip's memory, and updates the table status.

[0029] Furthermore, in the first embodiment, after the encoding process for the current frame has started, the encoding processing unit 110 determines the transfer status based on both the pre-transfer range information and the information in the management table.

[0030] Furthermore, if a single reference frame is referenced across multiple encoded frames, the encoding processing unit 110 continues to use the management table while it is being referenced. Once it is confirmed that the reference frame will no longer be referenced, it initializes the values ​​of all blocks in the management table and uses it as the management table for the new reference frame.

[0031] Next, the operation of the parallel video encoder device 100 according to the first embodiment will be described. Figures 6 and 7 are flowcharts illustrating the flow of parallel video encoder processing in the parallel video encoder device 100 according to the first embodiment. The CPU 11 reads the parallel video encoder processing program from the ROM 12 or storage 14, expands it into the RAM 13, and executes it, thereby executing processing in each encoder module. In the first embodiment, pre-transfer is performed according to flowchart 1 shown in Figure 6, and then immediate transfer is performed according to flowchart 2 shown in Figure 7. Each process in flowchart 1 is executed by the CPU 21E of each encoder module. Figure 8 is a diagram illustrating the pre-transfer range of frames. Flowchart 2 is the ME / MC and encoding process (hereinafter referred to as encoding process) for frames, which is executed by the CPU 21E of each encoder module as the encoding processing unit 110.

[0032] Flowchart 1 explains the process using the order of frames (n1 to n6) as an example. The pre-transfer processing in steps S1-1 and S1-2 is the processing performed by the pre-transfer unit 102. Steps S1-3 to S1-5 are the processing performed by the encoding processing unit 110.

[0033] In step S1-1, when encoding the frame (n1), the pre-transfer processing is performed. In step S1-1, when encoding the current frame (n1), the CPU 21E determines the pre-transfer range for a portion of the reference image frame (n2) based on the reference range for the reference frame (n0). The reference range here is the range used when performing the encoding process with the reference frame (n0) as the reference image. The pre-transfer range can be determined, for example, by determining the vertical pixel width of the pre-transfer based on the history (reference range) of how far pixels from the upper and lower division boundaries have been referenced for each divided region. In this case, it is assumed that information about which vertical range of reference image data has been transferred is transmitted from the transmitting side to the receiving side chip.

[0034] In step S1-2, the system moves to the next frame (n2) and performs pre-transfer processing when encoding frame (n2). In step S1-2, the CPU 21E, for the current frame (n2), immediately after the local decoded image, which is the reference image, is generated, transfers the reference image to the chip responsible for the upper or lower divided image, based on the pre-transfer range determined in the previous frame (n1).

[0035] In step S1-3, the process moves to the next frame (n3) and performs encoding on frame (n2). In step S1-3, the CPU 21E uses the reference frame (n2) as the reference image for the current frames (n3, n4, n5, n6) and performs encoding based on the pre-transfer range information and the management table information. The encoding process is carried out while deciding whether to request the necessary reference image from the memory of the chip itself or from an adjacent chip. The encoding process will be explained in detail with reference to flowchart 2 in Figure 7.

[0036] In step S1-4, the CPU 21E determines whether there are any further references to the reference frame used in step S1-3. This determination can be made by thresholding based on the Decode Picture Buffer size, etc. If there are no further references, the process proceeds to step S1-5. If there are further references, the process returns to step S1-3 and performs encoding on the next frame (nn).

[0037] In step S1-5, CPU21E initializes the values ​​of all blocks in the management table once it confirms that there are no further references to the reference frame (n2), and reuses it as a management table for a new reference frame. Subsequently, if there are frames, the processes in steps S1-1 to S1-5 of flowchart 1 are executed again.

[0038] Next, we will explain the encoding process of the frame in flowchart 2 of Figure 7.

[0039] In step S2-1, the CPU 21E specifies the target frame and determines the necessary reference frame and reference range for each coding process of each CU (Coding Unit) in that frame. Here, the motion search method and motion search range for the CU are determined based on the ME / MC processing results and coding processing results of spatially and temporally adjacent processed CUs, and the necessary reference frame and reference range are determined based on that. In the example in Figure 8, the reference frame (n2) is referenced for the target frames (n3, n4, n5, n6).

[0040] In step S2-2, CPU21E sets all 8x8 blocks (x,y) included in the reference range as targets for the following processing. The target block is the requesting ME block.

[0041] In step S2-3, CPU21E checks whether the requesting ME block is within the pre-transfer range. The pre-transfer range can be determined, for example, by the vertical coordinates of an 8x8 block. If it is not within the pre-transfer range, the process proceeds to step S2-4; if it is within the pre-transfer range, the process proceeds to step S2-5.

[0042] In step S2-4, if the data is outside the scope of the pre-transfer, the CPU21E then checks the information of block (x,y) in the management table on the transfer interface and determines the transfer status. If the status is "transferred," the process proceeds to step S2-5. If the status is "not transferred," the process proceeds to step S2-7. If the status is "transferring," the process proceeds to step S2-11.

[0043] In step S2-5, CPU21E requests a read from memory in the requesting ME block if the state has already been transferred.

[0044] In step S2-6, CPU21E waits for the read operation to complete, and after the read operation is complete, proceeds to the next step S2-14.

[0045] In step S2-7, if the state is not yet transferred, the CPU21E requests a transfer from the transfer interface to the adjacent chip and changes the state of block (x,y) to "transfer in progress". In step S2-8, the completion of the transfer is confirmed.

[0046] In step S2-9, after the transfer is complete, CPU21E transfers the received data to the requesting ME block. Then it proceeds to step S2-14. After a certain period of time, step S2-10 is performed.

[0047] In step S2-10, after a certain period of time, the CPU 21E writes the data to memory and changes the state of block (x,y) to "transferred".

[0048] In step S2-11, if the status is "transferring", the CPU21E adds the request information to the transfer waiting queue of the transfer interface. In step S2-12, the completion of the transfer is confirmed.

[0049] In step S2-13, after confirming the completion of the transfer, CPU21E transfers it to the requesting ME block. Then it proceeds to step S2-14.

[0050] In step S2-14, CPU21E determines whether all 8x8 block data has been collected within the time limit. If it has been collected, the process proceeds to step S2-15; otherwise, it proceeds to step S2-16.

[0051] In step S2-15, CPU21E performs ME processing.

[0052] In step S2-16, if the components are not matched, CPU21E takes action such as selecting another encoding mode, which will be treated as an ME processing error.

[0053] In step S2-17, the CPU 21E determines whether the encoding process has been completed for all CUs in the frame. If it has been completed, the process ends; otherwise, it returns to step S2-1 and repeats the process.

[0054] As described above, the parallel video encoder device 100 of the first embodiment makes it possible to reduce the amount of data transferred between chips while maintaining performance.

[0055] [Second Embodiment] In the second embodiment, pre-transfer as in the first embodiment is not performed, and immediate transfer is performed as shown in flowchart 3 of Figure 9. This makes implementation simpler compared to the first embodiment. Furthermore, the parallel video encoder device 100 of the second embodiment functionally includes an encoding processing unit 110 and does not have a pre-transfer unit 102.

[0056] In step S3-1, the CPU 21E specifies the target frame and determines the necessary reference frame and reference range for each coding process of each CU (Coding Unit) of that frame.

[0057] In step S3-2, CPU21E sets all 8x8 blocks (x,y) included in the reference range as targets for the following processing. The target block is the requesting ME block.

[0058] In step S3-4, if the data is outside the scope of the pre-transfer, the CPU21E then checks the information of block (x,y) in the management table on the transfer I / F and determines the transfer status. If the status is transferred, proceed to step S3-5. If the status is not transferred, proceed to step S3-7. If the status is being transferred, proceed to step S3-11.

[0059] In step S3-5, CPU21E requests a read from memory in the requesting ME block if the state has already been transferred.

[0060] In step S3-6, CPU21E waits for the read operation to complete, and after the read operation is complete, proceeds to the next step S3-14.

[0061] In step S3-7, if the state is not yet transferred, the CPU21E requests a transfer from the transfer interface to the adjacent chip and changes the state of block (x,y) to "transfer in progress". In step S3-8, the completion of the transfer is confirmed.

[0062] In step S3-9, after the transfer is complete, CPU21E writes the received data to memory and simultaneously changes the status to "transferred".

[0063] In step S3-10, CPU21E notifies the requesting ME block of the change in state. Then, the process proceeds to step S3-5.

[0064] In step S3-11, if the status is "transferring", the CPU 21E adds the request information to the transfer waiting queue of the transfer interface. In step S3-12, the completion of the transfer is confirmed.

[0065] In step S3-13, after confirming the completion of the transfer, CPU21E notifies the requesting ME of the completion of the transfer. Then, the process proceeds to step S3-5.

[0066] In step S3-14, CPU21E determines whether all 8x8 block data has been collected within the time limit. If it has been collected, the process proceeds to step S3-15; otherwise, it proceeds to step S3-16.

[0067] In step S3-15, CPU21E performs ME processing.

[0068] In step S3-16, if the components are not matched, CPU21E takes action such as selecting another encoding mode, which will be treated as an ME processing error.

[0069] In step S3-17, the CPU 21E determines whether the encoding process has been completed for all CUs in the frame. If it has been completed, the process ends; otherwise, it returns to step S3-1 and repeats the process.

[0070] As described above, the parallel video encoder device 100 of the second embodiment makes it possible to easily reduce the amount of data transferred between chips while maintaining performance.

[0071] In addition, the parallel video encoder processing that the CPU reads and executes in each of the above embodiments may be executed by various processors other than the CPU. Examples of such processors include dedicated electrical circuits, which are processors with circuit configurations specifically designed to perform specific processing, such as FPGAs (Field-Programmable Gate Arrays), PLDs (Programmable Logic Devices) whose circuit configuration can be changed after manufacturing, GPUs (Graphics Processing Units), and ASICs (Application Specific Integrated Circuits). Furthermore, the parallel video encoder processing may be executed by one of these various processors, or by a combination of two or more processors of the same or different types (for example, multiple FPGAs, and a combination of a CPU and an FPGA). More specifically, the hardware structure of these various processors is an electrical circuit that combines circuit elements such as semiconductor elements.

[0072] Furthermore, although the above embodiments describe a configuration in which the parallel video encoder processing program is pre-stored (installed) in the storage 14, the invention is not limited to this configuration. The program may be provided in a form stored on a non-transitory storage medium such as a CD-ROM (Compact Disk Read Only Memory), DVD-ROM (Digital Versatile Disk Read Only Memory), or USB (Universal Serial Bus) memory. Alternatively, the program may be provided in a form that can be downloaded from an external device via a network.

[0073] The following additional information is disclosed regarding the embodiments described above.

[0074] (Additional note 1) Memory and At least one processor connected to the memory, Includes, The aforementioned processor, A parallel video encoder processing device that divides an input image and transfers reference images between multiple encoder modules, Each encoder module has a management table, which manages the transfer status of reference images generated by neighboring encoder modules on a block-by-block basis. In the frame encoding process, when requesting a reference image necessary for motion detection or motion compensation, the management table is referenced for each block included in the reference range. If the data has already been transferred, a read request is sent to the chip's own memory. If a transfer is in progress, wait for reception without sending a transfer request to the adjacent chip. If the data has not yet been transferred, a transfer request is sent to the adjacent chip, and after receiving the data, it is stored in the memory of the chip itself, and the state of the management table is updated. A parallel video encoder device configured in such a way.

[0075] (Additional note 2) A non-temporary storage medium that stores a program executable by a computer to perform parallel video encoder processing, which involves dividing an input image and transferring reference images between multiple encoder modules, Each encoder module has a management table, which manages the transfer status of reference images generated by neighboring encoder modules on a block-by-block basis. In the frame encoding process, when requesting a reference image necessary for motion detection or motion compensation, the management table is referenced for each block included in the reference range. If the data has already been transferred, a read request is sent to the chip's own memory. If a transfer is in progress, wait for reception without sending a transfer request to the adjacent chip. If the data has not yet been transferred, a transfer request is sent to the adjacent chip, and after receiving the data, it is stored in the memory of the chip itself, and the state of the management table is updated. Non-transitory storage medium. [Explanation of Symbols]

[0076] 100 Parallel Video Encoder Devices 102 Pre-transfer section 110 Encoding Processing Unit

Claims

1. A parallel video encoder device that divides an input image and transfers reference images between multiple encoder modules, Each encoder module has a management table, which manages the transfer status of reference images generated by neighboring encoder modules on a block-by-block basis. In the frame encoding process, when requesting a reference image necessary for motion detection or motion compensation, the management table is referenced for each block included in the reference range. If the data has already been transferred, a read request is sent to the chip's memory. If a transfer is in progress, wait for reception without sending a transfer request to the adjacent chip. If the data has not been transferred, an encoding processing unit sends a transfer request to an adjacent chip, stores the data in its own chip's memory after receiving it, and updates the state of the management table. It includes a pre-transfer unit that pre-transfers a portion of the reference image according to the pre-transfer range before the encoding process of the current frame begins, The encoding processing unit is a parallel video encoder device that, after the encoding processing of the current frame has started, determines the transfer status based on both the pre-transfer range information and the information in the management table.

2. The parallel video encoder device according to claim 1, wherein if one reference frame is referenced across multiple encoded frames, the management table is used continuously while it is being referenced, and when it is confirmed that the reference frame will no longer be referenced, the values ​​of all blocks in the management table are initialized and used as the management table for the new reference frame.

3. A parallel video encoder processing method that divides an input image and transfers reference images between multiple encoder modules, Each encoder module has a management table, which manages the transfer status of reference images generated by neighboring encoder modules on a block-by-block basis. In the frame encoding process, when requesting a reference image necessary for motion detection or motion compensation, the management table is referenced for each block included in the reference range. If the data has already been transferred, a read request is sent to the chip's memory. If a transfer is in progress, wait for reception without sending a transfer request to the adjacent chip. If the data has not yet been transferred, a transfer request is sent to the adjacent chip, and after receiving it, the data is stored in the memory of the chip itself, and the state of the management table is updated. Before the encoding process for the current frame begins, a portion of the reference image is transferred in advance according to the pre-transfer range. In the encoding process described above, after the encoding process for the current frame has started, the transfer status is determined based on both the information of the pre-transfer range and the information in the management table. A parallel video encoder processing method that has a computer perform the processing.

4. A parallel video encoder processing program that divides an input image and transfers reference images between multiple encoder modules, Each encoder module has a management table, which manages the transfer status of reference images generated by neighboring encoder modules on a block-by-block basis. In the frame encoding process, when requesting a reference image necessary for motion detection or motion compensation, the management table is referenced for each block included in the reference range. If the data has already been transferred, a read request is sent to the chip's memory. If a transfer is in progress, wait for reception without sending a transfer request to the adjacent chip. If the data has not yet been transferred, a transfer request is sent to the adjacent chip, and after receiving it, the data is stored in the memory of the chip itself, and the state of the management table is updated. Before the encoding process for the current frame begins, a portion of the reference image is transferred in advance according to the pre-transfer range. In the encoding process described above, after the encoding process for the current frame has started, the transfer status is determined based on both the information of the pre-transfer range and the information in the management table. A parallel video encoder processing program that has a computer perform the processing.

Images