Graphics processors, chips, and electronic devices

Abstract

Provided are a graphics processor, a chip, and an electronic device. The graphics processor includes at least two data-instruction dispatchers and at least two graphics processor cores. Each data-instruction dispatcher is connected to at least one graphics processor core. One data-instruction dispatcher and one graphics processor core are connected via a set of data-instruction transmission lines. The graphics processor is configured to provide at least one virtual graphics processor. Each virtual graphics processor includes one data-instruction dispatcher and some or all of the graphics processor cores connected thereto. The graphics processor is capable of providing at least one virtual graphics processor, enabling the graphics processor to be shared by multiple users.

Description

[Technical Field]

[0001] This application belongs to the technical field of processors, and relates to graphics processors, and more particularly to graphics processors, chips, and electronic devices. [Background technology]

[0002] A graphics processing unit (GPU), also known as a display core, video processor, or display chip, is a microprocessor that specializes in image and graphics-related calculations in personal computers, workstations, game consoles, and some mobile devices (such as tablet PCs and smartphones). GPUs reduce the video card's reliance on the central processing unit (CPU) and complete some of the tasks previously performed by the CPU.

[0003] Typically, there is a limit to the number of graphics processors in electronic devices. Therefore, to utilize limited graphics processor resources more efficiently and better meet user needs, graphics processor virtualization technology has been developed. Graphics processor virtualization requires virtualizing the actual graphics processor into multiple virtual graphics processors to accommodate simultaneous use by multiple users. Each user uses one virtual graphics processor. Furthermore, each virtual graphics processor can use one or more graphics processor cores. However, in conventional graphics processor virtualization technologies, the graphics processor cores used by each virtual graphics processor are often fixed, making it difficult to flexibly configure according to actual needs. [Overview of the project] [Problems that the invention aims to solve]

[0004] This invention provides a graphics processor, chip, and electronic device in which the graphics processor cores included in each virtual graphics processor can be configured according to actual needs. [Means for solving the problem]

[0005] In a first aspect, an embodiment of the present application provides a graphics processor. The graphics processor includes at least two data-instruction dispatchers and at least two graphics processor cores. Each of the data-instruction dispatchers is connected to at least one of the graphics processor cores. One of the data-instruction dispatchers and one of the graphics processor cores are connected via a set of data-instruction transmission lines. The graphics processor is configured to provide at least one virtual graphics processor. Each of the virtual graphics processor includes one of the data-instruction dispatchers and some or all of the graphics processor cores connected thereto.

[0006] In the implementation of the first phase, the graphics processor is configured to provide n virtual graphics processors based on the received instructions. n is any positive integer less than or equal to N, where N is the number of graphics processor cores.

[0007] In the implementation method of the first phase, the i-th data instruction dispatcher of the graphics processor is floor(N / n i i and n are connected to ) of the aforementioned graphics processor cores. i These are all positive integers less than or equal to N, and floor is the floor function.

[0008] In the implementation of the first phase, the graphics processor includes N data instruction dispatchers. Of these, one data instruction dispatcher is connected to one of the N graphics processor cores. j -mj+1 Each of the data instruction dispatchers is N / m j connected to m of the graphics processor cores. j And m j+1 and m are adjacent positive integers divisible by N, 1 ≤ m j+1 <m j ≤ N.

[0009] In the implementation manner of the first aspect, the graphics processor further includes a data selector. The graphics processor cores connected to at least two of the data instruction dispatchers are connected to the data instruction dispatchers via the data selector.

[0010] In the implementation manner of the first aspect, the numbers of the data instruction dispatchers and the graphics processor cores are both 8. The connection manner between the data instruction dispatcher and the graphics processor core includes one 1-to-8 connection, one 1-to-4 connection, two 1-to-2 connections, and four 1-to-1 connections.

[0011] In the implementation manner of the first aspect, the number of physical layers of the graphics processor is configured based on the number of the data instruction transmission lines.

[0012] In the implementation manner of the first aspect, the data instruction dispatcher is fully connected to the graphics processor cores.

[0013] In the second aspect, the embodiments of the present application provide a chip. The chip includes the graphics processor and input / output pins described in any of the implementation manners of the first aspect of the present application.

[0014] In the second aspect, the embodiments of the present application provide an electronic device. The electronic device includes the graphics processor and a memory described in any of the implementation manners of the first aspect of the present application.

Advantages of the Invention

[0015] The graphics processor provided in the embodiments of the present application can provide at least one virtual graphics processor. The graphics processor cores included in each virtual graphics processor can be configured based on actual needs. Therefore, in specific applications, the graphics processor cores included in the virtual graphics processor can be flexibly configured based on actual needs.

[0016] In some embodiments of the present application, by optimizing the connection method between the data and instruction dispatcher and the graphics processor core, the number of connections between the data and instruction dispatcher and the graphics processor core can be reduced, and the congestion problem in the chip placement and routing (P&R) stage can be avoided. This is beneficial for reducing the chip area. Also, in some embodiments, the number of layers in the physical layer of the graphics processor is configured based on the number of data and instruction transmission lines. In these embodiments, by optimizing the connection method between the data and instruction dispatcher and the graphics processor core, the number of layers in the physical layer of the graphics processor can be reduced. Brief Description of the Drawings

[0017] [Figure 1] It shows a schematic structural diagram of an electronic device. [Figure 2] It shows a schematic structural diagram of a graphics processor. [Figure 3A] It shows a schematic structural diagram of the graphics processor provided in an embodiment of the present application. [Figure 3B] It shows a schematic diagram of the connection relationship between the data and instruction dispatcher and the graphics processor core in an embodiment of the present application. [Figure 4] It shows a schematic structural diagram of the graphics processor provided in an embodiment of the present application. [Figure 5A] It shows a schematic structural diagram of the graphics processor provided in an embodiment of the present application. [Figure 5B]A schematic diagram of the graphics processor provided in one embodiment of the present invention is shown. [Figure 5C] A schematic diagram of the graphics processor provided in one embodiment of the present invention is shown. [Figure 6] A schematic diagram of the graphics processor provided in one embodiment of the present invention is shown. [Figure 7] A schematic diagram of the chip provided in one embodiment of the present invention is shown. [Modes for carrying out the invention]

[0018] Embodiments of the present application will be described below by specific examples. Those skilled in the art will readily understand the other advantages and effects of the present application from the disclosures herein. Furthermore, the present application may be implemented or applied by other different specific embodiments. Also, various additions or modifications may be made to each detail herein, based on different perspectives and applications, without departing from the spirit of the present application. For the purposes of explanation, the following embodiments and features may be combined with each other, provided that they do not contradict each other.

[0019] In this application, unless otherwise explicitly defined and limited, terms such as "attach," "connect," "bond," and "fix" should be interpreted broadly. For example, a connection may be fixed, detachable, or form a single unit. It may also be mechanical or electrical. Furthermore, it may be a direct connection, an indirect connection via an intermediate medium, internal communication between two parts, or an interaction relationship between two parts. A person skilled in the art will be able to interpret the specific meaning of these terms in this application according to the specific circumstances.

[0020] It should be noted that the drawings provided in the following embodiments only provide a general overview of the basic concept of the present invention. The drawings only show assemblies relevant to the present invention and do not represent the number, shape, and size of assemblies that would actually be used in implementation. The form, number, and proportions of each assembly may be arbitrarily changed in actual implementation, and the layout and form of the assemblies may become more complex.

[0021] This application provides a graphics processor in the following embodiments. Application scenarios for the graphics processor include, but are not limited to, electronic devices. These electronic devices can be different types of electronic devices such as mobile phones, tablet PCs, personal computers (PCs), personal digital assistants (PDAs), smartwatches, netbooks, wearable electronic devices, augmented reality (AR) devices, virtual reality (VR) devices, in-vehicle devices, intelligent cars, smart speakers, robots, and smart glasses.

[0022] Refer to Figure 1, which shows a schematic diagram of an electronic device 100 in one embodiment of the present invention. The electronic device 100 includes a system processor 110 (which may be a CPU, for example), a graphics processor 120, memory 130, and a display 140.

[0023] In specific operation, the system processor 110, upon startup and entering the operating system (OS), enables the provision of various user system operations, including user applications, data processing services, communication services, storage services, game services, or other operations. The graphics processor 120 can provide the system processor 110 with operations such as graphics processing, rendering services, and correction. Specifically, referring to Figure 2, the graphics processor 120 provides operations related to the assembly, including graphics processor cores (e.g., 121-1, 121-2, ..., 121-k), instruction configuration processor 122, crossbar switch bus 123, etc., where k is a positive integer. As can be understood, operations such as graphics processing, rendering services, and correction can be completed by one or more functional modules of the graphics processor 120. For example, one functional module of the graphics processor 120 can appropriately complete one operation. The graphics processor 120 in Figure 1 may be an independent element connected to the system processor 110 via the communication circuit 150. However, it should be understood that in other examples, the graphics processor 120 may be integrated into the system processor 110.

[0024] Memory 130 may include random access memory (RAM), cache memory devices, or other volatile memory elements used in the system processor 110 or graphics processor 120. Other volatile memory elements used in the graphics processor 120 include, for example, caches that can be integrated into the graphics processor 120, such as the secondary (L2) caches 124-1, 124-2, ..., 124-k shown in Figure 2. Memory 130 may also further include non-volatile memory elements such as hard disk drives (HDD), flash memory devices, solid state drives (SSD), or other memory devices for storing operating systems, applications, or other software or firmware used in the electronic device 100.

[0025] Electronic devices 100 can communicate with each other via one or more communication links (e.g., one or more network links). For example, the communication links may use metal, glass, optics, air, space, or any other material as the transmission medium. Examples of communication links include various communication interfaces and protocols such as the Internet Protocol (IP), Ethernet, Universal Serial Bus (USB), Bluetooth®, WiFi, or other communication signaling or communication formats (including combinations, modifications, or variants thereof). The communication links may be direct links, include intermediate networks, systems, or devices, or include logical network links transmitted over multiple physical links.

[0026] The electronic device 100 may include software such as an operating system, logs, databases, utilities, drivers, network software, user applications, data processing applications, game applications, and other software stored on a computer-readable medium. The software of the electronic device 100 may include one or more platforms controlled by a distributed computing system or cloud computing service. The software of the electronic device 100 may include logical interface elements such as software-defined interfaces and application programming interfaces (APIs).

[0027] The software of the electronic device 100 can be used to generate data to be rendered by the graphics processor 120 and to control the operation of the graphics processor 120 to render graphics for output to one or more displays 140.

[0028] The system processor 110, graphics processor 120, memory 130, and display 140 can communicate with each other via a connected communication circuit 150. The illustrated communication circuit 150 may use metal, glass, optics, air, space, or any other material as a transmission medium. Various communication protocols and signaling, such as computer buses (including combinations or variants thereof), can be used in the communication circuit 150. The communication circuit 150 may be a direct link, may include an intermediate network, system, or device, or may include a logical network link that transmits over multiple physical links.

[0029] Figure 2 shows an example of a graphics processor 120 in an embodiment of the present invention. As shown in Figure 2, the graphics processor 120 specifically includes a plurality of graphics processor cores 121-1, 121-2, ... 121-k, an instruction configuration processor 122, a crossbar switch bus 123, and a plurality of L2 caches 124-1, 124-2, 124-3 ... 124-k. The crossbar switch bus 123 is connected between the graphics processor cores 121 and the L2 caches 124, providing a path for the graphics processor cores 121 to access the L2 caches 124 and a path for the L2 caches 124 to return data to the graphics processor cores 121. The L2 caches 124 are further connected to external memory 130 via a memory interface (MIF).

[0030] In the configuration provided in the embodiment of the present invention, the system processor 110 prepares the tasks and data to be executed by the graphics processor 120 and transmits them to the graphics processor core 121 in the form of an instruction configuration. Specifically, the instruction configuration processor 122 receives the instructions issued from the system processor 110, analyzes the tasks, and transmits them directly to the graphics processor core 121, thereby causing the graphics processor core 121 to start executing the tasks. Alternatively, the tasks may be transmitted from the instruction configuration processor 122 to the memory 130 via the crossbar switch bus 123, and then read and processed by the graphics processor core 121 from the memory 130.

[0031] The specific process by which the graphics processor core 121 executes a task includes the graphics processor core 121 reading and processing external data related to the task from memory 130 and writing the data back. The graphics processor core 121 uses multi-threaded processing, which processes a certain amount of data with a single instruction. Therefore, in order to reduce the delay in data acquisition and storage by the graphics processor core 121 and improve the processing efficiency of the graphics processor core 121, a typical design places an L2 cache 124 between the graphics processor core 121 and memory 130, and reduces the waiting time of the graphics processor core 121 by pre-acquiring and caching a large amount of data using the L2 cache 124.

[0032] In the following, the technical solution in the embodiment of this application will be described in detail by combining the drawings in the embodiment of this application.

[0033] Figure 3A shows a schematic diagram of a graphics processor 300 in one embodiment of the present invention. As shown in Figure 3A, the graphics processor 300 includes M data and instruction dispatchers 310-1 to 310-M and N graphics processor cores (clusters) 330-1 to 330-N. M and N are both positive integers of 2 or greater. Each graphics processor core 330 includes a graphics processing pipeline. In some implementations, the values ​​of M and N may be the same. In other implementations, the values ​​of M and N may be different. Each data and instruction dispatcher 310 can be connected to at least one graphics processor core 330 and can be connected to a maximum of N graphics processor cores 330. The connection method between the data / instruction dispatcher 310 and the graphics processor core 330 includes, but is not limited to, a direct connection between the data / instruction dispatcher 310 and the graphics processor core 330, or an indirect connection between the data / instruction dispatcher 310 and the graphics processor core 330 via a data selector or the like. One data / instruction dispatcher 310 and one graphics processor core 330 are connected via one set of data / instruction transmission lines. Each set of data / instruction transmission lines consists of, for example, 1000 to 2000 data / instruction transmission lines.

[0034] In embodiments of the present invention, the graphics processor 300 is used to provide at least one virtual graphics processor. Each virtual graphics processor includes one data-instruction dispatcher 310 and some or all of the graphics processor cores 330 connected to the data-instruction dispatcher 310. For example, in the graphics processor 300 shown in Figure 3A, the data-instruction dispatcher 310-1 and the graphics processor cores 330-1 and 330-N connected thereto can provide one virtual graphics processor, and the data-instruction dispatcher 310-2 and its associated graphics processor core 330-2 can provide another virtual graphics processor.

[0035] In some implementations, the graphics processor 300 can provide multiple virtual graphics processors at the same time. Each virtual graphics processor may contain multiple graphics processor cores 330, but each graphics processor core 330 is contained within only one virtual graphics processor. Each user can use one virtual graphics processor. Also, each graphics processor core 330 can only be used by one user at the same time.

[0036] Selectively, Figure 3B shows a schematic diagram of the connection relationship between the data / instruction dispatcher and the graphics processor core in an embodiment of the present invention. The data / instruction dispatcher 310-1, for example, is connected to double data rate SDRAM (DDR) via the advanced extensible interface (AXI) and the advanced high performance bus (AHB) interface (host interface, HI) 0. The advanced extensible interface protocol is a bus protocol that supports high performance, high bandwidth, and low latency on-chip buses. The advanced extensible interface protocol enables superior performance by making the system on chip (SoC) smaller in area and with lower energy loss. The advanced high performance bus is a high-performance bus primarily used for connecting high-performance modules, and its main features include single-clock edge operation, non-3-state execution, and burst transfer support. The graphics processor core 330-1 includes a shader module, a transform feedback (TFB) module, a position primitive assembly (PPA) module, a final primitive assembly (FPA) module, a pixel engine (PE) module, and other modules. The final primitive assembly module is used to write intermediate results to memory. Position primitive assembly is used to perform culling operations such as triangular back-face culling and zero-area culling. The FPA module is used to perform viewport frustum transformations, and the pixel engine module is used to perform operations such as alpha blending on pixels.

[0037] As is clear from the above description, the graphics processor 300 provided in the embodiment of the present application can provide a user with at least one virtual graphics processor. Virtualization of the graphics processor 300 makes it possible for multiple users to share the graphics processor 300.

[0038] According to one embodiment of the present invention, the graphics processor 300 is configured to provide n virtual graphics processors based on an received instruction. Herein, n is any positive integer less than or equal to N. Also, N is the number of graphics processor cores 330, and may be a number such as 4, 8, or 16. Selectively, the n virtual graphics processors include all N graphics processor cores 330, but the present invention is not limited to this.

[0039] In one embodiment of the present invention, the i-th data instruction dispatcher of the graphics processor is floor(N / n i It is connected to ) graphics processor cores. Note that i and n in1=4 is a positive integer less than or equal to N, and floor is the floor function. See Figure 4. For example, in the case of N=4, the first data instruction dispatcher 410-1 of the graphics processor 400 is connected to one graphics processor core 430-1 (n1=3), the second data instruction dispatcher 410-2 is connected to four graphics processor cores 430-1 to 430-4 (n2=1), the third data instruction dispatcher 410-3 is connected to two graphics processor cores 430-1 and 430-3 (n3=2), and the fourth data instruction dispatcher 410-4 is connected to two graphics processor cores 430-2 and 430-4 (n4=2). In the embodiments of the present invention, the connection method between the data / instruction dispatcher 410 and the graphics processor core 430 includes, but is not limited to, a direct connection between the data / instruction dispatcher 410 and the graphics processor core 430, or an indirect connection between the data / instruction dispatcher 410 and the graphics processor core 430 via a data selector or the like.

[0040] The graphics processor 400 shown in Figure 4 can be configured to provide 1 to 4 virtual graphics processors based on received instructions. When the graphics processor 400 is configured to provide one virtual graphics processor, a user can use the four graphics processor cores 430-1 to 430-4 via the data instruction dispatcher 410-2. When the graphics processor 400 is configured to provide two virtual graphics processors, a first user can use graphics processor cores 430-1 and 430-3 via the data instruction dispatcher 410-2, and a second user can use graphics processor cores 430-2 and 430-4 via the data instruction dispatcher 410-4. Furthermore, if the graphics processor 400 is configured to provide three virtual graphics processors, a first user can use the graphics processor core 430-1 via the data and instruction dispatcher 410-1, a second user can use the graphics processor cores 430-2 and 430-4 via the data and instruction dispatcher 410-2, and a third user can use the graphics processor core 430-3 via the data and instruction dispatcher 410-3. Furthermore, if the graphics processor 400 is configured to provide four virtual graphics processors, a first user can use the graphics processor core 430-1 via the data and instruction dispatcher 410-1, a second user can use the graphics processor core 430-2 via the data and instruction dispatcher 410-2, a third user can use the graphics processor core 430-3 via the data and instruction dispatcher 410-3, and a fourth user can use the graphics processor core 430-4 via the data and instruction dispatcher 410-4.

[0041] As is clear from the above description, the connection between the data / instruction dispatcher 410 and the graphics processor core 430 in the embodiment of the present application is simplified to one 1-to-4 connection (a total of 1 x 4 sets of connection lines), two 1-to-2 connections (a total of 2 x 2 sets of connection lines), and one 1-to-1 connection (a total of 1 x 1 set of connection lines). Therefore, there are a total of 9 sets of connection lines between the data / instruction dispatcher 410 and the graphics processor core 430 in the embodiment of the present application. Thus, compared to a system in which the data / instruction dispatcher 410 is fully coupled to the graphics processor core 430, the connection method provided in the embodiment of the present application requires fewer connection lines, which is advantageous in avoiding congestion problems in the P&R stage and reducing chip area.

[0042] It should be understood that the connection method between the data / instruction dispatcher 410 and the graphics processor core 430 in the case of N=4 shown in Figure 4 is only one of the executable methods in the embodiment of the present invention, and the present invention is not limited thereto. In some implementations, the graphics processor core 430 connected to the data / instruction dispatcher 410 may differ from that in Figure 4. For example, data / instruction dispatcher 410-1 may be connected to 430-2 instead of 430-1, and data / instruction dispatcher 410-3 may be connected to 430-2 and 430-4 instead of 430-1 and 430-3. Also, in some other implementations, the number of graphics processor cores 430 connected to the data / instruction dispatcher 410 may differ from that in Figure 4. For example, data instruction dispatcher 410-1 may be connected to two, three, or four graphics processor cores 430, and data instruction dispatcher 410-2 may be connected to one, two, or three graphics processor cores 430.

[0043] It should be explained that, in order to improve the efficiency of core utilization, all virtual graphics processors provided by the graphics processor 400 as exemplified above at the same time use all four graphics processor cores, but this invention is not limited to this. For example, if the graphics processor 400 is configured to provide only one virtual graphics processor, the user may use two graphics processor cores 430-1 and 430-3 via the data and instruction dispatcher 410-2. In this case, the remaining two graphics processor cores 430-2 and 430-4 will be idle. Also, for example, if the graphics processor 400 is configured to provide two virtual graphics processors, the first user may use one graphics processor core 430-1 via the data and instruction dispatcher 410-1, and the second user may use two graphics processor cores 430-2 and 430-4 via the data and instruction dispatcher 410-4. In this case, the remaining graphics processor core 430-3 will be idle.

[0044] In one embodiment of the present invention, the graphics processor includes N data instruction dispatchers. Of these, one data instruction dispatcher is connected to N graphics processor cores. j -m j+1 The data / instruction dispatcher has a capacity of N / m j It is connected to the graphics processor cores. j and m j+1 ∫ are adjacent positive integers divisible by N, where 1 ≤ m j+1 <m j ≤ N. For example, when N=4, m j and m j+1 The value of m j+1 = 1 and m j =2 and m j+1 = 2 and m jThis includes two types = 4. Based on this, if the graphics processor provided in the embodiment of the present application includes four data instruction dispatchers 410, one data instruction dispatcher 410 is connected to four graphics processor cores 430, and another data instruction dispatcher 410 is connected to two graphics processor cores 430 (m j+1 = 1 and m j =2), two other data instruction dispatchers 410 are connected to one graphics processor core 430 each (m j+1 = 2 and m j =4). In the embodiments of the present application, the connection method between the data instruction dispatcher 410 and the graphics processor core 430 includes, but is not limited to, a direct connection between the data instruction dispatcher 410 and the graphics processor core 430, or an indirect connection between the data instruction dispatcher 410 and the graphics processor core 430 via a data selector or the like.

[0045] Next, the above connection method will be explained in detail by illustrating the cases of N=8 and N=16. Refer to Figure 5A. In one example, N=8, and the graphics processor 500 includes eight data instruction dispatchers. Of these, one data instruction dispatcher 510-1 is directly connected to the graphics processor core 530-1, and indirectly connected to the graphics processor cores 530-2 to 530-8 via a data selector. Additionally, one data instruction dispatcher 510-5 is indirectly connected to the four graphics processor cores 530-5 to 530-8 via a data selector (m j+1 =1, m j(=2). Also, regarding the two data and instruction dispatchers 510-3 and 510-7, data and instruction dispatcher 510-3 is indirectly connected to the two graphics processor cores 530-3 and 530-4 via a data selector, and data and instruction dispatcher 510-7 is indirectly connected to the two graphics processor cores 530-7 and 530-8 via a data selector (m j+1 =2, m j (=4). In addition, the four data instruction dispatchers 510-2, 510-4, 510-6, and 510-8 are indirectly connected to the corresponding graphics processor cores 530-2, 530-4, 530-6, and 530-8 via data selectors (m j+1 =4, m j =8).

[0046] The graphics processor 500 shown in Figure 5A can be configured to provide 1 to 8 virtual graphics processors, supporting a minimum of 1 user (when the graphics processor 500 is configured to provide 1 virtual graphics processor) and a maximum of 8 users (when the graphics processor 500 is configured to provide 8 virtual graphics processors). The graphics processor cores 530 of the graphics processor 500 have 22 possible allocation scenarios, as shown in Table 1 below. For example, in the 10th case, the graphics processor 500 is configured to provide 3 virtual graphics processors for use by 3 users. In this case, 2 users occupy 3 graphics processor cores 530, and another user occupies 2 graphics processor cores 530. By combining Figure 5A, the allocation method for the graphics processor cores 530 may be such that the first user occupies graphics processor cores 530-1, 530-2, and 530-8, the second user occupies graphics processor cores 530-5, 530-6, and 530-7, and the third user occupies graphics processor cores 530-3 and 530-4.

[0047] It should be noted that the connection method between the data / instruction dispatcher 510 and the graphics processor core 530 in the embodiment of this application is not unique, and several other implementations may employ different connection methods. For example, Figure 5B shows an alternative connection method for the case N=8. This method has the same effect as the connection method shown in Figure 5A.

[0048] [Table 1]

[0049] In the above example, the connection between the data / instruction dispatcher 510 and the graphics processor core 530 is simplified to one 1-to-8 connection (a total of 1 x 8 sets of connection lines), one 1-to-4 connection (a total of 1 x 4 sets of connection lines), two 1-to-2 connections (a total of 2 x 2 sets of connection lines), and four 1-to-1 connections (a total of 4 x 1 set of connection lines). Therefore, in the embodiment of this application, there are a total of 20 sets of connection lines between the data / instruction dispatcher 510 and the graphics processor core 530. Each set of connection lines consists of, for example, 1000 to 2000 data / instruction connection lines. Thus, compared to a method in which the data / instruction dispatcher 510 is fully coupled to the graphics processor core 530, the connection method provided in this example requires fewer connection lines, which is advantageous in avoiding congestion problems in the P&R stage and reducing chip area.

[0050] Refer to Figure 5C. In another example, N=16, and the graphics processor 500 includes 16 data instruction dispatchers 510. Of these, the first data instruction dispatcher 510 is directly connected to the first graphics processor core 530 and indirectly connected to the remaining 15 graphics processor cores 530 via a data selector. The ninth data instruction dispatcher 510 is indirectly connected to eight graphics processor cores 530 via a data selector. The second data instruction dispatcher 510 is indirectly connected to five graphics processor cores 530 via a data selector. The seventh data instruction dispatcher 510 is indirectly connected to four graphics processor cores 530 via a data selector. The sixteenth data instruction dispatcher 510 is indirectly connected to three graphics processor cores 530 via a data selector. Furthermore, the 4th, 11th, and 13th data instruction dispatchers 510 are indirectly connected to two graphics processor cores 530 via data selectors. Additionally, the 3rd, 5th, 6th, 8th, 10th, 12th, 14th, and 15th data instruction dispatchers 510 are indirectly connected to one graphics processor core 530 via data selectors. In this example, the connections between the data instruction dispatchers 510 and the graphics processor cores 530 are simplified to one 1-to-16 connection (total of 1 x 16 connection lines), one 1-to-8 connection (total of 1 x 8 connection lines), one 1-to-5 connection (total of 1 x 5 connection lines), one 1-to-4 connection (total of 1 x 4 connection lines), one 1-to-3 connection (total of 1 x 3 connection lines), three 1-to-2 connections (total of 3 x 2 connection lines), and eight 1-to-1 connections (total of 8 x 1 connection lines). Therefore, in the embodiment of the present invention, there are a total of 50 sets of connection lines between the data / instruction dispatcher 510 and the graphics processor core 530.Therefore, compared to a configuration in which the data instruction dispatcher 510 is fully coupled to the graphics processor core 530, the connection method provided in this example requires fewer connection lines, thus avoiding congestion problems during the P&R phase and reducing chip area.

[0051] In one embodiment of the present invention, the graphics processor 500 may further include a data selector. A graphics processor core 530 connected to at least two data-instruction dispatchers 510 is indirectly connected to the data-instruction dispatchers 510 via the data selector. For example, the graphics processor 500 shown in Figure 5A includes data selectors 520-2 to 520-8. In the case of a graphics processor core 530 connected to at least two data-instruction dispatchers 510, for example, graphics processor core 530-5 is indirectly connected to the corresponding data-instruction dispatcher 510 via the data selector. In the embodiment of the present invention, the data selector selects at most one data-instruction dispatcher 510 at the same time and connects it to the graphics processor core 530.

[0052] In the case of a graphics processor core 530 that is selectively connected to only one data instruction dispatcher 510, for example, graphics processor core 530-1 may be connected to the data instruction dispatcher without going through a data selector.

[0053] It should be understood that the data selector in the embodiments of this application is not limited to any specific device or circuit, but includes any device or circuit capable of selecting and outputting a predetermined single signal from a set of input signals. In one embodiment of this application, the data instruction dispatcher 510 is fully coupled to the graphics processor core 530. Fully coupled means that each data instruction dispatcher 510 is connected to all graphics processor cores 530, and each graphics processor core 530 is connected to all data instruction dispatchers 510. The connection method between the data instruction dispatcher 510 and the graphics processor core 530 includes, but is not limited to, a direct connection between the data instruction dispatcher 510 and the graphics processor core 530, or an indirect connection between the data instruction dispatcher 510 and the graphics processor core 530 via a data selector or the like. Figure 6 shows a schematic diagram of the case where the data instruction dispatcher 510 is fully coupled to the graphics processor core 530 when N=8. In this case, the graphics processor 500 can be configured to provide 1 to 8 virtual graphics processors and can satisfy all allocations of processor cores.

[0054] In one embodiment of the present invention, the number of physical layers of the graphics processor is determined based on the number of data-instruction transmission lines. Specifically, the number of data-instruction transmission lines included in each physical layer of the graphics processor is limited to the maximum extent possible. The fewer the number of data-instruction transmission lines, the fewer the number of physical layers of the graphics processor. For example, if N=8, when the data-instruction dispatcher is fully connected to the graphics processor core, the number of data-instruction transmission lines becomes 64 sets, and the number of physical layers of the graphics processor is configured to be 8. On the other hand, when using the connection method shown in Figure 5A or Figure 5B, the number of data-instruction transmission lines becomes 20 sets, and the number of physical layers of the graphics processor 500 can be configured to be 4. In this case, by using the connection method shown in Figure 5A or Figure 5B, the number of physical layers of the graphics processor 500 can be reduced.

[0055] The present application further provides a chip. Figure 7 shows a schematic diagram of a chip in one embodiment of the present application. The chip includes a graphics processor and input / output pins as described in any embodiment of the present application.

[0056] The present application further provides an electronic device, which includes a graphics processor as described in any embodiment of the present application and a memory connected to the graphics processor.

[0057] As described above, the graphics processor provided in the embodiments of the present invention can provide at least one virtual graphics processor. Virtualization of the graphics processor makes it possible for multiple users to share the graphics processor. In some embodiments of the present invention, the connection method between the data instruction dispatcher and the graphics processor core is optimized to reduce the number of connection lines between the data instruction dispatcher and the graphics processor core, thereby avoiding congestion problems in the chip placement and wiring stages. This is advantageous for reducing the chip area and the number of physical layers of the graphics processor. Therefore, the present invention effectively eliminates various shortcomings of the prior art and has high industrial value.

[0058] The above embodiments are merely illustrative examples illustrating the principles and effects of the present application and do not limit it. Those familiar with the art may supplement or modify the above embodiments, provided they do not depart from the spirit and scope of the present application. Therefore, any equivalent supplement or modification that a person skilled in the art can complete without departing from the spirit and technical concept disclosed herein remains within the scope of the claims. [Explanation of symbols]

[0059] 100 Electronic equipment 110 System Processors 120 Graphics Processors 121-1~121-k Graphics Processor Cores 122-instruction processor 123 Crossbar Switch Bus 124-1~124-k L2 cache 130 memory 140 displays 300 Graphics Processors 310-1~310-M Data / Instruction Dispatcher 330-1~330-N Graphics Processor Cores 500 Graphics Processors 510-1~510-8 Data / Instruction Dispatcher 520-2~520-8 Data Selector 530-1~530-8 Graphics Processor Cores

Claims

1. A graphics processor, It includes at least two data instruction dispatchers and at least two graphics processor cores, each of which data instruction dispatchers is connected to at least one of the graphics processor cores, and one of the data instruction dispatchers and one of the graphics processor cores are connected via a set of data instruction transmission lines. The graphics processor is configured to provide at least one virtual graphics processor, each of which includes one data instruction dispatcher and some or all of the graphics processor cores connected to the one data instruction dispatcher.

2. The graphics processor according to claim 1, wherein the graphics processor is configured to provide n virtual graphics processors based on an instruction received, where n is any positive integer less than or equal to N, and N is the number of graphics processor cores.

3. The i-th data instruction dispatcher of the graphics processor is floor(N / n ｉ ) connected to the aforementioned graphics processor cores, i and n ｉ The graphics processor according to claim 2, characterized in that all of are positive integers less than or equal to N, and floor is the floor function.

4. The graphics processor includes N of the data instruction dispatchers, wherein one of the data instruction dispatchers is connected to N of the graphics processor cores, and m ｊ -m ｊ＋１ of the data instruction dispatchers are connected to N / m ｊ of the graphics processor cores, and m ｊ and m ｊ＋１ are adjacent positive integers divisible by N, and 1 ≤ m ｊ＋１ < m ｊ ≤ N. The graphics processor according to claim 3, characterized in that.

5. The graphics processor according to claim 4, further comprising a data selector, wherein the graphics processor core connected to at least two of the data instruction dispatchers is connected to the data instruction dispatchers via the data selector.

6. The graphics processor according to claim 4, wherein both the number of data instruction dispatchers and the graphics processor cores are eight, and the connection method between the data instruction dispatchers and the graphics processor cores includes one 1-to-8 connection, one 1-to-4 connection, two 1-to-2 connections, and four 1-to-1 connections.

7. The graphics processor according to claim 1, characterized in that the number of physical layers of the graphics processor is configured based on the number of data and instruction transmission lines.

8. The graphics processor according to claim 1, characterized in that the data instruction dispatcher is fully coupled to the graphics processor core.

9. A chip characterized by including a graphics processor and input / output pins according to any one of claims 1 to 8.

10. An electronic device comprising a graphics processor and memory according to any one of claims 1 to 8.

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