Heterojunction battery and method for manufacturing the same

Abstract

The present application provides a heterojunction battery and a manufacturing method thereof, the heterojunction battery including a semiconductor substrate layer and an intrinsic semiconductor composite layer located on at least one surface of the semiconductor substrate layer, the intrinsic semiconductor composite layer including an underlying intrinsic layer and a wide band gap intrinsic layer located on a surface of the underlying intrinsic layer opposite to the semiconductor substrate layer, the band gap of the wide band gap intrinsic layer being larger than the band gap of the underlying intrinsic layer. When the heterojunction battery is irradiated with sunlight due to the wide band gap of the wide band gap intrinsic layer, photons having smaller energy than the band gap of the wide band gap intrinsic layer cannot be parasitically absorbed, and the parasitic absorption of sunlight by the intrinsic semiconductor composite layer is reduced, so that the absorption of sunlight by the semiconductor substrate layer is increased, and the photo-generated carriers generated by the semiconductor substrate layer are increased, which may further improve the short-circuit current of the heterojunction battery and the conversion efficiency of the heterojunction battery.

Description

[Technical Field]

[0001] This application relates to the technology of solar cell manufacturing, and more specifically to heterojunction batteries and methods for manufacturing the same.

[0002] This application claims priority to the Chinese patent application filed with the China National Intellectual Property Office on July 7, 2021, application number 202110767660.2, with the title of the invention "Heterojunction battery and method for manufacturing the same," the entire contents of which are incorporated herein by reference. [Background technology]

[0003] Solar cells are clean energy batteries and are widely applied in daily life and production. Heterojunction batteries are an important type of solar cell. The heterojunction (HJT) structure is centered on an N-type single-crystal silicon substrate, with a P-type amorphous silicon layer and an N-type amorphous silicon layer on either side of the N-type single-crystal silicon substrate. An intrinsic amorphous silicon layer is added between the P-type amorphous silicon layer, the N-type amorphous silicon layer and the N-type single-crystal silicon substrate. After adopting this process, the passivation characteristics of the substrate silicon wafer are changed, thus improving the conversion efficiency of the heterojunction battery, making heterojunction batteries a highly competitive solar cell technology.

[0004] However, because the intrinsic amorphous silicon layer itself can parasitically absorb sunlight, it affects the conversion efficiency of heterojunction batteries, and further improvements in the conversion efficiency of heterojunction batteries are necessary. [Overview of the Initiative] [Problems that the invention aims to solve]

[0005] Therefore, the technical problem that this application aims to solve is to provide a heterojunction battery and a method for manufacturing the same by overcoming the problem of needing to further improve the conversion efficiency of heterojunction batteries in the prior art. [Means for solving the problem]

[0006] The present invention provides a heterojunction battery comprising a semiconductor substrate layer and an intrinsic semiconductor composite layer located on at least one side of the semiconductor substrate layer, wherein the intrinsic semiconductor composite layer comprises a base intrinsic layer and a wide-bandgap intrinsic layer located on the side of the base intrinsic layer opposite to the semiconductor substrate layer, and the bandgap of the wide-bandgap intrinsic layer is larger than the bandgap of the base intrinsic layer.

[0007] The intrinsic semiconductor composite layer may be located only on the surface side of the semiconductor substrate layer, or only on the back side of the semiconductor substrate layer, or on both sides of the semiconductor substrate layer.

[0008] Optionally, the wide-bandgap intrinsic layer includes a first sub-wide-bandgap intrinsic layer to the Nth sub-wide-bandgap intrinsic layer, where N is an integer of 1 or more.

[0009] The material for the nth subwide bandgap intrinsic layer can be optionally oxygen-doped amorphous silicon, carbon-doped amorphous silicon, oxygen-doped nanocrystalline silicon, or carbon-doped nanocrystalline silicon, where n is an integer between 1 and N.

[0010] Optionally, the underlying intrinsic layer includes a first sub-sub

[0011] Optionally, the ratio of the thickness of the first sub-underlying intrinsic layer to the thickness of the second sub-underlying intrinsic layer is 0.15:1 to 0.35:1.

[0012] Optionally, the thickness of the first sub-underlying intrinsic layer is 0.3 nm to 0.8 nm, and the thickness of the second sub-underlying intrinsic layer is 1 nm to 2.5 nm.

[0013] Optionally, the total thickness of the intrinsic semiconductor composite layer located on one side of the semiconductor substrate layer is 2 nm to 10 nm.

[0014] Optionally, N is an integer of 2 or more, the k-th sub-wide bandgap intrinsic layer is located between the (k + 1)-th sub-wide bandgap intrinsic layer and the semiconductor substrate layer, and k is an integer from 1 to N - 1.

[0015] Optionally, N = 2.

[0016] Optionally, the material of the first sub-wide bandgap intrinsic layer includes oxygen-doped amorphous silicon or oxygen-doped nanocrystalline silicon, the material of the second sub-wide bandgap intrinsic layer includes carbon-doped amorphous silicon or carbon-doped nanocrystalline silicon, the molar ratio of oxygen to silicon in the first sub-wide bandgap intrinsic layer is 1:1 to 1:5, and the molar ratio of carbon to silicon in the second sub-wide bandgap intrinsic layer is 1:1 to 1:5.

[0017] Optionally, the bandgap of the first sub-wide bandgap intrinsic layer is 2.0 eV to 9 eV, and the bandgap of the second sub-wide bandgap intrinsic layer is 2.0 eV to 9 eV.

[0018] The material of the first subwide-bandgap intrinsic layer may optionally include carbon-doped amorphous silicon or carbon-doped nanocrystalline silicon, the material of the second subwide-bandgap intrinsic layer may include oxygen-doped amorphous silicon or oxygen-doped nanocrystalline silicon, the molar ratio of carbon to silicon in the first subwide-bandgap intrinsic layer may be 1:1 to 1:5, and the molar ratio of oxygen to silicon in the second subwide-bandgap intrinsic layer may be 1:1 to 1:5.

[0019] Optionally, the band gap of the first subwide bandgap intrinsic layer is 2.0 eV to 9 eV, and the band gap of the second subwide bandgap intrinsic layer is 2.0 eV to 9 eV.

[0020] Selectively, the ratio of the thickness of the second subwide bandgap intrinsic layer to the thickness of the first subwide bandgap intrinsic layer is 0.5:1 to 1.5:1, and the ratio of the thickness of the first subwide bandgap intrinsic layer to the thickness of the substrate intrinsic layer is 0.5:1 to 1.5:1.

[0021] Optionally, the thickness of the second subwide bandgap intrinsic layer is 1.5 nm to 4 nm, the thickness of the first subwide bandgap intrinsic layer is 1.5 nm to 4 nm, and the thickness of the underlying intrinsic layer is 1.3 nm to 3.3 nm.

[0022] Optionally, with respect to an intrinsic semiconductor composite layer located on the surface side of the semiconductor substrate layer, the refractive index of the k+1 sub-wide bandgap intrinsic layer in the intrinsic semiconductor composite layer is smaller than the refractive index of the k sub-wide bandgap intrinsic layer.

[0023] Optionally, for an intrinsic semiconductor composite layer located on the back side of the semiconductor substrate layer, the valence band difference between the intrinsic semiconductor composite layer and the semiconductor substrate layer is 0.6 eV to 1.2 eV.

[0024] Optionally, N is equal to 1, and the band gap of the wide-bandgap intrinsic layer is 2.0 eV to 9 eV.

[0025] Selectively, the ratio of the thickness of the wide bandgap intrinsic layer to the thickness of the substrate intrinsic layer is 1:1 to 3:1.

[0026] Optionally, the thickness of the wide-bandgap intrinsic layer is 2 nm to 8 nm, and the thickness of the underlying intrinsic layer is 1.3 nm to 3.3 nm.

[0027] The present invention further provides a method for manufacturing a heterojunction battery, comprising the steps of: providing a semiconductor substrate layer; and forming an intrinsic semiconductor composite layer on at least one side of the semiconductor substrate layer, wherein the step of forming the intrinsic semiconductor composite layer comprises: forming a base intrinsic layer on at least one side of the semiconductor substrate layer; and forming a wide-bandgap intrinsic layer on the side of the base intrinsic layer opposite to the semiconductor substrate layer, wherein the bandgap of the wide-bandgap intrinsic layer is larger than the bandgap of the base intrinsic layer.

[0028] The intrinsic semiconductor composite layer may be formed only on the surface side of the semiconductor substrate layer, or only on the back side of the semiconductor substrate layer, or on both sides of the semiconductor substrate layer.

[0029] The step of optionally forming the wide bandgap intrinsic layer on the side of the underlying intrinsic layer opposite to the semiconductor substrate layer involves sequentially forming a first sub-wide bandgap intrinsic layer to the Nth sub-wide bandgap intrinsic layer on the side of the underlying intrinsic layer opposite to the semiconductor substrate layer, where N is an integer of 1 or more.

[0030] The material for the nth subwide bandgap intrinsic layer is optionally oxygen-doped amorphous silicon, carbon-doped amorphous silicon, carbon-doped nanocrystalline silicon, or oxygen-doped nanocrystalline silicon, where n is an integer between 1 and N.

[0031] Optionally, N is an integer greater than or equal to 2, the k-th subwide bandgap intrinsic layer is located between the k+1-th subwide bandgap intrinsic layer and the semiconductor substrate layer, and k is an integer between 1 and N-1.

[0032] Optionally, with respect to an intrinsic semiconductor composite layer located on the surface side of the semiconductor substrate layer, the refractive index of the k+1 sub-wide bandgap intrinsic layer in the intrinsic semiconductor composite layer is smaller than the refractive index of the k sub-wide bandgap intrinsic layer.

[0033] Optionally, for an intrinsic semiconductor composite layer located on the back side of the semiconductor substrate layer, the valence band difference between the intrinsic semiconductor composite layer and the semiconductor substrate layer is 0.6 eV to 7.9 eV.

[0034] The n-subwide bandgap intrinsic layer is optionally formed by a chemical vapor deposition process.

[0035] If the material of the nth subwide bandgap intrinsic layer optionally includes oxygen-doped amorphous silicon, the process parameters for forming the nth subwide bandgap intrinsic layer include silane, hydrogen gas, and carbon dioxide, where the volume ratio of silane to hydrogen gas is 1:1 to 1:10, the volume ratio of carbon dioxide to silane is 1:1 to 1:5, the chamber pressure is 0.2 mBar to 1 mBar, the growth temperature is 180°C to 240°C, and the source RF power density is 150 W / m². 2 ~600W / m 2 That is the case.

[0036] If the material of the n-th subwide bandgap intrinsic layer optionally includes oxygen-doped nanocrystalline silicon, the process parameters for forming the n-th subwide bandgap intrinsic layer include silane, hydrogen gas, and carbon dioxide, where the volume ratio of silane to hydrogen gas is 1:20 to 1:80, the volume ratio of carbon dioxide to silane is 1:1 to 1:5, the chamber pressure is 0.5 mBar to 5 mBar, the growth temperature is 180°C to 240°C, and the source RF power density is 500 W / m². 2 ~2250W / m 2 That is the case.

[0037] If the material of the n-th subwide bandgap intrinsic layer optionally includes carbon-doped amorphous silicon, the process parameters for forming the n-th subwide bandgap intrinsic layer include silane, hydrogen gas, and methane, where the volume ratio of silane to hydrogen gas is 1:1 to 1:10, the volume ratio of methane to silane is 1:1 to 1:5, the chamber pressure is 0.2 mBar to 1 mBar, the growth temperature is 180°C to 240°C, and the source RF power density is 150 W / m². 2 ~600W / m 2 That is the case.

[0038] If the material of the n-th subwide bandgap intrinsic layer optionally includes carbon-doped nanocrystalline silicon, the process parameters for forming the n-th subwide bandgap intrinsic layer are as follows: the gases used are silane, hydrogen gas, and methane, where the volume ratio of silane to hydrogen gas is 1:20 to 1:80, the volume ratio of methane to silane is 1:1 to 1:5, the chamber pressure is 0.5 mBar to 5 mBar, the growth temperature is 180°C to 240°C, and the source RF power density is 500 W / m². 2 ~2250W / m 2 That is the case.

[0039] Optionally, the step of forming the underlying intrinsic layer includes forming a first sub-sub [Effects of the Invention]

[0040] The technical solution of this application has the following beneficial effects. 1. In the heterojunction battery according to the present invention, the band gap of the wide-bandgap intrinsic layer is larger than the band gap of the underlying intrinsic layer. When sunlight is irradiated onto the heterojunction battery, photons with energy lower than the band gap of the wide-bandgap intrinsic layer cannot be parasitic absorbed. This reduces the parasitic absorption of the intrinsic semiconductor composite layer to sunlight, which in turn increases the absorption of sunlight by the semiconductor substrate layer, increases the number of photogenerated carriers generated by the semiconductor substrate layer, and further improves the short-circuit current of the heterojunction battery and improves the conversion efficiency of the heterojunction battery. 2. Furthermore, the defect density of the first sub-substrate intrinsic layer is high, mainly serving to prevent epitaxial growth of the semiconductor substrate layer. The thickness of the first sub-substrate intrinsic layer is thin, avoiding excessive composite formation of photogenerated carriers in the first sub-substrate intrinsic layer. The defect density of the second sub-substrate intrinsic layer is low and relatively thick, mainly serving to passivate the semiconductor substrate layer. This results in less composite formation of photogenerated carriers in the second sub-substrate intrinsic layer, which can increase the short-circuit current of the heterojunction battery. Additionally, the second sub-substrate intrinsic layer can be used as a transition layer between the first sub-substrate intrinsic layer and the wide-bandgap intrinsic layer, improving the contact performance between the wide-bandgap intrinsic layer and the first substrate intrinsic layer. 3. Furthermore, the refractive index of the k+1 sub-wide bandgap intrinsic layer on the surface side of the semiconductor substrate layer is smaller than the refractive index of the k sub-wide bandgap intrinsic layer. As a result, the refractive index of the intrinsic semiconductor composite layer on the surface of the heterojunction battery has a gradient effect, the intrinsic semiconductor composite layer on the surface of the heterojunction battery has better anti-reflective performance, more sunlight enters the semiconductor substrate layer and is absorbed by the semiconductor substrate layer, and the open-circuit voltage of the heterojunction battery can be increased. 4. Furthermore, by doping the wide-bandgap intrinsic layer on the back side of the semiconductor substrate layer with oxygen or carbon atoms, the valence band difference between the intrinsic semiconductor composite layer on the back side of the semiconductor substrate layer and the semiconductor substrate layer can be increased. This high valence band difference increases the hole carrier accumulation effect in photogenerated carriers, making the open-circuit voltage of the heterojunction battery higher than usual. This increases the probability that hole carriers in the semiconductor substrate layer can directly pass through the intrinsic semiconductor composite layer on the back side of the semiconductor substrate layer, improving the transmission efficiency of hole carriers within the intrinsic semiconductor composite layer on the back side of the semiconductor substrate layer. This reduces the resistance of the heterojunction battery and improves the conversion efficiency of the heterojunction battery. 5. The method for manufacturing a heterojunction battery according to the present invention has a large band gap in the wide-bandgap intrinsic layer. When sunlight is irradiated onto the heterojunction battery, photons with energy lower than the band gap of the wide-bandgap intrinsic layer cannot be parasitic absorbed. This reduces the parasitic absorption of the intrinsic semiconductor composite layer to sunlight, which in turn increases the absorption of sunlight by the semiconductor substrate layer. This increases the number of photogenerated carriers generated by the semiconductor substrate layer, which can further improve the short-circuit current of the heterojunction battery and improve the conversion efficiency of the heterojunction battery.

[0041] To more clearly describe specific embodiments of the present application or technical solutions in the prior art, the drawings used to describe specific embodiments or the prior art will be briefly described below. Clearly, the drawings described below are some embodiments of the present application, and those skilled in the art can obtain other drawings based on these without any creative effort. [Brief explanation of the drawing]

[0042] [Figure 1] This is a schematic diagram of the structure of a heterojunction battery according to Example 1 of the present application. [Figure 2] This is a schematic diagram of the structure of a heterojunction battery according to Example 2 of the present invention. [Figure 3] This is a schematic diagram of the structure of a heterojunction battery according to Example 3 of the present application. [Figure 4] This is a schematic diagram of the structure of a heterojunction battery according to Example 4 of the present application. [Figure 5] This is a flowchart of a method for manufacturing a heterojunction battery according to one embodiment of the present invention. [Figure 6] This is a flowchart illustrating the manufacturing method of a heterojunction battery according to Example 4 of this application. [Modes for carrying out the invention]

[0043] The technical solutions of the present application will be described clearly and completely below with reference to the drawings, and it will be clear that the embodiments described are some, but not all, embodiments of the present application. Any other embodiments that a person skilled in the art can obtain without creative work based on the embodiments of the present application are all within the scope of protection of the present application.

[0044] Furthermore, in the description of this application, the directions or positional relationships indicated by terms such as "center," "up," "down," "left," "right," "vertical," "horizontal," "inside," and "outside" are directions or positional relationships based on the illustrations and are merely for the purpose of facilitating or simplifying the description of this application. They do not indicate or imply that the device or element has a specific direction or is configured and operated in a specific direction, and therefore should not be understood as limiting this application. In addition, the terms "first," "second," and "third" are used solely for explanatory purposes and should not be understood as indicating or implying relative importance.

[0045] In this description, unless otherwise specified or limited, the terms "attachment," "connection," and "connection" should be understood in a broad sense. For example, they may be fixed connections, removable connections, or integral connections; they may be mechanical connections or electrical connections; they may be direct connections or indirect connections via an intermediate medium; or they may be internal communication between two elements. Those skilled in the art will be able to understand the specific meaning of these terms in this application depending on the specific circumstances.

[0046] Furthermore, the technical features of the various embodiments of the present application described below can be combined with each other, insofar as they do not contradict each other.

[0047] The present invention provides a heterojunction battery comprising a semiconductor substrate layer and an intrinsic semiconductor composite layer located on at least one side of the semiconductor substrate layer, wherein the intrinsic semiconductor composite layer comprises a base intrinsic layer and a wide-bandgap intrinsic layer located on the side of the base intrinsic layer opposite to the semiconductor substrate layer, the bandgap of the wide-bandgap intrinsic layer being larger than the bandgap of the base intrinsic layer.

[0048] When a heterojunction battery is irradiated with sunlight, the band gap of the wide-bandgap intrinsic layer is large, and photons with lower energy than the band gap of the wide-bandgap intrinsic layer cannot be parasitic absorbed. This reduces the parasitic absorption of the intrinsic semiconductor composite layer by sunlight, which in turn increases the absorption of sunlight by the semiconductor substrate layer, leading to an increase in photogenerated carriers produced by the semiconductor substrate layer. Furthermore, this can improve the short-circuit current of the heterojunction battery and thus improve its conversion efficiency.

[0049] In one embodiment, the intrinsic semiconductor composite layer is located only on the surface side of the semiconductor substrate layer. In another embodiment, the intrinsic semiconductor composite layer is located only on the back side of the semiconductor substrate layer. In yet another embodiment, the intrinsic semiconductor composite layer is located on both sides of the semiconductor substrate layer.

[0050] The semiconductor substrate layer includes an N-type single-crystal silicon substrate, which has a narrow band gap, typically between 1.0 eV and 1.2 eV.

[0051] The aforementioned widebandgap intrinsic layer includes the first sub-widebandgap intrinsic layer to the Nth sub-widebandgap intrinsic layer, where N is an integer of 1 or more.

[0052] The material for the nth subwide bandgap intrinsic layer includes oxygen-doped amorphous silicon, carbon-doped amorphous silicon, oxygen-doped nanocrystalline silicon, or carbon-doped nanocrystalline silicon, where n is an integer between 1 and N.

[0053] Example 1 Referring to Figure 1, the direction indicated by the arrow in Figure 1 indicates the direction of sunlight irradiation. This embodiment will be described as an example of a heterojunction battery structure in which the intrinsic semiconductor composite layer 2 is located only on the surface side of the semiconductor substrate layer 1.

[0054] In this case, optionally, the band gap of the wide bandgap intrinsic layer 22 is 2.0 eV to 9 eV, for example, 2.0 eV, 2.4 eV, 2.8 eV, 3.2 eV, and 9 eV. Optionally, the ratio of the thickness of the wide bandgap intrinsic layer 22 to the thickness of the underlying intrinsic layer 21 is 1:1 to 3:1, for example, 1:1:2, 1, or 3, 1. Optionally, the thickness of the wide bandgap intrinsic layer 22 is 2 nm to 8 nm, for example, 2 nm, 5 nm, 7 nm, or 8 nm, and the thickness of the underlying intrinsic layer 21 is 1.3 nm to 3.3 nm, for example, 1.3 nm, 2 nm, 3 nm, or 3.3 nm.

[0055] The aforementioned intrinsic base layer 21 includes a first sub-intrinsic base layer 211 and a second sub-intrinsic base layer 212 located on the side of the first sub-intrinsic base layer 211 opposite to the semiconductor substrate layer 1, wherein the defect density of the second sub-intrinsic base layer 212 is smaller than that of the first sub-intrinsic base layer 211, that is, the proportion of silylene (-SiH2-) in the second sub-intrinsic base layer 212 is smaller than the proportion of silylene (-SiH2-) in the first sub-intrinsic base layer 211. The first sub-substrate intrinsic layer 211 has a high defect state density, mainly serving to prevent epitaxial growth of the semiconductor substrate layer 1. The first sub-substrate intrinsic layer 211 is thin, avoiding excessive aggregation of photogenerated carriers in the first sub-substrate intrinsic layer 211. The second sub-substrate intrinsic layer 212 has a low defect state density and is relatively thick, mainly serving to passivate the semiconductor substrate layer 1. This results in less aggregation of photogenerated carriers in the second sub-substrate intrinsic layer 212, which can increase the short-circuit current of the heterojunction battery. Furthermore, the second sub-substrate intrinsic layer 212 can be used as a transition layer between the first sub-substrate intrinsic layer 211 and the wide-bandgap intrinsic layer 22, improving the contact performance between the wide-bandgap intrinsic layer 22 and the substrate intrinsic layer 21.

[0056] In this embodiment, the ratio of the thickness of the first sub-substrate intrinsic layer 211 to the thickness of the second sub-substrate intrinsic layer 212 is 0.15:1 to 0.35:1, for example, 0.15:1, 0.2:1, 0.25:1, 0.3:1, or 0.35:1.

[0057] In this embodiment, the thickness of the first sub-substrate intrinsic layer 211 is 0.3 nm to 0.8 nm, for example, 0.3 nm, 0.5 nm, 0.7 nm, or 0.8 nm. When the defect state density of the first sub-substrate intrinsic layer 211 is large, the first sub-substrate intrinsic layer 211 mainly plays a role in preventing epitaxial growth of the semiconductor substrate layer 1. If the first sub-substrate intrinsic layer 211 is too thin, it is difficult for it to play a role in preventing epitaxial growth of the semiconductor substrate layer 1. If the first sub-substrate intrinsic layer 211 is too thick, there is too much photogenerated carrier composite in the first sub-substrate intrinsic layer 211, and the conversion efficiency of the heterojunction battery decreases. The thickness of the second sub-substrate intrinsic layer 212 is 1 nm to 2.5 nm, for example, 1 nm, 1.5 nm, 2 nm, or 2.5 nm. The second sub-substrate intrinsic layer 212 mainly plays a role in passivating the semiconductor substrate layer 1 and carrier transmission. If the second sub-substrate intrinsic layer 212 is too thin, the passivation effect of the second sub-substrate intrinsic layer 212 on the semiconductor substrate layer 1 decreases. If the second sub-substrate intrinsic layer 212 is too thick, there is a lot of parasitic absorption of sunlight by the second sub-substrate intrinsic layer 212, its own bulk resistance is high, the carrier transmission efficiency in the second sub-substrate intrinsic layer 212 is poor, and the short-circuit current of the heterojunction battery decreases.

[0058] Optionally, the thickness of the first sub-substrate intrinsic layer 211 is 0.5 nm, the thickness of the second sub-substrate intrinsic layer 212 is 2 nm, and the thickness of the wide-bandgap intrinsic layer 22 is 5 nm. In this case, the intrinsic semiconductor composite layer 2 has a good passivation effect on the semiconductor substrate layer 1, reducing the aggregation of photogenerated carriers on the surface of the semiconductor substrate layer 1, resulting in a low bulk resistance of the intrinsic semiconductor composite layer 2 and low parasitic absorption of sunlight by the intrinsic semiconductor composite layer 2. Furthermore, the second sub-substrate intrinsic layer 212 acts as a transition layer between the first sub-substrate intrinsic layer 211 and the wide-bandgap intrinsic layer 22, improving the contact performance between the wide-bandgap intrinsic layer 22 and the substrate intrinsic layer 21.

[0059] The total thickness of the intrinsic semiconductor composite layer 2 located on one side of the semiconductor substrate layer 1 is 2 nm to 10 nm, for example, 2 nm, 5 nm, 7 nm, 9 nm, or 10 nm. A thin intrinsic semiconductor composite layer 2 reduces parasitic absorption from sunlight, which can improve the short-circuit current of the heterojunction battery and improve the conversion efficiency of the heterojunction battery.

[0060] The wide-bandgap intrinsic layer 22 includes the first sub-wide-bandgap intrinsic layer to the Nth sub-wide-bandgap intrinsic layer, where N is an integer of 1 or more.

[0061] In one case, as shown in Figure 1, the wide-bandgap intrinsic layer 22 is a monolayer structure, meaning N is equal to 1.

[0062] In another case, the wide-bandgap intrinsic layer 22 has a multilayer structure, where N is an integer greater than or equal to 2, and the k-th sub-wide-bandgap intrinsic layer is located between the k+1-th sub-wide-bandgap intrinsic layer and the semiconductor substrate layer, where k is an integer between 1 and N-1.

[0063] The material for the nth subwide bandgap intrinsic layer includes oxygen-doped amorphous silicon, carbon-doped amorphous silicon, oxygen-doped nanocrystalline silicon, or carbon-doped nanocrystalline silicon, where n is an integer between 1 and N.

[0064] In one particular embodiment, N is equal to 2, and the wide-bandgap intrinsic layer 22 includes a first sub-wide-bandgap intrinsic layer and a second sub-wide-bandgap intrinsic layer located on the side of the first sub-wide-bandgap intrinsic layer opposite to the semiconductor substrate layer 1.

[0065] In one case, the material of the first subwide-bandgap intrinsic layer includes oxygen-doped amorphous silicon or oxygen-doped nanocrystalline silicon, and the material of the second subwide-bandgap intrinsic layer includes carbon-doped amorphous silicon or carbon-doped nanocrystalline silicon, the molar ratio of oxygen to silicon in the first subwide-bandgap intrinsic layer is 1:1 to 1:5, for example, 1:1, 1:2, 1:3, 1:4, or 1:5, and the molar ratio of carbon to silicon in the second subwide-bandgap intrinsic layer is 1:1 to 1:5, for example, 1:1, 1:2, 1:3, 1:4, or 1:5. Because the first sub-wide bandgap intrinsic layer is doped with oxygen atoms, the bandgap of the first sub-wide bandgap intrinsic layer is broad, ranging from 2.0 eV to 9 eV, for example, 2.0 eV, 2.4 eV, 2.6 eV, 3.2 eV, or 9 eV. Because the second sub-wide bandgap intrinsic layer is doped with carbon atoms, the bandgap of the second sub-wide bandgap intrinsic layer is broad, ranging from 2.0 eV to 9 eV, for example, 2.0 eV, 2.5 eV, 2.8 eV, 3.2 eV, or 9 eV.

[0066] In another case, the material of the first subwide-bandgap intrinsic layer includes carbon-doped amorphous silicon or carbon-doped nanocrystalline silicon, and the material of the second subwide-bandgap intrinsic layer includes oxygen-doped amorphous silicon or oxygen-doped nanocrystalline silicon, the molar ratio of carbon to silicon in the first subwide-bandgap intrinsic layer is 1:1 to 1:5, for example, 1:1, 1:2, 1:3, 1:4, or 1:5, and the molar ratio of oxygen to silicon in the second subwide-bandgap intrinsic layer is 1:1 to 1:5, for example, 1:1, 1:2, 1:3, 1:4, or 1:5. In this case, the band gap of the first subwide bandgap intrinsic layer is 2.3eV to 2.8eV, for example, 2.3eV, 2.5eV, 2.7eV, or 2.8eV, and the band gap of the second subwide bandgap intrinsic layer is 2.0eV to 2.6eV, for example, 2.0eV, 2.2eV, 2.6eV, 3.2eV, or 9eV.

[0067] The ratio of the thickness of the second subwide bandgap intrinsic layer to the thickness of the first subwide bandgap intrinsic layer is 0.5:1 to 1.5:1, for example 0.5:1, 0.8:1, 1:1, 1.2:1, or 1.5:1, and the ratio of the thickness of the first subwide bandgap intrinsic layer to the thickness of the substrate intrinsic layer is 0.5:1 to 1.5:1, for example 0.5:1, 0.8:1, 1:1, 1.2:1, 1.5:1, or 1.5:1.

[0068] The thickness of the second subwide bandgap intrinsic layer is 1.5 nm to 4 nm, for example, 1.5 nm, 2 nm, 3 nm, or 4 nm; the thickness of the first subwide bandgap intrinsic layer is 1.5 nm to 4 nm, for example, 1.5 nm, 2 nm, 3 nm, or 4 nm; and the thickness of the underlying intrinsic layer is 1.3 nm to 3.3 nm, for example, 1.3 nm, 2 nm, 3 nm, or 3.3 nm.

[0069] With respect to the intrinsic semiconductor composite layer 2 located on the surface side of the semiconductor substrate layer 1, the refractive index of the k+1 sub-wide bandgap intrinsic layer in the intrinsic semiconductor composite layer 2 is smaller than the refractive index of the k sub-wide bandgap intrinsic layer. Specifically, the refractive index of the second sub-wide bandgap intrinsic layer is smaller than the refractive index of the first sub-wide bandgap intrinsic layer, and as a result the refractive index of the intrinsic semiconductor composite layer 2 on the surface of the heterojunction battery has a gradient effect, the intrinsic semiconductor composite layer 2 on the surface of the heterojunction battery has better anti-reflective performance, more sunlight enters the semiconductor substrate layer 1 and is absorbed by the semiconductor substrate layer 1, and the open-circuit voltage of the heterojunction battery can be increased.

[0070] Continuing with Figure 1, the heterojunction battery further includes a back intrinsic layer 3 located on the side of the semiconductor substrate layer 1 opposite to the intrinsic semiconductor composite layer 2.

[0071] The aforementioned back intrinsic layer 3 may be a single layer or a multilayer structure, and is not limited to this.

[0072] Continuing with Figure 1, the heterojunction battery further includes a first doping layer 4 located on the side of the intrinsic semiconductor composite layer 2 opposite to the semiconductor substrate layer 1, a first transparent conductive film 6 located on the side of the first doping layer 4 opposite to the intrinsic semiconductor composite layer 2, a first grid electrode 8 located on the side of the first transparent conductive film 6 opposite to the intrinsic semiconductor composite layer 2, a second doping layer 5 located on the side of the back intrinsic layer 3 opposite to the semiconductor substrate layer 1, a second transparent conductive film 7 located on the side of the second doping layer 5 opposite to the back intrinsic layer 3, and a second grid electrode 9 located on the side of the second transparent conductive film 7 opposite to the second doping layer 5, wherein the conductivity type of the first doping layer 4 is the opposite of the conductivity type of the second doping layer 5. Example 2

[0073] Referring to Figure 2, this embodiment will be described as an example of a heterojunction battery structure in which the intrinsic semiconductor composite layer 2 is located only on the back side of the semiconductor substrate layer 1.

[0074] With respect to the intrinsic semiconductor composite layer 2 located on the back side of the semiconductor substrate layer 1, the valence band difference between the intrinsic semiconductor composite layer 2 and the semiconductor substrate layer 1 is 0.6 eV to 7.9 eV, for example, 0.6 eV, 1.0 eV, 2.1 eV, or 7.9 eV.

[0075] By doping the wide-bandgap intrinsic layer 22 with oxygen or carbon atoms, the valence band difference between the intrinsic semiconductor composite layer 2 on the back side of the semiconductor substrate layer 1 and the semiconductor substrate layer 1 can be increased. This increased valence band difference increases the hole carrier accumulation effect in photogenerated carriers, making the open-circuit voltage of the heterojunction battery higher than usual. This increases the probability that hole carriers in the semiconductor substrate layer 1 can directly pass through the intrinsic semiconductor composite layer 2 on the back side of the semiconductor substrate layer 1, thereby improving the transmission efficiency of hole carriers within the intrinsic semiconductor composite layer 2 on the back side of the semiconductor substrate layer 1. This reduces the resistance of the heterojunction battery and improves its conversion efficiency.

[0076] The wide-bandgap intrinsic layer 22 includes the first sub-wide-bandgap intrinsic layer to the Nth sub-wide-bandgap intrinsic layer, where N is an integer of 1 or more.

[0077] In one case, as shown in Figure 2, the wide-bandgap intrinsic layer 22 is a monolayer structure, meaning that N is equal to 1.

[0078] In another case, the wide-bandgap intrinsic layer 22 has a multilayer structure, where N is an integer greater than or equal to 2, and the k-th sub-wide-bandgap intrinsic layer is located between the k+1-th sub-wide-bandgap intrinsic layer and the semiconductor substrate layer, where k is an integer between 1 and N-1.

[0079] The material for the nth subwide bandgap intrinsic layer includes oxygen-doped amorphous silicon, carbon-doped amorphous silicon, oxygen-doped nanocrystalline silicon, or carbon-doped nanocrystalline silicon, where n is an integer between 1 and N.

[0080] In one particular embodiment, N is equal to 2, and the wide-bandgap intrinsic layer 22 includes a first sub-wide-bandgap intrinsic layer and a second sub-wide-bandgap intrinsic layer located on the opposite side of the first sub-wide-bandgap intrinsic layer from the semiconductor substrate layer 1.

[0081] Continuing with Figure 2, the heterojunction battery further includes a surface intrinsic layer 3a located on the semiconductor substrate layer 1 opposite to the intrinsic semiconductor composite layer 2.

[0082] The surface intrinsic layer 3a may be a single layer or a multilayer structure.

[0083] The structure of this embodiment is the same as that of Embodiment 1, so please refer to the description of Embodiment 1 and will not be described in detail here. Example 3

[0084] Referring to Figure 3, this embodiment will be described as an example of a heterojunction battery structure in which the intrinsic semiconductor composite layer is located on both sides of the semiconductor substrate layer 1, and the wide bandgap intrinsic layer has a single-layer structure (i.e., N is equal to 1).

[0085] The intrinsic semiconductor composite layer 2 includes a surface intrinsic semiconductor composite layer 2A located on the surface side of the semiconductor substrate layer 1 and a back surface intrinsic semiconductor composite layer 3A located on the back side of the semiconductor substrate layer 1.

[0086] The surface intrinsic semiconductor composite layer 2A includes a surface underlayment intrinsic layer 21A and a surface wide bandgap intrinsic layer 22A located on the side of the surface underlayment intrinsic layer 21A opposite to the semiconductor substrate layer 1, wherein the bandgap of the surface wide bandgap intrinsic layer 22A is larger than the bandgap of the surface underlayment intrinsic layer 21A.

[0087] The back intrinsic semiconductor composite layer 3A includes a back underlying intrinsic layer 31A and a back wide bandgap intrinsic layer 32A located on the side of the back underlying intrinsic layer 31A opposite to the semiconductor substrate layer 1, wherein the bandgap of the back wide bandgap intrinsic layer 32A is larger than the bandgap of the back underlying intrinsic layer 31A.

[0088] In this embodiment, the underlying intrinsic layer includes a surface underlying intrinsic layer 21A located on the surface side of the semiconductor substrate layer 1 and a back underlying intrinsic layer 31A located on the back side of the semiconductor substrate layer 1. The surface underlying intrinsic layer 21A includes a first sub-surface underlying intrinsic layer 211A located on the surface side of the semiconductor substrate layer 1 and a second sub-surface underlying intrinsic layer 212A located on the side of the first sub-surface underlying intrinsic layer 211A opposite to the semiconductor substrate layer 1, wherein the defect state density of the second sub-surface underlying intrinsic layer 212A is smaller than the defect state density of the first sub-surface underlying intrinsic layer 211A. The back-facing intrinsic layer 31A includes a first sub-back-facing intrinsic layer 311A ​​located on the back side of the semiconductor substrate layer 1, and a second sub-back-facing intrinsic layer 312A located on the side of the first sub-back-facing intrinsic layer 311A ​​opposite to the semiconductor substrate layer 1, wherein the defect state density of the second sub-back-facing intrinsic layer 312A is smaller than the defect state density of the first sub-back-facing intrinsic layer 311A.

[0089] The ratio of the thickness of the first subsurface substrate intrinsic layer 211A to the thickness of the second subsurface substrate intrinsic layer 212A is 0.15:1 to 0.35:1, for example, 0.15:1, 0.2:1, 0.25:1, 0.3:1, or 0.35:1. In this embodiment, the thickness of the first subsurface substrate intrinsic layer 211A is 0.3 nm to 0.8 nm, for example, 0.3 nm, 0.5 nm, 0.7 nm, or 0.8 nm, and the thickness of the second subsurface substrate intrinsic layer 212A is 1 nm to 2.5 nm, for example, 1 nm, 1.5 nm, 2 nm, or 2.5 nm.

[0090] The total thickness of the surface intrinsic semiconductor composite layer 2A is 2nm to 10nm, for example, 2nm, 5nm, 7nm, 9nm, or 10nm. The total thickness of the back surface intrinsic semiconductor composite layer 3A is 5nm to 10nm, for example, 5nm, 7nm, 9nm, or 10nm.

[0091] The material for the surface wide-bandgap intrinsic layer 22A includes oxygen-doped amorphous silicon, carbon-doped amorphous silicon, oxygen-doped nanocrystalline silicon, or carbon-doped nanocrystalline silicon. The material for the back wide-bandgap intrinsic layer 32A includes oxygen-doped amorphous silicon, carbon-doped amorphous silicon, oxygen-doped nanocrystalline silicon, or carbon-doped nanocrystalline silicon.

[0092] In a particular embodiment, the material of the surface wide-bandgap intrinsic layer 22A includes oxygen-doped amorphous silicon or oxygen-doped nanocrystalline silicon, and the molar ratio of oxygen to silicon in the surface wide-bandgap intrinsic layer 22A is 1:1 to 1:5, for example, 1:1, 1:2, 1:3, 1:4, or 1:5. Since the surface wide-bandgap intrinsic layer 22A is doped with oxygen atoms, the band gap of the surface wide-bandgap intrinsic layer 22A is wide, and the band gap of the surface wide-bandgap intrinsic layer 22A is 2.0 eV to 2.6 eV, for example, 2.0 eV, 2.2 eV, 2.4 eV, or 2.6 eV.

[0093] In another specific embodiment, the material of the surface wide-bandgap intrinsic layer 22A includes carbon-doped amorphous silicon or carbon-doped nanocrystalline silicon. The molar ratio of carbon to silicon in the surface wide-bandgap intrinsic layer 22A is 1:1 to 1:5, for example, 1:1, 1:2, 1:3, 1:4, or 1:5. Because the surface wide-bandgap intrinsic layer 22A is doped with carbon atoms, the band gap of the surface wide-bandgap intrinsic layer 22A is wide, and the band gap of the surface wide-bandgap intrinsic layer 22A is 2.3 eV to 2.8 eV, for example, 2.3 eV, 2.5 eV, 2.7 eV, or 2.8 eV.

[0094] In a particular embodiment, the material of the back wide-bandgap intrinsic layer 32A includes carbon-doped amorphous silicon or carbon-doped nanocrystalline silicon, and the molar ratio of carbon to silicon in the back wide-bandgap intrinsic layer 32A is 1:1 to 1:5, for example, 1:1, 1:2, 1:3, 1:4, or 1:5. The bandgap of the back wide-bandgap intrinsic layer 32A is 2.3 eV to 2.8 eV, for example, 2.3 eV, 2.5 eV, 2.7 eV, or 2.8 eV.

[0095] In other specific embodiments, the material of the back wide-bandgap intrinsic layer 32A includes oxygen-doped amorphous silicon or oxygen-doped nanocrystalline silicon. The molar ratio of oxygen to silicon in the back wide-bandgap intrinsic layer 32A is 1:1 to 1:5, for example, 1:1, 1:2, 1:3, 1:4, or 1:5. The bandgap of the back wide-bandgap intrinsic layer 32A is 2.0 eV to 9 eV, for example, 2.0 eV, 2.4 eV, 2.6 eV, 3.2 eV, or 9 eV.

[0096] The ratio of the thickness of the surface wide bandgap intrinsic layer 22A to the thickness of the surface underlayment intrinsic layer is 1:1 to 3:1. The thickness of the surface wide bandgap intrinsic layer 22A is 2 nm to 8 nm, and the thickness of the surface underlayment intrinsic layer is 1.3 nm to 3.3 nm.

[0097] The ratio of the thickness of the back wide bandgap intrinsic layer 32A to the thickness of the back substrate intrinsic layer is 1:1 to 3:1. The thickness of the back wide bandgap intrinsic layer 32A is 2 nm to 8 nm, and the thickness of the back substrate intrinsic layer is 1.3 nm to 3.3 nm.

[0098] In this embodiment, the present invention further includes a first doping layer 4 located on the side of the surface intrinsic semiconductor composite layer 2A opposite to the semiconductor substrate layer 1, a first transparent conductive film 6 located on the side of the first doping layer 4 opposite to the semiconductor substrate layer 1, a first grid electrode 8 located on the side of the first transparent conductive film 6 opposite to the semiconductor substrate layer 1, a second doping layer 5 located on the side of the back intrinsic semiconductor composite layer 3A opposite to the semiconductor substrate layer 1, a second transparent conductive film 7 located on the side of the second doping layer 5 opposite to the semiconductor substrate layer 1, and a second grid electrode 9 located on the side of the second transparent conductive film 7 opposite to the semiconductor substrate layer 1, wherein the conductivity type of the first doping layer 4 is the opposite of the conductivity type of the second doping layer 5.

[0099] The structure of this embodiment is the same as that of Embodiment 1, so please refer to the description of Embodiment 1 and will not be described in detail here. Example 4

[0100] In this embodiment, the heterojunction battery structure is such that the intrinsic semiconductor composite layer is located on both sides of the semiconductor substrate layer 1, the wide bandgap intrinsic layer is a stacked structure, the wide bandgap intrinsic layer includes the first sub-wide bandgap intrinsic layer to the Nth sub-wide bandgap intrinsic layer, where N is an integer of 2 or more, and the kth sub-wide bandgap intrinsic layer is located between the k+1th sub-wide bandgap intrinsic layer and the semiconductor substrate layer 1, where k is an integer of 1 or more and N-1 or less.

[0101] With respect to the intrinsic semiconductor composite layer 2 located on the surface side of the semiconductor substrate layer 1, the refractive index of the k+1 subwide bandgap intrinsic layer in the intrinsic semiconductor composite layer 2 is smaller than the refractive index of the k subwide bandgap intrinsic layer. As a result, the refractive index of the intrinsic semiconductor composite layer 2 on the surface of the heterojunction battery has a gradient effect, the intrinsic semiconductor composite layer 2 on the surface of the heterojunction battery has better anti-reflective performance, more sunlight enters the semiconductor substrate layer 1 and is absorbed by the semiconductor substrate layer 1, and the open-circuit voltage of the heterojunction battery can be increased.

[0102] With respect to the intrinsic semiconductor composite layer 2 located on the back side of the semiconductor substrate layer 1, the valence band difference between the intrinsic semiconductor composite layer 2 and the semiconductor substrate layer 1 is 0.6 eV to 7.9 eV.

[0103] Referring to Figure 4, we will explain using the example that N is equal to 2 in Figure 4. The intrinsic semiconductor composite layer 2 includes a surface intrinsic semiconductor composite layer 2A located on the surface side of the semiconductor substrate layer 1 and a back surface intrinsic semiconductor composite layer 3A located on the back side of the semiconductor substrate layer 1.

[0104] The surface intrinsic semiconductor composite layer 2A includes a surface underlayment intrinsic layer 21A and a surface wide bandgap intrinsic layer 22A located on the side of the surface underlayment intrinsic layer 21A opposite to the semiconductor substrate layer 1, wherein the bandgap of the surface wide bandgap intrinsic layer 22A is larger than the bandgap of the surface underlayment intrinsic layer 21A. For a description of the surface underlayment intrinsic layer 21A, please refer to the content corresponding to Example 3, and it will not be described in detail here.

[0105] The surface wide bandgap intrinsic layer 22A includes a first sub-surface wide bandgap intrinsic layer 221A and a second sub-surface wide bandgap intrinsic layer 222A located on the opposite side of the first sub-surface wide bandgap intrinsic layer 221A from the surface underlayment intrinsic layer 21A.

[0106] The back intrinsic semiconductor composite layer 3A includes a back underlying intrinsic layer 31A and a back wide bandgap intrinsic layer 32A located on the side of the back underlying intrinsic layer 31A opposite to the semiconductor substrate layer 1, wherein the bandgap of the back wide bandgap intrinsic layer 32A is larger than the bandgap of the back underlying intrinsic layer 31A. For a description of the back underlying intrinsic layer 31A, please refer to the content corresponding to Example 3, and it will not be described in detail here.

[0107] The aforementioned back wide band gap intrinsic layer 32A includes a first sub-back wide band gap intrinsic layer 321A and a second sub-back wide band gap intrinsic layer 322A located on the opposite side of the back substrate intrinsic layer 31A from the first sub-back wide band gap intrinsic layer 321A.

[0108] In this embodiment, the material of the first subsurface wide bandgap intrinsic layer 221A includes oxygen-doped amorphous silicon or oxygen-doped nanocrystalline silicon, and the material of the second subsurface wide bandgap intrinsic layer 222A includes carbon-doped amorphous silicon or carbon-doped nanocrystalline silicon. The molar ratio of oxygen to silicon in the first subsurface wide bandgap intrinsic layer 221A is 1:1 to 1:5, for example, 1:1, 1:2, 1:3, 1:4, or 1:5, and the molar ratio of carbon to silicon in the second subsurface wide bandgap intrinsic layer 222A is 1:1 to 1:5, for example, 1:1, 1:2, 1:3, 1:4, or 1:5. Because the first subsurface wide-bandgap intrinsic layer 221A is doped with oxygen atoms, the band gap of the first subsurface wide-bandgap intrinsic layer 221A is broad, and the band gap of the first subsurface wide-bandgap intrinsic layer 221A is 2.0 eV to 9 eV, for example, 2.0 eV, 2.4 eV, 2.6 eV, 3.2 eV, or 9 eV. Because the second subsurface wide-bandgap intrinsic layer 222A is doped with carbon atoms, the band gap of the second subsurface wide-bandgap intrinsic layer 222A is broad, and the band gap of the second subsurface wide-bandgap intrinsic layer 222A is 2.0 eV to 9 eV, for example, 2.0 eV, 2.5 eV, 2.8 eV, 3.2 eV, or 9 eV.

[0109] In other embodiments, the material of the first subsurface wide bandgap intrinsic layer 221A includes carbon-doped amorphous silicon or carbon-doped nanocrystalline silicon, and the material of the second subsurface wide bandgap intrinsic layer 222A includes oxygen-doped amorphous silicon or oxygen-doped nanocrystalline silicon, the molar ratio of carbon to silicon in the first subsurface wide bandgap intrinsic layer 221A is 1:1 to 1:5, for example, 1:1, 1:2, 1:3, 1:4, or 1:5, and the molar ratio of oxygen to silicon in the second subsurface wide bandgap intrinsic layer 222A is 1:1 to 1:5, for example, 1:1, 1:2, 1:3, 1:4, or 1:5. In this case, the band gap of the first subsurface wide bandgap intrinsic layer 221A is 2.0 eV to 9 eV, for example, 2.0 eV, 2.5 eV, 2.8 eV, 3.2 eV, or 9 eV, and the band gap of the second subsurface wide bandgap intrinsic layer 222A is 2.0 eV to 9 eV, for example, 2.0 eV, 2.4 eV, 2.6 eV, 3.2 eV, or 9 eV.

[0110] The ratio of the thickness of the second subsurface wide bandgap intrinsic layer 222A to the thickness of the first subsurface wide bandgap intrinsic layer 221A is 0.5:1 to 1.5:1, for example 0.5:1, 0.8:1, 1:1, 1.2:1, or 1.5:1, and the ratio of the thickness of the first subsurface wide bandgap intrinsic layer 221A to the thickness of the surface base intrinsic layer 21A is 0.5:1 to 1.5:1, for example 0.5:1, 0.8:1, 1:1, 1.2:1, 1.5:1, or 1.5:1.

[0111] The thickness of the second subsurface wide bandgap intrinsic layer 222A is 1.5 nm to 4 nm, for example, 1.5 nm, 2 nm, 3 nm, or 4 nm; the thickness of the first subsurface wide bandgap intrinsic layer 221A is 1.5 nm to 4 nm, for example, 1.5 nm, 2 nm, 3 nm, or 4 nm; and the thickness of the surface underlay intrinsic layer 21A is 1.3 nm to 3.3 nm, for example, 1.3 nm, 2 nm, 3 nm, or 3.3 nm.

[0112] The material, thickness, and band gap of the first sub-backside wide bandgap intrinsic layer 321A are described in reference to the first sub-surface wide bandgap intrinsic layer 221A, and the material, thickness, and band gap of the second sub-backside wide bandgap intrinsic layer 322A are described in reference to the second sub-surface wide bandgap intrinsic layer 222A; these details are not described here.

[0113] In other embodiments, the surface wide bandgap intrinsic layer 22A may have a single-layer structure and the second wide bandgap intrinsic layer 32A may have a multi-layer structure, or the surface wide bandgap intrinsic layer 22A may have a multi-layer structure and the second wide bandgap intrinsic layer 32A may have a single-layer structure.

[0114] The structure of this embodiment is the same as that of Embodiment 3, and will not be described in detail here, as please refer to the description of Embodiment 3. Example 5

[0115] This embodiment provides a method for manufacturing a heterojunction battery, and includes steps S1 to S2, with reference to Figure 5. Step S1: Provide the semiconductor substrate layer 1. Step S2, an intrinsic semiconductor composite layer 2 is formed on at least one side of the semiconductor substrate layer 1, and the step of forming the intrinsic semiconductor composite layer 2 includes forming an underlying intrinsic layer on at least one side of the semiconductor substrate layer 1 and forming a wide bandgap intrinsic layer on the side of the underlying intrinsic layer opposite to the semiconductor substrate layer 1, wherein the bandgap of the wide bandgap intrinsic layer is larger than the bandgap of the underlying intrinsic layer 1.

[0116] Regarding the formation position of the intrinsic semiconductor composite layer 2, the intrinsic semiconductor composite layer 2 may be formed only on the surface side of the semiconductor substrate layer 1, or only on the back side of the semiconductor substrate layer 1, or on both sides of the semiconductor substrate layer 1.

[0117] The step of forming the wide bandgap intrinsic layer on the side of the underlying intrinsic layer opposite to the semiconductor substrate layer 1 involves sequentially forming a first sub-wide bandgap intrinsic layer to the Nth sub-wide bandgap intrinsic layer on the side of the underlying intrinsic layer opposite to the semiconductor substrate layer 1, where N is an integer of 1 or more.

[0118] The material for the nth subwide bandgap intrinsic layer is optionally oxygen-doped amorphous silicon, carbon-doped amorphous silicon, carbon-doped nanocrystalline silicon, or oxygen-doped nanocrystalline silicon, where n is an integer between 1 and N.

[0119] Optionally, N is an integer greater than or equal to 2, the k-th subwide bandgap intrinsic layer is located between the k+1-th subwide bandgap intrinsic layer and the semiconductor substrate layer, and k is an integer between 1 and N-1.

[0120] Optionally, for an intrinsic semiconductor composite layer 2 located on the surface side of the semiconductor substrate layer 1, the refractive index of the k+1 subwide bandgap intrinsic layer in the intrinsic semiconductor composite layer 2 is smaller than the refractive index of the k subwide bandgap intrinsic layer.

[0121] Optionally, for an intrinsic semiconductor composite layer 2 located on the back side of the semiconductor substrate layer 1, the valence band difference between the intrinsic semiconductor composite layer 2 and the semiconductor substrate layer 1 is 0.6 eV to 7.9 eV, for example, 0.6 eV, 1.0 eV, 1.2 eV, 2.1 eV, or 7.9 eV.

[0122] When the material of the nth sub-wide bandgap intrinsic layer contains oxygen-doped amorphous silicon, as the process parameters for forming the nth sub-wide bandgap intrinsic layer, the gases used include silane, hydrogen gas, and carbon dioxide. Here, the volume ratio of silane to hydrogen gas is 1:1 to 1:10, for example, 1:2, 1:4, 1:6, 1:8, or 1:10, the volume ratio of carbon dioxide to silane is 1:1 to 1:5, for example, 1:1, 1:2, 1:3, 1:4, or 1:5, the chamber pressure is 0.2 mBar to 1 mBar, for example, 0.2 mBar, 0.4 mBar, 0.6 mBar, 0.8 mBar, or 1 mBar, the growth temperature is 180°C to 240°C, for example, 180°C, 200°C, 220°C, or 240°C, and the source RF power density is 150 W / m 2 ~600 W / m 2 For example, 150 W / m 2 250 W / m 2 350 W / m 2 450 W / m 2 550 W / m 2 Or 600 W / m 2 is.

[0123] When the material of the nth sub-wide bandgap intrinsic layer contains oxygen-doped nanocrystalline silicon, as the process parameters for forming the nth sub-wide bandgap intrinsic layer, the gases used include silane, hydrogen gas, and carbon dioxide. Here, the volume ratio of silane to hydrogen gas is 1:20 to 1:80, for example, 1:20, 1:40, 1:60, or 1:80, the volume ratio of carbon dioxide to silane is 1:1 to 1:5, for example, 1:1, 1:2, 1:3, 1:4, or 1:5, the chamber pressure is 0.5 mBar to 5 mBar, for example, 0.5 mBar, 1 mBar, 3 mBar, 4 mBar, or 5 mBar, the growth temperature is 180°C to 240°C, for example, 180°C, 200°C, 220°C, or 240°C, and the source RF power density is 500 W / m 2 ~2250 W / m 2 For example, 500 W / m 2 1000 W / m 2 1500 W / m 2 2000 W / m 2or 2250W / m 2 That is the case.

[0124] When the material for the n-subwide bandgap intrinsic layer includes carbon-doped amorphous silicon, the process parameters for forming the n-subwide bandgap intrinsic layer include silane, hydrogen gas, and methane, where the volume ratio of silane to hydrogen gas is 1:1 to 1:10, e.g., 1:2, 1:4, 1:6, 1:8, or 1:10; the volume ratio of methane to silane is 1:1 to 1:5, e.g., 1:1, 1:2, 1:3, 1:4, or 1:5; the chamber pressure is 0.2 mBar to 1 mBar, e.g., 0.2 mBar, 0.4 mBar, 0.6 mBar, 0.8 mBar, or 1 mBar; the growth temperature is 180°C to 240°C, e.g., 180°C, 200°C, 220°C, or 240°C; and the source RF power density is 150 W / m². 2 ~600W / m 2 For example, 150W / m 2 , 250W / m 2 , 350W / m 2 , 450W / m 2 , 550W / m 2 or 600W / m 2 That is the case.

[0125] When the material for the n-subwide bandgap intrinsic layer includes carbon-doped nanocrystalline silicon, the process parameters for forming the n-subwide bandgap intrinsic layer include silane, hydrogen gas, and methane, where the volume ratio of silane to hydrogen gas is 1:20 to 1:80, e.g., 1:20, 1:40, 1:60, or 1:80; the volume ratio of methane to silane is 1:1 to 1:5, e.g., 1:1, 1:2, 1:3, 1:4, or 1:5; the chamber pressure is 0.5 mBar to 5 mBar, e.g., 0.5 mBar, 1 mBar, 3 mBar, 4 mBar, or 5 mBar; the growth temperature is 180°C to 240°C, e.g., 180°C, 200°C, 220°C, or 240°C; and the source RF power density is 500 W / m². 2 ~2250W / m 2 For example, 500W / m 2 , 1000W / m2 , 1500W / m 2 , 2000W / m 2 or 2250W / m 2 That is the case.

[0126] The step of forming the underlying intrinsic layer includes forming a first sub-sub

[0127] Referring to Figure 6, and using the heterojunction battery according to Example 4 as an example, the manufacturing method of the heterojunction battery will be described in detail, using as an example a laminated structure in which the surface intrinsic semiconductor composite layer 2A includes a first sub-surface wide bandgap intrinsic layer 221A and a second sub-surface wide bandgap intrinsic layer 222A, and the back intrinsic semiconductor composite layer 3A includes a first sub-back wide bandgap intrinsic layer 321A and a second sub-back wide bandgap intrinsic layer 322A.

[0128] Step A1: Provide a semiconductor substrate layer. The semiconductor substrate layer includes an N-type single-crystal silicon substrate. Step A2: Texture and cleaning treatment is performed on semiconductor substrate layer 1. The semiconductor substrate layer 1 is textured to form a light-trapping structure on its surface, reducing the reflection of sunlight. After the textured treatment, the semiconductor substrate layer 1 is cleaned to remove the oxide layer and impurities from its surface. Step A3: A first subsurface intrinsic layer 211A, a second subsurface intrinsic layer 212A, a first subsurface wide bandgap intrinsic layer 221A, a second subsurface wide bandgap intrinsic layer 222A, and a first doping layer are sequentially formed on one side surface of the semiconductor substrate layer 1 by a chemical vapor deposition process. The process parameters for forming the first subsurface wide bandgap intrinsic layer 221A and the second subsurface wide bandgap intrinsic layer 222A are as described above. Step A4: A first sub-backside intrinsic layer 311A, a second sub-backside intrinsic layer 312A, a first sub-backside wide bandgap intrinsic layer 321A, a second sub-backside wide bandgap intrinsic layer 322A, and a second doping layer are sequentially formed on the other side surface of the semiconductor substrate layer 1 by a chemical vapor deposition process. The process parameters for forming the first sub-backside wide bandgap intrinsic layer 321A and the second sub-backside wide bandgap intrinsic layer 322A are as described above. In other embodiments, the first doping layer and the second doping layer may be formed after the second sub-surface wide bandgap intrinsic layer 222A and the second sub-back surface wide bandgap intrinsic layer 322A have been formed. Step A5: A first transparent conductive film 6 is formed on the surface of the first doping layer by a physical vapor phase growth process, and a second transparent conductive film 7 is formed on the surface of the second doping layer. Amorphous silicon structures are disordered, resulting in low electron and hole mobility and poor lateral conductivity, which is unfavorable for collecting photogenerated carriers. The first transparent conductive film 6 and the second transparent conductive film 7 are used to collect carriers and transmit them to electrodes. Step A6: A first grid electrode 8 is formed on the surface of the first transparent conductive film by a screen printing process, and a second grid electrode 9 is formed on the surface of the second transparent conductive film 7. The first grid electrode 8 is used to collect the current transmitted from the first transparent conductive film 6, and the second grid electrode 9 is used to collect the current transmitted from the second transparent conductive film 7. In step A7, the first grid electrode 8 and the second grid electrode 9 are subjected to curing and photo-injection annealing treatments. By irradiating the surface of a heterojunction battery with strong light for a certain period of time at a constant temperature, the conversion efficiency of the heterojunction battery is improved.

[0129] In the manufacturing method of the heterojunction battery according to this embodiment, the band gap of the wide-bandgap intrinsic layer is large, and when sunlight is irradiated onto the heterojunction battery, photons with energy smaller than the band gap of the wide-bandgap intrinsic layer cannot be parasitic absorbed, thus reducing the parasitic absorption of the intrinsic semiconductor composite layer to sunlight. As a result, the absorption of sunlight by the semiconductor substrate layer increases, the number of photogenerated carriers generated by the semiconductor substrate layer increases, and furthermore, the short-circuit current of the heterojunction battery may improve, and the conversion efficiency of the heterojunction battery may improve.

[0130] Clearly, the above embodiments are merely illustrative examples to clearly illustrate the technical essentials of the present application and do not limit the embodiments. Those skilled in the art can make various other variations or modifications based on the above description. It is not necessary, nor is it possible, to cover all embodiments here. Any obvious variations or modifications derived therefrom still fall within the scope of the patent created by the present invention. [Explanation of Symbols]

[0131] 1. Semiconductor substrate layer 2. Intrinsic semiconductor composite layer 21 Base intrinsic layer 211 First Sub-Substrate True Layer 212 Second Sub-Substrate True Layer 22 Wide bandgap intrinsic layer 2A Surface intrinsic semiconductor composite layer 21A Surface underlying intrinsic layer 211A First Subsurface Substrate Intrinsic Layer 212A Second Subsurface Substrate Intrinsic Layer 22A Surface wide bandgap intrinsic layer 221A First subsurface wide bandgap intrinsic layer 222A Second subsurface wide bandgap intrinsic layer 3 Dorsal intrinsic layer 3a Surface intrinsic layer 3A Backside intrinsic semiconductor composite layer 31A Back base intrinsic layer 311A First Sub-backside True Layer 312A Second Sub-back Rear Substrate True Layer 32A Backside widebandgap intrinsic layer 321A First sub-backside widebandgap intrinsic layer 322A Second sub-rear widebandgap intrinsic layer 4. First Doping Layer 5. Second Doping Layer 6. First transparent conductive film 7. Second transparent conductive film 8. First grid electrode 9. Second grid electrode

Claims

1. A heterojunction battery, It includes a semiconductor substrate layer and an intrinsic semiconductor composite layer located on at least one side of the semiconductor substrate layer, The intrinsic semiconductor composite layer includes a base intrinsic layer and a wide-bandgap intrinsic layer located on the side of the base intrinsic layer opposite to the semiconductor substrate layer, wherein the bandgap of the wide-bandgap intrinsic layer is larger than the bandgap of the base intrinsic layer. The wide-bandgap intrinsic layer includes the first sub-wide-bandgap intrinsic layer to the Nth sub-wide-bandgap intrinsic layer, where N is an integer of 2 or more. The k-th subwide bandgap intrinsic layer is located between the k+1-th subwide bandgap intrinsic layer and the semiconductor substrate layer, where k is an integer between 1 and N-1. A heterojunction battery characterized in that, in the intrinsic semiconductor composite layer located on the front side of the semiconductor substrate layer, the refractive index of the k+1 subwide bandgap intrinsic layer included in the intrinsic semiconductor composite layer is smaller than the refractive index of the k subwide bandgap intrinsic layer.

2. The heterojunction battery according to claim 1, characterized in that the intrinsic semiconductor composite layer is located on the front side of the semiconductor substrate layer, or the intrinsic semiconductor composite layer is located on both the front and back sides of the semiconductor substrate layer.

3. The heterojunction battery according to claim 1, characterized in that each material from the first subwide bandgap intrinsic layer to the N subwide bandgap intrinsic layer independently includes oxygen-doped amorphous silicon, carbon-doped amorphous silicon, oxygen-doped nanocrystalline silicon, or carbon-doped nanocrystalline silicon.

4. The aforementioned true underlayment layer is, The first sub-substrate true layer, The first sub-sub The defect density of the second sub-substrate intrinsic layer is smaller than the defect density of the first sub-substrate intrinsic layer. The heterojunction battery according to claim 1.

5. N = 2, The heterojunction battery according to claim 3, characterized in that, when the material of the first subwide bandgap intrinsic layer includes oxygen-doped amorphous silicon or oxygen-doped nanocrystalline silicon, and the material of the second subwide bandgap intrinsic layer includes carbon-doped amorphous silicon or carbon-doped nanocrystalline silicon, the molar ratio of oxygen to silicon in the first subwide bandgap intrinsic layer is 1:1 to 1:5, and the molar ratio of carbon to silicon in the second subwide bandgap intrinsic layer is 1:1 to 1:5, and when the material of the first subwide bandgap intrinsic layer includes carbon-doped amorphous silicon or carbon-doped nanocrystalline silicon, and the material of the second subwide bandgap intrinsic layer includes oxygen-doped amorphous silicon or oxygen-doped nanocrystalline silicon, the molar ratio of carbon to silicon in the first subwide bandgap intrinsic layer is 1:1 to 1:5, and the molar ratio of oxygen to silicon in the second subwide bandgap intrinsic layer is 1:1 to 1:

5.

6. The band gap of the first subwide bandgap intrinsic layer is 2.0 eV to 9 eV. The second subwide bandgap intrinsic layer is characterized in that its bandgap is 2.0 eV to 9 eV. The heterojunction battery according to claim 5.

7. The ratio of the thickness of the second subwide bandgap intrinsic layer to the thickness of the first subwide bandgap intrinsic layer is in the range of 0.5:1 to 1.5:

1. The ratio of the thickness of the first sub-wide bandgap intrinsic layer to the thickness of the substrate intrinsic layer is in the range of 0.5:1 to 1.5:

1. The thickness of the second subwide bandgap intrinsic layer is in the range of 1.5 nm to 4 nm. The thickness of the first subwide bandgap intrinsic layer is in the range of 1.5 nm to 4 nm. The thickness of the aforementioned intrinsic substrate layer is in the range of 1.3 nm to 3.3 nm. The heterojunction battery according to claim 5.

8. The intrinsic semiconductor composite layer located on the back side of the semiconductor substrate layer is characterized in that the valence band difference between the intrinsic semiconductor composite layer and the semiconductor substrate layer is in the range of 0.6 eV to 7.9 eV. The heterojunction battery according to claim 1.

9. A method for manufacturing a heterojunction battery, The steps include providing a semiconductor substrate layer, The step includes forming an intrinsic semiconductor composite layer on at least one side of the semiconductor substrate layer, The step of forming the intrinsic semiconductor composite layer is: The steps include forming an underlying intrinsic layer on at least one side of the semiconductor substrate layer, The step includes forming a wide bandgap intrinsic layer on the side of the underlying intrinsic layer opposite to the semiconductor substrate layer, The band gap of the wide band gap intrinsic layer is larger than the band gap of the underlying intrinsic layer. The step of forming the wide bandgap intrinsic layer on the side of the underlying intrinsic layer opposite to the semiconductor substrate layer includes the step of sequentially forming a first sub-wide bandgap intrinsic layer to the Nth sub-wide bandgap intrinsic layer on the side of the underlying intrinsic layer opposite to the semiconductor substrate layer, where N is an integer of 2 or more. The k-th subwide bandgap intrinsic layer is located between the k+1-th subwide bandgap intrinsic layer and the semiconductor substrate layer, where k is an integer between 1 and N-1. A method for manufacturing a heterojunction battery, characterized in that, in the intrinsic semiconductor composite layer located on the front side of the semiconductor substrate layer, the refractive index of the k+1 subwide bandgap intrinsic layer included in the intrinsic semiconductor composite layer is smaller than the refractive index of the k subwide bandgap intrinsic layer.

10. Each of the N sub-wide bandgap intrinsic layers is formed independently from the first sub-wide bandgap intrinsic layer by a chemical vapor deposition process. When oxygen-doped amorphous silicon is independently included in the materials of each of the first sub-wide bandgap intrinsic layer to the N sub-wide bandgap intrinsic layer, the gases used as process parameters for independently forming each of the first sub-wide bandgap intrinsic layer to the N sub-wide bandgap intrinsic layer include silane, hydrogen gas, and carbon dioxide, where the volume ratio of silane to hydrogen gas is 1:1 to 1:10, the volume ratio of carbon dioxide to silane is 1:1 to 1:5, the chamber pressure is 0.2 mBar to 1 mBar, the growth temperature is 180°C to 240°C, and the source RF power density is 150 W / m². ２ ~600W / m ２ And, When oxygen-doped nanocrystalline silicon is independently included in the materials of each of the first sub-wide bandgap intrinsic layer to the N sub-wide bandgap intrinsic layer, the gases used as process parameters for independently forming each of the first sub-wide bandgap intrinsic layer to the N sub-wide bandgap intrinsic layer include silane, hydrogen gas, and carbon dioxide, where the volume ratio of silane to hydrogen gas is 1:20 to 1:80, the volume ratio of carbon dioxide to silane is 1:1 to 1:5, the chamber pressure is 0.5 mBar to 5 mBar, the growth temperature is 180°C to 240°C, and the source RF power density is 500 W / m². ２ ~2250W / m ２ And, When carbon-doped amorphous silicon is independently included in the materials of each of the first sub-wide bandgap intrinsic layer to the N sub-wide bandgap intrinsic layer, the gases used as process parameters for independently forming each of the first sub-wide bandgap intrinsic layer to the N sub-wide bandgap intrinsic layer include silane, hydrogen gas, and methane, where the volume ratio of silane to hydrogen gas is 1:1 to 1:10, the volume ratio of methane to silane is 1:1 to 1:5, the chamber pressure is 0.2 mBar to 1 mBar, the growth temperature is 180°C to 240°C, and the source RF power density is 150 W / m². ２ ~600W / m ２ And, When carbon-doped nanocrystalline silicon is independently included in the materials of each of the first sub-wide bandgap intrinsic layer to the N sub-wide bandgap intrinsic layer, the gases used as process parameters for independently forming each of the first sub-wide bandgap intrinsic layer to the N sub-wide bandgap intrinsic layer include silane, hydrogen gas, and methane, where the volume ratio of silane to hydrogen gas is 1:20 to 1:80, the volume ratio of methane to silane is 1:1 to 1:5, the chamber pressure is 0.5 mBar to 5 mBar, the growth temperature is 180°C to 240°C, and the source RF power density is 500 W / m². ２ ~2250W / m ２ The method for manufacturing a heterojunction battery according to claim 9, characterized in that it is as described above.

11. The step of forming the aforementioned true underlayment layer is, A first sub-substrate intrinsic layer is formed on at least one side of the semiconductor substrate layer, This includes forming a second sub-sub-sub-sub-intrinsic layer on the side of the first sub-sub The method for manufacturing a heterojunction battery according to claim 9, characterized in that the defect density of the second sub-substrate intrinsic layer is smaller than the defect density of the first sub-substrate intrinsic layer.

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