Low-temperature drift ring oscillators, chips, and communication terminals

Abstract

A low temperature drift ring oscillator, a chip and a communication terminal are provided. [Solution] A low-temperature drift ring oscillator includes a temperature tracking compensation circuit, an inverter oscillation circuit, and a buffer shaping circuit. The temperature-dependent impedance of diode-connected PMOS and NMOS transistors is used to track and compensate for the temperature characteristics of the impedance of the PMOS and NMOS transistors of an inverter in the inverter oscillation circuit. At the same time, the proportional relationship of the temperature coefficients of each variable in the temperature tracking compensation circuit is adjusted based on a bias current with a specific temperature coefficient, thereby converting the impedance temperature characteristics of the diode-connected PMOS and NMOS transistors into a voltage with a compensated temperature characteristic, and using this voltage as the supply voltage for the inverter oscillation circuit. This ensures that the oscillation frequency of the clock signal output from the ring oscillator is hardly affected by temperature.

Description

[Technical Field]

[0001] The present invention relates to a low-temperature drift ring oscillator, as well as an integrated circuit chip equipped with this low-temperature drift ring oscillator and a corresponding communication terminal, and belongs to the field of radio frequency integrated circuits. [Background technology]

[0002] With the development of integrated circuits and the increasing complexity of chip application environments, the demand for high-precision integrated circuits is also rising. Oscillators are commonly used high-precision integrated circuits. Among them, ring oscillators are widely used in various types of integrated circuits, especially in phase-locked loop circuits, due to their advantage of being easy to integrate. The complexity of chip application environments includes many influencing factors, the most common of which is temperature. Therefore, it is essential to minimize the effect of temperature on ring oscillators. A typical ring oscillator is constructed by connecting several delay cells from end to end. Among these, the delay units may consist of inverters or differential amplifiers. When forming delay units with inverter connections, the ring oscillator is constructed by connecting cascaded inverters from end to end. A notable feature of ring oscillators is that they form a closed-loop circuit via an odd number of inverters connected in series (i.e., the last output becomes the first input). If the first trigger is "1", the last output is "0", and then the input naturally becomes "0", and the output becomes "1" again. In this way, "0" and "1" are oscillated alternately at a fixed frequency.

[0003] The magnitude of the frequency of the clock signal output from the ring oscillator is determined by the delay time of a single-stage inverter. A single-stage inverter can be regarded as the charging and discharging of a ground capacitor at the output end, and its delay time can be regarded as the charging and discharging time of the ground capacitor. The length of the charging and discharging time of the ground capacitor is determined by the magnitude of the resistance in the charging and discharging path and the capacitance of the ground capacitor. Among them, since the resistance in the charging and discharging path is easily affected by temperature, reducing the influence of the resistance of the charging and discharging path accompanying temperature change is one of the important factors for realizing a low-temperature drift ring oscillator.

Summary of the Invention

[0004] The first technical problem to be solved by the present invention is to provide a low-temperature drift ring oscillator.

[0005] Other technical problems to be solved by the present invention are to provide a chip equipped with a low-temperature drift ring oscillator and a corresponding communication terminal.

Means for Solving the Problems

[0006] To achieve the above object, the present invention uses the following technical solutions. In a first aspect according to an embodiment of the present invention, a low-temperature drift ring oscillator is provided, which includes a temperature tracking compensation circuit, an inverter oscillation circuit, and a buffer shaping circuit. The output end of the temperature tracking compensation circuit is connected to the input end of the inverter oscillation circuit, and the output end of the inverter oscillation circuit is connected to the input end of the buffer shaping circuit.

[0007] Preferably, the inverter oscillation circuit is composed of an odd number of first inverters and capacitors of the same number of stages as the first inverters connected in cascade. The cascaded first inverters are connected from end to end, all the first inverters are connected to the temperature tracking compensation circuit, and the last-stage first inverter is connected to the buffer shaping circuit.

[0008] Preferably, the capacitor is a MOS capacitor or a MIM capacitor.

[0009] Preferably, the temperature tracking compensation circuit includes a temperature tracking compensation unit, a first enable control unit, a voltage follower unit, a first filter unit, and a second filter unit. The voltage follower unit is connected to the temperature tracking compensation unit, the first enable control unit, the first filter unit, and the bias current generation circuit respectively. The second filter unit is connected to the voltage follower unit, and the temperature tracking compensation unit, the first enable control unit, the voltage follower unit, the first filter unit, and the second filter unit are further connected to the ground respectively.

[0010] Preferably, the temperature tracking compensation unit is composed of a diode-connected second PMOS transistor and a fourth NMOS transistor. Alternatively, the temperature tracking compensation unit is realized by a third PMOS transistor or a seventh NMOS transistor.

[0011] Preferably, the voltage follower unit is realized by using a voltage follower or a voltage non-inverting amplifier.

[0012] Preferably, the buffer shaping circuit is composed of a level conversion unit including a second inverter.

[0013] Preferably, by providing a PMOS transistor or an NMOS transistor as an enable control transistor at one or more positions of the temperature tracking compensation circuit, the inverter oscillation circuit, and the buffer shaping circuit, the on / off of the temperature tracking compensation circuit, the inverter oscillation circuit, and the buffer shaping circuit is controlled.

[0014] Preferably, the temperature tracking compensation circuit tracks the temperature characteristics of the first inverter impedance in the inverter oscillator circuit, generates a supply voltage having temperature characteristics that compensate for the oscillation frequency of the inverter oscillator circuit, and outputs it to the inverter oscillator circuit.

[0015] A second embodiment of the present invention provides an integrated circuit chip including the low-temperature drift ring oscillator described above.

[0016] A third embodiment of the present invention provides a communication terminal including the low-temperature drift ring oscillator described above. [Effects of the Invention]

[0017] The low-temperature drift ring oscillator, chip, and communication terminal provided by the present invention utilize the temperature-dependent impedance of diode-connected PMOS and NMOS transistors to track and compensate for the temperature characteristics of the impedance of the inverter's PMOS and NMOS transistors in the inverter oscillator circuit. Simultaneously, each variable μ in the temperature tracking compensation circuit is compensated based on a bias current having a specific temperature coefficient. n ,μ p ,Vth n ,Vth p By adjusting the proportional relationship of the temperature coefficients, the impedance temperature characteristics of the diode-connected PMOS and NMOS transistors are compensated for by converting them into a voltage with temperature characteristics. This voltage is then used as the supply voltage for the inverter oscillator circuit, thereby realizing an output clock signal for a ring oscillator whose oscillation frequency is hardly affected by temperature. [Brief explanation of the drawing]

[0018] [Figure 1] This is a schematic block diagram of a low-temperature drift ring oscillator provided by an embodiment of the present invention. [Figure 2] This is a schematic diagram of the circuit of a low-temperature drift ring oscillator provided by an embodiment of the present invention. [Figure 3a]This is a schematic diagram of the inverter delay charging model of the inverter oscillator circuit in a low-temperature drift ring oscillator provided by an embodiment of the present invention. [Figure 3b] This is a schematic diagram of the inverter delay discharge model of the inverter oscillator circuit in a low-temperature drift ring oscillator provided by an embodiment of the present invention. [Figure 4] This is a circuit diagram 1 of a temperature tracking compensation circuit in a low-temperature drift ring oscillator provided by an embodiment of the present invention. [Figure 5a] This is a circuit diagram 2 of a temperature tracking compensation circuit in a low-temperature drift ring oscillator provided by an embodiment of the present invention. [Figure 5b] This is a circuit diagram 3 of a temperature tracking compensation circuit in a low-temperature drift ring oscillator provided by an embodiment of the present invention. [Modes for carrying out the invention]

[0019] The technical details of the present invention will be described in more detail below with reference to the drawings and specific embodiments. The objective is to improve the stability and reliability of the circuit system by ensuring that the oscillation frequency of the clock signal output by the ring oscillator is hardly affected by temperature. As shown in Figure 1, a low-temperature drift ring oscillator provided by one embodiment of the present invention comprises a temperature tracking compensation circuit 401, an inverter oscillation circuit 402, and a buffer shaping circuit 403. Here, the output terminal of the temperature tracking compensation circuit 401 is connected to the input terminal of the inverter oscillation circuit 402, and the output terminal of the inverter oscillation circuit 402 is connected to the input terminal of the buffer shaping circuit 403.

[0020] The inverter oscillator circuit 402 is used to generate a clock signal with the oscillation frequency required for the design. The inverter oscillator circuit 402 is configured by cascading odd-numbered stages of first inverters and the same number of capacitors as the number of stages of the first inverters. Here, the cascaded first inverters are connected from end to end, all first inverters are connected to the temperature tracking compensation circuit 401, and the last stage of the first inverters is connected to the buffer shaping circuit 403. In the embodiment shown in Figure 2, the inverter oscillator circuit 402 is configured by cascading three stages of first inverters 4020 and three capacitors from end to end, with each stage of the first inverter comprising a first NMOS transistor and a first PMOS transistor. The first NMOS transistor is connected corresponding to the gate and drain of the first PMOS transistor, the source of the first PMOS transistor is connected to the temperature tracking compensation circuit 401, and the source of the first NMOS transistor is grounded. Furthermore, the drains of the first NMOS transistor and the first PMOS transistor of the first inverter located in the final stage are connected to each other and then connected to the buffer shaping circuit 403. Here, the capacitor of the inverter oscillator circuit 402 may be a MOS capacitor or an MIM capacitor.

[0021] As shown in Figure 2, the first NMOS transistor 504 and the first PMOS transistor 505, the first NMOS transistor 508 and the first PMOS transistor 509, the first NMOS transistor 511 and the first PMOS transistor 512 each constitute an inverter to obtain a three-stage first inverter. Here, the cascaded first inverters are connected end to end, that is, the drains of the first NMOS transistor 511 and the first PMOS transistor 512 in the third-stage first inverter are connected together and then connected to the gates of the first NMOS transistor 504 and the first PMOS transistor 505 in the first-stage first inverter. The second NMOS transistor 507, the second NMOS transistor 510 and the second NMOS transistor 513 are connected in a MOS capacitor manner. Specifically, the gate of the second NMOS transistor 507 is connected to the drains of the first NMOS transistor 504 and the first PMOS transistor 505, and to the gates of the first NMOS transistor 508 and the first PMOS transistor 509, respectively. The gate of the second NMOS transistor 510 is connected to the drains of the first NMOS transistor 508 and the first PMOS transistor 509, and to the gates of the first NMOS transistor 511 and the first PMOS transistor 512, respectively. The gate of the second NMOS transistor 513 is connected to the drains of the first NMOS transistor 511 and the first PMOS transistor 512, and the sources and drains of the second NMOS transistor 507, the second NMOS transistor 510, and the second NMOS transistor 513 are grounded, respectively. Thus, the above three stages of the first inverter and the three MOS capacitors are cascaded to form the inverter oscillator circuit 402.

[0022] To ensure the on / off switching of the inverter oscillator circuit 402, enable control tubes can be provided at corresponding positions in the inverter oscillator circuit 402. Here, depending on the actual demands of the circuit, it is selected to provide PMOS transistors or NMOS transistors as enable control tubes at one or more positions in the inverter oscillator circuit 402 to control the on / off switching of the inverter oscillator circuit 402. In the embodiment shown in Figure 2, a third NMOS transistor 506 may be provided as an enable control tube between the first inverter and the second NMOS transistor 507 in the first stage of the inverter oscillator circuit 402. The gate of this third NMOS transistor 506 receives an enable signal, the drain of the third NMOS transistor 506 is connected to the drains of the first NMOS transistor 504 and the first PMOS transistor 505 in the first inverter of the first stage, and the source of the third NMOS transistor 506 is grounded.

[0023] For the inverter oscillator circuit 402 to oscillate, the positive feedback condition must be met. Therefore, when configuring a delay unit using the first inverter, the number of stages of the first inverter must be an odd number greater than 1. The delay time of the first inverter of the first stage is t d Assuming that an odd number of N (N>1) first inverters and the same number of capacitors are connected from end to end, and these are cascaded to form an inverter oscillator circuit 402, the oscillation frequency of the inverter oscillator circuit 402 is f = 1 / (2Nt d As can be seen from the formula, the delay time of the first inverter in each stage determines the oscillation frequency of the inverter oscillator circuit 402.

[0024] As shown in FIG. 2, by alternately switching between the high level and the low level of the enable signal, the first NMOS transistor and the first PMOS transistor in the first inverter of each stage are alternately turned on and off, and the load capacitors (such as the second NMOS transistor 507, the second NMOS transistor 510, and the second NMOS transistor 513 illustrated in FIG. 2) are charged and discharged sequentially. The charging and discharging time of the capacitor is the delay time of the first inverter of each stage.

[0025] FIG. 3a shows the delay charging model of the inverter in the inverter oscillation circuit. FIG. 3b shows the delay discharging model of the inverter in the inverter oscillation circuit. In the inverter oscillation circuit, when the first PMOS transistor of the first inverter is turned on and the first NMOS transistor of the first inverter is turned off, the conduction equivalent resistance Rp of the first PMOS transistor and the power supply charge the capacitor CL. Here, the resistance Rp is the resistance on the charging circuit. The charging formula of the capacitor is

Equation

[0026] In the formula, V c is the voltage at the capacitor terminal, V dd is the power supply voltage, CL is the capacitance, τ is the time constant, and t is the charging time of the capacitor.

[0027] When the first NMOS transistor of the first inverter is turned on and the first PMOS transistor of the first inverter is turned off, the conduction equivalent resistance Rn of the first NMOS transistor and the capacitor CL discharge to the ground. Here, the resistance Rn is the resistance on the charging circuit. The discharging formula of the capacitor is

Equation

[0028] In the formula, V c is the voltage at the capacitor terminal, Vo θ is the voltage across the capacitor before discharge, CL is the capacitance, τ is the time constant, and t is the discharge time of the capacitor.

[0029] Based on equations (1) and (2), the delay time of the first inverter of the first stage,

number

number

number

number

number

number

number

[0030] As can be seen from the above, the amplitude of the oscillation frequency of the clock signal output from the inverter oscillator circuit 402 is determined by the magnitude of the impedance of the first PMOS transistor and the first NMOS transistor in the first inverter, and the capacitance of the capacitor in the inverter oscillator circuit 402. Here, the impedance of the first PMOS transistor and the first NMOS transistor is greatly affected by temperature, while the capacitance of the capacitor is less affected by temperature. Therefore, the variable μ n ,μ p ,Vth n ,Vth p By changing the proportional relationship of the temperature coefficients,

number

[0031] As shown in Figures 4, 5a, and 5b, the temperature tracking compensation circuit 401 comprises a temperature tracking compensation unit 4010, a first enable control unit 4011, a voltage tracking unit 4012, a first filter unit 4013, and a second filter unit 4014. The voltage tracking unit 4012 is connected to the temperature tracking compensation unit 4010, the first enable control unit 4011, the first filter unit 4013, and the bias current generation circuit, respectively. The second filter unit 4014 is connected to the voltage tracking unit 4012, and the temperature tracking compensation unit 4010, the first enable control unit 4011, the voltage tracking unit 4012, the first filter unit 4013, and the second filter unit 4014 are each further connected to ground.

[0032] As shown in Figure 4, the temperature tracking compensation unit 4010 may consist of a diode-connected second PMOS transistor 602 and a fourth NMOS transistor 601. That is, the gate of the second PMOS transistor 602 is connected to the drain, the gate of the fourth NMOS transistor 601 is connected to the drain, and the drains of the second PMOS transistor 602 and the drain of the fourth NMOS transistor 601 are connected. The source of the second PMOS transistor 602 is connected to the first enable control unit 4011, the voltage tracking unit 4012, the first filter unit 4013, and the bias current generation circuit, respectively, and the source of the fourth NMOS transistor 601 is grounded. Here, the bias current generated by the bias current generation circuit is a bias current having a specific temperature coefficient. This bias current may be a current with a zero temperature coefficient, or a current with a positive or negative temperature coefficient, in order to better balance the temperature characteristics of the oscillation frequency of the clock signal output from this low-temperature drift ring oscillator.

[0033] The diode connections used in the above-mentioned PMOS and NMOS transistors may also be gate-source connection methods related to the manufacturing process of integrated circuits. In integrated circuits, the diodes used correspond to a combination of source-gate junction or drain-gate junction of a MOS transistor, depending on the application.

[0034] Since the second PMOS transistor 602 and the fourth NMOS transistor 601 of the temperature tracking compensation unit 4010 are integrated on the same integrated circuit chip as the PMOS and NMOS transistors in the inverter oscillator circuit 402, the temperature change trends of the second PMOS transistor 602 and the fourth NMOS transistor 601 are basically the same as the characteristics of the PMOS and NMOS transistors in the inverter oscillator circuit 402. Therefore, the temperature-dependent impedances shown by the second PMOS transistor 602 and the fourth NMOS transistor 601 can be used to track the temperature characteristics of the PMOS and NMOS transistor impedances in the tracking inverter oscillator circuit 402.

[0035] Specifically, based on the temperature-dependent impedances shown by the second PMOS transistor 602 and the fourth NMOS transistor 601 of the temperature tracking compensation unit 4010, the temperature characteristics of the PMOS and NMOS transistor impedances in the inverter oscillator circuit 402 are tracked, and the aspect ratios of the second PMOS transistor 602 and the fourth NMOS transistor 601 are adjusted, respectively, thereby controlling the variable μ of the second PMOS transistor 602. p ,Vth p and the variable μ of the fourth NMOS transistor 601 n ,Vth nThe proportional relationship of the temperature coefficients is adjusted to obtain an impedance with a specific temperature coefficient. Furthermore, the second PMOS transistor 602 and the fourth NMOS transistor 601 are biased based on a bias current with a specific temperature coefficient provided by the bias current generation circuit, generating a supply voltage Vtrim with a temperature characteristic that compensates for the oscillation frequency of the inverter oscillator circuit 402. This supply voltage Vtrim is driven or amplified via the voltage tracking unit 4012 before providing a supply voltage Vdd to the inverter oscillator circuit 402. Thus, the variable μ of the second PMOS transistor 602... p ,Vth p and the variable μ of the fourth NMOS transistor 601 n ,Vth n The proportional relationship of the temperature coefficient is adjusted, and the variable μ of the inverter oscillator circuit 402 is adjusted. n ,μ p ,Vth n ,Vth p ,V dd By compensating for the temperature coefficient, the inverter oscillator circuit 402 can output a clock signal whose oscillation frequency is not affected by temperature.

[0036] Here, as shown in Figure 4, the voltage tracking unit 4012 can be implemented using a voltage follower 605. This voltage follower 605 is used to enhance the driving of the supply voltage Vtrim generated by the temperature tracking compensation unit 4010, which has temperature characteristics that compensate for the oscillation frequency of the inverter oscillator circuit 402.

[0037] As shown in Figures 5a and 5b, the voltage tracking unit 4012 can use a voltage common-mode amplifier according to different design requirements. This voltage common-mode amplifier comprises an operational amplifier 705, a first resistor R1, and a second resistor R2. The positive-sequence input terminal of the operational amplifier 705 is connected to the source of a second PMOS transistor 701, a first enable control unit 4011, a first filter unit 4013, and a bias current generation circuit. The inverting input terminal of the operational amplifier 705 is connected to one end of the first resistor R1 and the second resistor R2, and the output terminal of the operational amplifier 705 is connected to the source of the first PMOS transistor of the first inverter in the second filter unit 4014 and the inverter oscillator circuit 402. The supply voltage Vtrim generated by the temperature tracking compensation unit 4010, which has a temperature characteristic to compensate for the oscillation frequency of the inverter oscillator circuit 402, is amplified by the voltage common-mode amplifier and then provides the power source voltage Vdd to the inverter oscillator circuit 402. The power supply voltage is Vdd = {(R1+R2) / R1}·Vtrim.

[0038] As shown in Figures 5a and 5b, the temperature tracking compensation unit 4010 can also be implemented using a third PMOS transistor 701 or a seventh NMOS transistor 801. Specifically, the source of the third PMOS transistor 701 is connected to the first enable control unit 4011, the voltage tracking unit 4012, the first filter unit 4013, and the bias current generation circuit, respectively, and the gate and drain of the third PMOS transistor 701 are grounded. The gate and drain of the seventh NMOS transistor 801 are connected to the first enable control unit 4011, the voltage tracking unit 4012, the first filter unit 4013, and the bias current generation circuit, respectively, and the source of the seventh NMOS transistor 801 is grounded.

[0039] Based on the temperature-dependent impedance shown by the third PMOS transistor 701 or the seventh NMOS transistor 801 of the temperature tracking compensation unit 4010, the temperature characteristics of the PMOS and NMOS transistor impedances in the inverter oscillator circuit 402 are tracked. By adjusting the aspect ratio of the third PMOS transistor 701 or the seventh NMOS transistor 801, respectively, the variable μ of the third PMOS transistor 701 is tracked. p ,Vth p and the variable μ of the 7th NMOS transistor 801 n ,Vth n The proportional relationship of the temperature coefficients is adjusted to obtain an impedance with a specific temperature coefficient. Furthermore, based on the current with a specific temperature coefficient provided by the bias current generation circuit, a bias is applied to the third PMOS transistor 701 or the seventh NMOS transistor 801 to generate a supply voltage Vtrim with a temperature characteristic that compensates for the oscillation frequency of the inverter oscillator circuit 402. This supply voltage Vtrim is amplified by a voltage common-mode amplifier and then supplied to the inverter oscillator circuit 402 with a supply voltage Vdd, thereby controlling the variable μ of the third PMOS transistor 701. p ,Vth p and the variable μ of the 7th NMOS transistor 801 n ,Vth n The proportional relationship of the temperature coefficient is adjusted, and the variable μ of the inverter oscillator circuit 402 is adjusted. n ,μ p ,Vth n ,Vth p ,V dd This compensates for the temperature coefficient. Therefore, the inverter oscillator circuit 402 outputs a clock signal whose oscillation frequency is hardly affected by temperature.

[0040] The first filter unit 4013 and the second filter unit 4014 perform filtering and voltage stabilization functions. As shown in Figures 4, 5a, and 5b, the first filter unit 4013 can be realized using a fifth NMOS transistor 606. The second filter unit 4014 can be realized using a sixth NMOS transistor 607. The gate of the fifth NMOS transistor 606 is connected to the source of the second PMOS transistor 602, the drain of the eighth NMOS transistor 604, and the positive-sequence input terminal of the voltage follower 605, respectively, and the source and drain of the fifth NMOS transistor are grounded, respectively. The gate of the sixth NMOS transistor 607 is connected to the output terminal of the voltage follower 605 and the source of the first PMOS transistor of the inverter in each stage of the inverter oscillator circuit 402, and the source and drain of the sixth NMOS transistor 607 are grounded, respectively.

[0041] The first enable control unit 4011 controls the on / off state of the temperature tracking compensation circuit 401. This first enable control unit 4011 can be provided at corresponding locations on the temperature tracking compensation circuit 401. Depending on the design requirements of the circuit, it is possible to select to provide a PMOS transistor or an NMOS transistor as an enable control tube at one or more locations on the temperature tracking compensation circuit 401 to control the on / off state of the temperature tracking compensation circuit 401. As shown in Figure 4, an eighth NMOS transistor 604 may be provided as an enable control tube between the second PMOS transistor 602 of the temperature tracking compensation circuit 401 and the fifth NMOS transistor 606 of the first filter unit 4013. The gate of this eighth NMOS transistor 604 is connected to the enable signal, the drain of the eighth NMOS transistor 604 is connected to the source of the second PMOS transistor 602, the gate of the fifth NMOS transistor 606 and the positive-sequence input terminal of the voltage follower 605, and the source of the eighth NMOS transistor 604 is grounded.

[0042] The buffer shaping circuit 403 is used to shape the clock signal output from the inverter oscillator circuit, adjust the duty cycle, and enhance the drive capability to meet signal quality requirements. This may generally be implemented by a level conversion circuit or by other circuits.

[0043] In one embodiment of the present invention, as shown in Figure 2, the buffer shaping circuit 403 is composed of a multi-stage second inverter cascade, that is, a level conversion unit consisting of second inverters. As shown in Figure 2, as one example, the buffer shaping circuit 403 is configured by cascading four stages of second inverters 4030, and each stage of the second inverter 4030 includes a ninth NMOS transistor and a fourth PMOS transistor. The ninth NMOS transistor is connected correspondingly to the gate and drain of the fourth PMOS transistor, the source of the fourth PMOS transistor is connected to the power supply voltage, and the source of the ninth NMOS transistor is grounded. In addition, the gates of the ninth NMOS transistor and the fourth PMOS transistor in the first stage of the second inverter 4030 are connected together and used as the input terminal of the first stage of the second inverter 4030 to connect the drains of the first NMOS transistor and the first PMOS transistor of the first inverter in the final stage of the inverter oscillator circuit 402. The ninth NMOS transistor of the final stage second inverter 4030 is connected to the output terminal of the first stage second inverter 4030, along with the drain of the fourth PMOS transistor.

[0044] As shown in Figure 2, the ninth NMOS transistor 514 and the fourth PMOS transistor 517, the ninth NMOS transistor 519 and the fourth PMOS transistor 520, the ninth NMOS transistor 521 and the fourth PMOS transistor 522, and the ninth NMOS transistor 523 and the fourth PMOS transistor 524 each constitute a second inverter of their respective stages, thereby obtaining a four-stage second inverter. The above four-stage second inverters are cascaded to form a buffer shaping circuit 403. In this buffer shaping circuit 403, the duty cycle is adjusted by the aspect ratio of the ninth NMOS transistor and the fourth PMOS transistor in the first two stages of the second inverter, and the drive capability is enhanced by the aspect ratio of the ninth NMOS transistor and the fourth PMOS transistor in the last two stages of the second inverter.

[0045] To ensure the on / off state of the buffer shaping circuit 403, enable control tubes can be provided at corresponding locations in the buffer shaping circuit 403. Here, depending on the design requirements of the circuit, it is selected to provide PMOS transistors or NMOS transistors as enable control tubes at one or more locations in the buffer shaping circuit 403 to control the on / off state of the buffer shaping circuit 403. As shown in Figure 2, a 10th NMOS transistor 515 and a 5th PMOS transistor 516 may be provided as enable control tubes between the 9th NMOS transistor 514 and the 4th PMOS transistor 517 of the second inverter of the first stage in the buffer shaping circuit 403, respectively. The gates of the 10th NMOS transistor 515 and the 5th PMOS transistor 516 are connected to the enable signal, the source of the 10th NMOS transistor 515 is connected to the drain of the 9th NMOS transistor 514, and the source of the 5th PMOS transistor 516 is connected to the drain of the 4th PMOS transistor 517. Furthermore, a sixth PMOS transistor 518 is provided as an enable control tube between the power supply voltage and the output terminal of the second inverter of the first stage, and the gate of the sixth PMOS transistor 518 is connected to the enable signal. The drain of the sixth PMOS transistor 518 is connected to the drains of the tenth NMOS transistor 515 and the fifth PMOS transistor 516, and to the gates of the ninth NMOS transistor 519 and the fourth PMOS transistor 520, respectively.

[0046] In summary, the temperature tracking compensation circuit 401 tracks the temperature characteristics of the first inverter impedance in the inverter oscillator circuit 402 and generates a supply voltage with temperature characteristics that compensate for the oscillation frequency of the inverter oscillator circuit 402, outputting it to the inverter oscillator circuit 402. As a result, the oscillation frequency of the clock signal output from the inverter oscillator circuit 402 is hardly affected by temperature. The clock signal output from the inverter oscillator circuit is shaped and driven via the buffer shaping circuit 403 to meet the signal quality requirements.

[0047] Furthermore, the low-temperature drift ring oscillator provided by the embodiments of the present invention may be used in an integrated circuit chip. The specific structure of the low-temperature drift ring oscillator in this integrated circuit chip will not be described in detail here.

[0048] The low-temperature drift ring oscillator described above can also be used in communication terminals as an important component of RF integrated circuits. The communication terminals referred to here are computer devices that can be used in mobile environments and support various communication standards such as GSM, EDGE, TD_SCDMA, TDD_LTE, and FDD_LTE, including mobile phones, laptops, tablet PCs, and in-vehicle PCs. Furthermore, the technical solutions provided in this invention are applicable to other RF integrated circuit applications, such as communication base stations.

[0049] The low-temperature drift ring oscillator, chip, and communication terminal provided by embodiments of the present invention utilize the temperature-dependent impedance of diode-connected PMOS and NMOS transistors to track and compensate for the temperature characteristics of the impedance of the inverter's PMOS and NMOS transistors in the inverter oscillator circuit. Simultaneously, each variable μ in the temperature tracking compensation circuit is adjusted based on a bias current having a specific temperature coefficient. n ,μ p ,Vth n ,Vth p By adjusting the proportional relationship of the temperature coefficients, the impedance temperature characteristics of the diode-connected PMOS and NMOS transistors are converted into a voltage with temperature characteristics that compensates for these characteristics. By using this voltage as the supply voltage for the inverter oscillator circuit, the oscillation frequency of the clock signal output from the ring oscillator is hardly affected by temperature.

[0050] The low-temperature drift ring oscillator, chip, and communication terminal provided by the present invention have been described in detail above. Those skilled in the art will know that any obvious modifications made thereto without departing from the substantial content of the invention will all fall within the scope of the patent protection of the present invention.

Claims

1. A low-temperature drift ring oscillator, The system comprises a temperature tracking compensation circuit, an inverter oscillator circuit, and a buffer shaping circuit, wherein the output terminal of the temperature tracking compensation circuit is connected to the input terminal of the inverter oscillator circuit, and the output terminal of the inverter oscillator circuit is connected to the input terminal of the buffer shaping circuit. The inverter oscillation circuit comprises multiple inverters connected in a ring shape, a power supply voltage is supplied to the input terminal of the inverter oscillation circuit from the output terminal of the temperature tracking compensation circuit, and the temperature tracking compensation circuit compensates for changes in the oscillation frequency of the inverter oscillation circuit due to temperature. The temperature tracking compensation circuit comprises a temperature tracking compensation unit, a first enable control unit, a voltage tracking unit, a first filter unit, and a second filter unit, wherein the voltage tracking unit is connected to the temperature tracking compensation unit, the first enable control unit, the first filter unit, and the bias current generation circuit, respectively, and the second filter unit is connected to the voltage tracking unit, and the temperature tracking compensation unit, the first enable control unit, the voltage tracking unit, the first filter unit, and the second filter unit are each further connected to ground. The temperature tracking compensation unit generates a temperature-dependent voltage based on the bias current provided by the bias current generation circuit and outputs it to the voltage tracking unit. The voltage tracking unit generates an output voltage that tracks the temperature-dependent voltage, and outputs the output voltage from the output terminal of the temperature tracking compensation circuit to the inverter oscillation circuit as the power supply voltage. The first enable control unit controls the on / off state of the temperature tracking compensation circuit. The first filter unit filters the input signal of the voltage tracking unit, and the second filter unit filters the output signal of the voltage tracking unit. A low-temperature drift ring oscillator characterized by the following features.

2. The inverter oscillator circuit is configured by cascading an odd-numbered first inverter and capacitors of the same number as the first inverter. The low-temperature drift ring oscillator according to claim 1, characterized in that the cascaded first inverters are connected from end to end, all of the first inverters are connected to the temperature tracking compensation circuit, and the final stage first inverter is connected to the buffer shaping circuit.

3. The low-temperature drift ring oscillator according to claim 2, characterized in that the capacitor is a MOS capacitor or an MIM capacitor.

4. The low-temperature drift ring oscillator according to claim 1, characterized in that the temperature tracking compensation unit is composed of a diode-connected second PMOS transistor and a fourth NMOS transistor.

5. The low-temperature drift ring oscillator according to claim 1, characterized in that the temperature tracking compensation unit is implemented by a third PMOS transistor or a seventh NMOS transistor.

6. The low-temperature drift ring oscillator according to claim 1, characterized in that the voltage tracking unit is implemented using a voltage follower or a non-inverting amplifier.

7. The low-temperature drift ring oscillator according to claim 1, characterized in that the buffer shaping circuit is composed of a level conversion unit consisting of a second inverter.

8. The low-temperature drift ring oscillator according to claim 1, characterized in that a PMOS transistor or an NMOS transistor is provided as an enable control tube at one or more positions of the temperature tracking compensation circuit, the inverter oscillation circuit, and the buffer shaping circuit in order to control the on / off state of the temperature tracking compensation circuit, the inverter oscillation circuit, and the buffer shaping circuit.

9. The low-temperature drift ring oscillator according to any one of claims 1 to 8, characterized in that the temperature tracking compensation circuit tracks the temperature characteristics of the first inverter impedance in the inverter oscillation circuit, generates a supply voltage having temperature characteristics that compensate for the oscillation frequency of the inverter oscillation circuit, and outputs it to the inverter oscillation circuit.

10. An integrated circuit chip characterized by comprising a low-temperature drift ring oscillator according to any one of claims 1 to 9.

11. A communication terminal characterized by comprising a low-temperature drift ring oscillator according to any one of claims 1 to 9.

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