Analog-to-digital converters and electronic equipment

Abstract

[Problem] To provide an analog-digital converter having excellent AD conversion accuracy and SNDR. [Solution] An analog-digital converter for converting an analog signal into a digital signal in a sampling period including, successively, a first interval, a second interval, and a third interval, the analog-digital converter comprising: a digital-analog converter for sampling an analog signal in the first interval, converting the sampled signal into a digital signal with redundancy provided in the second interval and one bit after another successively, and outputting residual signals that have not been converted; a filter unit for sampling the residual signals in the third interval, and, in at least the second interval, performing, on the basis of some of the residual signals sampled in the third interval in the last sampling period and some of the residual signals sampled in the third interval in the last-but-one sampling period, charge transfer or charge redistribution to generate a noise shaping signal; and a DAC control unit for controlling, on the basis of the residual signals and the noise shaping signal, the digital-analog converter in the second interval.

Description

Technical Field

[0004] , , , ,

[0005] , , ,

[0001] The present disclosure relates to an analog-digital converter and an electronic device.

Background Art

[0002] A successive approximation register analog digital converter (SAR ADC) that performs noise shaping is known (see Patent Document 1). This type of SAR ADC holds the residual voltage of a capacitive digital-to-analog converter (CDAC), and adds the held residual voltage to the output of the CDAC in the next sampling period to perform noise shaping. In Patent Document 1, higher-order noise shaping can be performed by holding the residual voltage with an arbitrary time delay.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In a SAR ADC, it is necessary to provide a period for sampling an input signal, a period for AD-converting the sampled input signal, and a period for sampling a residual voltage within one sampling period.

[0005] During the AD conversion period, it is necessary to compare the sampled input signal with a comparator and control the CDA based on the comparison result. However, if temperature conditions or skew conditions worsen, the AD conversion takes longer, which may result in insufficient time to sample the residual voltage. If the residual voltage sampling is incomplete, noise shaping will not be performed correctly, and the SNDR (Signal-to-Noise and Distortion Ratio) will deteriorate.

[0006] To solve this problem, one could consider shortening the sampling period for the input signal to ensure sufficient time for AD conversion and residual voltage sampling. However, in SAR ADCs, the noise-shaping signal is sometimes generated by transferring all the charge from one capacitor to another within the input signal sampling period. In this case, if the input signal sampling period is shortened, the entire charge transfer may not be completed in time. If the entire charge transfer is not completed in time, the SNDR will also deteriorate.

[0007] Patent Document 1 performs residual signal sampling using a method different from the method described above, and does not offer a solution to the problems of the method described above.

[0008] Therefore, this disclosure provides an analog-to-digital converter and electronic device that can correctly sample the residual signal after the AD conversion of the input signal is completed, and that has excellent AD conversion accuracy and SNDR. [Means for solving the problem]

[0009] To solve the above problems, the present disclosure provides an analog-to-digital converter that converts an analog signal to a digital signal within a sampling period including a continuous first period, a second period, and a third period, A digital-to-analog converter that samples the analog signal within a first period, converts the sampled signal into a digital signal bit by bit with redundancy within a second period, and outputs the unconverted residual signal. A filter unit that samples the residual signal within the third period and generates a noise-shaping signal by performing charge transfer or charge redistribution based at least within the second period on a portion of the residual signal sampled in the third period within the immediately preceding sampling period and a portion of the residual signal sampled in the third period within the sampling period two periods prior; An analog-to-digital converter is provided, comprising: a DAC control unit that controls the digital-to-analog converter within the second period based on the residual signal and the noise shaping signal.

[0010] The filter unit may generate the noise shaping signal by transferring charge between a portion of the residual signal sampled in the third period within the immediately preceding sampling period and a portion of the residual signal sampled in the third period within the sampling period two periods prior, during the first and second periods.

[0011] The filter unit may generate the noise shaping signal by redistributing charge between a portion of the residual signal sampled in the third period within the immediately preceding sampling period and a portion of the residual signal sampled in the third period within the sampling period two periods prior, during the first and second periods.

[0012] The filter unit is Multiple first capacitors, The system includes a plurality of first switches that switch whether or not to store charge in each of the plurality of first capacitors, Some of the plurality of first capacitors accumulate charge corresponding to the residual signal during the third period. During the first and second periods, charge transfer is performed from one of the first capacitors that accumulated the residual signal during the third period of the immediately preceding sampling period to another first capacitor. The noise shaping signal may be generated by the charge transferred to the other first capacitor.

[0013] The filter unit is A first differential amplifier having a first differential input terminal into which the residual signal is input, and a first differential output terminal that outputs a differential signal corresponding to the residual signal, A second differential amplifier is provided, having a second differential input terminal and a second differential output terminal, and outputting the differential noise shaping signal from the second differential output terminal. The other first capacitor may be connected between the second differential input terminal and the second differential output terminal of the second differential amplifier.

[0014] A first chopper that periodically swaps the differential input signals input to at least one of the first differential input terminal of the first differential amplifier and the second differential input terminal of the second differential amplifier, The system may further include a second chopper that periodically switches the differential output signals output from at least one of the first differential output terminal of the first differential amplifier and the second differential output terminal of the second differential amplifier, in synchronization with the switching of the first chopper.

[0015] The filter unit is Multiple first capacitors, The system includes a plurality of first switches that switch whether or not to store charge in each of the plurality of first capacitors, Some of the plurality of first capacitors accumulate charge corresponding to the residual signal during the third period. During the first and second periods, the accumulated charge of a portion of the first capacitors that accumulated the residual signal during the third period of the immediately preceding sampling period may be redistributed between the portion of the first capacitors and another first capacitor to generate the noise shaping signal.

[0016] Among some of the plurality of first capacitors, charge accumulation and transfer are performed for each sampling period, and for the remaining first capacitors, charge accumulation and transfer may be performed in one of two consecutive sampling periods.

[0017] The analog signal is a differential analog signal, Two digital-to-analog converters for converting the differential analog signal into a differential digital signal are provided, A differential residual signal is output from the two digital-to-analog converters, The filter unit generates a differential noise shaping signal within the first period and the second period, The DAC control unit may control the two digital-to-analog converters based on the differential residual signal and the differential noise shaping signal within the second period.

[0018] The DAC control unit may control the two digital-to-analog converters such that the sum value of the signal difference of the differential residual signal and the signal difference of the differential noise shaping signal approaches zero.

[0019] The DAC control unit, a comparator that outputs a signal corresponding to the sum value of the signal difference of the differential residual signal and the signal difference of the differential noise shaping signal, and a logic circuit that controls the digital-to-analog converter based on the output signal of the comparator may be included.

[0020] The digital-to-analog converter, a plurality of second capacitors to which the analog signal is supplied at one end of each or from which the residual signal is output at one end of each, and a plurality of second switches for setting the other end sides of the plurality of second capacitors to any one of a plurality of voltages. The DAC control unit may control the switching of the plurality of second switches based on the residual signal and the noise shaping signal.

[0021] The aforementioned digital-to-analog converter is A plurality of second capacitors, each supplied with the analog signal at one end, or with the residual signal output from one end, The system includes a plurality of second switches that set the other end of the plurality of second capacitors to one of a plurality of voltages, The filter unit may, within the second period, redistribute the charge of a portion of the residual signal sampled in the third period within the immediately preceding sampling period and a portion of the residual signal sampled in the third period within the sampling period two periods prior, with the plurality of second capacitors in the digital-to-analog converter, to generate the noise shaping signal.

[0022] The filter unit is Multiple first capacitors, The system includes a plurality of first switches that switch whether or not to store charge in each of the plurality of first capacitors, Some of the plurality of first capacitors accumulate charge corresponding to the residual signal during the third period. During the second period, the accumulated charge of some of the first capacitors that accumulated the residual signal during the third period of the immediately preceding sampling period may be redistributed between the first capacitors in the filter section, which includes some of the first capacitors, and the plurality of second capacitors to generate the noise shaping signal.

[0023] The aforementioned analog signal is a differential analog signal. Two digital-to-analog converters are provided to convert the differential analog signal into the differential digital signal. The differential residual signals are output from the two digital-to-analog converters. The filter unit generates the differential noise shaping signal within the second period, The DAC control unit may control the two digital-to-analog converters within the second period based on the differential residual signal and the differential noise shaping signal.

[0024] At least some of the plurality of second capacitors may have a capacitance value obtained by multiplying the reference capacitance by a value less than a multiple of 2, while the remaining second capacitors may have a capacitance value that is a multiple of 2 or a power of 2 of the reference capacitance.

[0025] The plurality of second capacitors have capacitance values ​​that are multiples of 2 with respect to the reference capacitance. Some of the aforementioned multiple second capacitors, two or more of them, may have the same capacitance value.

[0026] The filter unit may update the noise shaping signal in units of two consecutive sampling periods.

[0027] The first period may be shorter than the combined period of the second and third periods.

[0028] According to this disclosure, an analog-to-digital converter converts an analog signal to a digital signal within a sampling period including consecutive first, second, and third periods, An electronic device comprising an information processing unit that performs information processing based on the aforementioned digital signal, The aforementioned analog-to-digital converter is A digital-to-analog converter that samples the analog signal within a first period, converts the sampled signal into a digital signal bit by bit with redundancy within a second period, and outputs the unconverted residual signal. A filter unit that samples the residual signal within the third period and generates a noise-shaping signal by performing charge transfer or charge redistribution based at least within the second period on a portion of the residual signal sampled in the third period within the immediately preceding sampling period and a portion of the residual signal sampled in the third period within the sampling period two periods prior; An electronic device is provided, comprising a DAC control unit that controls the digital-to-analog converter within the second period based on the residual signal and the noise shaping signal. [Brief explanation of the drawing]

[0029] [Figure 1A] A block diagram showing the schematic configuration of an analog-to-digital converter according to the first embodiment. [Figure 1B] A diagram showing an example of a CDA without redundant features. [Figure 2] A timing diagram for the ADC in Figure 1. [Figure 3] ADC timing diagram based on the first comparative example. [Figure 4] ADC timing diagram based on the second comparative example. [Figure 5] A circuit diagram showing an example of the internal configuration of the filter section. [Figure 6] Timing diagram for the filter section. [Figure 7] A flowchart illustrating the processing operation of the ADC in Figure 1. [Figure 8] A circuit diagram showing an example of the internal configuration of the logic circuit in Figure 1. [Figure 9A] State transition diagram of the switch in the filter section according to the first embodiment. [Figure 9B] State transition diagram of the switch in the filter section according to the first embodiment. [Figure 9C] State transition diagram of the switch in the filter section according to the first embodiment. [Figure 9D] State transition diagram of the switch in the filter section according to the first embodiment. [Figure 10] A circuit diagram showing the first example of a CDA with redundant functions. [Figure 11] Figure 10 illustrates the AD conversion operation of the CDA. [Figure 12] Circuit diagram showing the internal configuration of a CDA in one comparative example. [Figure 13] Figure 12 illustrates the AD conversion operation of the CDA. [Figure 14] A circuit diagram showing a second example of a CDA with redundant functions. [Figure 15A] Figure 14 illustrates the AD conversion operation of the CDA. [Figure 15B] Figure 14 illustrates the AD conversion operation of the CDA. [Figure 16] A block diagram showing an example of connecting a chopper to an integrating amplifier. [Figure 17] A circuit diagram showing an example of the internal configuration of a chopper. [Figure 18] Figure 16 shows the timing of the chopper's operation. [Figure 19] A circuit diagram showing the internal configuration of the filter section within the ADC according to the second embodiment. [Figure 20] A timing diagram of the ADC according to the second embodiment. [Figure 21] A flowchart illustrating the processing operation of the ADC according to the second embodiment. [Figure 22A] State transition diagram of the switch in the filter section according to the second embodiment. [Figure 22B] State transition diagram of the switch in the filter section according to the second embodiment. [Figure 22C] State transition diagram of the switch in the filter section according to the second embodiment. [Figure 23] A block diagram showing the schematic configuration of the ADC according to the third embodiment. [Figure 24] ADC timing diagram in Figure 23. [Figure 25] Timing diagram based on one comparative example. [Figure 26] A circuit diagram showing an example of the internal configuration of the filter section in Figure 23. [Figure 27] Figure 23 shows the timing diagram of the filter section. [Figure 28]A flowchart illustrating the processing operation of the ADC in Figure 23. [Figure 29] A circuit diagram showing an example of the internal configuration of the logic circuit in Figure 23. [Figure 30A] A diagram showing the state transitions of the switches within the filter section according to the third embodiment. [Figure 30B] A diagram showing the state transitions of the switches within the filter section according to the third embodiment. [Figure 30C] A diagram showing the state transitions of the switches within the filter section according to the third embodiment. [Figure 30D] A diagram showing the state transitions of the switches within the filter section according to the third embodiment. [Figure 31] A block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system. [Figure 32] A diagram showing examples of installation locations for the imaging unit and the external information detection unit. [Modes for carrying out the invention]

[0030] Embodiments of the analog-to-digital converter and electronic equipment will be described below with reference to the drawings. While the main components of the analog-to-digital converter and electronic equipment will be described below, there may be components and functions not shown or described. The following description does not exclude any components or functions not shown or described.

[0031] (First Embodiment) Figure 1A is a block diagram showing the schematic configuration of an analog-to-digital converter (hereinafter referred to as ADC) 1 according to the first embodiment. For simplification, Figure 1A shows a fully differential circuit in a single-ended configuration. The ADC 1 in Figure 1A repeatedly performs the process of converting an analog signal to a digital signal within a sampling period that includes consecutive first, second, and third periods, over multiple sampling periods. The first period is the sampling period of the input analog signal, the second period is the AD conversion period of the sampled analog signal, and the third period is the sampling period of the residual signal after bit-by-bit AD conversion.

[0032] The ADC1 in Figure 1A comprises a sample switch 2, a capacitive DA converter (hereinafter sometimes referred to as CDA) 3, a comparator 4, a logic circuit 5, a decoder 6, a filter section (hereinafter sometimes referred to as L(z)) 7, and a filter switch 8.

[0033] Sample switch 2 is turned on or off by the sample clock signal SAMPLE_CLK. For example, when the sample clock signal SAMPLE_CLK is high, sample switch 2 turns on, and an external analog signal is input to CDAC3.

[0034] The CDAC3 samples the analog signal during the first period, and during the second period, it sequentially converts the sampled signal into a digital signal bit by bit with redundancy, while also outputting the unconverted residual signal. The first period is when the sample switch 2 is turned on and an analog signal is input to the CDAC3 from an external source. The sample switch 2 is turned on during the first period and turned off during the second and third periods.

[0035] Figure 1B shows an example of a CDAC3 without redundancy. Figure 1B also shows an example of a fully differential ADC1. In a fully differential ADC1, the differentially input analog signal (hereinafter also called a differential input signal) is converted bit by bit from the most significant bit by the corresponding CDAC3 for each signal constituting the differential input signal. The unconverted residual signal from each CDAC is input to a comparator 4, and the logic circuit 5 controls the AD conversion of the next bit of each CDAC3 based on the comparison judgment signal of the comparator 4. As a result, AD conversion is performed so that the output signal of the comparator 4 approaches zero.

[0036] The CDAC3 in Figure 1B has five capacitors C1 to C5 with capacitance values ​​that differ by powers of 2 or multiples of 2, and three switches SW11 to SW13 connected to each of the capacitors C1 to C5. In this specification, capacitors C1 to C5 in the CDAC3 are sometimes collectively referred to as the second capacitor. Note that the filter section 7 is omitted in Figure 1B.

[0037] One end of each capacitor C1 to C5 is connected to the input terminals of sample switch 2 and comparator 4. Switch SW11 toggles whether to set one end of capacitor C1 to C5 to 0V. Switch SW12 toggles whether to set the other end of capacitor C1 to C5 to the common voltage Vcom. Switch SW13 toggles whether to set one end of capacitor C1 to C5 to the reference voltage Vref. The common voltage Vcom is, for example, half the voltage level of the reference voltage Vref.

[0038] Switches SW11 to SW13 are switched on or off based on control signals from logic circuit 5. Logic circuit 5 turns on switch SW12 during the sampling period (first period). During the AD conversion period (second period), logic circuit 5 turns on switch SW11 if it wants to lower the output voltage of CDAC3, and turns on switch SW13 if it wants to raise the output voltage of CDAC3.

[0039] The filter unit 7 in Figure 1 samples the residual signal within the third period and generates a noise-shaping signal by performing charge transfer or charge redistribution based on a portion of the residual signal sampled in the third period of the immediately preceding sampling period and a portion of the residual signal sampled in the third period of the sampling period two periods prior, at least within the second period. Various modifications are possible for the internal configuration of the filter unit 7, and some representative examples will be described later.

[0040] Comparator 4 receives the residual signal output from CDAC3 and the noise shaping signal output from filter section 7. In this embodiment, ADC1 is configured as a fully differential circuit as shown in Figure 1B, and comparator 4 actually receives the differential residual signal and the differential noise shaping signal. Comparator 4 outputs a signal corresponding to the sum of the signal difference of the differential residual signal and the signal difference of the differential noise shaping signal.

[0041] Logic circuit 5 provides feedback control to CDA3 so that the sum of the signal difference of the differential residual signal input to comparator 4 and the signal difference of the differential noise shaping signal approaches zero. Logic circuit 5 also supplies a control signal EN_COMP to comparator 4, which controls the timing of comparator 4's comparison operation. Comparator 4 performs the comparison operation, for example, when the control signal EN_COMP is high. Since comparator 4 stops the comparison operation when the control signal EN_COMP is low, power consumption can be reduced.

[0042] In this specification, the comparator 4 and the logic circuit 5 together may be referred to as the DAC control unit 9. The DAC control unit 9 controls the CDAC 3 within a second period based on the residual signal and the noise shaping signal.

[0043] Figure 2 is a timing diagram of ADC1 in Figure 1, showing the timing of each signal within one sampling period. In Figure 2, times t1 to t2 represent the sampling period of the analog signal (first period). Times t2 to t3 represent the AD conversion period of the sampled analog signal (second period). Times t3 to t4 represent the sampling period of the residual voltage by the filter section 7 (third period). Times t1 to t4 constitute one sampling period, and the sampling period of times t1 to t4 is repeated. In Figure 2, the ratio of the length of the first period (times t1 to t2) to the lengths of the second and third periods (times t2 to t4) is set to, for example, 1:2. This ensures a third period of sufficient length to sample the residual signal. It is desirable to optimize the ratio for each use case depending on the buffer capability of the preceding block of ADC1, the judgment result of the comparator 4 in ADC1, the feedback speed of CDAC3, etc. Therefore, the above ratio is not limited to 1:2.

[0044] Figure 2 illustrates the timing of the sample clock signal SAMPLE_CLK, the control signal EN_COMP, the control signal CONV_END, and the output signal of the integrating amplifier 12 in the filter section 7, which will be described later, for one sampling period.

[0045] As will be described later, the filter unit 7 according to this embodiment has a group of capacitors and an integrating amplifier 12 inside it, and during the third period from time t3 to t4, the residual signal of the CDAC3 is sampled by some of the capacitors in the filter unit 7. In this specification, the group of capacitors in the filter unit 7 may be referred to as a plurality of first capacitors. Some of the first capacitors in the filter unit 7 accumulate charge corresponding to the residual signal of the CDAC3 during the third period.

[0046] Furthermore, during the first and second periods from time t1 to t3, the filter unit 7 generates a noise-shaping signal by transferring charge from a portion of the residual signal sampled in the third period of the immediately preceding sampling period and a portion of the residual signal sampled in the third period of the sampling period two periods prior to the current one to the integrating amplifier 12.

[0047] In this specification, the transfer of charge from a portion of the first capacitor in the filter section 7 to the integrating amplifier 12 is sometimes referred to as total charge transfer.

[0048] The filter switch 8 in Figure 1 is turned on or off by the control signal CONV_END. For example, the filter switch 8 is turned on when the control signal CONV_END is high, and turned off when the control signal CONV_END is low. When the filter switch 8 is turned on, the residual signal is input to the filter unit 7. Since the control signal CONV_END is turned on in the third period, the filter unit 7 samples the residual signal in the third period.

[0049] Thus, in this embodiment, the entire charge transfer within the filter section 7 is performed using both the first and second periods. Therefore, sufficient time is available for the entire charge transfer, and the problem of the entire charge transfer being interrupted midway is eliminated.

[0050] The second period from time t2 to t3 is the AD conversion period of the sampled analog signal, where the AD conversion is performed bit by bit from the most significant bit, and the residual signal changes over time. Also, during the second period, total charge transfer occurs inside the filter section 7, so the noise shaping signal output from the integrating amplifier 12 in the filter section 7 also changes over time. Figure 2 shows the change in the output signal of the integrating amplifier 12 in the filter section over time from time t2 to t3 as a solid waveform. As a result, the comparison judgment result of the comparator 4 also fluctuates, and there is a risk that the CDAC3 will make an incorrect switch selection.

[0051] Therefore, in this embodiment, as will be described later, the CDAC3 is provided with redundancy, so that even if an error occurs in the control of the CDAC3 by the logic circuit 5 due to the noise shaping signal changing over time, the redundancy of the CDAC3 can correct the error correctly. The redundancy of the CDAC3 will be described later.

[0052] Figure 3 is a timing diagram of ADC1 according to the first comparative example. In Figure 3, the length of the first period from time t1 to t2 and the lengths of the second and third periods from time t2 to t4 are set to approximately 1:1. In this case, the first period from time t1 to t2 can be made longer than in Figure 2, so sufficient time can be secured for the total charge transfer to the integrating amplifier 12 in the filter section 7. Moreover, since the total charge transfer is performed during the sampling period of the input signal and not during the AD conversion period, the comparison judgment of the comparator 4 is not affected by the total charge transfer in the filter section 7, and the possibility of CDAC3 making an incorrect switch selection is reduced.

[0053] However, as a result, the period from time t2 to t4 is shorter than in Figure 2. Therefore, if the AD conversion process from time t2 to t3 takes a long time due to temperature conditions, skew conditions, etc., the sampling of the residual signal by the filter unit 7 during the third period from time t3 to t4 may be incomplete. Incomplete sampling of the residual signal may result in poor AD conversion accuracy and SNDR.

[0054] Figure 4 is a timing diagram of ADC1 according to the second comparative example. In Figure 4, the ratio of the length of the period from time t1 to t2 to the length of the period from time t2 to t4 is set to 1:2, similar to Figure 2. Therefore, even if the AD conversion processing from time t2 to t3 takes time, the sampling of the residual signal by the filter section 7, which is performed in the third period from time t3 to t4, can be performed correctly. On the other hand, in Figure 4, it is necessary to transfer the entire charge to the integrating amplifier 12 in the filter section 7 within the sampling period from time t1 to t2. Therefore, the entire charge transfer may not be completed by time t2, resulting in insufficient transfer and preventing proper noise shaping.

[0055] In contrast, in this embodiment, as shown in Figure 2, the entire charge transfer to the integrating amplifier 12 is performed between times t1 and t3 (first period + second period), so that a sufficient period for the entire charge transfer can be secured, and the noise-shaping signal can be output after the entire charge transfer has been performed correctly.

[0056] Figure 5 is a circuit diagram showing an example of the internal configuration of the filter unit 7. The filter unit 7 in Figure 5 includes a buffer 11, a plurality of first capacitors CA, CB1, CB2, a plurality of switches (first selectors) SW1 to SW6, and an integrating amplifier 12. Since the filter unit 7 in Figure 5 has an integrating amplifier 12, it is an active type filter unit 7.

[0057] Buffer 11 has differential input terminals and differential output terminals. The differential residual signal output from CDAC3 is input to the differential input terminals, and after being buffered, the differential residual signal is output from the differential output terminals.

[0058] The filter section 7 has a capacitor group 7g consisting of three capacitors CA, CB1, and CB2, and six switches SW1 to SW6 for each signal constituting the differential signal. Since the capacitance values ​​of the three capacitors CA, CB1, and CB2 and the switching timing of switches SW1 to SW6 are symmetrical, the same symbols are used in Figure 5 for the symmetrical capacitors CA, CB1, CB2, and CC and switches SW1 to SW6. Switches SW1 to SW6 are switched by switch control signals φ1 to φ6. The integrating amplifier 12 has a differential amplifier 12a with differential input and differential output, and two capacitors CC connected between the differential input terminal and differential output terminal of the differential amplifier 12a.

[0059] Switch SW1 switches whether or not to sample one of the signals constituting the differential signal into capacitor CA. Switch SW2 switches whether or not to sample one of the signals constituting the differential signal into capacitor CB1. Switch SW3 switches whether or not to sample one of the signals constituting the differential signal into capacitor CB2. Switch SW4 switches whether or not to transfer the stored charge of capacitor CA to capacitor CC. Switch SW5 switches whether or not to transfer the stored charge of capacitor CB1 to capacitor CC. Switch SW6 switches whether or not to transfer the stored charge of capacitor CB2 to capacitor CC.

[0060] The capacitance values ​​of capacitors CA, CB1, CB2, and CC are, for example, CA = CC = 3CB1 = 3CB2.

[0061] Figure 6 is a timing diagram of the filter section 7. The switching period of switches SW1 to SW6 within the filter section 7 corresponds to the 2-sampling period of ADC1. Therefore, Figure 6 illustrates the 2-sampling period of ADC1.

[0062] The periods t1-t2 and t4-t5 represent the first period (analog signal sampling period), t2-t3 and t5-t6 represent the second period (AD conversion period), and t3-t4 and t6-t7 represent the third period (residual signal sampling period). In the following, we will refer to the period t1-t4 as the first sampling period and the period t4-t7 as the second sampling period.

[0063] Figure 6 illustrates the timing of the sample clock signal SAMPLE_CLK, the control signals EN_COMP and CONV_END, and the switch control signals φ1 to φ6 for two sampling periods. Figure 6 also illustrates the switching states of switches SW1 to SW6 within the filter section 7. For simplification, Figure 6 only shows the three capacitors CA, CB1, and CB2 connected to one of the signals constituting the differential signal within the filter section 7, the switches SW1 to SW6, and one of the capacitors CC of the integrating amplifier 12.

[0064] During times t1 to t3 (the first and second periods) within the first sampling period, switches SW4 and SW5 in the filter section 7 are turned on, while the other switches SW1 to SW3 and SW6 are turned off. As a result, the accumulated charge of capacitors CA and CB1 is fully transferred to capacitor CC of the integrating amplifier 12. The accumulated charge of capacitor CA is a portion of the residual signal sampled in the sampling period immediately preceding the first sampling period, and the accumulated charge of capacitor CB1 is a portion of the residual signal sampled in the sampling period two periods prior to the first sampling period.

[0065] In this way, the entire charge transfer from capacitors CA and CB1 to capacitor CC in the filter section 7 is performed not only during the sampling period of the analog signal at time t1 to t2, but also during the subsequent AD conversion period at time t2 to t3, thus ensuring sufficient time for the entire charge transfer.

[0066] Between times t3 and t4, the control signal CONV_END goes high, switches SW1 and SW2 in the filter section 7 are turned on, and the other switches SW3 to SW6 are turned off. As a result, the residual signal output from CDA3 is sampled by capacitors CA and CB1 in the filter section 7.

[0067] During the time intervals t4 to t6 (first and second periods) within the second sampling period, switches SW4 and SW6 in the filter section 7 are turned on, while the other switches SW1 to SW3 and SW5 are turned off. As a result, the accumulated charge of capacitors CA and CB2 is fully transferred to capacitor CC of the integrating amplifier 12. The accumulated charge of capacitor CA is a portion of the residual signal sampled in the first sampling period immediately preceding the second sampling period, and the accumulated charge of capacitor CB2 is a portion of the residual signal sampled in the sampling period two periods prior to the second sampling period.

[0068] Thus, when transferring the accumulated charge from capacitors CA and CB2 in the filter section 7 to capacitor CC during the second sampling period, both the first and second periods are utilized, ensuring sufficient time for the total charge transfer.

[0069] Between times t6 and t7, the control signal CONV_END goes high, switches SW1 and SW3 in the filter section 7 are turned on, and the other switches SW2, SW4 to SW6 are turned off. As a result, the residual signal output from CDA3 is sampled by capacitors CA and CB2 in the filter section 7.

[0070] Thus, capacitor CA in the filter section 7 accumulates and transfers charge with each sampling period, while capacitors CB1 and CB2 alternately accumulate and transfer charge with each sampling period. By controlling the charge and discharge of capacitors CA, CB1, and CB2 in this way, a noise-shaping signal can be generated in the filter section 7, and by controlling the CDAC3 using the generated noise-shaping signal, the AD conversion accuracy and SNDR can be improved.

[0071] The ratio of the length of time t1~t2 (first period) to the length of time t2~t4 (second and third periods) is, for example, 1:2. Since the sampling period for the residual signal from time t3~t4 is also sufficiently long, a sufficient sampling period for the residual signal can be secured.

[0072] Figure 7 is a flowchart showing the processing operation of ADC1 in Figure 1, and, similar to the timing diagram in Figure 6, it shows the processing operation with two sampling periods. First, the variable n is initialized to zero, and the analog signal input from the outside is sampled (step S1). Step S1 shows the operation at times t1 to t2 (first period) in Figure 6. The variable n is a variable that counts the number of times the comparator 4 performs a comparison judgment.

[0073] Next, the AD conversion operation is performed based on the comparison judgment of the comparator 4 (step S2). Steps S2 to S4 show the operation at times t2 to t3 (second period) in Figure 6. Next, the variable n is incremented by 1 (step S3). Next, it is determined whether the variable n has reached the number of bits N of the physical resolution of the ADC1 (step S4). If the variable n has not reached N, the process returns to step S2. While the processing of steps S1 to S4 is being performed, the charges of capacitors CA and CB1 in the filter section 7 are all transferred to capacitor CC of the integrating amplifier 12.

[0074] If it is determined in step S4 that the variable n has reached N, the residual signal output from CDAC3 is sampled into capacitors CA and CB1 in the filter section 7 (step S5). Step S5 shows the operation at times t3 to t4 (third period) in Figure 6.

[0075] Steps S1 to S5 described above are performed during the first sampling period, from time t1 to t4 in Figure 6. Subsequently, in the second sampling period, the variable n is initialized to zero, similar to step S1, and the externally input analog signal is sampled (step S6). Step S6 shows the operation from time t4 to t5 (first period) in Figure 6.

[0076] Next, the AD conversion operation is performed based on the comparison judgment of the comparator 4 (step S7). Steps S7 to S9 show the operation at time t5 to t6 (second period) in Figure 6. Next, the variable n is incremented by 1 (step S8). Next, it is determined whether the variable n has reached the number of bits N of the physical resolution of the ADC1 (step S9). If the variable n has not reached N, the process returns to step S2. While the processing in steps S6 to S9 is being performed, the charges of capacitors CA and CB2 in the filter section 7 are all transferred to capacitor CC of the integrating amplifier 12.

[0077] If it is determined in step S9 that the variable n has reached N, the residual signal output from CDAC3 is sampled into capacitors CA and CB2 in the filter section 7 (step S10). Step S10 shows the operation at times t6 to t7 (third period) in Figure 6.

[0078] Figure 8 is a circuit diagram showing an example of the internal configuration of the logic circuit 5 in Figure 1. The logic circuit 5 in Figure 8 includes a NOR gate 21, a shift register 22, inverters 23 and 24, AND gates 25 and 26, and pulse generation circuits 27 and 28.

[0079] The NOR gate 21 performs a NOR operation on the differential output signals of the comparator 4. When both differential output signals of the comparator 4 are at a low level, the output of the NOR gate 21 becomes high level. The shift register 22 is configured by cascading multiple flip-flops (hereinafter referred to as F / F), and the output signal of the NOR gate 21 is supplied to the clock terminal of each F / F. As a result, each time the output signal of the NOR gate 21 changes from a low level to a high level, each F / F in the shift register 22 sequentially propagates the high-level signal. The number of F / F stages in the shift register 22 is the number of bits of the physical resolution of the ADC1. The output signal of the final stage F / F is used as the control signal CONV_END. As shown in Figure 6, the control signal CONV_END becomes high level during the third period in which the residual signal is sampled. The control signal CONV_END is used to turn the filter switch 8 on or off. The filter switch 8 is turned on when the control signal CONV_END is high level. When the filter switch 8 is turned on, the filter section 7 takes the differential residual signal output from the CDA3 into the buffer 11 and samples it with capacitor CA and capacitor CB1 or CB2.

[0080] The AND gate 25 outputs a logical AND signal of the signal obtained by inverting the control signal CONV_END using the inverter 23 and the output signal of the NOR gate 21. The output signal of the AND gate 25 temporarily becomes high whenever the output signal of the comparator 4 becomes low during the second period. The output signal of the AND gate 25 is input to the control terminal of the comparator 4. As a result, the comparator 4 performs the comparison judgment operation only when the output signal of the AND gate 25 is high. With this control, the comparator 4 performs the comparison judgment only when the CDAC 3 performs AD conversion bit by bit.

[0081] The pulse generation circuit 27 generates switch control signals φ1 to φ3 based on the sample clock signal SAMPLE_CLK and the output signal of the AND gate 26. The AND gate 26 outputs a logical AND signal of the sample clock signal SAMPLE_CLK inverted by the inverter 24 and the control signal CONV_END. The pulse generation circuit 28 generates switch control signals φ4 to φ6 based on the sample clock signal SAMPLE_CLK and the control signal CONV_END.

[0082] Figures 9A, 9B, 9C, and 9D are state transition diagrams of switches SW1 to SW6 within the filter section 7.

[0083] As shown in Figure 9A, the switch control signal φ1 transitions from a low level to a high level when the sample clock signal SAMPLE_CLK is low and the control signal CONV_END is high, and the switch SW1 transitions from off to on. Subsequently, when the sample clock signal SAMPLE_CLK becomes high or the control signal CONV_END becomes low, the switch control signal φ1 transitions from a high level to a low level, and the switch SW1 transitions from on to off.

[0084] As shown in Figure 9B, when the sample clock signal SAMPLE_CLK is low and the control signal CONV_END is high, the switch control signal φ2 transitions from low to high, while the switch control signal φ3 remains low. Therefore, switch SW2 transitions from low to high, and switch SW3 remains off. Subsequently, when the sample clock signal SAMPLE_CLK becomes high or the control signal CONV_END becomes low, the switch control signal φ2 transitions from high to low, while the switch control signal φ3 remains low. Therefore, switch SW2 transitions from high to low, and switch SW3 remains off. Subsequently, when the sample clock signal SAMPLE_CLK becomes low and the control signal CONV_END becomes high, the switch control signal φ2 remains low, while the switch control signal φ3 transitions from low to high. Therefore, switch SW2 remains off, and switch SW3 transitions from off to on. Subsequently, when the sample clock signal SAMPLE_CLK becomes high level or the control signal CONV_END becomes low level, the switch control signal φ2 remains low level, and the switch control signal φ3 transitions from high level to low level. Therefore, switch SW2 remains off, and switch SW3 transitions from on to off.

[0085] As shown in Figure 9C, when the sample clock signal SAMPLE_CLK is at a high level or the control signal CONV_END is at a low level, the switch control signal φ4 transitions from a low level to a high level, and the switch SW4 transitions from off to on. Subsequently, when the sample clock signal SAMPLE_CLK is at a low level and the control signal CONV_END is at a high level, the switch control signal φ4 transitions from a high level to a low level, and the switch SW4 transitions from on to off.

[0086] As shown in Figure 9D, when the sample clock signal SAMPLE_CLK is high or the control signal CONV_END is low, the switch control signal φ5 remains low, and the switch control signal φ6 transitions from low to high. Therefore, switch SW5 remains off, and switch SW6 transitions from off to on. Subsequently, when the sample clock signal SAMPLE_CLK is low and the control signal CONV_END is high, the switch control signal φ5 remains low, and the switch control signal φ6 transitions from high to low. Therefore, switch SW5 remains off, and switch SW6 transitions from on to off. Subsequently, when the sample clock signal SAMPLE_CLK is high or the control signal CONV_END is low, the switch control signal φ5 transitions from low to high, and the switch control signal φ6 remains low. Therefore, switch SW5 transitions from off to on, and switch SW6 remains off. Subsequently, when the sample clock signal SAMPLE_CLK is at a low level and the control signal CONV_END is at a high level, the switch control signal φ5 transitions from a high level to a low level, while the switch control signal φ6 remains at a low level. Therefore, switch SW5 transitions from a high level to a low level, and switch SW6 remains off.

[0087] As explained in Figure 2, the ADC1 according to this embodiment utilizes not only the sampling period of the analog signal (first period) but also the AD conversion period (second period) to perform the total charge transfer from the capacitor group 7g in the filter section 7 to the integrating amplifier 12. Therefore, during AD conversion, the noise shaping signal output from the filter section 7 and input to the comparator 4 changes, which may cause errors in AD conversion. To address this, the CDAC3 according to this embodiment has a redundant function that can correct errors even if they occur in AD conversion. By having a redundant function, the CDAC3 can perform AD conversion with redundancy, and even if an error occurs during AD conversion, it can automatically correct that error.

[0088] Figure 10 is a circuit diagram showing a first example of a CDAC3 with redundant functionality. The CDAC3 in Figure 10 has a group of capacitors 10a consisting of multiple capacitors (sometimes referred to as second capacitors in this specification) with different capacitance values, and a group of switches 10b. Although the capacitance values ​​of the multiple second capacitors are different, at least some of the second capacitors have capacitance values ​​that are multiples of 2 or powers of 2 of the reference capacitance value, while the remaining second capacitors have capacitance values ​​that are less than multiples of 2 of the reference capacitance value. In the example in Figure 10, three of the six capacitors have capacitance values ​​of 1C, 2C, and 4C, with the reference capacitance value being C, while the remaining three capacitors have capacitance values ​​of 7C, 12C, and 23C. The ratio of the number of second capacitors with capacitance values ​​that are multiples of 2 or powers of 2 to the number of second capacitors with capacitance values ​​that are less than multiples of 2 is arbitrary.

[0089] Figure 11 illustrates the AD conversion operation of the CDA3 shown in Figure 10. When the most significant bit of the CDA3 is set to zero for an analog input signal, the output signal level LV1 of the CDA3 becomes lower than the analog input signal level. Therefore, 1 is selected for the second most significant bit, and the output signal level LV2 of the CDA3 becomes higher than the analog input signal level. Therefore, 0 is selected for the third most significant bit, and the output signal level LV3 of the CDA becomes lower than the analog input signal level. Therefore, 1 should be selected for the fourth most significant bit, but let's assume that 0 is mistakenly selected. In this case, the output signal level LV4 of the CDA3 will be a voltage level lower than the output signal level LV3.

[0090] However, since the capacitance value of the capacitor corresponding to the higher bits of CDAC3 is obtained by multiplying the reference capacitance value by a value less than a multiple of 2, even if an error occurs in the AD conversion midway, the error can be gradually reduced by repeating the correct AD conversion afterward. Ultimately, as shown in Figure 11, the correct digital value is obtained, and the residual signal also becomes small.

[0091] Figure 12 is a circuit diagram showing the internal configuration of a CDAC3 in one comparative example. The multiple capacitors in the CDAC3 in Figure 12 have capacitance values ​​that are powers of two times the reference capacitance value.

[0092] Figure 13 illustrates the AD conversion operation of the CDAC3 shown in Figure 12. Similar to Figure 11, Figure 13 shows an example where the AD conversion operation is incorrect at the 4th bit from the most significant bit. In this case, even if the correct AD conversion is performed from the 5th bit onward, the final digital signal will be more than 0.5 LSB away from the AD conversion value of the original analog input signal, and the residual signal will also be large.

[0093] As shown in Figures 10 to 13, by setting the capacitance values ​​of at least some of the capacitors in the CDAC3 to values ​​that are less than a multiple of 2 of the reference capacitance value, even if the CDAC3 makes an error in the AD conversion process, the AD conversion is performed in finer units than usual, gradually reducing the error and ultimately reducing the error in the resulting digital signal.

[0094] Figure 14 is a circuit diagram showing a second example of a CDAC3 with redundant functionality. The CDAC3 in Figure 14 has multiple capacitors C0 to C11, each of which has a capacitance value that is a power of two of the reference capacitance value C0. Among the multiple capacitors C0 to C11 are multiple capacitors C1, C1R and capacitors C6, C6R, all of the same capacitance value. Specifically, in the example in Figure 14, there are two capacitors C1 and C1R with a capacitance value of 2C0, and two capacitors C6 and C6R with a capacitance value of 64C0. Note that in Figure 14, the switches connected to the multiple capacitors are omitted, but in reality, switches similar to those in Figure 10 are connected to each capacitor.

[0095] Figures 15A and 15B illustrate the AD conversion operation of the CDAC3 in Figure 14. Figure 15A shows the AD conversion operation by capacitors C4 to C8 within the dashed box in Figure 14. Before performing AD conversion on the bit corresponding to capacitor C8 in Figure 14, the intermediate voltage level of the output signal VR1 of the CDAC3 is lower than the analog input signal level. Therefore, the bit corresponding to capacitor C8 becomes 1, and the intermediate voltage level of the output signal VR2 of the CDAC3 becomes higher than the analog input signal level. For this reason, the bit corresponding to capacitor C7 should normally be 0, but let's assume it is mistakenly set to 1. In this case, the intermediate voltage level of the output signal VR3 of the CDAC3 becomes higher than the analog input signal level. Therefore, the bit corresponding to capacitor C6 becomes 0. As a result, the intermediate voltage level of the output signal VR4 of the CDAC3 becomes higher than the analog input signal level. Therefore, the bit corresponding to capacitor C6R becomes 0. As a result, the intermediate voltage level of the output signal VR5 of the CDAC3 becomes lower than the analog input signal level. Therefore, the bit corresponding to capacitor C5 becomes 1. As a result, the intermediate voltage level of the output signal VR6 of the CDAC3 becomes higher than the analog input signal level. Therefore, the bit corresponding to capacitor C4 becomes 0.

[0096] Thus, even if the AD conversion operation is incorrect in some bits of the CDA3, the error can be corrected by providing multiple capacitors with the same capacitance value, and the accuracy of the final digital value can be maintained.

[0097] Figure 15B illustrates the AD conversion operation when the analog input signal level is lower than in Figure 15A. Before performing AD conversion on the bit corresponding to capacitor C8 in Figure 15, the intermediate voltage level of the output signal VR1 of the CDAC3 is higher than the analog input signal level. Therefore, the bit corresponding to capacitor C8 becomes 0, and the intermediate voltage level of the output signal VR2 of the CDAC3 becomes lower than the analog input signal level. For this reason, the bit corresponding to capacitor C7 should normally be 1, but let's assume it is incorrectly set to 0. In this case, the intermediate voltage level of the output signal VR3 of the CDAC3 becomes lower than the analog input signal level. Therefore, the bit corresponding to capacitor C6 becomes 1. As a result, the intermediate voltage level of the output signal VR4 of the CDAC3 becomes lower than the analog input signal level. Therefore, the bit corresponding to capacitor C6R becomes 1. As a result, the intermediate voltage level of the output signal VR5 of the CDAC3 becomes higher than the analog input signal level. Therefore, the bit corresponding to capacitor C5 becomes 0. As a result, the intermediate voltage level of the output signal VR6 of the CDAC3 becomes lower than the analog input signal level. Therefore, the bit corresponding to capacitor C4 becomes 1. As shown in Figures 15A and 15B, even if some bits in the CDAC3 are mis-AD converted, regardless of the analog input signal level, the error can be corrected by providing multiple capacitors with the same capacitance value.

[0098] As described above, the ADC1 according to this embodiment is intended to be a fully differential SAR ADC1 that converts differential analog signals to digital signals and outputs differential digital signals. To reduce the low-frequency noise of the fully differential SAR ADC1, it is desirable to implement a chopper. A chopper is a device that connects a group of switches to the differential input terminals and differential output terminals of an amplifier with differential input and differential output, and periodically switches between a through mode, which allows differential input and differential output signals to pass through, and a cross mode, which crosses the differential input and differential output signals, respectively. In the second mode, the differential input and differential output sides cross the differential signals in sync, so no problems occur in signal transmission.

[0099] Figure 16 is a block diagram showing an example in which choppers 31 and 32 are connected to at least one of the differential input terminals and differential output terminals of the buffer 11 and integrating amplifier 12 in the filter section 7, respectively. The left side of Figure 16 schematically shows the signal transmission path in through mode, and the right side shows the signal transmission path in cross mode.

[0100] Figure 17 is a circuit diagram showing an example of the internal configuration of choppers 31 and 32. Choppers 31 and 32 in Figure 17 have four switches SW16 to SW19 located between the differential input terminals TL1 and TL2 and the differential output terminals TL3 and TL4. Switch SW16 switches whether or not to short-circuit terminals TL1 and TL3. Switch SW17 switches whether or not to short-circuit terminals TL3 and TL4. Switch SW18 switches whether or not to short-circuit terminals TL1 and TL4. Switch SW19 switches whether or not to short-circuit terminals TL2 and TL3.

[0101] Figure 18 is a timing diagram of the operation of choppers 31 and 32 in Figure 16. As shown in the figure, the choppers alternately switch between through mode and cross mode. During through mode, switches SW16 and SW17 in Figure 17 are ON, and switches SW18 and SW19 are OFF. During cross mode, switches SW16 and SW17 in Figure 17 are OFF, and switches SW18 and SW19 are ON. It is desirable that the duration of through mode and cross mode be equal.

[0102] By providing choppers 31 and 32, the low-frequency noise of the SAR ADC1 can be shifted to the high-frequency side, resulting in a reduction of flicker noise.

[0103] Thus, in the SAR ADC1 according to the first embodiment, a noise-shaping signal is generated by transferring the entire charge from the capacitor group 7g in the filter section 7 to the integrating amplifier 12 using the period for sampling the analog signal and the period for performing AD conversion of the sampled analog signal. This ensures sufficient time for performing the entire charge transfer. If the entire charge transfer to the integrating amplifier 12 is performed in the filter section 7 during the AD conversion period, the output signal of the integrating amplifier 12 in the filter section 7 may fluctuate during the AD conversion, potentially causing errors in the AD conversion by the CDAC3. To address this, the CDAC3 according to this embodiment has a redundant function, so even if an error occurs in the AD conversion operation, the error can be corrected by performing redundant AD conversion within the CDAC3, thereby maintaining the accuracy of the final digital signal.

[0104] (Second embodiment) The ADC1 according to the first embodiment includes an active filter section 7 having an integrating amplifier 12, but it is also possible to configure the ADC1 using a passive filter section 7a that does not have an integrating amplifier 12.

[0105] The ADC1a according to the second embodiment has the same configuration as the ADC1 in Figure 1, but the internal configuration of the filter section 7a is different from the filter section 7 in the ADC1 in Figure 1.

[0106] Figure 19 is a circuit diagram showing the internal configuration of the filter section 7a in the ADC1a according to the second embodiment. The filter section 7a in Figure 19 has capacitors CA, CB1, CB2, and CC, and switches SW21 to SW24, for each signal constituting the differential signal, downstream of the buffer 11 for differential input and differential output. Switches SW21 and SW22 are connected in series between the output node of the buffer 11 and the output node of the filter section 7. Capacitor CA is connected between the common connection node and the ground node of switches SW21 and SW24. Switch SW23 and capacitor CB1 are connected in series between the common connection node and the ground node of switches SW21 and SW22. Switch SW24 and capacitor CB2 are connected in series between the common connection node and the ground node of switches SW21 and SW22. Capacitor CC is connected between the output node and the ground node of the filter section 7.

[0107] Figure 20 is a timing diagram of ADC1a according to the second embodiment. The switching period of switches SW1 to SW6 in the filter section 7a in Figure 19 corresponds to the two sampling periods of ADC1a (first sampling period and second sampling period), similar to Figure 6.

[0108] During the time intervals t1 to t3 (first period + second period) within the first sampling period, switches SW22 and SW23 in the filter section 7a are turned on, while the other switches are turned off. Therefore, the accumulated charge in capacitors CA and CB1 is redistributed among capacitors CA, CB1, and CC. Performing charge redistribution during the AD conversion period (second period) may cause fluctuations in the noise shaping signal output from the filter section 7a, potentially leading to incorrect capacitor selection within CDAC3. However, as explained in Figures 10 to 15B, providing redundancy in CDAC3 prevents a decrease in AD conversion accuracy.

[0109] During the time interval t3 to t4 (third period) within the first sampling period, switches SW21 and SW23 in the filter section 7a are turned on, and the other switches are turned off. Therefore, the residual signal output from CDAC3 is sampled by capacitors CA and CB1 in the filter section 7a.

[0110] During the time interval t4 to t6 (first period + second period) within the second sampling period, switches SW22 and SW24 in the filter section 7a are turned on, while the other switches are turned off. Therefore, the accumulated charge in capacitors CA and CB2 is redistributed among capacitors CA, CB2, and CC.

[0111] During the second switching cycle, at times t6 to t7 (third period), switches SW21 and SW24 in the filter section 7a are turned on, while the other switches are turned off. Therefore, the residual signal output from CDAC3 is sampled by capacitors CA and CB2 in the filter section 7a.

[0112] Thus, capacitor CA in the filter section 7a is used for sampling the residual signal at each sampling period, while capacitors CB1 and CB2 are used alternately for sampling at each sampling period. Capacitor CC is used for charge redistribution at each sampling period.

[0113] Figure 21 is a flowchart showing the processing operation of ADC1a according to the second embodiment, and, similar to the timing diagram in Figure 20, it shows the processing operation with two sampling periods. First, the variable n is initialized to zero, and the analog signal input from the outside is sampled (step S11). Step S11 shows the operation at times t1 to t2 (first period) in Figure 20. The variable n is a variable that counts the number of times the comparator 4 performs a comparison judgment.

[0114] Next, the AD conversion operation is performed based on the comparison judgment of the comparator 4 (step S12). Steps S12 to S14 show the operation at times t2 to t3 (second period) in Figure 20. Next, the variable n is incremented by 1 (step S13). Next, it is determined whether the variable n has reached the number of bits N of the physical resolution of the ADC1a (step S14). If the variable n has not reached N, the process returns to step S12. While the processing in steps S11 to S14 is being performed, the charge of capacitors CA and CB1 in the filter section 7a is redistributed among capacitors CA, CB1, and CC.

[0115] If it is determined in step S14 that the variable n has reached N, the residual signal output from CDAC3 is sampled into capacitors CA and CB1 in the filter section 7a (step S15). Step S15 shows the operation at times t3 to t4 (third period) in Figure 20.

[0116] Steps S11 to S15 described above are performed during the first sampling period from time t1 to t4 in Figure 20. Subsequently, when the second sampling period begins, the variable n is initialized to zero, similar to step S11, and the externally input analog signal is sampled (step S16). Step S16 shows the operation from time t4 to t5 (first period) in Figure 20.

[0117] Next, the AD conversion operation is performed based on the comparison judgment of the comparator 4 (step S17). Steps S17 to S9 show the operation at time t5 to t6 (second period) in Figure 20. Next, the variable n is incremented by 1 (step S18). Next, it is determined whether the variable n has reached the number of bits N of the physical resolution of the ADC1a (step S19). If the variable n has not reached N, the process returns to step S12. While the processing in steps S16 to S19 is being performed, the charge of capacitors CA and CB2 in the filter section 7a is redistributed among capacitors CA, CB2, and CC.

[0118] If it is determined in step S19 that the variable n has reached N, the residual signal output from CDAC3 is sampled into capacitors CA and CB2 in the filter section 7a (step S20). Step S20 shows the operation at times t6 to t7 (third period) in Figure 20.

[0119] The logic circuit 5 according to the second embodiment has the same internal configuration as in Figure 8, but the pulse generation circuits 27 and 28 within the logic circuit 5 output switch control signals φ1 to φ6 with different timings than the pulse generation circuits 27 and 28 in Figure 8.

[0120] Figures 22A, 22B, and 22C show the state transitions of switches SW1 to SW6 within the filter section 7a.

[0121] As shown in Figure 22A, the switch control signal φ1 transitions from a low level to a high level when the sample clock signal SAMPLE_CLK is low and the control signal CONV_END is high, and the switch SW1 transitions from off to on. Subsequently, when the sample clock signal SAMPLE_CLK becomes high or the control signal CONV_END becomes low, the switch control signal φ1 transitions from a high level to a low level, and the switch SW1 transitions from on to off.

[0122] As shown in Figure 22B, the switch control signal φ2 transitions from a low level to a high level when the sample clock signal SAMPLE_CLK is high level or the control signal CONV_END is low level, and the switch SW2 transitions from off to on. Subsequently, when the sample clock signal SAMPLE_CLK is low level and the control signal CONV_END is high level, the switch control signal φ2 transitions from a high level to a low level, and the switch SW2 transitions from on to off.

[0123] As shown in Figure 22C, on the rising edge of the sample clock signal SAMPLE_CLK, the switch control signal φ3 transitions from a high level to a low level, and the switch control signal φ4 transitions from a low level to a high level. Therefore, switch SW23 transitions from on to off, and switch SW24 transitions from off to on. Subsequently, on the rising edge of the sample clock signal SAMPLE_CLK, the switch control signal φ3 transitions from a low level to a high level, and the switch control signal φ4 transitions from a high level to a low level. Therefore, switch SW23 transitions from off to on, and switch SW24 transitions from on to off.

[0124] The ADC1a according to the second embodiment can be configured in the same way as the ADC1 according to the first embodiment, except that it includes a passive filter section 7a. The CDAC3 has redundant functions as shown in Figures 10 to 15B. A chopper as shown in Figure 16 may also be provided.

[0125] Thus, the ADC1a according to the second embodiment includes a passive filter section 7a, but since charge redistribution is performed within the filter section 7a using the analog signal sampling period (first period) and the AD conversion period (second period), sufficient time for charge redistribution can be secured. Performing charge redistribution during the AD conversion period may lead to incorrect selection of capacitors in the CDAC3, but by providing redundancy in the CDAC3, there is no risk of a decrease in AD conversion accuracy.

[0126] (Third embodiment) In the first embodiment, the SAR ADC1 receives the differential residual signal output from the CDAC3 and the differential noise shaping signal output from the filter section 7 as inputs to the comparator 4, thus requiring a comparator 4 to perform a comparison and determination of the two differential signals.

[0127] In contrast, the SAR ADC1b according to the third embodiment combines the differential noise-shaping signal output from the filter section 7b with the output signal of the CDAC3 and inputs it to the comparator 4. This allows the use of a comparator 4 that performs comparison and judgment of a single differential signal.

[0128] Figure 23 is a block diagram showing the schematic configuration of ADC1b according to the third embodiment. In Figure 23, components common to Figure 1 are denoted by the same reference numerals, and the differences will be explained below.

[0129] The ADC1b in Figure 23, like the ADIC in Figure 1A, includes a sample switch 2, a CDA3, a comparator 4, a logic circuit 5, a decoder 6, a filter section (L(z))7b, and a filter switch 8. In addition, the ADC1b in Figure 23 includes an adder 10.

[0130] The adder 10 updates the residual signal of the CDAC3 by redistributing charge between the capacitor in the filter section 7 and the capacitor in the CDAC3.

[0131] The ADC1b in Figure 23 can be called an error-feedback type SAR ADC1b because it feeds back the noise-shaping signal output from the filter section 7b to the residual signal of the CDAC3. The error-feedback residual signal of the CDAC3 is input to the comparator 4 in Figure 23 as a differential signal. Thus, the comparator 4 in Figure 23 receives only one differential input signal instead of two, which simplifies the internal configuration of the comparator 4.

[0132] The filter section 7b in Figure 23 has a different internal configuration from the filter section 7 in Figure 1, and the filter section 7b in Figure 23 does not include an integrating amplifier 12. The internal configuration of the filter section 7b in Figure 23 will be described later.

[0133] Figure 23 shows an example where ADC1b is input via sample switch 2, but in reality, it is a fully differential ADC1, similar to ADC1 in the first and second embodiments.

[0134] Figure 24 is a timing diagram of ADC1b in Figure 23, showing the timing of each signal within one sampling period. In ADC1b in Figure 23, during the period from time t2 to t3 in Figure 24 (second period), the sampled residual signal is redistributed with the capacitor in CDAC3 to a portion of the capacitor group 7g in the filter section 7b. The large fluctuation in the voltage level of the output voltage VCOPM of CDAC3 around time t2 in Figure 24 is caused by feeding back the judgment result of the comparator 4 to CDAC3. The slight change in voltage VCOPM from the holding voltage level in the first half of time t2 to t3 is due to the effect of the charge redistribution described above. Thus, at time t2 to t3, the fluctuation in voltage VCOPM due to the feedback of the judgment result of the comparator 4 to CDAC3 and the fluctuation in voltage VCOPM due to the charge redistribution between the charge in the filter section 7b and the charge in CDAC3 occur simultaneously. Furthermore, in the timing diagram in Figure 24, the ratio of the length of time t1~t2 (first period) to the length of time t2~t4 (second period + third period) is, for example, 1:2.

[0135] Performing charge redistribution during the AD conversion period can cause fluctuations in the residual signal input to comparator 4 during AD conversion, potentially leading to incorrect capacitor selection within CDAC3. However, as explained in Figures 10 to 15B, providing redundancy in CDAC3 allows for error correction, thus maintaining AD conversion accuracy.

[0136] Figure 25 is a timing diagram for one comparative example. In Figure 25, between the period for sampling the analog signal (first period) and the period for performing AD conversion (second period), there is a period (hereinafter referred to as the fourth period) in which the charge accumulated in the capacitor in the filter section 7b is redistributed between the capacitor in the filter section 7b and the capacitor in the CDAC3.

[0137] As shown in Figure 25, if the fourth period is placed between the first and second periods, and the sampling period remains unchanged, the length of the first to third periods must be shortened by the length of the fourth period, which may lead to a decrease in AD conversion accuracy or a deterioration in SNDR.

[0138] Figure 26 is a circuit diagram showing an example of the internal configuration of the filter section 7b in Figure 23. In addition to having differential input and differential output buffers 11, the filter section 7b in Figure 26 has switches SW31, SW32a, SW32b, SW33a, SW33b, SW34a, SW34b, SW35a, SW35b, SW36a, and SW36b, and capacitors CA, CB1, and CB2 for each signal constituting the differential signal.

[0139] Switches SW31 and SW34 are connected in series between the output node of buffer 11 and the output node of filter section 7b, and a capacitor CA is connected between the common connection node and the ground node of switches SW31 and SW34.

[0140] Switches SW32a and SW35a are connected in series between the output node and the ground node of buffer 11. Switches SW35b and SW32b are connected in series between the output node and the ground node of filter section 7b. Capacitor CB1 is connected between the common connection node of switches SW32a and SW35a and the common connection node of switches SW32b and SW35b.

[0141] Switches SW33a and SW36a are connected in series between the output node and the ground node of buffer 11. Switches SW36b and SW33b are connected in series between the output node and the ground node of filter section 7b. A capacitor CB2 is connected between the common connection node of switches SW33a and SW36a and the common connection node of switches SW33b and SW36b.

[0142] Switch SW31 is switched using switch control signal φ1, switches SW32a and SW32b are switched using switch control signal φ2, switches SW33a and SW33b are switched using switch control signal φ3, switch SW34 is switched using switch control signal φ4, switches SW35a and SW35b are switched using switch control signal φ5, and switches SW36a and SW36b are switched using switch control signal φ6.

[0143] Figure 27 is a timing diagram of the filter section 7b in Figure 23. The switching period of switches SW1 to SW6 in the filter section 7b in Figure 23 corresponds to the two sampling periods of ADC1b (first sampling period and second sampling period), similar to Figure 6.

[0144] During the time interval t1 to t2 (first period) within the first sampling period, all switches in the filter section 7b are in the off state. As a result, the accumulated charge in capacitors CA, CB1, and CB2 within the filter section 7b is maintained.

[0145] During the time interval t2-t3 (second period) within the first sampling period, switches SW34, SW35a, and SW35b in the filter section 7b are turned on, while the other switches are turned off. As a result, the stored charge in capacitors CA and CB1 is redistributed with the respective capacitors in CDAC3.

[0146] During the time interval t3 to t4 (third period) within the first sampling period, switches SW31, SW32a, and SW32b in the filter section 7b are turned on, while the other switches are turned off. Therefore, the residual signal output from CDAC3 is sampled by capacitors CA and CB1.

[0147] During the time interval t4-t5 (first period) within the second sampling period, all switches in the filter section 7b are in the off state. As a result, the accumulated charge in capacitors CA, CB1, and CB2 within the filter section 7b is maintained.

[0148] During the second sampling period, from time t5 to t6 (second period), switches SW34, SW36a, and SW36b in the filter section 7b are turned on, while the other switches are turned off. As a result, the stored charge in capacitors CA and CB2 is redistributed with the respective capacitors in CDAC3.

[0149] During the second sampling period, from time t6 to t7 (the third period), switches SW31, SW33a, and SW33b in the filter section 7b are turned on, while the other switches are turned off. Therefore, the residual signal output from CDAC3 is sampled by capacitors CA and CB2.

[0150] Figure 28 is a flowchart showing the processing operation of ADC1b in Figure 23, and, similar to the timing diagram in Figure 27, it shows the processing operation with two sampling periods. First, the variable n is initialized to zero, and the analog signal input from the outside is sampled (step S21). Step S21 shows the operation at times t1 to t2 (first period) in Figure 27. The variable n is a variable that counts the number of times the comparator 4 performs a comparison judgment.

[0151] Next, the AD conversion operation is performed based on the comparison judgment of the comparator 4 (step S22). Steps S22 to S24 show the operation at times t2 to t3 (second period) in Figure 27. Next, the variable n is incremented by 1 (step S23). Next, it is determined whether the variable n has reached the number of bits N of the physical resolution of the ADC1b (step S24). If the variable n has not reached N, the process returns to step S22. While the processing in steps S21 to S24 is being performed, the charges of capacitors CA and CB1 in the filter section 7b are redistributed with the respective capacitors in the CDAC3.

[0152] If it is determined in step S24 that the variable n has reached N, the residual signal output from CDAC3 is sampled into capacitors CA and CB1 in the filter section 7b (step S25). Step S25 shows the operation at times t3 to t4 (third period) in Figure 27.

[0153] Steps S21 to S25 described above are performed during the first sampling period from time t1 to t4 in Figure 27. Subsequently, when the second sampling period begins, the variable n is initialized to zero, similar to step S21, and the externally input analog signal is sampled (step S26). Step S26 shows the operation from time t4 to t5 (first period) in Figure 27.

[0154] Next, the AD conversion operation is performed based on the comparison judgment of the comparator 4 (step S27). Steps S27 to S29 show the operation at time t5 to t6 (second period) in Figure 27. Next, the variable n is incremented by 1 (step S28). Next, it is determined whether the variable n has reached the number of bits N of the physical resolution of the ADC1b (step S29). If the variable n has not reached N, the process returns to step S22. While the processing in steps S26 to S29 is being performed, the charges of capacitors CA and CB2 in the filter section 7b are redistributed with the respective capacitors in the CDAC3.

[0155] If it is determined in step S29 that the variable n has reached N, the residual signal output from CDAC3 is sampled into capacitors CA and CB2 in the filter section 7b (step S30). Step S30 shows the operation at times t6 to t7 (third period) in Figure 27.

[0156] Figure 29 is a circuit diagram showing an example of the internal configuration of logic circuit 5 in Figure 23. Logic circuit 5 in Figure 29 has basically the same circuit configuration as logic circuit 5 in Figure 8. However, the pulse generation circuits 27 and 28 in logic circuit 5 in Figure 29 output switch control signals φ1 to φ6 at different timings than the pulse generation circuits 27 and 28 in logic circuit 5 in Figure 8.

[0157] Figures 30A, 30B, 30C, and 30D are state transition diagrams for switches SW1 to SW6 within the filter section 7b. Since the state transition diagrams in Figures 30A, 30B, 30C, and 30D are basically the same as those in Figures 9A, 9B, 9C, and 9D, a detailed explanation is omitted.

[0158] The ADC1b according to the third embodiment differs from the ADC1b according to the first and second embodiments described above in that it is an error feedback type, but the CDAC3 within the ADC1b according to the third embodiment has a redundant function as shown in Figures 10 to 15B. A chopper as shown in Figure 16 may also be provided.

[0159] Thus, in the third embodiment, in the error feedback type ADC1b, the charge accumulated in the capacitor in the filter section 7b is redistributed between the capacitor in the filter section 7b and the capacitor in the CDAC3 during the AD conversion period, eliminating the need to separately set aside a period for charge redistribution. Therefore, charge redistribution for error feedback can be performed without shortening the analog signal sampling period (first period), the AD conversion period (second period), and the residual signal sampling period (third period). Although there is a risk of incorrect capacitance selection in the CDAC3 by performing charge redistribution during the AD conversion period, as explained in Figures 10 to 15B, the CDAC3 is equipped with a redundant function to correct the error, so there is no risk of a decrease in AD conversion accuracy.

[0160] <<4. Application Examples>> The technology disclosed herein can be applied to a variety of products. For example, the technology disclosed herein may be implemented as a device mounted on any type of mobile vehicle, such as automobiles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, personal mobility devices, airplanes, drones, ships, robots, construction machinery, or agricultural machinery (tractors).

[0161] Figure 31 is a block diagram showing a schematic configuration example of a vehicle control system 7000, which is an example of a mobile control system to which the technology described herein can be applied. The vehicle control system 7000 comprises a plurality of electronic control units connected via a communication network 7010. In the example shown in Figure 31, the vehicle control system 7000 comprises a drive system control unit 7100, a body system control unit 7200, a battery control unit 7300, an external information detection unit 7400, an internal information detection unit 7500, and an integrated control unit 7600. The communication network 7010 connecting these plurality of control units may be an in-vehicle communication network conforming to any standard such as CAN (Controller Area Network), LIN (Local Interconnect Network), LAN (Local Area Network), or FlexRay®.

[0162] Each control unit comprises a microcomputer that performs calculations according to various programs, a storage unit that stores programs executed by the microcomputer or parameters used in various calculations, and a drive circuit that drives various controlled devices. Each control unit is equipped with a network interface for communication with other control units via the communication network 7010, and a communication interface for communication with devices or sensors inside or outside the vehicle via wired or wireless communication. Figure 31 illustrates the functional configuration of the integrated control unit 7600, which includes a microcomputer 7610, a general-purpose communication interface 7620, a dedicated communication interface 7630, a positioning unit 7640, a beacon receiver 7650, an in-vehicle equipment interface 7660, an audio / image output unit 7670, an in-vehicle network interface 7680, and a storage unit 7690. Other control units similarly include a microcomputer, a communication interface, and a storage unit.

[0163] The drivetrain control unit 7100 controls the operation of devices related to the vehicle's drivetrain according to various programs. For example, the drivetrain control unit 7100 functions as a control device for generating driving force for the vehicle, such as an internal combustion engine or a drive motor; a driving force transmission mechanism for transmitting driving force to the wheels; a steering mechanism for adjusting the steering angle of the vehicle; and a braking device for generating braking force for the vehicle. The drivetrain control unit 7100 may also function as a control device such as ABS (Antilock Brake System) or ESC (Electronic Stability Control).

[0164] A vehicle state detection unit 7110 is connected to the drivetrain control unit 7100. The vehicle state detection unit 7110 includes, for example, a gyro sensor for detecting the angular velocity of the vehicle's axial rotational motion, an acceleration sensor for detecting the vehicle's acceleration, or at least one of the sensors for detecting the amount of operation of the accelerator pedal, the amount of operation of the brake pedal, the steering angle of the steering wheel, the engine speed, or the rotational speed of the wheels. The drivetrain control unit 7100 performs calculations using signals input from the vehicle state detection unit 7110 and controls the internal combustion engine, drive motor, electric power steering system, brake system, etc.

[0165] The body system control unit 7200 controls the operation of various devices mounted on the vehicle body according to various programs. For example, the body system control unit 7200 functions as a control device for a keyless entry system, a smart key system, a power window system, or various lamps such as headlights, reverse lights, brake lights, turn signals, or fog lights. In this case, the body system control unit 7200 may receive radio waves transmitted from a portable device that replaces a key or signals from various switches. The body system control unit 7200 receives these radio waves or signals and controls the vehicle's door lock system, power window system, lamps, etc.

[0166] The battery control unit 7300 controls the secondary battery 7310, which is the power source for the drive motor, according to various programs. For example, the battery control unit 7300 receives information such as battery temperature, battery output voltage, or remaining battery capacity from the battery device equipped with the secondary battery 7310. The battery control unit 7300 uses these signals to perform calculations and controls the temperature of the secondary battery 7310 or the cooling device provided in the battery device.

[0167] The external information detection unit 7400 detects information from outside the vehicle equipped with the vehicle control system 7000. For example, at least one of the imaging unit 7410 and the external information detection unit 7420 is connected to the external information detection unit 7400. The imaging unit 7410 includes at least one of the following: a ToF (Time Of Flight) camera, a stereo camera, a monocular camera, an infrared camera, and other cameras. The external information detection unit 7420 includes at least one of the following: an environmental sensor for detecting the current weather or climate, or an ambient information detection sensor for detecting other vehicles, obstacles, or pedestrians around the vehicle equipped with the vehicle control system 7000.

[0168] The environmental sensor may be at least one of the following: a raindrop sensor for detecting rain, a fog sensor for detecting fog, a sunshine sensor for detecting the degree of sunlight, and a snow sensor for detecting snowfall. The ambient information detection sensor may be at least one of the following: an ultrasonic sensor, a radar device, and a LIDAR (Light Detection and Ranging, Laser Imaging Detection and Ranging) device. These imaging unit 7410 and external information detection unit 7420 may be provided as independent sensors or devices, or as a device in which multiple sensors or devices are integrated.

[0169] Here, Figure 32 shows examples of the installation locations of the imaging unit 7410 and the external information detection unit 7420. The imaging units 7910, 7912, 7914, 7916, and 7918 are installed, for example, at least one of the following locations on the vehicle 7900: the front nose, side mirrors, rear bumper, back door, and the upper part of the windshield inside the passenger compartment. The imaging unit 7910 installed on the front nose and the imaging unit 7918 installed on the upper part of the windshield inside the passenger compartment mainly acquire images of the front of the vehicle 7900. The imaging units 7912 and 7914 installed on the side mirrors mainly acquire images of the sides of the vehicle 7900. The imaging unit 7916 installed on the rear bumper or back door mainly acquires images of the rear of the vehicle 7900. The imaging unit 7918 installed on the upper part of the windshield inside the passenger compartment is mainly used for detecting preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, or lanes.

[0170] Figure 32 shows an example of the imaging range of each imaging unit 7910, 7912, 7914, and 7916. Imaging range a shows the imaging range of imaging unit 7910 located on the front nose, imaging ranges b and c show the imaging ranges of imaging units 7912 and 7914 located on the side mirrors, respectively, and imaging range d shows the imaging range of imaging unit 7916 located on the rear bumper or back door. For example, by superimposing the image data captured by imaging units 7910, 7912, 7914, and 7916, an overhead view image of the vehicle 7900 can be obtained.

[0171] The external information detection units 7920, 7922, 7924, 7926, 7928, and 7930, which are installed on the front, rear, sides, corners, and the upper part of the windshield inside the vehicle 7900, may be, for example, ultrasonic sensors or radar devices. The external information detection units 7920, 7926, and 7930, which are installed on the front nose, rear bumper, back door, and the upper part of the windshield inside the vehicle 7900, may be, for example, LIDAR devices. These external information detection units 7920 to 7930 are mainly used to detect preceding vehicles, pedestrians, or obstacles.

[0172] Returning to Figure 31, the explanation continues. The external information detection unit 7400 causes the imaging unit 7410 to capture images of the area outside the vehicle and receives the captured image data. The external information detection unit 7400 also receives detection information from the connected external information detection unit 7420. If the external information detection unit 7420 is an ultrasonic sensor, radar device, or LIDAR device, the external information detection unit 7400 emits ultrasonic waves or electromagnetic waves and receives information on the received reflected waves. Based on the received information, the external information detection unit 7400 may perform object detection processing such as detecting people, vehicles, obstacles, signs, or characters on the road surface, or distance detection processing. Based on the received information, the external information detection unit 7400 may perform environmental recognition processing to recognize rainfall, fog, or road surface conditions. Based on the received information, the external information detection unit 7400 may calculate the distance to an object outside the vehicle.

[0173] Furthermore, the external information detection unit 7400 may perform image recognition processing or distance detection processing to recognize people, vehicles, obstacles, signs, or characters on the road surface based on the received image data. The external information detection unit 7400 may perform distortion correction or alignment processing on the received image data, and may also synthesize image data captured by different imaging units 7410 to generate an overhead view image or a panoramic image. The external information detection unit 7400 may also perform viewpoint transformation processing using image data captured by different imaging units 7410.

[0174] The in-vehicle information detection unit 7500 detects information inside the vehicle. The in-vehicle information detection unit 7500 is connected to, for example, a driver status detection unit 7510 that detects the driver's state. The driver status detection unit 7510 may include a camera that images the driver, a biosensor that detects the driver's biometric information, or a microphone that collects sounds inside the vehicle. The biosensor is installed, for example, on the seat or steering wheel and detects the biometric information of a passenger sitting in the seat or a driver holding the steering wheel. Based on the detection information input from the driver status detection unit 7510, the in-vehicle information detection unit 7500 may calculate the driver's level of fatigue or concentration, or determine whether the driver is dozing off. The in-vehicle information detection unit 7500 may perform processing such as noise cancellation on the collected audio signals.

[0175] The integrated control unit 7600 controls the overall operation of the vehicle control system 7000 according to various programs. An input unit 7800 is connected to the integrated control unit 7600. The input unit 7800 is implemented by a device that can be operated by the passenger, such as a touch panel, buttons, a microphone, a switch, or a lever. The integrated control unit 7600 may also receive data obtained by voice recognition of voice input from the microphone. The input unit 7800 may be a remote control device using infrared or other radio waves, or an external device such as a mobile phone or PDA (Personal Digital Assistant) that is compatible with the operation of the vehicle control system 7000. The input unit 7800 may be a camera, in which case the passenger can input information by gesture. Alternatively, data obtained by detecting the movement of a wearable device worn by the passenger may be input. Furthermore, the input unit 7800 may include, for example, an input control circuit that generates an input signal based on the information input by the passenger using the above input unit 7800 and outputs it to the integrated control unit 7600. Passengers and others can input various data or instruct the vehicle control system 7000 to perform processing operations by operating this input unit 7800.

[0176] The memory unit 7690 may include a ROM (Read Only Memory) for storing various programs executed by a microcomputer, and a RAM (Random Access Memory) for storing various parameters, calculation results, or sensor values. The memory unit 7690 may also be implemented using a magnetic storage device such as an HDD (Hard Disk Drive), a semiconductor storage device, an optical storage device, or a magneto-optical storage device.

[0177] The general-purpose communication interface 7620 is a general-purpose communication interface that mediates communication between the vehicle and various devices present in the external environment 7750. The general-purpose communication interface 7620 may implement cellular communication protocols such as GSM (Global System of Mobile communications), WiMAX (registered trademark), LTE (registered trademark) (Long Term Evolution), or LTE-A (LTE-Advanced), or other wireless communication protocols such as wireless LAN (also known as Wi-Fi (registered trademark)) or Bluetooth (registered trademark). The general-purpose communication interface 7620 may connect to devices (e.g., application servers or control servers) located on an external network (e.g., the Internet, a cloud network, or a carrier-specific network) via, for example, a base station or access point. The general-purpose communication interface 7620 may also connect to terminals located near the vehicle (e.g., terminals for drivers, pedestrians, or shops, or MTC (Machine Type Communication) terminals) using, for example, P2P (Peer To Peer) technology.

[0178] The Dedicated Communication I / F 7630 is a communication interface that supports communication protocols developed for use in vehicles. The Dedicated Communication I / F 7630 may implement standard protocols such as WAVE (Wireless Access in Vehicle Environment), DSRC (Dedicated Short Range Communications), or cellular communication protocols, which are combinations of lower-layer IEEE 802.11p and upper-layer IEEE 1609. The Dedicated Communication I / F 7630 typically performs V2X communication, a concept that includes one or more of the following: vehicle-to-vehicle communication, vehicle-to-infrastructure communication, vehicle-to-home communication, and vehicle-to-pedestrian communication.

[0179] The positioning unit 7640 performs positioning by receiving GNSS signals from GNSS (Global Navigation Satellite System) satellites (for example, GPS signals from GPS (Global Positioning System) satellites) and generates location information including the vehicle's latitude, longitude, and altitude. The positioning unit 7640 may also determine its current location by exchanging signals with a wireless access point, or it may acquire location information from a terminal such as a mobile phone, PHS, or smartphone that has a positioning function.

[0180] The beacon receiver 7650 receives radio waves or electromagnetic waves transmitted from, for example, a radio station installed on a road, and obtains information such as the current location, traffic congestion, road closures, or travel time. The functions of the beacon receiver 7650 may also be included in the dedicated communication interface 7630 described above.

[0181] The In-Vehicle Equipment I / F 7660 is a communication interface that mediates connections between the microcomputer 7610 and various in-vehicle equipment 7760 located inside the vehicle. The In-Vehicle Equipment I / F 7660 may establish a wireless connection using wireless communication protocols such as Wi-Fi, Bluetooth®, NFC (Near Field Communication), or WUSB (Wireless USB). Furthermore, the in-vehicle equipment I / F 7660 may establish a wired connection such as USB (Universal Serial Bus), HDMI (Registered Trademark) (High-Definition Multimedia Interface), or MHL (Mobile High-Definition Link) via connection terminals (and, if necessary, cables) not shown. The in-vehicle equipment 7760 may include, for example, at least one of the following: a mobile device or wearable device owned by a passenger, or an information device brought into or installed in the vehicle. The in-vehicle equipment 7760 may also include a navigation device that performs route searching to any destination. The in-vehicle equipment I / F 7660 exchanges control signals or data signals with these in-vehicle equipment 7760s.

[0182] The in-vehicle network interface 7680 is an interface that mediates communication between the microcomputer 7610 and the communication network 7010. The in-vehicle network interface 7680 transmits and receives signals and other data in accordance with a predetermined protocol supported by the communication network 7010.

[0183] The microcomputer 7610 of the integrated control unit 7600 controls the vehicle control system 7000 according to various programs based on information acquired via at least one of the general-purpose communication I / F 7620, dedicated communication I / F 7630, positioning unit 7640, beacon receiver 7650, in-vehicle equipment I / F 7660, and in-vehicle network I / F 7680. For example, the microcomputer 7610 may calculate control target values ​​for the drive force generator, steering mechanism, or braking device based on acquired in-vehicle and out-of-vehicle information and output control commands to the drive system control unit 7100. For example, the microcomputer 7610 may perform coordinated control aimed at realizing ADAS (Advanced Driver Assistance System) functions, including vehicle collision avoidance or impact mitigation, following driving based on distance between vehicles, maintaining vehicle speed, vehicle collision warning, or vehicle lane departure warning. Furthermore, the microcomputer 7610 may perform cooperative control for purposes such as autonomous driving, where the vehicle drives autonomously without driver intervention, by controlling the drive force generating device, steering mechanism, or braking device, etc., based on the acquired information about the vehicle's surroundings.

[0184] The microcomputer 7610 may generate three-dimensional distance information between the vehicle and surrounding structures, people, and other objects based on information acquired via at least one of the general-purpose communication I / F 7620, dedicated communication I / F 7630, positioning unit 7640, beacon receiver 7650, in-vehicle equipment I / F 7660, and in-vehicle network I / F 7680, and create local map information including surrounding information of the vehicle's current location. Furthermore, the microcomputer 7610 may predict dangers such as vehicle collision, proximity of pedestrians, or entry into a closed road based on the acquired information, and generate a warning signal. The warning signal may, for example, be a signal to generate a warning sound or illuminate a warning lamp.

[0185] The audio-image output unit 7670 transmits at least one of audio and image output signals to an output device capable of visually or audibly notifying the vehicle's occupants or those outside the vehicle. In the example shown in Figure 31, the output devices are exemplified as an audio speaker 7710, a display unit 7720, and an instrument panel 7730. The display unit 7720 may include, for example, at least one of an onboard display and a head-up display. The display unit 7720 may also have an AR (Augmented Reality) display function. The output device may be other devices besides these, such as headphones, wearable devices such as glasses-type displays worn by occupants, projectors, or lamps. If the output device is a display device, the display device visually displays the results obtained from various processes performed by the microcomputer 7610 or information received from other control units in various formats such as text, images, tables, and graphs. If the output device is an audio output device, the audio output device converts the audio signal, consisting of reproduced audio data or sound data, into an analog signal and outputs it audibly.

[0186] In the example shown in Figure 31, at least two control units connected via the communication network 7010 may be integrated into a single control unit. Alternatively, each control unit may be composed of multiple control units. Furthermore, the vehicle control system 7000 may include other control units not shown. Also, in the above description, some or all of the functions performed by one control unit may be assigned to other control units. In other words, as long as information is transmitted and received via the communication network 7010, predetermined calculation processing may be performed by any of the control units. Similarly, a sensor or device connected to one control unit may be connected to another control unit, and multiple control units may transmit and receive detection information to and from each other via the communication network 7010.

[0187] When converting the detection signals of various sensors used in the vehicle control system 7000 described above into digital signals, the ADC1, 1a, and 1b according to this embodiment, as described with reference to Figures 1 to 30B, can be used.

[0188] Furthermore, this technology can take the following configuration. (1) An analog-to-digital converter that converts an analog signal to a digital signal within a sampling period including a continuous first period, a second period, and a third period, A digital-to-analog converter that samples the analog signal within a first period, converts the sampled signal into a digital signal bit by bit with redundancy within a second period, and outputs the unconverted residual signal. A filter unit that samples the residual signal within the third period and generates a noise-shaping signal by performing charge transfer or charge redistribution based at least within the second period on a portion of the residual signal sampled in the third period within the immediately preceding sampling period and a portion of the residual signal sampled in the third period within the sampling period two periods prior; An analog-to-digital converter comprising: a DAC control unit that controls the digital-to-analog converter within the second period based on the residual signal and the noise shaping signal. (2) The analog-to-digital converter according to (1), wherein the filter unit generates the noise shaping signal by charge-transferring a portion of the residual signal sampled in the third period of the immediately preceding sampling period and a portion of the residual signal sampled in the third period of the sampling period two periods prior, during the first and second periods. (3) The analog-to-digital converter according to (1), wherein the filter unit generates the noise shaping signal by redistributing charge between a portion of the residual signal sampled in the third period of the immediately preceding sampling period and a portion of the residual signal sampled in the third period of the sampling period two periods prior, during the first and second periods. (4) The filter section is Multiple first capacitors, The system includes a plurality of first switches that switch whether or not to store charge in each of the plurality of first capacitors, Some of the plurality of first capacitors accumulate charge corresponding to the residual signal during the third period. During the first and second periods, charge transfer is performed from one of the first capacitors that accumulated the residual signal during the third period of the immediately preceding sampling period to another first capacitor. The analog-to-digital converter according to (2), wherein the noise-shaping signal is generated by the charge transferred to the other first capacitor. (5) The filter section is A first differential amplifier having a first differential input terminal into which the residual signal is input, and a first differential output terminal that outputs a differential signal corresponding to the residual signal, A second differential amplifier is provided, having a second differential input terminal and a second differential output terminal, and outputting the differential noise shaping signal from the second differential output terminal. The analog-to-digital converter described in (4), wherein the other first capacitor is connected between the second differential input terminal and the second differential output terminal of the second differential amplifier. (6) A first chopper that periodically swaps the differential input signals input to at least one of the first differential input terminal of the first differential amplifier and the second differential input terminal of the second differential amplifier, The analog-to-digital converter according to (5), further comprising: a second chopper that periodically swaps the differential output signals output from at least one of the first differential output terminal of the first differential amplifier and the second differential output terminal of the second differential amplifier in synchronization with the swapping of the first chopper. (7) The filter section is Multiple first capacitors, The system includes a plurality of first switches that switch whether or not to store charge in each of the plurality of first capacitors, Some of the plurality of first capacitors accumulate charge corresponding to the residual signal during the third period. The analog-to-digital converter according to (3), wherein, during the first and second periods, the charge accumulated in a portion of the first capacitors that accumulated the residual signal during the third period of the immediately preceding sampling period is redistributed between the portion of the first capacitors and another first capacitor to generate the noise-shaping signal. (8) The analog-to-digital converter according to any one of (4) to (7), wherein some of the plurality of first capacitors perform charge accumulation and transfer for each sampling period, and the remaining first capacitors perform charge accumulation and transfer for one of two consecutive sampling periods. (9) The analog signal is a differential analog signal, Two digital-to-analog converters are provided to convert the differential analog signal into the differential digital signal. The differential residual signals are output from the two digital-to-analog converters. The filter unit generates the differential noise shaping signal within the first and second periods. The analog-to-digital converter according to any one of (1) to (8), wherein the DAC control unit controls the two digital-to-analog converters based on the differential residual signal and the differential noise shaping signal during the second period. (10) The analog-to-digital converter according to (9), wherein the DAC control unit controls the two digital-to-analog converters such that the sum of the signal difference of the differential residual signal and the signal difference of the differential noise shaping signal approaches zero. (11) The DAC control unit, A comparator that outputs a signal corresponding to the sum of the signal difference of the differential residual signal and the signal difference of the differential noise shaping signal, The analog-to-digital converter according to (9) or (10), further comprising a logic circuit that controls the digital-to-analog converter based on the output signal of the comparator. (12) The digital-to-analog converter is A plurality of second capacitors, each supplied with the analog signal at one end, or with the residual signal output from one end, The system includes a plurality of second switches that set the other end of the plurality of second capacitors to one of a plurality of voltages, The analog-to-digital converter according to any one of (1) to (11), wherein the DAC control unit controls the switching of the plurality of second switches based on the residual signal and the noise shaping signal. (13) The digital-to-analog converter is A plurality of second capacitors, each supplied with the analog signal at one end, or with the residual signal output from one end, The system includes a plurality of second switches that set the other end of the plurality of second capacitors to one of a plurality of voltages, The analog-to-digital converter according to (1), wherein the filter unit, within the second period, redistributes the charge of a portion of the residual signal sampled in the third period within the immediately preceding sampling period and a portion of the residual signal sampled in the third period within the sampling period two periods prior, with the plurality of second capacitors in the digital-to-analog converter to generate the noise-shaping signal. (14) The filter section is Multiple first capacitors, The system includes a plurality of first switches that switch whether or not to store charge in each of the plurality of first capacitors, Some of the plurality of first capacitors accumulate charge corresponding to the residual signal during the third period. The analog-to-digital converter according to (13), wherein, during the second period, the accumulated charge of a portion of the first capacitors that accumulated the residual signal during the third period of the immediately preceding sampling period is redistributed between the first capacitors in the filter section, which includes the portion of the first capacitors, and the plurality of second capacitors to generate the noise shaping signal. (15) The analog signal is a differential analog signal, Two digital-to-analog converters are provided to convert the differential analog signal into the differential digital signal. The differential residual signals are output from the two digital-to-analog converters. The filter unit generates the differential noise shaping signal within the second period, The analog-to-digital converter according to (14), wherein the DAC control unit controls the two digital-to-analog converters based on the differential residual signal and the differential noise shaping signal during the second period. (16) The analog-to-digital converter according to any one of (13) to (15), wherein at least some of the plurality of second capacitors have a capacitance value obtained by multiplying the reference capacitance by a value less than a multiple of 2, and the remaining second capacitors have a capacitance value that is a multiple of 2 or a power of 2 of the reference capacitance. (17) The plurality of second capacitors have capacitance values ​​that are multiples of 2 with respect to the reference capacitance, The analog-to-digital converter according to any one of (13) to (15), wherein two or more of the plurality of second capacitors have the same capacitance value. (18) The analog-to-digital converter according to any one of (1) to (17), wherein the filter unit updates the noise shaping signal in units of two consecutive sampling periods. (19) The analog-to-digital converter described in any one of paragraphs (1) to (18), wherein the first period is shorter than the combined period of the second and third periods. (20) An analog-to-digital converter that converts an analog signal to a digital signal within a sampling period including a continuous first period, a second period and a third period, An electronic device comprising an information processing unit that performs information processing based on the aforementioned digital signal, The aforementioned analog-to-digital converter is A digital-to-analog converter that samples the analog signal within a first period, converts the sampled signal into a digital signal bit by bit with redundancy within a second period, and outputs the unconverted residual signal. A filter unit that samples the residual signal within the third period and generates a noise-shaping signal by performing charge transfer or charge redistribution based at least within the second period on a portion of the residual signal sampled in the third period within the immediately preceding sampling period and a portion of the residual signal sampled in the third period within the sampling period two periods prior; An electronic device comprising: a DAC control unit that controls the digital-to-analog converter within the second period based on the residual signal and the noise shaping signal.

[0189] The aspects of this disclosure are not limited to the individual embodiments described above, but include various modifications that a person skilled in the art could conceive, and the effects of this disclosure are not limited to those described above. In other words, various additions, modifications, and partial deletions are possible, as long as they do not depart from the conceptual idea and spirit of this disclosure derived from the claims and their equivalents. [Explanation of symbols]

[0190] 1, 1a, 1b Analog-to-Digital Converter (ADC), 2 Sample Switch, 3 CDAC, 4 Comparator, 5 Logic Circuit, 6 Decoder, 7, 7a, 7b Filter Section, 7g Capacitor Group, 8 Filter Switch, 9 DAC Control Section, 10a Capacitor Group, 10b Switch, 11 Buffer, 12 Integrating Amplifier, 12a Differential Amplifier, 21 NOR Gate, 22 Shift Register, 23, 24 Inverter, 25, 26 AND Gate, 27, 28 Pulse Generation Circuit, 31, 32 Chopper, 7000 Vehicle Control System, 7010 Communication Network, 7100 Drive System Control Unit, 7110 Vehicle Status Detection Unit, 7200 Body System Control Unit, 7300 Battery Control Unit, 7310 Secondary Battery, 7400 External Information Detection Unit, 7410 Imaging Unit, 7420 External Information Detection Unit, 7500 In-vehicle information detection unit, 7510 Driver status detection unit, 7600 Integrated control unit, 7610 Microcomputer, 7640 Positioning unit, 7650 Beacon receiver, 7670 Audio and image output unit 7690 Memory Unit, 7710 Audio Speaker, 7720 Display Unit, 7730 Instrument Panel, 7750 External Environment, 7760 In-Vehicle Equipment, 7800 Input Unit, 7900 Vehicle, 7910, 7912, 7914, 7916, 7918 Imaging Unit, 7920, 7921, 7922, 7923, 7924, 7925, 7926, 7927, 7928, 7929, 7930 External Information Detection Unit

Claims

1. An analog-to-digital converter that converts an analog signal to a digital signal within a sampling period including a continuous first period, a second period, and a third period, A digital-to-analog converter that samples the analog signal within a first period, converts the sampled signal into a digital signal bit by bit with redundancy within a second period, and outputs the unconverted residual signal. A filter unit that samples the residual signal within the third period and generates a noise-shaping signal by performing charge transfer or charge redistribution based at least within the second period on a portion of the residual signal sampled in the third period within the immediately preceding sampling period and a portion of the residual signal sampled in the third period within the sampling period two periods prior; The system includes a DAC control unit that controls the digital-to-analog converter within the second period based on the residual signal and the noise shaping signal, The filter unit has a plurality of first capacitors that transfer charge during the first and second periods to generate a noise shaping signal. One of the plurality of first capacitors transfers charge from a portion of the residual signal sampled in the third period within the immediately preceding sampling period to the first and second periods. The other two of the plurality of first capacitors are analog-to-digital converters that alternately transfer charge from a portion of the residual signal sampled in the third period within the second previous sampling period, with each sampling period.

2. An analog-to-digital converter that converts an analog signal to a digital signal within a sampling period including a continuous first period, a second period, and a third period, A digital-to-analog converter that samples the analog signal within a first period, converts the sampled signal into a digital signal bit by bit with redundancy within a second period, and outputs the unconverted residual signal. A filter unit that samples the residual signal within the third period and generates a noise-shaping signal by performing charge transfer or charge redistribution based at least within the second period on a portion of the residual signal sampled in the third period within the immediately preceding sampling period and a portion of the residual signal sampled in the third period within the sampling period two periods prior; The system includes a DAC control unit that controls the digital-to-analog converter within the second period based on the residual signal and the noise shaping signal, The filter section has a plurality of first capacitors that perform charge transfer and charge redistribution within the first and second periods to generate a noise shaping signal. One of the plurality of first capacitors performs charge transfer and charge redistribution on a portion of the residual signal sampled in the third period within the immediately preceding sampling period during the first and second periods. The other two of the plurality of first capacitors are analog-to-digital converters that alternately transfer and redistribute charge on a portion of the residual signal sampled in the third period within the second previous sampling period, with each sampling period.

3. The filter unit is The system includes a plurality of first switches that switch whether or not to store charge in each of the plurality of first capacitors, Some of the plurality of first capacitors accumulate charge corresponding to the residual signal during the third period. During the first and second periods, charge transfer is performed from one of the first capacitors that accumulated the residual signal during the third period of the immediately preceding sampling period to another first capacitor. The analog-to-digital converter according to claim 1, wherein the noise shaping signal is generated by the charge transferred to the other first capacitor.

4. The filter unit is A first differential amplifier having a first differential input terminal into which the residual signal is input, and a first differential output terminal that outputs a differential signal corresponding to the residual signal, A second differential amplifier is provided, having a second differential input terminal and a second differential output terminal, and outputting the differential noise shaping signal from the second differential output terminal. The analog-to-digital converter according to claim 3, wherein the other first capacitor is connected between the second differential input terminal and the second differential output terminal of the second differential amplifier.

5. A first chopper that periodically swaps the differential input signals input to at least one of the first differential input terminal of the first differential amplifier and the second differential input terminal of the second differential amplifier, The analog-to-digital converter according to claim 4, further comprising: a second chopper that periodically swaps the differential output signals output from at least one of the first differential output terminal of the first differential amplifier and the second differential output terminal of the second differential amplifier in synchronization with the swapping of the first chopper.

6. The filter unit is The system includes a plurality of first switches that switch whether or not to store charge in each of the plurality of first capacitors, Some of the plurality of first capacitors accumulate charge corresponding to the residual signal during the third period. The analog-to-digital converter according to claim 2, wherein, during the first and second periods, the charge accumulated in a portion of the first capacitors that accumulated the residual signal during the third period of the immediately preceding sampling period is redistributed between the portion of the first capacitors and another first capacitor to generate the noise shaping signal.

7. The analog-to-digital converter according to any one of claims 3 to 6, wherein some of the plurality of first capacitors perform charge accumulation and transfer for each sampling period, and the remaining first capacitors perform charge accumulation and transfer for one of two consecutive sampling periods.

8. The aforementioned analog signal is a differential analog signal. Two digital-to-analog converters are provided to convert the differential analog signal into the differential digital signal. The differential residual signals are output from the two digital-to-analog converters. The filter unit generates the differential noise shaping signal within the first and second periods. The analog-to-digital converter according to any one of claims 1 to 7, wherein the DAC control unit controls the two digital-to-analog converters based on the differential residual signal and the differential noise shaping signal during the second period.

9. The analog-to-digital converter according to claim 8, wherein the DAC control unit controls the two digital-to-analog converters such that the sum of the signal difference of the differential residual signal and the signal difference of the differential noise shaping signal approaches zero.

10. The DAC control unit, A comparator that outputs a signal corresponding to the sum of the signal difference of the differential residual signal and the signal difference of the differential noise shaping signal, The analog-to-digital converter according to claim 8, further comprising a logic circuit that controls the digital-to-analog converter based on the output signal of the comparator.

11. The aforementioned digital-to-analog converter is A plurality of second capacitors, each supplied with the analog signal at one end, or each outputting the residual signal from one end, The system includes a plurality of second switches that set the other end of the plurality of second capacitors to one of a plurality of voltages, The analog-to-digital converter according to any one of claims 1 to 10, wherein the DAC control unit controls the switching of the plurality of second switches based on the residual signal and the noise shaping signal.

12. The aforementioned digital-to-analog converter is A plurality of second capacitors, each supplied with the analog signal at one end, or each outputting the residual signal from one end, The system includes a plurality of second switches that set the other end of the plurality of second capacitors to one of a plurality of voltages, The analog-to-digital converter according to any one of claims 1 to 11, wherein the filter unit, within the second period, redistributes the charge of a portion of the residual signal sampled in the third period within the immediately preceding sampling period and a portion of the residual signal sampled in the third period within the sampling period two periods prior to the current sampling period with the plurality of second capacitors in the digital-to-analog converter to generate the noise shaping signal.

13. The filter unit is The system includes a plurality of first switches that switch whether or not to store charge in each of the plurality of first capacitors, Some of the plurality of first capacitors accumulate charge corresponding to the residual signal during the third period. The analog-to-digital converter according to claim 12, wherein, during the second period, the accumulated charge of a portion of the first capacitors that accumulated the residual signal during the third period of the immediately preceding sampling period is redistributed between the first capacitors in the filter section, which includes the portion of the first capacitors, and the plurality of second capacitors to generate the noise shaping signal.

14. The aforementioned analog signal is a differential analog signal. Two digital-to-analog converters are provided to convert the differential analog signal into the differential digital signal. The differential residual signals are output from the two digital-to-analog converters. The filter unit generates the differential noise shaping signal within the second period, The analog-to-digital converter according to claim 13, wherein the DAC control unit controls the two digital-to-analog converters based on the differential residual signal and the differential noise shaping signal during the second period.

15. The analog-to-digital converter according to any one of claims 12 to 14, wherein at least some of the plurality of second capacitors have a capacitance value obtained by multiplying the reference capacitance by a value less than a multiple of 2, and the remaining second capacitors have a capacitance value that is a multiple of 2 or a power of 2 of the reference capacitance.

16. The plurality of second capacitors have capacitance values ​​that are multiples of 2 with respect to the reference capacitance. The analog-to-digital converter according to any one of claims 12 to 14, wherein two or more of the plurality of second capacitors have the same capacitance value.

17. The analog-to-digital converter according to any one of claims 1 to 16, wherein the filter unit updates the noise shaping signal in units of two consecutive sampling periods.

18. The analog-to-digital converter according to any one of claims 1 to 17, wherein the first period is shorter than the combined period of the second and third periods.

19. An analog-to-digital converter that converts an analog signal to a digital signal within a sampling period including consecutive first, second, and third periods, An electronic device comprising an information processing unit that performs information processing based on the aforementioned digital signal, The aforementioned analog-to-digital converter is A digital-to-analog converter that samples the analog signal within a first period, converts the sampled signal into a digital signal bit by bit with redundancy within a second period, and outputs the unconverted residual signal. A filter unit that samples the residual signal within the third period and generates a noise-shaping signal by performing charge transfer or charge redistribution based at least within the second period on a portion of the residual signal sampled in the third period within the immediately preceding sampling period and a portion of the residual signal sampled in the third period within the sampling period two periods prior; The system includes a DAC control unit that controls the digital-to-analog converter within the second period based on the residual signal and the noise shaping signal, The filter unit has a plurality of first capacitors that transfer charge during the first and second periods to generate a noise shaping signal. One of the plurality of first capacitors transfers charge from a portion of the residual signal sampled in the third period within the immediately preceding sampling period to the first and second periods. The other two of the plurality of first capacitors alternately transfer charge from a portion of the residual signal sampled in the third period within the two previous sampling periods, in each sampling period, in an electronic device.

Images