Matching of pre-processed substrate sample and post-processed substrate sample

Abstract

Various embodiments herein relate to a system, method, and medium for matching pre-processed substrate samples and post-processed substrate samples. In some embodiments, a computer program product for matching pre-processed substrate samples and post-processed substrate samples is provided, the computer program product comprises a non-transitory computer-readable medium on which are provided computer-executable instructions for receiving a plurality of samples associated with a first set of dimensions characterizing the substrate after pre-processing and a plurality of samples associated with a second set of dimensions characterizing the substrate after post-processing, computer-executable instructions for receiving identification of one of the pre-processing dimensions and one of the post-processing dimensions to be matched, computer-executable instructions for generating a first probability distribution of samples for the identified pre-processing dimension and a second probability distribution of samples for the identified post-processing dimension, and computer-executable instructions for matching the identified pre-processing dimension sample with the identified post-processing dimension sample based on the first probability distribution and the second probability distribution.

Description

Technical Field

[0001] Incorporation by Reference A PCT application is filed simultaneously with this specification as part of this application. Each application that this application claims the benefit or priority of, identified in the PCT application filed simultaneously, is incorporated by reference in its entirety for all purposes into this specification.

Background Art

[0002] Semiconductor device manufacturing processes are often analyzed (e.g., by process engineers developing and / or maintaining the process) using pre- and post-process substrates such as semiconductor wafers. For example, pre- and post-process measurement data can be evaluated. However, such analysis tends to provide an overall substrate profile of substrate characteristics, including, for example, statistical representations (e.g., mean, variance, etc.) of the pre- and post-process substrates. It can be difficult to fully analyze a process using an overall substrate profile. For example, it can be difficult for a process engineer to separate the effects of wafer variations on a pre-process substrate from the effects of various process conditions.

[0003] The background description provided herein is for the purpose of presenting the context of the present disclosure generally. Neither the research of the currently named inventors in the scope described in this background section, nor aspects of the description that may not ordinarily qualify as prior art at the time of filing, are admitted as prior art to the present disclosure, either expressly or implicitly.

Summary of the Invention

[0004] Systems, methods, and media for matching a pre-process substrate sample with a post-process substrate sample are disclosed herein.

[0005] According to some embodiments, a computer program product is provided for matching pre-processed substrate samples and post-processed substrate samples, the computer program product comprising a non-temporary computer-readable medium on which the following are provided: a computer executable instruction for receiving a plurality of samples associated with a first set of dimensions characterizing a pre-processed substrate and a plurality of samples associated with a second set of dimensions characterizing a post-processed substrate; a computer executable instruction for receiving identification of one of the pre-processed dimensions and one of the post-processed dimensions to be matched; a computer executable instruction for generating a first probability distribution of samples for the identified pre-processed dimensions and a second probability distribution of samples for the identified post-processed dimensions; and a computer executable instruction for matching the samples of the identified pre-processed dimensions with the samples of the identified post-processed dimensions based on the first and second probability distributions.

[0006] In some embodiments, identification is based on finding a monotonic relationship between the value of one pre-processed dimension and the value of one post-processed dimension.

[0007] In some embodiments, the first and second probability distributions are cumulative distribution functions, and the identified pre-treated dimensions are matched with the identified post-treated dimensions based on the fact that the identified pre-treated substrate values ​​have approximately the same probability of occurrence as the identified post-treated dimensions in each cumulative distribution function.

[0008] In some embodiments, the computer program product further includes instructions for matching the values ​​of one or more remaining pre-processed dimensions with the values ​​of one or more remaining post-processed dimensions, based on matching samples of identified pre-processed dimensions and identified post-processed dimensions.

[0009] In some embodiments, the identified post-pretreatment dimensions are pre-treatment critical dimension (CD) measurements.

[0010] In some embodiments, the identified post-processing dimensions are post-processing critical dimension (CD) measurements.

[0011] In some embodiments, identified pre-processed dimension values ​​are generated using a model.

[0012] In some embodiments, the model is an ion confinement model that predicts the ion paths used to etch two stacked substrate layers.

[0013] In some embodiments, the computer program product further includes instructions for determining, based on an ion confinement model, whether ions have passed through a junction where two substrate layers are stacked, and instructions for selecting identified pre-treated dimensions to be abutted, based on the determination of whether ions have passed through the junction.

[0014] In some embodiments, it is determined that ions have passed through the junction, and the identified post-pretreatment dimensions correspond to the cross-sectional area showing the overlap between the ion path and the junction.

[0015] In some embodiments, the identified post-processing dimensions correspond to the etching volume of the lower end layer of the two substrate layers.

[0016] In some embodiments, it is determined that ions did not pass through the junction, and the identified post-pretreatment dimensions correspond to the cross-sectional area that indicates the difference between the ion path and the junction.

[0017] In some embodiments, the identified post-processing dimensions correspond to the liner loss area of ​​the sidewall.

[0018] According to some embodiments, a computer program product for evaluating a semiconductor manufacturing process is provided, the computer program product comprises a non-temporary computer-readable medium on which a computer executable instruction for receiving a dataset comprising a first plurality of samples having pre-processing dimensions that match a second plurality of samples having post-processing dimensions, wherein the first plurality of samples are matched with the second plurality of samples based on a first probability distribution of sample values ​​of one of the pre-processing dimensions and a second probability distribution of sample values ​​of one of the post-processing dimensions; a computer executable instruction for identifying a criterion for a given one of the post-processing dimensions indicating a process failure based on a value of the given post-processing dimension against a threshold; and a computer executable instruction for identifying a potential cause of a process failure based on a value of the pre-processing dimension that matches a given post-processing dimension.

[0019] In some embodiments, a given post-processing dimension value exceeding a threshold indicates a process failure.

[0020] In some embodiments, the computer program product further includes instructions for identifying modifications to pre-processing dimension values ​​that generate a value of a given post-processing dimension below a threshold.

[0021] In some embodiments, a given post-processing dimension corresponds to the liner loss area of ​​the sidewalls during etching of two stacked substrate layers.

[0022] In some embodiments, a given post-processing dimension value below a threshold indicates a process failure.

[0023] In some embodiments, the computer program product further includes instructions for identifying a shift in the value of a pre-processing dimension that generates a value of a given post-processing dimension that exceeds a threshold.

[0024] In some embodiments, a given post - processing dimension corresponds to the etch volume during the etching of two stacked substrate layers.

[0025] In some embodiments, a pre - processing dimension corresponds to the critical dimension (CD) of the junction where two substrate layers are stacked.

[0026] In some embodiments, a pre - processing dimension is the angle at which ions pass through the upper layer of two stacked substrate layers and reach the lower layer of the two stacked substrate layers.

[0027] In some embodiments, at least one of one of the pre - processing dimensions and one of the post - processing dimensions is generated by a computational model.

Brief Description of the Drawings

[0028] [Figure 1] FIG. is a schematic diagram of the use of a mating system configured to mate a pre - processed substrate sample and a post - processed substrate sample according to some embodiments of the disclosed subject matter.

[0029] [Figure 2] FIG. is a diagram showing the operation of a processor for mating a pre - processed substrate sample and a post - processed substrate sample according to some embodiments of the disclosed subject matter.

[0030] [Figure 3A] FIG. is a diagram showing exemplary data used to mate a pre - processed substrate sample and a post - processed substrate sample according to some embodiments of the disclosed subject matter. [Figure 3B] FIG. is a diagram showing exemplary data used to mate a pre - processed substrate sample and a post - processed substrate sample according to some embodiments of the disclosed subject matter. [Figure 3C] FIG. is a diagram showing exemplary data used to mate a pre - processed substrate sample and a post - processed substrate sample according to some embodiments of the disclosed subject matter.

[0031] [Figure 4A] This graph shows the separation of wafer variation from process variation as a result of comparing a pre-processed substrate sample with a post-processed substrate sample, according to several embodiments of the disclosed subject matter. [Figure 4B] This graph shows the separation of wafer variation from process variation as a result of comparing a pre-processed substrate sample with a post-processed substrate sample, according to several embodiments of the disclosed subject matter.

[0032] [Figure 5A] This is a schematic diagram of a two-layer stacked etching process according to several embodiments of the disclosed subject matter.

[0033] [Figure 5B] This figure shows the pre-processing and post-processing dimensions that can be matched for the etching process shown in Figure 5A, according to some embodiments of the disclosed subject matter. [Figure 5C] This figure shows the pre-processing and post-processing dimensions that can be matched for the etching process shown in Figure 5A, according to some embodiments of the disclosed subject matter.

[0034] [Figure 6] This is an illustrative graph for evaluating the etching process shown in Figure 5A after multidimensional sample matching, according to several embodiments of the disclosed subject matter.

[0035] [Figure 7A] Figure 5A is an illustrative graph for identifying and mitigating obstacles in the etching process, as shown in some embodiments of the disclosed subject matter. [Figure 7B] Figure 5A is an illustrative graph for identifying and mitigating obstacles in the etching process, as shown in some embodiments of the disclosed subject matter.

[0036] [Figure 8] This figure shows the operation of a processor that generates process modification recommendations according to several embodiments of the disclosed subject matter.

[0037] [Figure 9] This figure shows an exemplary computer system that may be used to implement some of the embodiments described herein. [Modes for carrying out the invention]

[0038] The following terms will be used throughout this specification.

[0039] The terms “semiconductor wafer,” “wafer,” “substrate,” “wafer substrate,” and “partially manufactured integrated circuit” may be used interchangeably. Those skilled in the art should understand that the term “partially manufactured integrated circuit” may refer to a semiconductor wafer in the midst of any of the many stages of integrated circuit manufacturing on a semiconductor wafer. Wafers or substrates used in the semiconductor device industry typically have a diameter of 200 mm, 300 mm, or 450 mm. In addition to semiconductor wafers, other workpieces that may utilize the disclosed embodiments include various articles such as printed circuit boards, magnetic recording media, magnetic recording sensors, mirrors, optical elements, display devices, or components such as backplanes for pixelated display devices, and micromechanical devices. Workpieces may vary in shape, size, and material.

[0040] As used herein, “semiconductor device manufacturing operation” refers to an operation performed during the manufacturing of a semiconductor device. Typically, the entire manufacturing process includes multiple semiconductor device manufacturing operations, each performed using its own semiconductor manufacturing tools, such as plasma reactors, electroplating cells, chemical mechanical planarization tools, and wet etching tools. Categories of semiconductor device manufacturing operations include subtractive methods, such as etching and planarization processes, and material additive methods, such as deposition processes (e.g., physical vapor deposition, chemical vapor deposition, atomic layer deposition, electrochemical deposition, electroless deposition). In the context of etching processes, a substrate etching process includes a process of etching a mask layer, or more generally, a process of etching any layer of material previously deposited on and / or present on the substrate surface. Such an etching process may etch a stack of layers within the substrate.

[0041] "Manufacturing equipment" refers to equipment in which a manufacturing process is carried out. Manufacturing equipment often has a process chamber in which a workpiece is placed during processing. Typically, when in use, manufacturing equipment performs one or more semiconductor device manufacturing operations. Examples of manufacturing equipment for semiconductor device manufacturing include deposition reactors such as electroplating cells, physical vapor deposition reactors, chemical vapor deposition reactors, and atomic layer deposition reactors, and subtractive process reactors such as dry etching reactors (e.g., chemical and / or physical etching reactors), wet etching reactors, and ashers.

[0042] As used herein, “measurement data” refers to data that is at least partially generated by measuring the features of a processed substrate. Measurements may be performed before or after semiconductor device manufacturing operations.

[0043] In some embodiments, measurement data is generated by a measurement system that performs microscopy (e.g., scanning electron microscopy (SEM), transmission electron microscopy (TEM), scanning transmission electron microscopy (STEM), reflection electron microscopy (REM), atomic force microscopy (AFM)) or optical measurements on an etched substrate. In some embodiments, measurement data is generated by performing reflectivity measurements, dome light scattering measurements, angle-resolved light scattering measurements, small-angle X-ray scattering measurements, and / or polarization analysis measurements on the processed substrate. In some embodiments, measurement data includes spectral data, for example, from energy-dispersive X-ray spectroscopy (EDX). In some cases, optical measurements are performed using a standalone or integrated optical measurement tool configured to accurately characterize one or more properties of a manufactured or partially manufactured electronic device. Such an optical measurement tool may be configured to generate a small beam spot (e.g., with a diameter of about 5 mm or less) on the substrate surface. In some embodiments, measurement data may include optical critical dimension (OCD) information corresponding to the features. As a specific example, in some embodiments, the OCD information may indicate the etching depth.

[0044] The measurement system may acquire information about the dimensions of various features such as edges, vias, trenches, and pillars (e.g., size, depth, width, area, etc.). Furthermore, the measurement system may acquire information about potential defects or faults during manufacturing, such as the amount or area of ​​protective liner removed during the etching process (e.g., sidewall liner). The measurement system may acquire information about materials contained within or on the substrate. Such information may include optical information (e.g., absorption coefficient and / or refractive index), chemical information (e.g., chemical composition and / or atomic composition), and morphological information such as crystal structure.

[0045] It should be noted that in some embodiments, the measurement may be destructive. For example, in some embodiments, the measurement values ​​obtained using a SEM system may include a delayering process in which the top layer is removed before the measurement values ​​are obtained.

[0046] Furthermore, it should be noted that measurement data may be collected before substrate processing and / or post-processing.

[0047] As used herein, the “cumulative distribution function” or CDF describes a function that represents the probability that a variable X takes a value less than or equal to x. That is, for a variable X, CDF(x) = P(X ≤ x).

[0048] In some embodiments, the CDF may be constructed empirically based on measured or observed values ​​of a variable. For example, an empirically constructed CDF may be a histogram showing the frequency of observations less than or equal to a specific value x of the variable X.

[0049] As used herein, “sample” refers to a measured value containing information about one of several different substrate surface properties. For example, a sample taken on a pre-treated wafer may include the critical dimensions of a feature, the depth of a feature, the sidewall angles of a feature, one or more optical properties of a coating on a feature, the chemical composition of a structure having a feature, and so on. Similarly, a sample taken on a post-treated substrate may include the same or different sets of surface properties of a given feature on the post-treated substrate. Each of these properties may be considered a dimension of the sample. In some discussions herein, a sample on a pre-treated substrate is represented by X, and a sample on a post-treated substrate is represented by Y. Each of the X samples has dimensions X1, X2, ... XN, each representing a different pre-treated substrate property such as CD, depth, etc. Similarly, each of the Y samples has dimensions Y1, Y2, ... YM, each representing a different post-treated substrate property, each representing a different post-treated substrate property.

[0050] Note that the notations X1, X2, ..., XN and Y1, Y2, ..., YM are used herein to represent sets of pre-processing dimensions and sets of post-processing dimensions, respectively, and should be considered to include cases where N is 1 or 2. For example, a set of pre-processing dimensions (generally referred to herein as X1, X2, ..., XN) may have only one dimension X1, or two dimensions X1 and X2. As another example, a set of post-processing dimensions (generally referred to herein as Y1, Y2, ..., YM) may have only one dimension Y1, or two dimensions Y1 and Y2. Furthermore, note that the notations X1, X2, ..., XN and Y1, Y2, ..., YM should be considered to include cases where there are a different number of pre-processing dimensions than the number of post-processing dimensions. For example, a set of pre-processing dimensions could be X1, and a set of post-processing dimensions could be Y1 and Y2. As another example, the set of pre-processing dimensions could be X1 and X2, and the set of post-processing dimensions could be Y1, Y2, and Y3.

[0051] Furthermore, it should be noted that in some embodiments, dimensions X1 and Y1 may be the same pre-treatment and post-treatment values. For example, in some embodiments, X1 may be the pre-treatment CD and Y1 may be the post-treatment CD. Conversely, in some embodiments, dimensions X1 and Y1 may be different dimensions. For example, in some embodiments, X1 may be the CD and Y1 may be the depth.

[0052] It should be noted that in some embodiments, the sample may not include values ​​for all dimensions. For example, the first sample may include values ​​for pre-processing dimensions X1, X2, ... XN. However, the second sample may lack values ​​for certain pre-processing dimensions such as X1, X2, etc.

[0053] Furthermore, it should be noted that in some embodiments, the values ​​for specific dimensions may be values ​​generated or calculated using a model, equation, or other computational representation of the physical system.

[0054] As described herein, a “butt-matching system” refers to a computational system configured to match a pre-processed substrate sample with a post-processed substrate sample. For example, a butt-matching system may be configured to match a sample j having a specific value for the pre-processed sample dimension X1 with a sample k having a specific value for the post-processed sample dimension Y1.

[0055] As a more specific example, sample j may be associated with measured values ​​for pre-processing sample dimensions X1, X2, ... XN. Continuing this example, sample k may be associated with measured values ​​for post-processing sample dimensions Y1, Y2, ... YM. The matching system may be configured to match sample j with sample k based on the values ​​of X1 and Y1, respectively. For example, sample j and sample k may be matched based on the probability distributions of X1 and Y1. In some embodiments, by matching the values ​​of X1 and Y1, the matching system may further associate the values ​​of other pre-processing sample dimensions X2, ... XN for sample j with the values ​​of other post-processing sample dimensions Y2, ... YM for sample k.

[0056] overview In some conventional analyses of semiconductor device manufacturing processes, pre- and post-processed substrates (e.g., semiconductor wafers and / or test structures) may be evaluated and characterized. Evaluation may include metrological measurements using one of several measurement techniques, such as electron microscopy, chemical analysis (e.g., emission spectroscopy), and optical measurement. In some embodiments, the measurement technique is a “top-down” process, such as critical-dimension scanning electron microscopy (CDSEM). The metrological measurements may provide information about the substrate and features formed on it. Such information may include geometric information (e.g., critical dimensions, width, sidewall angles, and feature pitch on the substrate), optical information (e.g., absorption coefficient and refractive index of coatings on the substrate), and chemical information (e.g., chemical composition of layers on the substrate).

[0057] The characterization of pre-treated and post-treated substrates may include statistical representations of the measured values ​​performed on each substrate. These statistical representations may include, for example, the central trend (e.g., mean), variance, and / or other properties of the distribution of measured characteristics for the pre-treated and post-treated substrates.

[0058] Unfortunately, these existing methods only provide an overall overview of the substrate characteristics. This overall overview does not match the substrate characteristics within each individual pre- and post-processed substrate. For example, the overall overview does not match the substrate characteristics for a given feature or location on the substrate after pre- and post-processing. In other words, these techniques do not achieve a one-to-one match of pre- and post-processed substrate surface characteristics.

[0059] As a result, much information that would be invaluable to process designers and other personnel responsible for developing, maintaining, and / or modifying processes is unavailable. For example, existing methods make it difficult or impossible to isolate the effects of resulting wafer variations (e.g., some features on a given pre-treated substrate being deeper than others) and process conditions. In other words, the observed conditions for a post-treated substrate may be a result of the substrate conditions of the pre-treated wafer and / or one or more process conditions used during substrate processing, but existing methods do not isolate these effects. Without knowing how a given feature on the pre-treated substrate corresponds to that identical feature on the post-treated substrate, it is essentially impossible to identify the effects of point-to-point variations on the surface of the pre-treated substrate after modifications through the process under consideration.

[0060] In some embodiments, sample locations from pre-treated and post-treated substrates are matched without requiring that the measurement values ​​of the pre-treated and post-treated substrates be measured at the same location.

[0061] To understand how this process works, it is important to understand that both the pre-processed and post-processed substrates are evaluated by a series of samples (for example, a series of measurements taken at different locations on the substrate). Each sample is a separate measurement, such as a separate CDSEM measurement, at a location on the substrate.

[0062] Each sample is a measured value containing information about one of several different substrate surface characteristics. For example, a sample taken on a pre-treated wafer may include the critical dimension (CD) of a feature, the depth of the feature, the sidewall angle of the feature, one or more optical properties of the coating on the feature, the chemical composition of the structure having the feature, etc. Similarly, a sample taken on a post-treated substrate may include the same or different sets of surface characteristics of a given feature on the post-treated substrate. Each of these characteristics may be considered a dimension of the sample. In some discussions herein, a sample on a pre-treated substrate is represented by X, and a sample on a post-treated substrate is represented by Y. Each of the X samples has dimensions X1, X2, ... XN, each representing a different pre-treated substrate characteristic such as CD, depth, etc. Similarly, each of the Y samples has dimensions Y1, Y2, ... YM, each representing a different post-treated substrate characteristic, each representing a different post-treated substrate characteristic.

[0063] It should be noted that measurement information does not need to be limited to a single feature; rather, it can include information from a set of adjacent features. One example is an optical signal taken from a regularly repeating structure on a memory cell, where the regularly repeating features act as a diffraction grating, generating a signal that can be measured and analyzed using optical measurement.

[0064] In some implementations, samples from a pre-processed substrate are matched against samples from a post-processed substrate. The matching may be based on a criterion for matching individual samples from the pre-processed substrate against identical or similar samples from the post-processed substrate.

[0065] In some embodiments, the processes described herein analyze sample data of pre-treated and post-treated substrates to identify dimensions of such samples that vary monotonically with respect to each other. That is, pre-treated sample dimensions (referred to herein as X1) and post-treated sample dimensions (referred to herein as Y1) are identified such that the sample value of Y1 is a monotonic result of the sample value of X1. A particular example of X1 is the upper edge CD of a high-aspect-ratio hole before the etching process is performed, and Y1 is the etching depth after the etching process is performed. The dimensions are given in the form of a histogram plotting their abundance as a function of the values ​​of the dimensions under consideration. Such a histogram may be given as a cumulative distribution function corresponding to a probability density function for the dimensions under consideration.

[0066] After identifying and selecting the dimensions (X1) from a pre-processed wafer sample and the corresponding dimensions (Y1) from a post-processed substrate sample such that X1 and Y1 satisfy the monotonicity requirement, the sample values ​​corresponding to these two dimensions are matched. The matching can be performed by identifying the values ​​of the X1 and Y1 dimensions from the pre-processed and post-processed substrate samples that have the same or nearly similar relative abundance values ​​in the cumulative distribution function.

[0067] Based on the matched sample values, pairs of pre-treated and post-treated samples may be matched. After the pre-treated and post-treated sample pairs are matched, other pre-treated and post-treated dimensions of the matched samples (e.g., X2, Y2, X3, Y3, etc.) may be similarly linked based on this pairing. Using this information, the entire set of dimensions of all samples in the pre-treated and post-treated substrates can now be matched or linked to each other.

[0068] This information can be used to determine how individual features with different properties on the pre-processed substrate affect corresponding features in the post-processed substrate. Similarly, the effects of process variations on individual features of the substrate can be identified. In other words, this abundance matching method makes it possible to separate the effects of feature variations on the pre-processed wafer from process condition variations. Furthermore, by identifying the effects of process variations on individual features of the substrate, process engineers can identify process modifications that produce specific feature properties.

[0069] In some embodiments, dimensions X1, X2, ..., XN for a post-processed substrate sample are generated using a model of a physical process or other representation, either in place of or in conjunction with measured values. Similarly, in some embodiments, dimensions Y1, Y2, ..., YM for a post-processed substrate sample are generated using a model of a physical process or other representation, either in place of or in conjunction with measured values. For example, an ion confinement model can calculate the ion flux for a particular area or volume of a feature, given the location and / or geometric configuration of the feature on the substrate. When using a model of a physical process or other representation instead of measured values, the matching can still be performed as described above.

[0070] Matching of pre-processed substrate sample and post-processed substrate sample. Pre-processed substrate samples and post-processed substrate samples can be matched in such a way that pre-processed substrate features and post-processed substrate features are matched one-to-one.

[0071] Samples may be received that are associated with a set of pre-processing dimensions X1, X2, ... XN that characterize the pre-processed substrate. In some embodiments, each sample may be associated with a specific measurement, such as a CDSEM measurement. Each dimension is a different type of pre-processing feature property, such as the CD of the feature before processing. Similarly, samples may be received that are associated with a set of post-processing dimensions Y1, Y2, ... YM that characterize the post-processed substrate, each dimension being a different type of post-processing feature property, such as the CD of the feature on the processed substrate, the etching depth, area, or volume after the etching process has been performed, the area of ​​the protective liner etched off after the etching process, or the amount of strain indicating the degree of torsion of a hole-type feature.

[0072] Pre-processing dimension X1 and post-processing dimension Y1 can be identified, and the identified X1 and Y1 correspond to the dimensions for which sample values ​​should be matched. X1 and Y1 can be identified such that Y1 is a monotonic result of X1. A particular example is when, after the etching process has been carried out, X1 corresponds to the CD of the trench opening and Y1 corresponds to the depth of the trench.

[0073] A probability distribution corresponding to the sample values ​​of the pre-processing dimension X1 and a probability distribution corresponding to the sample values ​​of the post-processing dimension Y1 can be generated. For example, each probability distribution may be a cumulative distribution function (CDF). As a more specific example, the CDF(x) for X1 is the sample value x drawn from X1. j This can show the probability P that is less than the value x. Similarly, CDF(y) for Y1 is the sample value y drawn from Y1. k This can show the probability P that is less than the value y. Note that while the examples described herein generally use the cumulative distribution function, other types of probability functions such as the complementary cumulative distribution function, tail distribution, or quantile function may also be used.

[0074] The received samples can be matched based on the probability distributions of X1 and Y1. In particular, samples with a specific probability value in the probability distribution of X1 can be matched with samples with approximately similar or identical probability values ​​in the probability distribution of Y1. That is, samples are matched based on their respective values ​​for the dimensions of X1 and Y1 that have similar or identical abundances in the density distributions of X1 and Y1, where the abundances are represented by the CDF of X1 and the CDF of Y1, respectively.

[0075] The matched samples can be analyzed to determine the sensitivity of the process that generated the samples, and / or the process margin of the process that generated the samples. For example, for a particular process, such as a specific etching process, the matched samples may show how sensitive a particular post-processing dimension is to variations in pre-processing dimension values.

[0076] Figure 1 shows a matching system configured to receive a pre-processed substrate measurement sample 102 and a post-processed substrate measurement sample 104. The pre-processed substrate measurement sample 102 corresponds to the pre-processing CD measurement value, and the post-processed substrate measurement sample 104 corresponds to the post-processing CD measurement value. Note that the pre-processed substrate measurement sample 102 may be collected from the same location as the post-processed substrate measurement sample 104, or from different locations. For example, as shown in Figure 1, the pre-processed substrate measurement sample may be collected from a location including the pre-processing location 106. Continuing this example, the post-processed substrate measurement sample may be collected from a location including the post-processing location 108.

[0077] The butt-matching system 100 is configured to match a pre-processed substrate measurement sample 102 with a post-processed substrate measurement sample 104 to generate a post-butt-matched sample as shown in graph 110. In practice, the post-butt-matched sample shows the effect of the value of the pre-processed substrate measurement sample 102 on the value of the post-processed substrate measurement sample 104. For example, as shown in Figure 1, the post-butt-matched sample shows the effect of the pre-processed CD measurement value on the post-processed CD measurement value.

[0078] Graph 110 shows the relationship between post-treatment CD and pre-treatment CD for various different processes, with pre-treatment and post-treatment samples for each process being compared. For each process shown in Graph 110, the relationship between post-treatment CD and pre-treatment CD can be considered linear and can be represented by a slope. The slope indicates the process margin or process sensitivity of the process. For example, slope 112 is shallower than slope 114, indicating that the process corresponding to slope 112 is less sensitive to variations in pre-treatment CD than the process corresponding to slope 114.

[0079] Referring to Figure 2, flowcharts illustrating operations that may be performed by a processor to match a pre-processed substrate sample with a post-processed substrate sample are shown according to some embodiments of the disclosed subject.

[0080] In 202, pre-processing samples associated with a set of pre-processing dimensions X1, X2, ... XN and post-processing samples associated with a set of post-processing dimensions Y1, Y2, ... YM may be received.

[0081] Each sample may correspond to a set of measurements or values ​​at a specific location on the wafer before processing (in the case of a pre-processed sample) or after processing (in the case of a post-processed sample). In some embodiments, the measurements or values ​​may be measured values ​​taken using any suitable measurement system (e.g., CDSEM, XSEM, HVSEM, etc.). For example, the measured values ​​may be CDs of specific lines, edges, trenches, vias, holes, pillars, etc. In some embodiments, as will be described in more detail in relation to Figures 5A, 5B, and 5C, the values ​​may be calculated values ​​derived from equations, sets of equations, or models.

[0082] Each dimension may represent a different characteristic of the feature. Dimensions corresponding to feature characteristics may include pre-treatment CD, post-treatment CD, etching depth, etching volume, the amount or area of ​​protective liner etched off during the etching process, and gradient (e.g., high aspect ratio structure or structural gradient of the feature before etching).

[0083] It should be noted that a minimum number of pre-processed and / or post-processed samples may be required to perform the matching technique shown in blocks 204-210 and described below in relation to blocks 204-210. For example, the matching technique may require enough samples to determine that values ​​of various dimensions meet certain criteria, such as that the sample distribution is stationary. In some embodiments, expected sample variances, such as Poisson variance, may be calculated to determine whether the derived CDF of the samples is likely to be stable. In some embodiments, the process terminates in response to determining that the minimum required number of samples have not been received in block 202.

[0084] Figure 3A shows an illustrative table illustrating values ​​associated with different pre-treatment and post-treatment dimensions for a group of samples, according to several embodiments of the disclosed subject matter.

[0085] Table 302 shows values ​​for four samples (0, 1, 2, and 3) for three pre-processing dimensions (X1, X2, and X3). Table 304 shows values ​​for four samples (0, 1, 2, and 3) for three post-processing dimensions (Y1, Y2, and Y3). Note that while Tables 302 and 304 each show four samples labeled 0, 1, 2, and 3, the four samples shown in Tables 302 and 304 do not necessarily correspond to each other. For example, sample 0 in Table 302 does not necessarily have any relationship to sample 0 in Table 304.

[0086] Returning to Figure 2, at 204, the identification of one pre-treated sample dimension and one post-treated sample dimension to be used for butt joint is received. Note that the identified pre-treated sample dimension is referred to herein as "X1" and the identified post-treated sample dimension is referred to herein as "Y1".

[0087] In some embodiments, X1 and Y1 may be required to satisfy any appropriate criteria. For example, in some embodiments, the distributions of the values ​​of X1 and Y1 may be required to be stationary. As another example, in some embodiments, the values ​​of Y1 may be required to have a monotonic relationship with X1. That is, in some embodiments, the observed values ​​of Y1 may be the result of X1 having a monotonic relationship. Note that X1 and Y1 do not need to have similar distribution characteristics, do not need to extend similar ranges, or have other relationships other than being monotonic and stationary.

[0088] In a specific example, X1 may be the CD of the opening before the etching process, and Y1 may be the etching depth after the etching process. In another specific example, X1 may be the CD of the feature before processing, and Y1 may be the CD of the feature after processing. Additional specific examples are shown in Figures 5A, 5B, and 5C, and are described below in relation to Figures 5A, 5B, and 5C.

[0089] In some embodiments, X1 and Y1 can be identified manually, for example, by a process engineer. Alternatively, in some embodiments, X1 and Y1 can be identified algorithmically. For example, X1 and Y1 can be identified algorithmically as dimensions having values ​​that satisfy the aforementioned criteria.

[0090] In step 206, the probability distribution of the sample for X1 and the probability distribution of the sample for Y1 can be generated.

[0091] For example, in some embodiments, each probability distribution may be represented as a histogram showing the frequency of samples below a particular value. Thus, such a probability distribution may be regarded as a cumulative distribution function corresponding to the area under the probability density function for each dimension.

[0092] Note that the examples discussed herein use cumulative distribution functions, but in some embodiments, other types of probability distributions may be used. For example, a complementary cumulative distribution function or tail distribution showing the probability that a sample exceeds a particular value may be used. As another example, an inverse cumulative distribution function or quantile function showing the sample value associated with a particular probability in a cumulative distribution function may be used.

[0093] As a more specific example, FIG. 3B shows an exemplary X1 histogram 306 and an exemplary Y1 histogram 308. As shown, the X1 histogram 306 shows the probability that a sample value from X1 is less than a given value x of X1. Similarly, the Y1 histogram 308 shows the probability that a sample value from Y1 is less than a given value y of Y1.

[0094] Returning to FIG. 2, at 208, for the X1 sample values, matching Y1 sample values can be identified based on the probability distributions of X1 and Y1. That is, the sample values can be matched based on having the same or nearly similar abundances in their respective cumulative distribution functions.

[0095] For example, returning to FIG. 3B and referring to the X1 histogram 306, the value x of X1 for which P(X1 < x) = 0.4 is approximately -0.4. Thus, a sample j of X1 having a value of -0.4 can be matched with a sample k from the Y1 distribution for which P(Y1 < y) = 0.4. Referring to the Y1 histogram 308, the matching sample k can be identified as a sample k having a value of approximately -0.2.

[0096] Returning to Figure 2, in some embodiments, when a pre-processed substrate sample is matched against a post-processed substrate sample, the probability that a pre-processed substrate sample matches a particular post-processed substrate sample can be calculated. For example, the probability that sample j associated with dimension X1 matches sample k associated with dimension Y1 can be calculated. In some embodiments, match probabilities can be calculated for multiple potential samples, and the matching sample can be identified based on the highest match probability. For example, for a particular sample j, the probability that j matches samples k1, k2, and k3 can be calculated. Continuing this example, sample j may be matched against one of k1, k2, and k3 based on the highest match probability assigned to each of k1, k2, and k3.

[0097] It should be noted that the probability that sample j matches sample k can be calculated, and the corresponding probability that sample k matches sample j can be further calculated. In general, the two probabilities may be nearly the same or identical. In some examples, a substantial difference between the two probabilities may indicate that the sample size used to construct the underlying CDF is not large enough, and / or that the underlying sample is not stationary.

[0098] In block 210, the sample values ​​of the remaining pre-processing sample dimensions X2, ... XN and the sample values ​​of the remaining post-processing sample dimensions Y2, ... YM can be linked based on the post-matched sample values ​​matched for X1 and Y1. Note that in some embodiments, block 210 may be omitted.

[0099] Figure 3C shows an exemplary table with samples butted across all dimensions.

[0100] As shown in line 310, the pre-processed sample index 0 is matched with the post-processed sample index 332. In this example, the pre-processed sample index 0 is matched with the post-processed sample index 332 based on the probability distributions of X1 and Y1. That is, the pre-processed sample index 0 is matched with the post-processed sample index 332 based on the fact that the cumulative distribution probability value P(X1=1.76)=0.93 matches the cumulative distribution probability value P(Y1=0.61)=0.93. Note that a probability of 0.931 is assigned to the match of the pre-processed sample index 0 with respect to the post-processed sample index 332. Similarly, a probability of 0.93 is assigned to the match of the post-processed sample index 332 with respect to the pre-processed sample index 0.

[0101] Furthermore, with respect to row 310, note that sample values ​​for X2, X3, Y2, and Y3 are included in the table to show that the values ​​of X2, X3, Y2, and Y3 can be similarly associated after matching pre-processed sample index 0 with post-processed sample index 332. In other words, even if the distribution of dimensions X2, X3, Y2, and Y3 does not meet the criteria described above in relation to block 204, the dimensions of X2, X3, Y2, and Y3 can be associated by matching the sample using the dimensions of X1 and Y1, and by simply associating it with the sample matched using the dimensions of X1 and Y1.

[0102] Returning to Figure 2, the process may terminate at 212.

[0103] After linking the remaining pre-processing sample dimensions with the remaining post-processing sample dimensions, a multidimensional dataset of the post-butt samples is created. This dataset can be used for many purposes, such as isolating and identifying the effect of specific pre-processing dimensions on specific post-processing dimensions, identifying specific pre-processing dimension values ​​that are likely to cause faults or defects, indicated by specific post-processing dimension values, and identifying changes to pre-processing dimension values ​​that can mitigate process failures. The use of the multidimensional dataset is shown in Figure 8 and is described below in relation to Figure 8.

[0104] Furthermore, in some cases, the post-butt sample dataset may be missing values ​​for some samples and / or some dimensions. In some cases, the relationship between pre-processing dimensions and post-processing dimensions can be used to interpolate or extrapolate the missing values. For example, in cases where the post-butt sample dataset indicates that the relationship between pre-processing dimension X1 and post-processing dimension can be considered linear, the missing value for Y1 for a particular sample can be calculated based on the linear relationship, using known or measured values ​​for X1 for that sample. Conversely, the missing value for X1 can be calculated in a similar manner.

[0105] Referring to Figures 4A and 4B, graphs illustrating how the aforementioned matching pre- and post-processing samples can separate wafer variation from process variation are shown according to some embodiments of the disclosed subject.

[0106] Figure 4A shows graphs of post-processing CD for three processes (Process 1, Process 2, and Process 3) as a function of pre-processing CD, where the three processes are identical, but there is potential wafer population variation for the three processes (e.g., due to differences in sampling and / or potential differences in the substrate surface before processing). After sample matching (e.g., using the technique described above in relation to Figure 2), the relationship between post-processing CD and pre-processing CD is identical for all three processes, which should be expected without process variation. This indicates that the sample matching technique can correctly match pre-processed substrate samples with post-processed substrate samples regardless of potential wafer population variation when there is no process variation.

[0107] Conversely, referring to Figure 4B, if the three processes are different (for example, using different setpoints or different recipes), the three processes can be clearly distinguished after comparing the pre-processed and post-processed samples.

[0108] Note that the different process slopes shown in Figure 4B may indicate the process sensitivity or process margin. For example, a process with a steeper slope can be said to be more sensitive (or have a smaller process margin) than a process with a shallower slope.

[0109] Two-layer stacking etching process Figures 5A, 5B, 5C, 6, 7A, and 7B show the techniques and data for butting pre-treated and post-treated samples using the butt technique described above in relation to Figure 2, relating to a two-layer stacking etching process. In particular, ions are used to etch the "dimples" of the lower layer that are stacked on top of the upper layer, and the upper and lower layers are stacked before the etching process. Note that the point where the upper and lower layers are stacked is referred to herein as the "junction".

[0110] Figure 5A shows a schematic diagram of the two-layer stacking etching process and related parameters.

[0111] Measurement values ​​502 show the upper and lower layers of a wafer processed using a two-layer stack etching process. In particular, measurement values ​​502 include HVSEM of the upper layer 504 and HVSEM of the lower layer 506. Note that both the upper and lower layers may contain high aspect ratio holes, and these holes have a relatively high depth-to-width CD ratio.

[0112] The dimples in the lower layer 506 can be etched by ions passing through the upper hole 508 to the lower layer. In some embodiments, the upper hole 508 may have a CD in the range of about 20–60 nanometers, about 30–50 nanometers, etc. After passing through the upper layer, the ions can then etch the dimples in the lower layer. In some embodiments, the dimples may have etching depths in the range of about 0–70 nanometers, about 20–50 nanometers, about 0–20 nanometers, etc. Each dimple may be described as having a dimple volume which is the product of the etching depth and the etching area. It should be noted that a protective liner may be attached to the sidewall portions associated with the dimples, and the protective liner may be attached before the etching process. Ideally, the etching process produces dimples with the desired etching depth without etching away or damaging the protective liner on the sidewalls.

[0113] Each ion follows an ionic pathway 510. The ionic pathway 510 is confined by a deposition process performed before the etching process. The junction 512 indicates the region where the upper and lower layers are stacked. The CD of the junction 512 may be in the range of approximately 30–50 nanometers, approximately 35–45 nanometers, etc.

[0114] However, in some cases, the ion path may have a tilt angle 514. For example, the tilt angle 514 may be introduced between the stacking of the upper and lower layers, such as when the upper and lower layers are not aligned with respect to the junction. The tilt angle 514 may introduce an offset of the ion path 510 relative to the junction 512. This offset may be characterized by an offset radius 518. The overlapping portion between the ion path 510 and the junction 512 is shown as an overlapping area 520.

[0115] It should be noted that the overlapping area 520 corresponds to the dimples to be etched. In some embodiments, the overlapping area 520 may correspond to the pre-processing dimensions that are matched with the post-processing dimensions of the dimple volume, as described below in relation to Figure 5B. The non-overlapping area 522 shown in Figure 5A corresponds to the area where the ion path 510 does not overlap with the junction 512. Thus, the non-overlapping area 522 may correspond to the area where the protective liner of the sidewall is etched away. In some embodiments, the non-overlapping area 522 may correspond to the pre-processing dimensions that are matched with the post-processing dimensions of the liner loss area, as described below in relation to Figure 5C.

[0116] In some embodiments, the dimensional values ​​used to match the pre-treated and post-treated samples may be calculated or generated using a model. Figures 5B and 5C show diagrams for calculating values ​​for the pre-treated dimension X1 using the ion confinement model for the two-layer stacking etching process shown in Figure 5A and described above in relation to Figure 5A.

[0117] Figure 5B shows the dimensions used to align the pre-treated and post-treated samples when the ion path from the upper layer to the lower layer overlaps with the desired junction location.

[0118] Graph 530 shows the calculated overlap area 532, which is used as the value for the X1 dimension used for butt joint. The overlap area 532 is a scalar value that indicates the area where dimples generated by ions used for etching overlap with the joint, as shown in Figure 5A and described above in relation to Figure 5A.

[0119] The overlapping area 532 is calculated using an ion confinement model that computes the value of the overlapping area 532. The ion confinement model may include any suitable equation or other expression that encompasses the positions of ions reaching the lower layer, for example, having a specific slope angle, temperature information, ion species information, etc. As a more specific example, the overlapping area 532 may be calculated based on geometric information obtained from the upper and lower layer HVSEM images, such as the HVSEM of the lower layer 502 and the HVSEM of the upper layer 504.

[0120] In some embodiments, the Y1 dimension used for butt joints may be the volume of the resulting dimple on the lower layer, as shown in Graph 534. The dimple volume may be calculated based on measured values ​​of the etching area and etching depth.

[0121] Figure 5C shows the dimensions used to align the pre-treated and post-treated samples when the ion pathways do not overlap with the desired junction location.

[0122] Graph 540 shows the calculated mis-area 542, which is used as the value for the X1 dimension used for butt joints. The mis-area 542 is a scalar value that indicates the area where ions are outside the junction location. Similar to the one described above in relation to the overlapping area 532 in Figure 5B, the mis-area 542 can be calculated using an ion confinement model.

[0123] In some embodiments, the Y1 dimension used for butt joints may be a measured value indicating the liner loss area. The liner loss area represents the area of ​​the protective liner on the etched-off sidewall. Graph 544 shows a liner loss area calculation that can be used as Y1 to match a value.

[0124] From Figures 2 and 3C, it should be noted that after the pre-processed and post-processed samples are matched using the dimensions X1 and Y1, the values ​​of other dimensions (X2, X3, Y2, Y3, etc.) are similarly associated. Therefore, the resulting dataset is multidimensional, with the pre-processed sample matching the post-processed sample along with matched values ​​for multiple pre-processed and post-processed dimensions.

[0125] Multidimensional relationships can be analyzed for multiple purposes, such as identifying pre-processing dimension shifts or modifications that mitigate or reduce the likelihood of process failures. Note that Figures 6, 7A, and 7B show a matched multidimensional dataset and the use of the matched multidimensional dataset for failure mitigation in the two-layer stack etching process, as shown in and related to Figures 5A, 5B, and 5C and described above. Figure 8 shows a generalized illustrative flowchart for using a matched multidimensional dataset for failure mitigation.

[0126] Figure 6 shows a multidimensional plot that can be constructed to illustrate the multidimensional relationship between pre-processed sample dimensions and post-processed sample dimensions for the two-layer stacking etching process described above in relation to Figures 5A, 5B, and 5C.

[0127] Graph 602 shows the multidimensional relationship when the ion path overlaps with the location of the desired junction. (As shown in Figure 5B) In such cases, the matching relationship is calculated using the X1 dimension of the overlapping area (between the ion path and the junction) and the Y1 dimension of the dimple volume, and it should be noted that the overlapping area is calculated using the ion confinement model.

[0128] In some embodiments, the pre-processing dimensions may further include a tilt angle (X2) and a joint CD (X3). The tilt angle (shown in Figure 5A) describes the angular deviation from the vertical path of a straight line, and the joint CD describes the CD where two stacked layers are joined. As described above in relation to Figures 2 and 3C, after the samples are butted using the values ​​of dimensions X1 and Y1, the sample values ​​corresponding to the dimensions X2 and X3 may be coupled accordingly. Thus, Graph 602 shows the dimple volume (i.e., the Y1 value) as a function of the tilt angle (i.e., the X2 value) and the joint CD (i.e., the X3 value) after the dimensions X2 and X3 have been coupled.

[0129] Graph 604 shows the multidimensional relationship when the ion path does not overlap with the desired junction location (as shown in Figure 5C). In such cases, the matching relationship is obtained using the X1 dimension of the misarea and the Y1 dimension of the liner loss area, and it should be noted that the misarea is calculated using the ion confinement model.

[0130] In some embodiments, the pre-processing dimensions may further include the inclination angle (X2) and joint CD (X3) as described above in relation to Graph 602. As described above, after the samples are butted using the values ​​of dimensions X1 and Y1, the sample values ​​corresponding to dimensions X2 and X3 may be associated accordingly. Thus, Graph 604 shows the liner loss area (i.e., Y1 value) as a function of the inclination angle (i.e., X2 value) and joint CD (i.e., X3 value) after the dimensions X2 and X3 have been associated.

[0131] Figure 7A shows contour plots that can be used to identify modifications to process parameters to reduce the number of failures associated with the two-layer stack etching process described above, as shown in Figures 5A, 5B, and 5C.

[0132] In some embodiments, defects may be classified based on the value of any suitable post-processing feature that satisfies a specific defect criterion. For example, with respect to a two-layer stack etching process, defects may be classified when 1) the dimple volume is less than a threshold dimple volume, and / or 2) the liner loss area exceeds a threshold liner loss area. In some embodiments, defects may be binary, such that wafers that satisfy either of the above defect criteria (i.e., not meeting the minimum dimple volume or exceeding the maximum liner loss area) are classified as defective, and conversely, wafers that do not meet either of the above defect criteria are classified as satisfactory or not defective.

[0133] The contour plot 702 in Figure 7A shows the distribution of features on the wafer classified as faults as a function of specific values ​​of slope and junction CD. Note that in contour plots 702 and 704, region 706 shows a higher density distribution of features, and fault zone 708 shows areas on the wafer where features are generally classified as faults.

[0134] The contour plot 704 in Figure 7A shows the distribution of wafers classified as faulty as a function of identified recommended values ​​for tilt and junction CD. Recommended values ​​may represent recommendations to keep the tilt angle below a specific value (e.g., less than 5 nanometers, less than 3 nanometers, etc.) and / or to increase the junction CD by a specific amount (e.g., 1 nanometer, 2 nanometers, etc.). Note that the faulty zone in contour plot 704 shifts as a result of the recommended changes to the tilt and / or junction CD, so that a higher percentage of wafers are classified as passable.

[0135] It should be noted that contour plot 704 can be generated based on graphs 602 and 604 in Figure 6. For example, dimple volume impairment can be classified as a dimple volume below the dimple volume threshold. Continuing this example, a plane section at the level of the dimple volume threshold on graph 602 can be used to identify the slope and junction CD values ​​that produce a dimple volume impairment and, conversely, a satisfactory dimple volume. Further continuing this example, liner loss area impairment can be classified as a liner loss area exceeding the liner loss threshold. Further continuing this example, a plane section at the level of the liner loss threshold on graph 604 can be used to identify the slope and junction CD values ​​that produce a liner loss area impairment and, conversely, a satisfactory amount of liner loss. Contour plot 704 can then be constructed by superimposing the graphs generated by the plane sections of graphs 602 and 604.

[0136] Figure 7B shows graphs constructed from pre- and post-processing samples after multidimensional butt jointing, where butt jointing is performed on the entire wafer sample.

[0137] Graphs 750 and 752 show post-tie samples using two different stacking etching processes, respectively. In each of graphs 750 and 752, two entire wafers are analyzed, and the wafer variation between the two wafers is greater for the wafer associated with graph 752 than for the wafer associated with group 750. In graphs 750 and 752, the z-axis corresponds to the failure rate based on calculations used to generate contour plots 702 and 704, and the x and y axes correspond to the x and y wafer coordinates, respectively. Note that for each of graphs 750 and 752, each process is performed twice, and the matching of the pre-processed and post-processed samples is performed on the entire wafer sample.

[0138] Graphs 750 and 752 further show contour plots 762 and 764, respectively, which correspond to the contour plots in the plane of graphs 750 and 752.

[0139] As shown in graphs 750 and 752, process variations can be separated from wafer variations even when the matching is performed on the entire wafer sample after the pre-processed and post-processed samples have been matched. Contours 754–760 in graphs 750 and 752 each represent failure analyses of different wafers. In particular, with respect to graph 750, if the two wafers being analyzed are similar, the failure rates associated with each of the two wafers are similar, as shown by the similar contours 754 and 756. Continuing further, graph 752 shows different failure rates associated with each of the wafers being analyzed to produce graph 752 (as shown by contours 758 and 760), and the different failure rates are due to greater wafer variations between the two wafers. Furthermore, variations between the etching process associated with Graph 750 and the etching process associated with Graph 752 can be observed due to the difference between contour lines 754 and 756 in Graph 750 and contour lines 758 and 760 in Graph 752.

[0140] Generating recommendations to mitigate the problem Referring to Figure 8, flowcharts illustrating the operation of the processor for generating recommendations to mitigate failures based on post-match pre-processing and post-processing samples are shown according to several embodiments of the disclosed subject matter.

[0141] In 802, a dataset of multidimensional post-matched samples may be received, with each sample associated with sample values ​​for pre-processed sample dimensions (e.g., X1, X2, ...XN) and post-processed sample dimensions (e.g., Y1, Y2, ...YM). For example, the received dataset may be in a format similar to that described above in relation to the table in Figure 3C. In some embodiments, the dataset may be in a format similar to that shown in Figure 2 and described above in relation to Figure 2.

[0142] In 804, instructions for failure criteria may be received. In some embodiments, the failure criteria may indicate thresholds for specific post-processing dimensions (e.g., Y1, Y2, ..., YM) that constitute a failure of the post-processed substrate. Exemplary failure criteria may include etching depths less than a threshold depth, post-processing CD less than a desired CD, and so on.

[0143] As a more specific example, as described above in relation to the two-layer stacking etching process in Figure 7A, the failure criteria may include a dimple volume below a minimum volume threshold and / or a liner loss area exceeding a liner loss threshold. It should be noted that this is merely illustrative, and in some embodiments, the failure criteria may be specific to any suitable process.

[0144] In some embodiments, failure criteria may be specified manually, for example, by a process engineer. Additionally or alternatively, in some embodiments, failure criteria may be retrieved from a database, such as a failure database, that contains specifications for various manufacturing processes.

[0145] In 806, pre-processed sample dimensions that are likely to cause defects can be identified based on defect criteria and a dataset of multidimensional post-butt samples. Note that pre-processed sample dimensions can be identified as dimensions that can be practically controlled or modified, such as pre-processed CD and inclination angle.

[0146] For example, a graph can be constructed that plots the value of the post-processing dimension as a function of the value of one or more pre-processing dimensions. Continuing this example, a plane corresponding to a horizontal cross-section of the graph may be used to identify the value pre-processing sample dimension, and the plane is positioned at the z-axis value corresponding to the fault threshold.

[0147] As a specific example, if a wafer is classified as faulty when its dimple volume is below a minimum dimple volume threshold, then the plane may be located at the minimum dimple volume threshold (i.e., on graph 602 in Figure 6). Continuing with this specific example, then the tilt angle and junction CD values ​​that produce a dimple volume below the plane (i.e., below the minimum dimple volume threshold) can be identified.

[0148] As another specific example, if a wafer is classified as faulty when the liner loss area exceeds the maximum allowable loss threshold, the plane may be located at the maximum allowable loss threshold (i.e., on graph 604 in Figure 6). Continuing with this specific example, the tilt angle and junction CD values ​​that produce liner loss area above the plane (i.e., above the maximum allowable loss threshold) can then be identified.

[0149] In some embodiments, block 808 may identify one or more modifications to the pre-processed sample dimension values ​​in order to reduce the number of defects and / or shift the defect distribution. For example, in some embodiments, pre-processed sample dimension values ​​that are likely to produce post-processed sample dimension values ​​that are not classified as defects may be identified. Note that in some embodiments, block 808 may be omitted.

[0150] As a more specific example, with respect to a multidimensional butt-jointed sample of the two-layer stack etching process shown in Figure 6 and described above in relation to Figure 6, tilt angles and / or junction CDs that are less likely to produce dimple volumes classified as faults (i.e., below the minimum allowable dimple volume threshold) can be identified. As another more specific example, tilt angles and / or junction CDs that are less likely to produce liner loss areas classified as faults (i.e., exceeding the maximum allowable liner loss) can be identified.

[0151] After identifying one or more modifications to the sample dimensions after pretreatment, recommendations indicating the identified modifications may be presented. For example, recommendations such as shifting or increasing the pretreatment CD by a certain amount, or keeping the inclination angle below a certain amount, may be presented (e.g., to a process engineer).

[0152] The process may terminate with an error code of 810.

[0153] Applicable By mapping pre-processed substrate features to post-processed substrate features, the techniques described herein enable process engineers to isolate the effects of wafer variations from process variations. In particular, by isolating the effects of wafer variations from process variations, process engineers can evaluate various characteristics of a particular process, such as the process's sensitivity to changes in one or more process conditions.

[0154] Furthermore, a relationship between post-treatment dimensions (e.g., post-treatment CD, etching depth or volume, liner loss area, etc.) and pre-treatment dimensions (e.g., pre-treatment CD, ion gradient, etc.) may be provided so that process engineers can identify the effect of changes in specific pre-treatment dimensions on the post-treatment dimensions in question. In a particular example, if the liner loss area on the sidewall during the etching process should be minimized, the process engineer can use the relationship between the liner loss area and one or more pre-treatment dimensions (e.g., ion gradient during etching, pre-treatment CD, etc.) to identify the optimal value of the pre-treatment dimension to minimize the liner loss area.

[0155] Therefore, the techniques described herein for matching pre-processed substrate features to post-processed substrate features can improve the manufacturing process by enabling process engineers to quickly identify the effects of process condition changes on the wafer that provide improved post-processed substrate features. For example, by identifying the relationship between pre-processed and post-processed dimensions, process engineers do not need to rely on trial and error to identify potential process condition changes, thus saving time and other resources.

[0156] Context of the disclosed computational embodiments Some embodiments disclosed herein relate to a computational system for matching pre-processed substrate samples with post-processed substrate samples.

[0157] Many types of computing systems having any of the various computer architectures can be used as disclosed systems for implementing algorithms such as those described herein. For example, a system may include software components running on one or more general-purpose processors, or on specially designed processors such as application-specific integrated circuits (ASICs) or programmable logic devices (e.g., field-programmable gate arrays (FPGAs)). Furthermore, a system may be implemented on a single device or distributed across multiple devices. The functions of the computing elements may be merged with each other or further divided into multiple submodules.

[0158] In some embodiments, code executed during the generation or execution of a technique for matching sample dimensions on a properly programmed system may be embodied as a software element that can be stored in a non-volatile storage medium (such as an optical disc, flash memory device, or mobile hard disk), which includes several instructions for creating a computer device (such as a personal computer, server, or network equipment).

[0159] At level 1, software elements are implemented as a set of commands prepared by the programmer / developer. However, module software that can be executed by computer hardware is executable code that is committed to memory using a specific set of machine language instructions, or "machine code," selected from "native instructions," designed within the hardware processor. The machine language instruction set, or native instruction set, is known to the hardware processor and is essentially built into the hardware processor. It is the "language" that system and application software uses to communicate with the hardware processor. Each native instruction is a distinct piece of code that is recognized by the processing architecture and can specify specific registers, specific memory locations or offsets, and specific addressing modes used to interpret operands for arithmetic, addressing, or control functions. By combining these simple native instructions, which are executed sequentially or directed by control flow instructions, more complex operations are constructed.

[0160] The relationship between executable software instructions and the hardware processor is structural. In other words, an instruction is, in itself, a set of symbols or numbers. Instructions inherently do not convey any information. It is the processor that, by design, is pre-configured to interpret symbols / numbers and gives meaning to the instructions.

[0161] The methods and techniques used herein may be configured to run on a single machine in a single location, on multiple machines in a single location, or on multiple machines in multiple locations. When multiple machines are used, each machine may be optimized for its particular task. For example, operations requiring large blocks of code and / or significant processing power may be implemented on large machines and / or stationary machines.

[0162] Furthermore, some embodiments relate to tangible and / or non-temporary computer-readable media or computer program products containing program instructions and / or data (including data structures) for performing operations implemented on various computers. Examples of computer-readable media include, but are not limited to, semiconductor memory devices, phase-change devices, disk drives, magnetic media such as magnetic tape, optical media such as CDs, magneto-optical media, and hardware devices specifically configured to store and execute program instructions, such as read-only memory devices (ROM) and random-access memory (RAM). Computer-readable media may be directly controlled by an end user, or the media may be indirectly controlled by an end user. Examples of directly controlled media include media located on user equipment and / or not shared with other entities. Examples of indirectly controlled media include media that are indirectly accessible to the user via an external network and / or via a service that provides shared resources such as a “cloud”. Examples of program instructions include both machine code, such as that generated by a compiler, and files containing higher-level code that can be executed by a computer using an interpreter.

[0163] In various embodiments, the data or information used in the disclosed methods and apparatus is provided in electronic format. Such data or information may include measured values, cumulative distributions, and the like. As used herein, data or other information provided in electronic format is available for storage on machines and transmission between machines. Conventionally, data in electronic format is provided digitally and can be stored as bits and / or bytes in various data structures, lists, databases, etc. The data can be materialized electronically, optically, and the like.

[0164] System software typically interfaces with computer hardware and associated memory. In some embodiments, system software includes operating system software and / or firmware, as well as any middleware and drivers installed within the system. System software provides the computer's basic, non-task-specific functions. Modules and other application software, on the other hand, are used to accomplish specific tasks. Each native instruction for a module is stored in a memory device and represented numerically.

[0165] An exemplary computer system 900 is shown in Figure 9. As illustrated, the computer system 900 includes an input / output subsystem 902, which may implement an interface for interacting with a human user and / or other computer systems, depending on the application. Embodiments of the present disclosure may be implemented in program code on system 900 having an I / O subsystem 902 used to receive input program statements and / or data from a human user (e.g., via a GUI or keyboard) and to display them back to the user. The I / O subsystem 902 may include, for example, a keyboard, mouse, graphical user interface, touchscreen, or other interface for input, and, for example, an LED or other flat screen display, or other interface for output.

[0166] The communication interface 907 may include any suitable components or circuits used for communication using any suitable communication network (e.g., the Internet, an intranet, a wide area network (WAN), a local area network (LAN), a wireless network, a virtual private network (VPN), and / or any other suitable type of communication network). For example, the communication interface 907 may include a network interface card circuit, a wireless communication circuit, and the like.

[0167] Program code may be stored in a non-temporary medium such as secondary memory 910 or memory 908 or both. In some embodiments, secondary memory 910 may be persistent storage. One or more processors 904 read program code from one or more non-temporary media and execute the code to enable the computer system to perform the methods implemented according to the embodiments herein. Those skilled in the art will understand that a processor may accept source code, such as statements for performing training and / or modeling operations, and may interpret or compile the source code into machine code understandable at the processor's hardware gate level. A bus 905 connects the I / O subsystem 902, the processors 904, peripheral devices 906, communication interfaces 907, memory 908, and secondary memory 910.

[0168] conclusion This description includes numerous specific details to provide a complete understanding of the presented embodiments. The disclosed embodiments may be implemented without some or all of these specific details. In other examples, well-known process behaviors were not described in detail so as not to unnecessarily obscure the disclosed embodiments. While the disclosed embodiments are described in conjunction with specific embodiments, it should be understood that the specific embodiments are not intended to limit the disclosed embodiments.

[0169] Unless otherwise indicated, the method operations and device features disclosed herein include techniques and apparatus commonly used in measurement, semiconductor device manufacturing techniques, software design and programming, and statistics, within the scope of the art in this field.

[0170] Unless otherwise defined herein, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art. Various scientific dictionaries containing the terms included herein are well known and available to those skilled in the art. Any methods and materials similar to or equivalent to those described herein may be found to be useful in carrying out or testing the embodiments disclosed herein, although some methods and materials are described.

[0171] A numerical range includes the number that defines the range. Any maximum numerical limit given throughout this specification is intended to include any lower numerical limit as if it were explicitly stated herein. Any minimum numerical limit given throughout this specification includes any higher numerical limit as if it were explicitly stated herein. Any numerical range given throughout this specification includes any narrower numerical ranges that are contained within such a wider numerical range as if they were all explicitly stated herein.

[0172] The headings provided herein shall not limit this disclosure.

[0173] As used herein, the singular terms “a,” “an,” and “the” include multiple references unless the context otherwise indicates. As used herein, the term “or” refers to a non-exclusive OR unless otherwise indicated.

[0174] Various computing elements, including processors, memory, instructions, routines, models, or other components, may be described or claimed as “configured to perform a task.” In such contexts, the phrase “configured to perform” is used to mean a structure, indicating that the component includes a structure (e.g., stored instructions, circuits, etc.) that performs a task while in operation. Thus, it can be said that a unit / circuit / component is configured to perform a task even when a given component is not necessarily operational at the moment (e.g., not turned on).

[0175] The components used with the phrase "configured to" may refer to hardware, such as circuits, or memory that stores executable program instructions to implement an operation. Furthermore, "configured to" may refer to a general-purpose structure (e.g., general-purpose circuitry) operated by software and / or firmware (e.g., an FPGA, or a general-purpose processor running the software) to operate in a manner capable of performing the tasks described. Furthermore, "configured to" may refer to one or more memories or memory elements that store computer executable instructions for performing the tasks described. Such memory elements may include memory on a computer chip having processing logic. In such contexts, "configured to" may also include adapting a manufacturing process (e.g., a semiconductor manufacturing facility) to produce a device (e.g., an integrated circuit) that is adapted to implement or perform one or more tasks. Application Example 1: A computer program product for comparing a pre-processed substrate sample and a post-processed substrate sample, comprising a non-temporary computer-readable medium, wherein on the non-temporary computer-readable medium, A computer executable instruction for receiving a plurality of samples associated with a first set of dimensions characterizing a pre-processed substrate and a plurality of samples associated with a second set of dimensions characterizing a post-processed substrate, A computer executable instruction to receive identification of one of the pre-processed dimensions and one of the post-processed dimensions that should be matched, A computer executable instruction for generating a first probability distribution of samples for identified pre-processed dimensions and a second probability distribution of samples for identified post-processed dimensions, Based on the first and second probability distributions, a computer executable instruction is provided to match the identified pre-processed dimension sample with the identified post-processed dimension sample. A computer program product that includes a feature. Application example 2: A computer program product as described in Application Example 1, wherein the identification is based on finding a monotonic relationship between the value of one of the pre-processed dimensions and the value of one of the post-processed dimensions. Application Example 3: A computer program product according to Application Example 1 or 2, wherein the first probability distribution and the second probability distribution are each a cumulative distribution function, and based on the fact that the value of the identified pre-processed substrate has approximately the same probability of occurrence as the value of the identified post-processed dimension in each cumulative distribution function, the value of the identified pre-processed dimension is matched with the value of the identified post-processed dimension. Application Example 4: A computer program product as described in Application Example 1 or 2, further comprising a computer executable instruction for matching the values ​​of one or more remaining pre-processed dimensions with the values ​​of one or more remaining post-processed dimensions based on a sample in which the identified pre-processed dimensions and the identified post-processed dimensions match. Application Example 5: A computer program product as described in Application Example 1 or 2, wherein the identified post-pretreatment dimension is a pre-treatment critical dimension (CD) measurement. Application example 6: A computer program product as described in Application Example 1 or 2, wherein the identified post-processed dimension is a post-processed critical dimension (CD) measurement. Application example 7: A computer program product as described in Application Example 1 or 2, wherein the identified pre-processed dimensional values ​​are generated using a model. Application Example 8: A computer program product as described in Application Example 7, wherein the model is an ion confinement model that predicts the ion paths used to etch two stacked substrate layers. Application example 9: The computer program product described in Application Example 8, A computer-executable instruction for determining whether the ions have passed through the junction where the two substrate layers are stacked, based on the ion confinement model, Based on the determination of whether the ions have passed through the junction, a computer executable instruction for selecting the identified pre-treated dimensions to be abutted, Computer program products, including, furthermore. Application Example 10: A computer program product as described in Application Example 9, wherein it is determined that the ion has passed through the junction, and the identified post-pretreatment dimensions correspond to the cross-sectional area showing the overlap between the ion's path and the junction. Application Example 11: A computer program product as described in Application Example 10, wherein the identified post-processed dimensions correspond to the etching volume of the lower end layer of the two substrate layers. Application Example 12: A computer program product as described in Application Example 9, wherein it is determined that the ions did not pass through the junction, and the identified post-pretreatment dimensions correspond to the cross-sectional area showing the difference between the ion's path and the junction. Application Example 13: A computer program product as described in Application Example 12, wherein the identified post-processed dimensions correspond to the liner loss area of ​​the side wall. Application Example 14: A computer program product for evaluating semiconductor manufacturing processes, comprising a non-temporary computer-readable medium, wherein on the non-temporary computer-readable medium, A computer executable instruction for receiving a dataset comprising a first plurality of samples having pre-processing dimensions that match a second plurality of samples having post-processing dimensions, wherein the first plurality of samples are matched with the second plurality of samples based on a first probability distribution of sample values ​​of one of the pre-processing dimensions and a second probability distribution of sample values ​​of one of the post-processing dimensions. A computer executable instruction for identifying a criterion for a given post-processing dimension that indicates a process failure, based on the value of a given post-processing dimension relative to a threshold, A computer executable instruction for identifying potential causes of process failures, based on the value of the pre-processing dimension that matches the given post-processing dimension. A computer program product that includes a feature. Application Example 15: A computer program product as described in Application Example 14, wherein a value of the given post-processing dimension exceeding the threshold indicates the process failure. Application Example 16: A computer program product as described in Application Example 15, further comprising a computer executable instruction for identifying a modification of the value of the preprocessing dimension that generates a value of the given postprocessing dimension less than the threshold. Application Example 17: A computer program product as described in Application Example 15, wherein the given post-processing dimension corresponds to the liner loss area of ​​the side wall during etching of two stacked substrate layers. Application Example 18: A computer program product according to any one of Application Examples 14 to 17, wherein a value of the given post-processing dimension below the threshold indicates the process failure. Application Example 19: A computer program product as described in Application Example 18, further comprising a computer executable instruction for identifying a shift in the value of the preprocessing dimension that generates a value of the given postprocessing dimension that exceeds the threshold. Application Example 20: A computer program product as described in Application Example 18, wherein the given post-processing dimension corresponds to the etching volume during etching of two stacked substrate layers. Application Example 21: A computer program product as described in Application Example 20, wherein the pre-processing dimension corresponds to the critical dimension (CD) of the junction where the two substrate layers are stacked. Application Example 22: A computer program product as described in Application Example 20, wherein the pretreatment dimension is the angle at which ions pass through the upper end layer of the two stacked substrate layers to the lower end layer of the two stacked substrate layers. Application Example 23: A computer program product according to any one of Application Examples 14 to 17, wherein at least one of the pre-processing dimensions and the post-processing dimensions is generated by a calculation model.

Claims

1. A computer program for causing a computer to perform a process of comparing a pre-processed substrate sample with a post-processed substrate sample, A function to receive multiple samples associated with a first set of dimensions characterizing the substrate after pre-processing, and multiple samples associated with a second set of dimensions characterizing the substrate after post-processing, A function that receives identification of one of the pre-processed dimensions and one of the post-processed dimensions that should be matched, A function to generate a first probability distribution of samples for identified pre-processed dimensions and a second probability distribution of samples for identified post-processed dimensions. Based on the first and second probability distributions, a function is provided to compare the identified pre-processed size sample with the identified post-processed size sample. A computer program that enables a computer to realize something.

2. A computer program according to claim 1, wherein the identification is based on finding a monotonic relationship between the value of one of the pre-processed dimensions and the value of one of the post-processed dimensions.

3. A computer program according to Claim 2, wherein the first probability distribution and the second probability distribution are each a cumulative distribution function, and based on the fact that the value of the identified pre-processed substrate has a probability of occurrence approximately the same as the value of the identified post-processed dimensions in each cumulative distribution function, the value of the identified pre-processed dimensions is compared with the value of the identified post-processed dimensions.

4. A computer program according to claim 1 or 2, further enabling the computer to perform a function of matching the values ​​of one or more remaining pre-processed dimensions with the values ​​of one or more remaining post-processed dimensions based on a sample in which the identified pre-processed dimensions and the identified post-processed dimensions match.

5. A computer program according to claim 1 or 2, wherein the identified pre-processed dimension is a pre-processed critical dimension (CD) measurement.

6. A computer program according to claim 1 or 2, wherein the identified post-processed dimension is a post-processed critical dimension (CD) measurement.

7. A computer program according to claim 1 or 2, wherein the identified pre-processed dimensional values ​​are generated using a model.

8. A computer program according to claim 7, wherein the model is an ion confinement model that predicts the paths of ions used to etch two stacked substrate layers.

9. A computer program according to claim 8, Based on the ion confinement model, a function is provided to determine whether the ions have passed through the junction where the two substrate layers are stacked. Based on the determination of whether the ions have passed through the junction, a function is provided to select the identified pre-treated dimensions to be butted together. A computer program that further enables a computer to realize this.

10. A computer program according to claim 9, wherein it is determined that the ion has passed through the junction, and the identified pre-treated dimensions correspond to the cross-sectional area showing the overlap between the ion's path and the junction.

11. A computer program according to claim 10, wherein the identified post-processed dimensions correspond to the etching volume of the lower end layer of the two substrate layers.

12. A computer program according to claim 9, wherein it is determined that the ion did not pass through the junction, and the identified post-pretreatment dimensions correspond to the cross-sectional area showing the difference between the ion's path and the junction.

13. A computer program according to claim 12, wherein the identified post-processed dimensions correspond to the liner loss area of ​​the side wall.

14. A computer program for causing a computer to perform a process for evaluating a semiconductor manufacturing process, A function that receives a dataset containing a first plurality of samples having pre-processing dimensions that match a second plurality of samples having post-processing dimensions, wherein the first plurality of samples are matched with the second plurality of samples based on a first probability distribution of sample values ​​of one of the pre-processing dimensions and a second probability distribution of sample values ​​of one of the post-processing dimensions. A function to identify a criterion for one given post-processing dimension that indicates a process failure, based on the value of a given post-processing dimension relative to a threshold, A function to identify potential causes of process failures based on the value of the pre-processing dimension that matches the given post-processing dimension. A computer program that enables a computer to realize something.

15. A computer program according to claim 14, wherein a value of the given post-processing dimension exceeding the threshold indicates a process failure.

16. A computer program according to claim 15, further enabling the computer to implement a function to identify a modification of the value of the pre-processing dimension that generates a value of the given post-processing dimension that is less than the threshold.

17. A computer program according to claim 15, wherein the given post-processing dimension corresponds to the liner loss area of ​​the side wall during etching of two stacked substrate layers.

18. A computer program according to any one of claims 14 to 17, wherein a value of the given post-processing dimension less than the threshold indicates the process failure.

19. A computer program according to claim 18, further enabling the computer to implement a function to identify a shift in the value of the pre-processing dimension that generates a value of the given post-processing dimension that exceeds the threshold.

20. A computer program according to claim 18, wherein the given post-processing dimension corresponds to the etching volume during etching of two stacked substrate layers.

21. A computer program according to claim 20, wherein the pre-processing dimension corresponds to the critical dimension (CD) of the joint where the two substrate layers are stacked.

22. A computer program according to claim 20, wherein the pretreatment dimension is the angle at which ions pass through the upper end layer of the two stacked substrate layers to the lower end layer of the two stacked substrate layers.

23. A computer program according to any one of claims 14 to 17, wherein at least one of the pre-processing dimensions and the post-processing dimensions is generated by a calculation model.

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