Semiconductor equipment

Abstract

This semiconductor device comprises: a first latch circuit (L1) including a first inverting circuit (i1), a second inverting circuit (i2), a third inverting circuit (i3), and a fourth inverting circuit (i4); first-type well regions (Wp1, Wp2); and a second-type well region (Wn1). A distance between a drain (p1) and a drain (p3) is smaller than that between the drain (p1) and a drain (p4) in plan view.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device including a latch circuit and a flip-flop circuit.

Background Art

[0002] In a semiconductor device, a soft error in a latch circuit (also called a flip-flop circuit) in a logic circuit has been a problem. A soft error refers to a temporary error in which noise enters due to a particle beam such as a cosmic ray colliding with the latch circuit, and the state of the latch is inverted.

[0003] As a circuit with high soft error tolerance, for example, in the latch circuit shown in FIG. 2 of Patent Document 1, it is composed of four inverter circuits, and the same data is input to the gates of the PMOS transistor and the NMOS transistor of each inverter circuit, but they are connected to different nodes. Even if noise that can cause a soft error enters any one of those four nodes, it can be restored by other nodes. However, if two nodes having the same data among the four nodes are simultaneously affected by a soft error, there is a weakness that the state of the latch is likely to be inverted. In Patent Document 1, the above weakness is overcome by alternately arranging PMOS transistors and NMOS transistors so as to cancel out noise.

[0004] On the other hand, since the flip-flop circuit is one of the most important basic circuits that greatly affects the chip area, miniaturization is required. Therefore, according to the arrangement shown in FIG. 12 of Patent Document 1, two or more N wells in which PMOS transistors are arranged and two or more P wells in which NMOS transistors are arranged must be separated from each other, and the arrangement efficiency deteriorates, so miniaturization cannot be achieved.

[0005] For example, in the arrangement shown in Fig. 7 of Non-Patent Document 1, all PMOS transistors can be efficiently arranged in one N well, so it is suitable for miniaturization.

Prior Art Documents

[0006] [Patent Document 1] Patent No. 5369771 [Non-patent literature]

[0007] [Non-Patent Document 1] “A Low-Power and Area-Efficient Radiation-Hard Redundant Flip-Flop, DICE ACFF, in a 65 nm Thin-BOX FD-SOI”, IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL.61, NO.4, AUGUST 2014 [Overview of the project] [Problems that the invention aims to solve]

[0008] When the PMOS transistors in the conventional latch circuit described above are placed in a single N-well to reduce their area, two of the four nodes in the latch circuit that have the same data are placed close together, making them susceptible to noise simultaneously and resulting in a problem of low soft error tolerance.

[0009] This disclosure provides a semiconductor device equipped with a latch circuit that has high soft error tolerance and can be constructed in a small area. [Means for solving the problem]

[0010] A semiconductor device according to one aspect of the present disclosure comprises a first latch circuit consisting of first to fourth inverting circuits, first and second first-type well regions, and a second-type well region, wherein each of the first to fourth inverting circuits comprises a first-type MOS transistor, a second-type MOS transistor, and an output node connected to the drain of the first-type MOS transistor and the drain of the second-type MOS transistor, the output node of the first inverting circuit is connected to the gate of the first-type MOS transistor of the second inverting circuit and the gate of the second-type MOS transistor of the fourth inverting circuit, the output node of the second inverting circuit is connected to the gate of the first-type MOS transistor of the third inverting circuit and the gate of the second-type MOS transistor of the first inverting circuit, the output node of the third inverting circuit is connected to the gate of the first-type MOS transistor of the fourth inverting circuit and the gate of the second-type MOS transistor of the second inverting circuit, and the output of the fourth inverting circuit The power node is connected to the gate of the first type MOS transistor of the first inverting circuit and the gate of the second type MOS transistor of the third inverting circuit, and each of the drains of the first type MOS transistors of the first to fourth inverting circuits is located in the second type well region, each of the drains of the first and second type MOS transistors of the first and second inverting circuits is located in the first first type well region, each of the drains of the second type MOS transistors of the third and fourth inverting circuits is located in the second first type well region, and the second type well region is located between the first first type well region and the second first type well region, and in plan view, the distance between the drain of the first type MOS transistor of the first inverting circuit and the drain of the first type MOS transistor of the third inverting circuit is greater than the distance between the drain of the first type MOS transistor of the first inverting circuit and the drain of the first type MOS transistor of the fourth inverting circuit. The sources of the first type MOS transistors in the first and second inverting circuits are shared and connected to the power line, and the sources of the first type MOS transistors in the third and fourth inverting circuits are shared and connected to the power line. . [Effects of the Invention]

[0011] According to this disclosure, a latch circuit for a semiconductor device can be configured with high soft error tolerance and in a small area.

Brief Description of the Drawings

[0012] [Figure 1] FIG. 1 is a diagram showing a planar layout example of a semiconductor device according to Embodiment 1. [Figure 2] FIG. 2 is a diagram showing a circuit example of a semiconductor device according to Embodiment 1. [Figure 3] FIG. 3 is an explanatory diagram of the operating state of a semiconductor device according to Embodiment 1. [Figure 4] FIG. 4 is a diagram showing a planar layout example of a semiconductor device according to Embodiment 2. [Figure 5] FIG. 5 is a diagram showing a planar layout example of a semiconductor device according to Embodiment 3. [Figure 6] FIG. 6 is a diagram showing a circuit example of a semiconductor device according to Embodiment 3. [Figure 7] FIG. 7 is a diagram showing a planar layout example of a semiconductor device according to Embodiment 4. [Figure 8A] FIG. 8A is a diagram showing a circuit example of a semiconductor device according to Embodiment 4. [Figure 8B] FIG. 8B is a diagram showing a circuit example of the data input circuit in FIG. 8A. [Figure 8C] FIG. 8C is a diagram showing a circuit example of the clock input circuit in FIG. 8A. [Figure 9] FIG. 9 is a diagram showing a planar layout example of a semiconductor device according to Embodiment 5. [Figure 10] FIG. 10 is a diagram showing a planar layout example of a semiconductor device according to Embodiment 6. [Figure 11] FIG. 11 is a diagram showing a circuit example of a semiconductor device according to Embodiment 6. [Figure 12] FIG. 12 is a diagram showing a circuit example formed in the semiconductor device according to Embodiment 1. [Figure 13] FIG. 13 is a diagram showing a first example of a wiring layout in a wiring layer. [Figure 14] FIG. 14 is a diagram showing a second example of a wiring layout in a wiring layer. [Figure 15]FIG. 15 is a diagram showing a third example of a wiring layout in a wiring layer. [Figure 16] FIG. 16 is a diagram showing a fourth example of a wiring layout in a wiring layer. [Figure 17] FIG. 17 is a diagram showing a fifth example of a wiring layout in a wiring layer. [[ID=...]] [Figure 18] FIG. 18 is a diagram showing a sixth example of a wiring layout in a wiring layer. [Figure 19] FIG. 19 is a diagram showing a seventh example of a wiring layout in a wiring layer. [Figure 20] FIG. 20 is a diagram showing an eighth example of a wiring layout in a wiring layer. [Figure 21] FIG. 21 is a diagram showing a first example of a wiring layout between wiring layers. [Figure 22A] FIG. 22A is a diagram showing a second example of a wiring layout between wiring layers. [Figure 22B] FIG. 22B is a diagram showing a modified example of the second example of a wiring layout between wiring layers. [Figure 23] FIG. 23 is a diagram showing another circuit example formed in the semiconductor device according to Embodiment 1. [Figure 24] FIG. 24 is a circuit diagram showing an example of element C in FIG. 23. [Figure 25] FIG. 25 is an explanatory diagram showing a short example of a latch circuit in a comparative example.

Embodiments for Carrying Out the Invention

[0013] The embodiments will be described in detail below with reference to the drawings. The embodiments described below are all preferred examples of the present invention. The numerical values, shapes, materials, components, arrangement and connection configurations of components, steps, and the order of steps shown in the following embodiments are examples only and are not intended to limit the present invention. Furthermore, components in the following embodiments that are not described in the independent claims representing an implementation of one embodiment of this disclosure will be described as optional components. The implementations of this disclosure are not limited to the current independent claims and may also be expressed by other independent claims. Also, the figures are schematic diagrams and do not necessarily represent precise dimensions.

[0014] (Embodiment 1) In this embodiment, the semiconductor device has a redundant latch circuit configuration with four inverting circuits, and the drain nodes are arranged such that the distance between two drain nodes with different data is smaller than the distance between two drain nodes with the same data. This arrangement increases the likelihood that noise from alpha rays or neutron rays will also enter the drain nodes with different data, even if noise from alpha rays or neutron rays enters the two drain nodes with the same data simultaneously. In other words, the noise cancellation effect is enhanced, resulting in high soft error tolerance. Furthermore, it is possible to construct a semiconductor device equipped with a latch circuit or flip-flop circuit that can be constructed in a small area.

[0015] Figure 1 shows an example of a planar arrangement of a semiconductor device according to Embodiment 1. Figure 2 shows an example of a circuit of the semiconductor device according to Embodiment 1.

[0016] As shown in Figure 2, the semiconductor device includes a first latch circuit L1 consisting of first to fourth inverting circuits i1 to i4. The semiconductor device also includes a first type I well region Wp1, a second type I well region Wp2, and a type II well region Wn1. The first type I well region Wp1, the second type I well region Wp2, and the type II well region Wn1 are for forming the latch circuit L1.

[0017] The first inverting circuit i1 includes a first-type MOS transistor pt1, a second-type MOS transistor nt1, and an output node o1 connected to the drain p1 of the first-type MOS transistor pt1 and the drain of the second-type MOS transistor nt1.

[0018] The second inverting circuit i2 includes a first-type MOS transistor pt2, a second-type MOS transistor nt2, and an output node o2 connected to the drain p2 of the first-type MOS transistor pt2 and the drain of the second-type MOS transistor nt2.

[0019] The third inverting circuit i3 includes a first-type MOS transistor pt3, a second-type MOS transistor nt3, and an output node o3 connected to the drain p3 of the first-type MOS transistor pt3 and the drain of the second-type MOS transistor nt3.

[0020] The fourth inverting circuit i4 includes a first-type MOS transistor pt4, a second-type MOS transistor nt4, and an output node o4 connected to the drain p4 of the first-type MOS transistor pt4 and the drain of the second-type MOS transistor nt4.

[0021] The sources of the first to fourth inverting circuits i1 to i4, each of the first type MOS transistors, are connected to the power line VDD at potential, and the sources of the second type MOS transistors are connected to the GND line at potential VSS.

[0022] Note that Type 1 refers to one of the conductivity types, P-type and N-type. Type 2 refers to the other conductivity type, P-type and N-type. In the examples in Figures 1 and 2, Type 1 is P-type and Type 2 is N-type. Hereafter, Type 1 may be denoted as P and Type 2 as N. Also, Type 1 MOS transistors may be denoted as PMOS transistors and Type 2 MOS transistors as NMOS transistors.

[0023] As shown in Figure 2, the output node o1 of the first inverting circuit i1 is connected to the gate g2 of the first type MOS transistor pt1 of the second inverting circuit i2 and to the gate of the second type MOS transistor nt4 of the fourth inverting circuit i4.

[0024] The output node o2 of the second inverting circuit i2 is connected to the gate g3 of the first type MOS transistor pt3 of the third inverting circuit i3 and to the gate of the second type MOS transistor nt1 of the first inverting circuit i1.

[0025] The output node o3 of the third inverting circuit i3 is connected to the gate g4 of the first type MOS transistor pt4 of the fourth inverting circuit i4 and to the gate of the second type MOS transistor nt2 of the second inverting circuit i2.

[0026] The output node o4 of the fourth inverting circuit i4 is connected to the gate g1 of the first type MOS transistor pt1 of the first inverting circuit i1 and to the gate of the second type MOS transistor nt3 of the third inverting circuit i3.

[0027] As shown in Figure 1, the drains P1 to p4 of the first to fourth inverting circuits i1 to i4, each of the first type MOS transistors pt1 to pt4, are located in the second type well region Wn1.

[0028] The drains n1 and n2 of the first and second inverting circuits i1 and i2, respectively, of the type 2 MOS transistors nt1 and nt2, are located in the first type 1 well region Wp1.

[0029] The drains n3 and n4 of the type 2 MOS transistors nt3 and nt4 of the third and fourth inverting circuits i3 and i4 are respectively located in the second type 1 well region Wp2.

[0030] Furthermore, the second type well region Wn1 is located between the first type I well region Wp1 and the second type I well region Wp2.

[0031] In a plan view, the distance d13 between the drain p1 of the first type MOS transistor pt1 of the first inverting circuit i1 and the drain p4 of the first type MOS transistor pt4 of the fourth inverting circuit i4 is smaller than the distance d13 between the drain p1 of the first type MOS transistor pt1 of the first inverting circuit i1 and the drain p3 of the first type MOS transistor pt3 of the third inverting circuit i3. Here, a plan view refers to viewing the main surface of the semiconductor device from the normal direction. For example, Figure 1 is a plan view of a semiconductor device.

[0032] The term "drain" is also referred to as a drain node and means the drain region in a circuit configuration like that shown in Figure 2.

[0033] In this configuration, drain node p1 is closer to drain node p4, which has different data, than to drain node p3, which has the same data, thus increasing the noise cancellation effect.

[0034] Next, we will explain the effect of increasing soft error tolerance.

[0035] Figure 3 is an explanatory diagram of the operating state of a semiconductor device according to Embodiment 1. Figure 3(a) schematically shows how noise is received in the initial state in the circuit diagram of Figure 2, where drain nodes p1 and p3 are at a low level and drain node p4 is at a high level. Figure 3(b) is an explanatory diagram of the operating state, showing the potential state V when drain nodes p1, p3, and p4 are subjected to noise at time t1 within time T, starting from the initial state described above. The effects will be explained below using Figures 1, 2, and 3.

[0036] Generally, for the drain node of a PMOS transistor, the potential temporarily increases when holes generated by a particle beam are collected at the drain node, which is a P-type diffusion region. In the circuit diagram shown in FIG. 2, for example, when drain nodes p1 and p3 are simultaneously affected by noise, if the distance between drain nodes p1 and p3 is close (when d13 < d14), the potential becomes as shown by the dashed line in (b) of FIG. 3, and the latch state is inverted. However, according to the present disclosure, as shown in FIG. 1, the distance d14 between drain node p1 and drain node p4 having different data is closer than the distance d13 between drain node p1 and drain node p3 having the same data. Therefore, in FIG. 2, not only drain nodes p1 and p3 but also drain node p4 is likely to be affected by noise, enhancing the effect of canceling out noise. That is, even if the PMOS transistor of drain node p4 is about to transition from ON to OFF due to noise applied to drain node p3, the potential of drain node p4 increases due to the noise, so the ON state of the NMOS transistor of drain node n3 is maintained, and an effect of returning drain nodes p3 and n3 to a low level is exerted. As a result, there is an effect of suppressing the inversion of the latch state, as in the potential state shown by the solid line in (b) of FIG. 3.

[0037] According to the present embodiment, by arranging PMOS transistors p1, p2, p3, and p4 in one N-well Wn1, a semiconductor device with a latch circuit having high soft error tolerance can be realized, which can be configured with a small area and by arranging drain nodes p1, p3, and p4 so as to cancel out noise.

[0038] As described above, the semiconductor device according to Embodiment 1 comprises a first latch circuit L1 consisting of first to fourth inverting circuits i1 to i4, a first type 1 well region Wp1, a second type 1 well region Wp2, and a second type 2 well region Wn1, wherein the first to fourth inverting circuits i1 to i4 each consist of a first type MOS transistor pt1 / pt2 / pt3 / pt4, a second type MOS transistor nt1 / nt2 / nt3 / nt4, and output nodes o1 / o connected to the drains of the first type MOS transistors and the drains of the second type MOS transistors. The circuit has 2 / o3 / o4, and the output node o1 of the first inverting circuit i1 is connected to the gate g2 of the first type MOS transistor pt1 of the second inverting circuit i2 and the gate of the second type MOS transistor nt4 of the fourth inverting circuit i4, the output node o2 of the second inverting circuit i2 is connected to the gate g3 of the first type MOS transistor pt3 of the third inverting circuit i3 and the gate of the second type MOS transistor nt1 of the first inverting circuit i1, and the output node o3 of the third inverting circuit i3 is connected to the gate of the first type MOS transistor pt4 of the fourth inverting circuit i4 The drains g4 of the fourth inverting circuit i4 are connected to the gate g1 of the first inverting circuit i1 and the gate nt3 of the third inverting circuit i3. The drains P1 to p4 of the first to fourth inverting circuits are located in the second well region Wn1, and the drains n1 and n2 of the second inverting circuits i1 and i2 are connected to the gates g1 and n2 of the second inverting circuit i2. Each of these is located in the first type I well region Wp1, and the drains n3 and n4 of the type II MOS transistors nt3 and nt4 of the third and fourth inverting circuits i3 and i4 are located in the second type I well region Wp2, and the type II well region Wn1 is located between the first type I well region Wp1 and the second type I well region Wp2, and in a plan view, the distance d13 between the drain p1 of the type I MOS transistor pt1 of the first inverting circuit i1 and the drain p3 of the type I MOS transistor pt3 of the third inverting circuit i3 is greater thanThe distance d14 between the drain p1 of the first type MOS transistor pt1 in the first inverting circuit i1 and the drain p4 of the first type MOS transistor pt4 in the fourth inverting circuit i4 is smaller.

[0039] According to this, the latch circuit of the semiconductor device can be constructed with high soft error tolerance and in a small area. Since the distance d14 between drain node p1 and drain node p4, which has different data, is closer than the distance d13 between drain node p3, which has the same data, the noise cancellation effect can be enhanced. In addition, the second type well region Wn1 can be made in a small area because it is placed between two well regions Wp1.

[0040] Here, the first and second Type 1 well regions Wp1 and Wp2 may be Type P wells, and the Type 2 well region Wn1 may be Type N well.

[0041] According to this, for example, by using a circuit arrangement like that shown in Figure 1, soft error tolerance can be increased.

[0042] (Embodiment 2) Embodiment 2 describes a circuit arrangement example that differs from Embodiment 1.

[0043] Figure 4 shows an example of a planar arrangement of a semiconductor device according to Embodiment 2. According to the arrangement diagram shown in Figure 4, the semiconductor device of Embodiment 2 realizes the circuit of Embodiment 1 with a different arrangement. The explanation of the reference numerals shown in Figure 4 is the same as in Embodiment 1, but the arrangement of the drain nodes p4, p3, n2, and n1 is different.

[0044] In the circuit arrangement example shown in Figure 1 of Embodiment 1, the circuit elements of the latch circuit L1 are arranged in two separate rectangular regions. In contrast, in the circuit arrangement example shown in Figure 4 of Embodiment 2, the circuit elements of the latch circuit L1 are efficiently arranged within a single rectangular region.

[0045] Similar to Embodiment 1, drain node p1 is closer to drain node p4 (d14) with different data than drain node p3 (d13) with the same data. Furthermore, according to the arrangement in Figure 4, drain node p2 is closer to drain node p3 (p3) with different data than drain node p4 (p4) with the same data. Therefore, the noise cancellation effect is even higher than in Embodiment 1.

[0046] As described above, in a plan view, the semiconductor device according to Embodiment 2 has a distance of greater than the distance between the drain p2 of the first type MOS transistor pt1 of the second inverting circuit i2 and the drain p4 of the first type MOS transistor pt4 of the fourth inverting circuit i4, and greater than the distance between the drain p2 of the first type MOS transistor pt2 of the second inverting circuit i2 and the drain p3 of the first type MOS transistor pt3 of the third inverting circuit i3, and greater than the distance between the drain p3 of the first type MOS transistor pt3 of the third inverting circuit i3 and the drain p4 of the first type MOS transistor pt4 of the fourth inverting circuit i4.

[0047] According to this, for example, by using a circuit arrangement like that shown in Figure 4, soft error tolerance can be increased, and the circuit area can be reduced.

[0048] (Embodiment 3) Embodiment 3 describes an example in which the latch circuit L1 of Embodiments 1 and 2 includes at least one clocked inverter circuit.

[0049] Figure 5 shows an example of a planar arrangement of the semiconductor device according to Embodiment 3. Figure 6 shows an example of a circuit of the semiconductor device according to Embodiment 3.

[0050] The latch circuit L1 shown in Figure 6 differs from that in Figure 3 in that a PMOS transistor pc2 and an NMOS transistor nc2 have been added to the second inverting circuit i2, and a PMOS transistor pc4 and an NMOS transistor nc4 have been added to the fourth inverting circuit i4. The following will explain the differences in detail.

[0051] The second inverting circuit i2 and the fourth inverting circuit i4 are clocked inverting circuits that take a clock signal as input. In the figure, the clock signal CKIN represents the inverted clock signal supplied to the gates of PMOS transistor pc2 and PMOS transistor pc4. The clock signal CKI represents the uninverted clock signal supplied to the gates of NMOS transistor nc2 and NMOS transistor nc4.

[0052] In semiconductor devices that operate in synchronization with such clock signals CKI and CKIN, a function is needed to interrupt the connection state of the latch circuit L1 when the data held by the latch circuit L1 is forcibly rewritten. Therefore, the second inverting circuit i2 and the fourth inverting circuit i4, which constitute the feedback path of the latch, are configured as clocked inverting circuits. The latch circuit L1 can be used as an element circuit to configure a flip-flop circuit on which arbitrary data can be written. The same effects as in Embodiment 1 are obtained in terms of soft error tolerance and area.

[0053] As described above, in the semiconductor device according to Embodiment 3, at least one of the first and second first to fourth inverting circuits i1 to i4 is a clocked inverting circuit that takes a clock signal as input.

[0054] According to this, a latch circuit having a clocked inverting circuit can be constructed with high soft error tolerance and in a small area.

[0055] (Embodiment 4) Embodiment 4 describes an example configuration of a master-slave type flip-flop circuit equipped with two latch circuits from Embodiment 3.

[0056] Figure 7 shows an example of a planar arrangement of a semiconductor device according to Embodiment 4. Figure 8A shows an example of a circuit of a semiconductor device according to Embodiment 4. Figure 8B shows an example of the data input circuit of Figure 8A. Figure 8C shows an example of the clock input circuit of Figure 8A.

[0057] In Figure 8A, the flip-flop circuit F1 includes a data input circuit Id, a clock input circuit Ick, a switch circuit S1, a switch circuit S2, a latch circuit L1, a latch circuit L2, and an output circuit O1.

[0058] The data input circuit Id is an inverting buffer circuit that receives data D as input and outputs the inverted data D.

[0059] The clock input circuit Ick receives the clock input signal CK and generates the non-inverted clock signal CKI and its inverted version, the clock signal CKIN.

[0060] The switch circuit S1 is a transmission circuit that transmits and interrupts data from the data input circuit Id to the latch circuit L1. The switch circuit S1's transmission and interruption (i.e., conduction and non-conduction) states are controlled by the clock signals CKI and CKIN. In the example shown in the figure, the circuit is in a conduction state when the clock signal CKI is low level (when the clock signal CKIN is high level), and in a non-conduction state when it is high level.

[0061] Switch circuit S2 is a transmission circuit that transmits and blocks data from latch circuit L1 to latch circuit L2. Switch circuit S2 can have the same configuration as switch circuit S1. However, the clock signals CKI and CKIN input to switch circuit S2 are swapped compared to switch circuit S1.

[0062] The latch circuit L1 has the same configuration as the latch circuit L1 with a clocked inverter circuit shown in Figure 6.

[0063] The latch circuit L2 has the same configuration as the latch circuit L1, which has a clocked inverting circuit as shown in Figure 6. However, the clock signals CKI and CKIN input to the latch circuit L2 are swapped compared to the latch circuit L1 in Figure 8A. This is to transmit data sequentially from the master (latch circuit L1) to the slave (latch circuit L2). The four inverting circuits of latch circuit L2 are referred to as the fifth inverting circuit i5 to the eighth inverting circuit i8.

[0064] The fifth inverting circuit i5 includes a first-type MOS transistor pt12, a second-type MOS transistor nt12, and an output node o12 connected to the drain p12 of the first-type MOS transistor pt12 and the drain of the second-type MOS transistor nt12.

[0065] The sixth inverting circuit i6 has a first-type MOS transistor pt22, a second-type MOS transistor nt22, and an output node o22 connected to the drain p22 of the first-type MOS transistor pt22 and the drain of the second-type MOS transistor nt22.

[0066] The seventh inverting circuit i7 includes a first-type MOS transistor pt32, a second-type MOS transistor nt32, and an output node o32 connected to the drain p32 of the first-type MOS transistor pt32 and the drain of the second-type MOS transistor nt32.

[0067] The eighth inverting circuit i8 has a first-type MOS transistor pt42, a second-type MOS transistor nt42, and an output node o42 connected to the drain p42 of the first-type MOS transistor pt42 and the drain of the second-type MOS transistor nt42.

[0068] The output node o12 of the fifth inverter circuit i5 is connected to the gate g22 of the first type MOS transistor pt22 of the sixth inverter circuit i6 and to the gate of the second type MOS transistor nt42 of the eighth inverter circuit i8.

[0069] The output node o22 of the sixth inverting circuit i6 is connected to the gate g32 of the first type MOS transistor pt32 of the seventh inverting circuit i7 and to the gate of the second type MOS transistor nt12 of the fifth inverting circuit i5.

[0070] The output node o32 of the seventh inverting circuit i7 is connected to the gate g42 of the first type MOS transistor pt42 of the eighth inverting circuit i8 and to the gate of the second type MOS transistor nt22 of the sixth inverting circuit i6.

[0071] The output node o42 of the eighth inverter circuit i8 is connected to the gate g12 of the first type MOS transistor pt12 of the fifth inverter circuit i5 and to the gate of the second type MOS transistor nt32 of the seventh inverter circuit i7.

[0072] The drains of the first-type MOS transistors pt12, pt22, pt32, and pt42 of the fifth to eighth inverting circuits i5 to i8 are each placed in the second-type well region Wn1.

[0073] The drains of the type 2 MOS transistors of the fifth and sixth inverting circuits are each located in the first type 1 well region Wp1.

[0074] The drains of the seventh and eighth inverting circuits, respectively, are located in the second first-type well region Wp2.

[0075] As shown in Figure 7, in a plan view, the distance between the drain p12 of the type 1 MOS transistor pt12 of the fifth inverting circuit i5 and the drain p42 of the type 1 MOS transistor pt42 of the eighth inverting circuit i8 is smaller than the distance between the drain p12 of the type 1 MOS transistor pt12 of the fifth inverting circuit i5 and the drain p32 of the type 1 MOS transistor pt32 of the seventh inverting circuit i7.

[0076] Furthermore, in a plan view, among the drains of the first type MOS transistors in the first to eighth inverting circuits i1 to i8, the drain closest to the drain p11 of the first type MOS transistor pt11 in the first inverting circuit i1 is included in the seventh inverting circuit i7. Among the drains of the first type MOS transistors in the first to eighth inverting circuits i1 to i8, the drain closest to the drain p21 of the first type MOS transistor pt21 in the second inverting circuit i2 is included in the eighth inverting circuit i8. In other words, drain p11 is located near drain p32. Drain p21 is located near drain p42.

[0077] Output circuit O1 is an inverting buffer circuit for outputting data from the latch circuit.

[0078] In Figure 8B, the data input circuit Id is an inverter circuit including at least a first-type MOS transistor 111. Specifically, the data input circuit Id comprises a PMOS transistor 111, an NMOS transistor 112, and output nodes connected to the drain 113 of the PMOS transistor 111 and the drain of the NMOS transistor 112.

[0079] In Figure 8C, the clock input circuit Ick includes a two-stage inverter circuit.

[0080] The two-stage inverter circuit includes at least a first-type MOS transistor 101. Specifically, the first-stage inverter circuit comprises a PMOS transistor 101, an NMOS transistor 102, and output nodes connected to the drain 103 of the PMOS transistor 101 and the drain of the NMOS transistor 102.

[0081] The second-stage inverter circuit comprises a PMOS transistor 104, an NMOS transistor 105, and output nodes connected to the drain 106 of the PMOS transistor 104 and the drain of the NMOS transistor 105.

[0082] The first-stage output node is connected to the gates of the second-stage PMOS transistor 104 and NMOS transistor 105. This first-stage output node outputs the clock signal CKIN. The second-stage output node also outputs the clock signal CKI.

[0083] In the circuit layout example shown in Figure 7, one of the drains 113 of the first type MOS transistor 111 of the data input circuit Id and the drain 103 of the first type MOS transistor 101 of the clock input circuit Ick is aligned in the first direction with the drain p11 of the first type MOS transistor pt11 of the first inverting circuit i1 and the drain p21 of the first type MOS transistor pt21 of the second inverting circuit i2. The other of the drains 113 of the first type MOS transistor 111 of the data input circuit Id and the drain 113 of the first type MOS transistor 101 of the clock input circuit Ick is aligned in the first direction with the drain p31 of the first type MOS transistor pt31 of the third inverting circuit i3 and the drain p41 of the first type MOS transistor pt41 of the fourth inverting circuit i4. This arrangement allows the data input circuit Id and the clock input circuit Ick to be efficiently arranged as shown in Figure 7, thereby reducing the circuit area.

[0084] According to the arrangement diagram shown in Figure 7 and the circuit diagrams shown in Figures 8A to 8C, the semiconductor device of Embodiment 4 uses two latch circuits from Embodiment 3, designated as latch circuits L1 and L2, and includes a clock input circuit Ick that receives a clock input signal CK and generates an internal clock signal CKI and its inverted signal CKIN, and a flip-flop circuit F1 composed of a data input circuit Id that receives a data input signal D, switch circuits S1 and S2, and an output circuit O1.

[0085] As shown in Figure 7, in the latch circuit L1, the drain nodes p11, p21, p31, and p41 of the PMOS transistors pt11, pt21, pt31, and pt41 are located in the N-well region Wn1. The drain nodes n11 and n21 of the NMOS transistors nt11 and nt21 are located in the P-well region Wp1. The drain nodes n31 and n41 of the NMOS transistors nt31 and nt41 are located in the P-well region Wp2. Transistors pt11 and nt31 with drain nodes p11 and n31 share gate g11. Transistors pt21 and nt41 with drain nodes p21 and n41 share gate g21. Transistors pt31 and nt11 with drain nodes p31 and n11 share gate g31. Transistors pt41 and nt21 with drain nodes p41 and n21 share gate g41.

[0086] In the latch circuit L2, the drain nodes p12, p22, p32, and p42 of the PMOS transistors pt12, pt22, pt32, and pt42 are located in the N-well region Wn1. The drain nodes n12 and n22 of the NMOS transistors nt12 and nt22 are located in the P-well region Wp1. The drain nodes n32 and n42 of the NMOS transistors nt32 and nt42 are located in the P-well region Wp2. Transistors pt12 and nt32 with drain nodes p12 and n32 share gate g12. Transistors pt22 and nt42 with drain nodes p22 and n42 share gate g22. Transistors pt32 and nt12 with drain nodes p32 and n12 share gate g32. Transistors pt42 and nt22 with drain nodes p42 and n22 share gate g42. Regarding the arrangement of the clock input circuit Ick, data input circuit Id, switch circuits S1 and S2, and output circuit O1, some parts are omitted in the example arrangement shown in Figure 7.

[0087] As shown in Figure 7, in the latch circuit L1, drain node p11 is closer to drain node p41, which has different data, than to drain node p31, which has the same data, thus increasing the noise cancellation effect. Furthermore, in the latch circuit L2, drain node p12 is closer to drain node p42, which has different data, than to drain node p32, which has the same data, thus further increasing the noise cancellation effect. Also, for example, as shown in Figure 7, if the gate gck that receives the internal clock inversion signal CKIN is shared by multiple transistors, the number of connections in the flip-flop circuit can be reduced, contributing to a smaller area.

[0088] According to this embodiment, by arranging PMOS transistors p11, p21, p31, p41, p12, p22, p32, and p42 within a single N-well Wn1, it is possible to construct a semiconductor device with a flip-flop circuit that has high soft error tolerance by arranging drain nodes p11, p31, p41 and drain nodes p12, p32, and p42 in a manner that cancels out noise.

[0089] As described above, the semiconductor device according to Embodiment 4 includes a second latch circuit L2 consisting of fifth to eighth inverting circuits after the first latch circuit L1, and the fifth to eighth inverting circuits i5 to i8 each have a first-type MOS transistor pt12 / pt22 / pt32 / pt42, a second-type MOS transistor nt12 / nt22 / nt32 / nt42, and output nodes o12 / o22 / o32 / o42 connected to the drains of the first-type MOS transistor and the drains of the second-type MOS transistor, respectively, and the output node of the fifth inverting circuit i5 Node o12 is connected to the gate g22 of the type 1 MOS transistor pt22 of the 6th inverting circuit i6 and the gate of the type 2 MOS transistor nt42 of the 8th inverting circuit i8, the output node o22 of the 6th inverting circuit i6 is connected to the gate g32 of the type 1 MOS transistor pt32 of the 7th inverting circuit i7 and the gate of the type 2 MOS transistor nt12 of the 5th inverting circuit i5, the output node o32 of the 7th inverting circuit i7 is connected to the gate g42 of the type 1 MOS transistor pt42 of the 8th inverting circuit i8 and the 6th inverting circuit i6 The output node o42 of the eighth inverter circuit i8 is connected to the gate g12 of the first type MOS transistor pt12 of the fifth inverter circuit i5 and to the gate of the second type MOS transistor nt32 of the seventh inverter circuit i7. The drains of the first type MOS transistors pt12, pt22, pt32, and pt42 of the fifth to eighth inverter circuits i5 to i8 are located in the second type well region Wn1. The drains of the second type MOS transistors of the fifth and sixth inverter circuits are located in the first well region Wn1. The drains of the type 2 MOS transistors of the 7th and 8th inverting circuits are located in the type well region Wp1, and in a plan view, the distance between the drain p12 of the type 1 MOS transistor pt12 of the 5th inverting circuit i5 and the drain p42 of the type 1 MOS transistor pt42 of the 8th inverting circuit i8 is smaller than the distance between the drain p12 of the type 1 MOS transistor pt12 of the 5th inverting circuit i5 and the drain p32 of the type 1 MOS transistor pt32 of the 7th inverting circuit i7.

[0090] According to this, a master-slave type flip-flop circuit can be constructed with high soft error tolerance and in a small area.

[0091] Here, in a plan view, the drain closest to the drain p11 of the first type MOS transistor pt11 of the first type MOS transistor pt11 of the first inverting circuit i1 is included in the seventh inverting circuit i7, and in a plan view, the drain closest to the drain p21 of the first type MOS transistor pt21 of the second inverting circuit i2 is included in the eighth inverting circuit i8.

[0092] According to this, for example, by using a circuit arrangement like that shown in Figure 7, soft error tolerance can be increased.

[0093] Here, the semiconductor device comprises a data input circuit Id and a clock input circuit Ick, the data input circuit Id being an inverter circuit including at least one type 1 MOS transistor 111, the clock input circuit Ick including two-stage inverter circuits i10, i11, the two-stage inverter circuits including at least one type 1 MOS transistor 101 / 104, and one of the drains 113 of the type 1 MOS transistor 111 of the data input circuit Id and the drains 103 / 106 of the type 1 MOS transistors 101 / 104 of the clock input circuit Ick being a first inverter The drain p11 of the first type MOS transistor pt11 of the inverting circuit i1 and the drain p21 of the first type MOS transistor pt21 of the second inverting circuit i2 are arranged in a first direction, and the other drain 113 of the first type MOS transistor 111 of the data input circuit Id and the drain 103 of the first type MOS transistor 101 of the clock input circuit Ick may be arranged in a first direction, along with the drain p31 of the first type MOS transistor pt31 of the third inverting circuit i3 and the drain p41 of the first type MOS transistor pt41 of the fourth inverting circuit i4.

[0094] (Embodiment 5) Embodiment 5 describes a different circuit arrangement example compared to Embodiment 4.

[0095] Figure 9 shows an example of a planar arrangement of a semiconductor device according to Embodiment 5. The arrangement diagram and the semiconductor device of Embodiment 5 shown in Figure 9 realize the circuit of Embodiment 4 with a different arrangement. The explanation of the reference numerals shown in Figure 9 is the same as in Embodiment 4, and the effect of increased soft error tolerance is also the same. In Figure 9, the arrangement of the clock input circuit Ick and the data input circuit Id is different from that in Figure 7. The latch circuits L1 and L2 are arranged so that they fit efficiently into a single rectangular area.

[0096] As shown in Figure 9, in a plan view, among the drains of the first type MOS transistors of the first to eighth inverting circuits, the drain closest to the drain p11 of the first type MOS transistor pt11 of the first inverting circuit i1 is included in the seventh inverting circuit i7. In other words, drain p11 is placed as close as possible to drain p32.

[0097] In a plan view, among the drains of the first type MOS transistors in the first to eighth inverting circuits, the drain closest to drain p21 of the first type MOS transistor pt21 in the second inverting circuit i2 is included in the eighth inverting circuit i8. In other words, drain p21 is placed as close as possible to drain p42.

[0098] In a plan view, among the drains of the first type MOS transistors in the first to eighth inverting circuits, the drain closest to drain p31 of the first type MOS transistor pt31 in the third inverting circuit i3 is included in the fifth inverting circuit i5. In other words, drain p31 is placed as close as possible to drain p12.

[0099] In a plan view, among the drains of the first type MOS transistors in the first to eighth inverting circuits, the drain closest to drain p41 of the first type MOS transistor pt41 in the fourth inverting circuit i4 is included in the sixth inverting circuit i6. In other words, drain p41 is placed as close as possible to drain p22.

[0100] In other words, latch circuit L1 is divided into two circuit parts, as shown in the dashed box. The two circuit parts are approximately the same size. Latch circuit L2 is divided into two circuit parts, as shown in the dotted box. The two circuit parts are approximately the same size. The four circuit parts of latch circuits L1 and L2 are arranged alternately so as to fit efficiently into one rectangular area (approximately a square area). Here, "alternate arrangement" refers to an arrangement like a diagonal cross or a checkerboard pattern.

[0101] In this way, by optimizing the arrangement of the circuit components, it is possible to realize a semiconductor device that incorporates a flip-flop circuit in a small area while maintaining high soft error tolerance.

[0102] As described above, in the semiconductor device according to Embodiment 5, in a plan view, the drain closest to the drain p11 of the first type MOS transistor pt11 of the first inverting circuit i1 is included in the seventh inverting circuit i7, the drain closest to the drain p21 of the first type MOS transistor pt21 of the second inverting circuit i2 is included in the eighth inverting circuit i8, the drain closest to the drain p31 of the first type MOS transistor pt31 of the third inverting circuit i3 is included in the fifth inverting circuit i5, and the drain closest to the drain p41 of the first type MOS transistor pt41 of the fourth inverting circuit i4 is included in the sixth inverting circuit i6.

[0103] According to this, for example, by using a circuit arrangement like that shown in Figure 9, soft error tolerance can be increased, and the circuit area can be reduced.

[0104] (Embodiment 6) Embodiment 6 describes an example in which the master-slave type flip-flop circuit of Embodiment 4 is further equipped with a reset function.

[0105] Figure 10 shows an example of a planar arrangement of a semiconductor device according to Embodiment 6 of the present invention. Figure 11 shows an example of a circuit of a semiconductor device according to Embodiment 6 of the present invention.

[0106] Figure 11 differs from the circuit example in Figure 8A in that PMOS transistors pr21 and nr21 have been added to the second inverting circuit i2, PMOS transistors pr41 and nr41 have been added to the fourth inverting circuit i4, PMOS transistors pr22 and nr22 have been added to the sixth inverting circuit i6, and PMOS transistors pr42 and nr42 have been added to the eighth inverting circuit i8. The following will explain the differences in detail.

[0107] A reset input signal is supplied to the gates of the added PMOS transistors and NMOS transistors.

[0108] According to the arrangement diagram shown in Figure 10 and the circuit diagram shown in Figure 11, the semiconductor device of Embodiment 6 has a reset function in which the second, fourth, sixth, and eighth inverting circuits i2, i4, i6, and i8 are composed of two-input NAND gates, in addition to the semiconductor device of Embodiment 4, by adding a transistor that receives a reset input signal R. The explanation of the symbols shown in Figure 10 is the same as in Embodiment 4, and the effect of increased soft error tolerance is also the same. As shown in Figure 10, by arranging the gate gr that receives the reset input signal R to be shared by multiple transistors, the number of connections in the flip-flop circuit can be reduced, contributing to a smaller area and enabling the realization of a semiconductor device with a flip-flop circuit that has high soft error tolerance.

[0109] As described above, in the semiconductor device according to Embodiment 6, at least one of the first to eighth inverting circuits i1 to i8 is a NAND type inverting circuit that takes a reset signal or a set signal as input.

[0110] According to this, it is possible to improve the soft error tolerance of a flip-flop circuit that has a reset function (or set function).

[0111] (Embodiment 7) In this embodiment, a semiconductor device that solves the following problems with respect to a circuit with high soft error tolerance will be described.

[0112] First, we will explain this problem in detail using Figure 25.

[0113] Figure 25 is an explanatory diagram showing an example of a short circuit in a latch circuit in a comparative example. The latch circuit shown in Figure 25(a) comprises four PMOS transistors and four NMOS transistors. The series-connected pairs of PMOS and NMOS transistors constitute an inverter circuit.

[0114] While a typical latch circuit has two inverter circuits, Figure 25(a) has four inverter circuits. The latch circuit in Figure 25(a) improves soft error tolerance through a redundant, duplicated configuration.

[0115] In Figure 25(a), the four inverter circuits are connected by four wires w1 to w4. Wires w1 and w3 are a redundant pair, having the same signal level but being independent wires. Similarly, wires w2 and w4 are a redundant pair, having the same signal level but being independent wires.

[0116] In the figure, the wiring w1 and w3 of the redundant wiring pair are drawn with thin lines to show an example of a low level. The wiring w2 and w4 of another redundant wiring pair are drawn with thick lines to show an example of a high level.

[0117] The same signal level is input to the gates of the PMOS and NMOS transistors in each inverter circuit, but they are connected to different wiring. That is, one of the redundant wiring pairs is connected to the gate of the PMOS transistor, and the other of the redundant wiring pair is connected to the gate of the NMOS transistor. In this way, the loop is formed by the four inverter circuits, so even if the output of one inverter circuit is inverted, the other three inverter circuits maintain the correct value. In this way, the latch circuit in the figure has increased soft error tolerance.

[0118] Figure 25(b) shows that wiring w1 and wiring w3 are short-circuited, as indicated by the dashed box sh1. Figure 25(c) also shows that wiring w2 and wiring w4 are short-circuited, as indicated by the dashed box sh2. Such short circuits can occur in the manufacturing process of semiconductor devices containing latch circuits, for example, due to the inclusion of conductive foreign matter such as metal particles.

[0119] In both Figure 25(b) and (c), redundant wiring pairs are short-circuited. That is, the wiring pairs short-circuited in dashed boxes sh1 and sh2 are independent wirings that are not connected to each other, but in the operation of the latch circuit they always have the same signal level. Therefore, in both Figure 25(b) and (c), the latch circuit operates normally and does not show any abnormalities. However, because the redundancy of the wiring pairs is lost due to the short circuit, there is a problem in that the soft error tolerance is deteriorated.

[0120] Furthermore, short circuits in dashed frames sh1 and sh2 are undetectable during the inspection phase of the semiconductor device manufacturing process. In other words, there is a problem in that it is impossible to detect the deterioration of soft error tolerance caused by short circuits in dashed frames sh1 and sh2.

[0121] Therefore, this disclosure provides a semiconductor device that reduces the deterioration of soft error tolerance caused by short circuits of redundant wiring pairs.

[0122] To solve such problems, a semiconductor device according to one aspect of the present disclosure comprises a first wiring, a second wiring that is not connected to the first wiring and is redundantly provided to transmit the same signal level as the first wiring, and other wiring that is different from the first wiring and the second wiring, wherein within the wiring layer, the distance between the first wiring and the second wiring is greater than the distance between the first wiring and the other wiring, and greater than the distance between the second wiring and the other wiring.

[0123] This approach reduces the deterioration of soft error tolerance caused by short circuits in redundant wiring pairs. This is because, when foreign objects of roughly the same size as the distance between wirings are introduced, a short circuit is more likely to occur between the first or second wiring and other wirings than between the first and second wirings. As a result, the occurrence of undetectable short circuits is suppressed, or in other words, the occurrence of short circuits in redundant wiring pairs is suppressed.

[0124] If a short circuit occurs between the first or second wiring and other wiring due to foreign matter contamination, there is a high probability that it will cause abnormal operation. Therefore, the short circuit can be detected during the inspection stage before leaving the factory.

[0125] In this way, the deterioration of soft error tolerance caused by short circuits in redundant wiring pairs can be reduced.

[0126] The embodiments will be described in detail below with reference to the drawings.

[0127] [7.1 Examples of Semiconductor Device Circuits] Figure 12 shows an example of a circuit formed in a semiconductor device according to Embodiment 1.

[0128] Compared to Figure 2, this figure mainly differs in that the symbols for drains p1 to p4 are omitted, and the symbols for wiring w11, w12, w21, and w22 are added. The following will explain the differences in detail.

[0129] The first to fourth inverting circuits are connected by four wires w11, w12, w21, and w22. Wires w11 and w12 are a redundant wire pair; they have the same signal level but are independent wires that are not connected to each other. Similarly, wires w21 and w22 are a redundant wire pair; they have the same signal level but are independent wires that are not connected to each other. Note that each wire constituting a redundant wire pair refers to a series of conductors including not only the metal wiring portion within the wiring layer, but also via contacts between wiring layers, the gate, source, and drain electrodes of the transistor, and the terminal electrodes of the circuit elements. Hereafter, via contacts may be simply referred to as vias.

[0130] Wiring w11 connects the output node o1 of the first inverting circuit i1 to the gate g2 of the first type MOS transistor pt2 of the second inverting circuit i2 and to the gate of the second type MOS transistor nt4 of the fourth inverting circuit i4.

[0131] Wiring w21 connects the output node o2 of the second inverting circuit i2 to the gate g3 of the first type MOS transistor pt3 of the third inverting circuit i3 and to the gate of the second type MOS transistor nt1 of the first inverting circuit i1.

[0132] Wiring w12 connects the output node o3 of the third inverting circuit i3 to the gate g4 of the first type MOS transistor pt4 of the fourth inverting circuit i4 and to the gate of the second type MOS transistor nt2 of the second inverting circuit i2.

[0133] Wiring w22 connects the output node o4 of the fourth inverting circuit i4 to the gate g1 of the first type MOS transistor pt1 of the first inverting circuit i1 and to the gate of the second type MOS transistor nt3 of the third inverting circuit i3.

[0134] This connection creates a loop with four inverter circuits. Therefore, even if the output of one inverter circuit is inverted due to a soft error, the other three inverter circuits maintain the correct value. In this way, the latch circuit L1 in the figure has enhanced soft error tolerance.

[0135] The latch circuit L1 shown in Figure 12 constitutes a part of the semiconductor circuit formed on the semiconductor substrate within the semiconductor device. The semiconductor circuit formed on the semiconductor substrate includes multiple p-type impurity regions, multiple n-type impurity regions, multiple wiring layers, and multiple contacts connecting the wiring layers.

[0136] The redundant wiring pairs, which are components of the latch circuit L1 in Figure 12, are formed on one or more wiring layers. In this embodiment, the redundant wiring pairs are arranged in a way that makes it difficult for short circuits to occur in the redundant wiring pairs due to contamination of foreign matter during the semiconductor device manufacturing process.

[0137] Next, we will describe the routing layout of redundant routing pairs within a single routing layer.

[0138] [7.2.1 First example of wiring layout within a wiring layer] Figure 13 shows a first example of a wiring layout within a wiring layer of a semiconductor device. This figure is a plan view of a semiconductor substrate on which the latch circuit L1 shown in Figure 12 is formed. Figure 13 is also a schematic enlarged view of a portion of the multiple wirings formed within a single wiring layer. Figure 13 shows the layout of four wirings 11, 12, 21, and 22.

[0139] Wires 11 and 12 represent a redundant wiring pair. Specifically, wire 12 is not connected to wire 11 and is redundantly provided to transmit the same signal level as wire 11. Wires 11 and 12 correspond, for example, to wires w11 and w12 in Figure 12.

[0140] Wiring 21 is a different wire from wiring 11 and wiring 12. Wiring 22 is also a different wire from wiring 11 and wiring 12.

[0141] In the diagram, 'a' indicates the distance between wire 11 and wire 12. 'b1' indicates the distance between wire 11 and wire 21. 'b2' indicates the distance between wire 12 and wire 21. 'b3' indicates the distance between wire 11 and wire 22. 'b4' indicates the distance between wire 12 and wire 22. Note that all of these distances are the minimum distances between wires.

[0142] These wiring layouts satisfy the following relationship:

[0143] The distance a between wire 11 and wire 12 is greater than the distance b1 between wire 11 and wire 21.

[0144] The distance a between wire 11 and wire 12 is greater than the distance b2 between wire 12 and wire 21.

[0145] The distance a between wire 11 and wire 12 is greater than the distance b3 between wire 11 and wire 22.

[0146] The distance a between wire 11 and wire 12 is greater than the distance b4 between wire 12 and wire 22.

[0147] This relationship ensures that, in the event of contamination, a short circuit is more likely to occur between wire 11 or wire 12 and other wires (21, 22) than between the redundant wire pair wire 11 and wire 12. As a result, the occurrence of undetectable short circuits is suppressed, or in other words, the occurrence of short circuits in redundant wire pairs is suppressed.

[0148] Since short circuits are more likely to occur between wiring 11 or 12 and other wirings (21, 22), the short circuit can be detected. Therefore, the deterioration of soft error tolerance caused by short circuits in redundant wiring pairs can be reduced.

[0149] In Figure 13, in order to satisfy the above relationship, the wiring 22 includes an extension e1 that extends from a via v2 connected to the main body of the wiring 22. The end of the extension e1 may be an open end that is not connected within the wiring layer.

[0150] Note that wiring 21 and wiring 22 in Figure 13 may correspond to wiring w21 and w22 in Figure 12, for example. Alternatively, wiring 21 and wiring 22 may each be a power line or a ground line.

[0151] [7.2.2 Second example of wiring layout within a wiring layer] Figure 14 shows a second example of a wiring layout within a wiring layer. This figure is a schematic, enlarged view of a portion of the multiple wirings formed within a single wiring layer. Figure 14 shows the layout of wirings 11, 12, and 21. In the figure, v1 indicates a via contact connecting wiring 21 to wiring in other wiring layers. e1 indicates an extended portion of wiring 21.

[0152] Wires 11 and 12 represent a redundant wiring pair. Wire 21 is another wiring that is different from wires 11 and 12. Wires 11 and 12 of the redundant wiring pair have parallel sections within the wiring layer, with the other wiring 21 sandwiched between them.

[0153] The wiring layout example in Figure 14 satisfies the following relationship, similar to Figure 13.

[0154] The distance a between wire 11 and wire 12 is greater than the distance b1 between wire 11 and wire 21.

[0155] The distance a between wire 11 and wire 12 is greater than the distance b2 between wire 12 and wire 21.

[0156] In Figure 14, the redundant wiring pair, wiring 11 and wiring 12, are arranged so as to sandwich the other wiring 21 across a parallel section where wiring 11 and wiring 12 are arranged in parallel. For this purpose, wiring 21 has an extended portion e1. That is, wiring 21 includes an extended portion e1 that extends from a via v1 connected to the main body of wiring 21. This extended portion e1 is located between wiring 11 and wiring 12 within the aforementioned parallel section. Furthermore, the end of the extended portion e1 may be an open end that is not connected within the wiring layer.

[0157] According to the wiring layout example in Figure 14, if foreign matter is introduced, a short circuit is more likely to occur between wire 11 or wire 12 and other wire 21 before a short circuit occurs between the redundant wiring pair wires 11 and 12. In other words, there is a high probability that a short circuit in the redundant wiring pair will be replaced by another detectable short circuit. This reduces the deterioration of soft error tolerance caused by a short circuit in the redundant wiring pair.

[0158] Note that the wiring 21 in Figure 14 may, for example, be a wiring corresponding to one of the wirings w21 and w22 in Figure 12, or it may be a power line or a ground line.

[0159] [7.2.3 Third example of wiring layout within a wiring layer] Figure 15 shows a third example of a wiring layout within a wiring layer. This figure is a schematic, enlarged view of a portion of the multiple wirings formed within a single wiring layer. Figure 15 shows the layout of wirings 11, 12, and 21. In the figure, v1 indicates a via contact connecting wiring 21 to wiring in other wiring layers.

[0160] Wires 11 and 12 represent a redundant wiring pair. Wire 21 is another wiring that is different from wires 11 and 12. Wires 11 and 12 of the redundant wiring pair have parallel sections within the wiring layer, with the other wiring 21 sandwiched between them.

[0161] The wiring layout example in Figure 15 also satisfies the following relationship, similar to Figure 13.

[0162] The distance a between wire 11 and wire 12 is greater than the distance b1 between wire 11 and wire 21.

[0163] The distance a between wire 11 and wire 12 is greater than the distance b2 between wire 12 and wire 21.

[0164] In Figure 15, the redundant wiring pair, wiring 11 and wiring 12, are arranged so as to sandwich the other wiring 21 across a parallel section where wiring 11 and wiring 12 are arranged in parallel. For this reason, wiring 21 has extension portions e1 to e3. That is, wiring 21 includes extension portions e1 to e3 that extend from via v1 connected to the main body of wiring 21. Extension portions e1 to e3 are a single continuous wiring and are arranged to bypass the end of wiring 11 within the wiring layer. Part of extension portion e3 is arranged so as to be sandwiched between wiring 11 and wiring 12 across the parallel section. The end of extension portion e3 may also be an open end that is not connected within the wiring layer. Furthermore, distances b1 and b2 in Figure 15 may each be the minimum spacing between wirings according to the design rules for semiconductor devices. Also, the distance a between wiring 11 and wiring 12 is greater than the minimum spacing between wirings according to the design rules.

[0165] According to the wiring layout example in Figure 15, if foreign matter is introduced, a short circuit is more likely to occur between wire 11 or wire 12 and another wire 21 before a short circuit occurs between the redundant wiring pair, wires 11 and 12. In other words, there is a high probability that a short circuit in the redundant wiring pair will be replaced by another detectable short circuit. This reduces the deterioration of soft error tolerance caused by a short circuit in the redundant wiring pair.

[0166] Note that the wiring 21 in Figure 15 may, for example, be a wiring corresponding to one of the wirings w21 and w22 in Figure 12, or it may be a power line or a ground line.

[0167] [7.2.4 Fourth example of wiring layout within a wiring layer] Figure 16 shows a fourth example of a wiring layout within a wiring layer. This figure is a schematic, enlarged view of a portion of the multiple wirings formed within a single wiring layer. Figure 16 shows the layout of wirings 11, 12, 21, and 22. In the figure, v1 indicates a via contact connecting wiring 21 to wiring in other wiring layers.

[0168] Wires 11 and 12 represent a redundant wiring pair. Similarly, wires 21 and 22 also represent a redundant wiring pair. The wiring pair of wires 11 and 12 is called the first redundant pair, and the wiring pair of wires 21 and 22 is called the second redundant pair. In Figure 16, the four wires 11, 12, 21, and 22 are arranged in the following order: one wire 11 of the first redundant pair, one wire 21 of the second redundant pair, the other wire 12 of the first redundant pair, and the other wire 22 of the second redundant pair. In other words, the wires of the two redundant pairs are arranged alternately, and wires with the same signal level are not adjacent to each other.

[0169] The wiring layout example in Figure 16 also satisfies the following relationship, similar to Figure 13.

[0170] The distance a between wire 11 and wire 12 is greater than the distance b1 between wire 11 and wire 21.

[0171] The distance a between wire 11 and wire 12 is greater than the distance b2 between wire 12 and wire 21.

[0172] Each of the wires 11, 12, 21, and 22 in Figure 16 may be the main part of the wire or an extension.

[0173] According to the wiring layout example in Figure 16, if foreign matter is introduced, a short circuit is more likely to occur between wire 11 or wire 12 and another wire 21 or wire 22 before a short circuit occurs between the redundant wiring pair wires 11 and 12. In other words, there is a high probability that a short circuit in the redundant wiring pair will be replaced by another detectable short circuit. This reduces the deterioration of soft error tolerance caused by a short circuit in the redundant wiring pair.

[0174] Note that wiring 11 and wiring 12 in Figure 16 may correspond to wiring w11 and w12 in Figure 12, and wiring 21 and wiring 22 may correspond to wiring w21 and w22 in Figure 12.

[0175] [7.2.5 Fifth example of wiring layout within a wiring layer] Figure 17 shows a fifth example of a wiring layout within a wiring layer. This figure is a schematic, enlarged view of a portion of the multiple wirings formed within a single wiring layer. Figure 17 shows the layouts of wirings 11, 12, and 21. In the figure, v1 and v2 indicate via contacts connecting wiring 21 to wiring in other wiring layers. e1 refers to the extended portion of wiring 21.

[0176] Wires 11 and 12 represent a redundant wiring pair. Wire 21 is another wiring that is different from wires 11 and 12. Wires 11 and 12 of the redundant wiring pair have parallel sections within the wiring layer, with the other wiring 21 sandwiched across these parallel sections.

[0177] The wiring layout example in Figure 17 satisfies the following relationship, similar to Figure 13.

[0178] The distance a between wire 11 and wire 12 is greater than the distance b1 between wire 11 and wire 21.

[0179] The distance a between wire 11 and wire 12 is greater than the distance b2 between wire 12 and wire 21.

[0180] In Figure 17, the redundant wiring pair, wiring 11 and wiring 12, are arranged so as to sandwich the other wiring 21 across a parallel section where wiring 11 and wiring 12 are arranged in parallel. For this purpose, wiring 21 has an extended portion e1. That is, wiring 21 includes an extended portion e1 that extends from the main body of wiring 21. This extended portion e1 is located between wiring 11 and wiring 12 within the aforementioned parallel section. Furthermore, the end of the extended portion e1 may be an open end that is not connected within the wiring layer.

[0181] According to the wiring layout example in Figure 17, when foreign matter is introduced, a short circuit is more likely to occur between wire 11 or wire 12 and other wires 21 than between the redundant wire pair wires 11 and 12. In other words, there is a higher probability that a short circuit in a redundant wire pair will be replaced by another detectable short circuit. This reduces the deterioration of soft error tolerance caused by short circuits in redundant wire pairs.

[0182] Note that the wiring 21 in Figure 17 may, for example, be a wiring corresponding to one of the wirings w21 and w22 in Figure 12, or it may be a power line or a ground line.

[0183] [7.2.6 Sixth example of wiring layout within a wiring layer] Figure 18 shows a sixth example of a wiring layout within a wiring layer. This figure differs from Figure 17 in that the main body of wiring 21 belongs to another wiring layer, and the extension portion e1 extends from the main body of wiring 21 via via v3. The following will explain the differences in detail.

[0184] The main body of wiring 21 belongs to a different wiring layer than the wiring layer to which wiring 11 and wiring 12 belong, as shown by the dashed line in the figure.

[0185] The extended portion e1 extends from the main body of the wiring 21 belonging to another wiring layer via via v3. As a result, the redundant wiring pair wiring 11 and wiring 12 have a parallel section within the wiring layer, with the extended portion e1 of the other wiring 21 sandwiched across this parallel section.

[0186] As shown in the wiring layout example in Figure 18, similar to Figure 17, the deterioration of soft error tolerance caused by short circuits in redundant wiring pairs can be reduced.

[0187] [7.2.7 Seventh example of wiring layout within a wiring layer] Figure 19 shows the seventh example of a wiring layout within a wiring layer. This figure differs from Figure 14 in that power supply wiring has been added. The following will explain the differences in detail.

[0188] The wiring 21 is a power supply wiring and has extensions e1 and e2 extending from the main body of the power supply wiring. The power supply wiring may be, for example, wiring arranged to surround all or part of the latch circuit L1 within the wiring layer, or it may be shielded wiring formed in another wiring layer.

[0189] As shown in the wiring layout example in Figure 19, similar to Figure 14, the deterioration of soft error tolerance caused by short circuits in redundant wiring pairs can be reduced.

[0190] [7.2.8 Eighth example of wiring layout within a wiring layer] Figure 20 shows the eighth example of a wiring layout within a wiring layer. The figure is a schematic, enlarged view of a portion of the multiple wirings formed within a single wiring layer. Figure 20 shows the layout of wirings 11, 12, 21, and 22. In the figure, v1 indicates a via contact connecting wiring 21 to wiring in another wiring layer. v2 indicates a via contact connecting wiring 22 to wiring in another wiring layer. e1 indicates an extension of wiring 21. e2 indicates an extension of wiring 22.

[0191] Wires 11 and 12 represent a redundant wiring pair. Wire 21 is another wire, different from wires 11 and 12. Wire 22 is yet another wire, different from wires 11 and 12. Wires 21 and 22 are not a redundant wiring pair. The redundant wiring pair, wires 11 and 12, have parallel sections within the wiring layer, with the other wire 21 and the other another wire 22 sandwiching each other for most of the parallel section. The other wire 21 and the other another wire 22 are located on the same straight line with a gap d1 between them.

[0192] The wiring layout example in Figure 20 satisfies the following relationship, similar to Figure 13.

[0193] The distance a between wire 11 and wire 12 is greater than the distance b1 between wire 11 and wire 21 or wire 22.

[0194] The distance a between wire 11 and wire 12 is greater than the distance b2 between wire 12 and wire 21 or wire 22.

[0195] Furthermore, in Figure 20, the distance a between wire 11 and wire 12 is greater than the distance d1 between wire 21 and wire 22. In other words, the distance d1 of the section where wires 11 and 12 are adjacent and parallel (i.e., the section without other wires in between) is smaller than the distance a between wire 11 and wire 12.

[0196] In Figure 20, the redundant wiring pair, wiring 11 and wiring 12, are positioned so as to sandwich wiring 21 or wiring 22 over most of the parallel section in which wiring 11 and wiring 12 are arranged in parallel. For this reason, wiring 21 has an extended portion e1, and wiring 22 has an extended portion e2. In other words, the ends of the extended portions e1 and e2 may be open ends that are not connected within the wiring layer.

[0197] As shown in the wiring layout example in Figure 20, the deterioration of soft error tolerance caused by short circuits in redundant wiring pairs can be reduced, similar to Figure 14.

[0198] Note that wiring 21 in Figure 20 may be, for example, a power line or a ground line. Similarly, wiring 22 may be, for example, a power line or a ground line.

[0199] Figures 13 to 20 show examples of redundant wiring pair layouts within a single wiring layer. The following sections will describe redundant wiring pair layouts in different wiring layers.

[0200] [7.3.1 First example of wiring layout between wiring layers] Figure 21 shows a first example of a wiring layout between wiring layers. Figure (a) shows a plan view of the wiring layout of a semiconductor substrate on which a latch circuit L1 is formed. Figure (b) shows a cross-section of line AA in (a), which includes three wiring layers M1 to M3. Figure 21 shows a schematic enlarged view of the portion of the wiring formed in wiring layers M1 to M3 that relates to a redundant wiring pair. Figure 21 shows wiring 11 and wiring 12 of the redundant wiring pair.

[0201] As shown in Figure 21, the redundant wiring pair, wiring 11 and wiring 12, belong to different wiring layers. Specifically, wiring 11 belongs to wiring layer M3, and wiring 12 belongs to wiring layers M2 and M1 and includes via contacts.

[0202] Redundant wiring pairs on different wiring layers are arranged to satisfy the following relationship: If wiring 11 and wiring 12 are on different wiring layers, the distance a between wiring 11 and wiring 12 is greater than the interlayer distance c between adjacent wiring layers. In the figure, three distances a1, a2, and a3 are shown for wiring 11 and wiring 12, but the distance a between wiring 11 and wiring 12 is the minimum a1 or a3. Wiring 11 and wiring 12 are arranged such that a > c.

[0203] More specifically, in Figure 21, in a plan view of the semiconductor device, wiring 11 and wiring 12 have overlapping portions and intersect. Wiring 12 has a first partial wiring 12b corresponding to the overlapping portion, a second partial wiring 12a connected to one end of the first partial wiring 12b, and a third partial wiring 12c connected to the other end of the first partial wiring 12b. The first partial wiring 12b belongs to wiring layer M1. The second partial wiring 12a and the third partial wiring 12c belong to wiring layer M2, which is different from wiring layer M1, and are connected to the first partial wiring 12b via via contacts v1 and v2. Wiring 11 belongs to wiring layer M3, which is further away from wiring layer M1 than wiring layer M2. This arrangement layout easily satisfies the above relationship (i.e., a > c). In Figure 21, the distance a2 between wiring 11 and wiring 12 in the overlapping portion is arranged to satisfy at least twice the interlayer distance c.

[0204] According to the layout shown in Figure 21, the deterioration of soft error tolerance caused by short circuits in redundant wiring pairs can be reduced. This is because, even if a foreign object of roughly the same size as the interlayer distance c is introduced, a short circuit between wiring 11 and wiring 12 is less likely to occur. As a result, the occurrence of short circuits in redundant wiring pairs is suppressed.

[0205] Note that the wiring layers M1 to M3 in Figure 21 may be any three of multiple wiring layers, as long as they are arranged in this order. However, the interlayer distance c is not necessarily the distance between wiring layer M2 and wiring layer M3 in Figure 21, but rather the minimum distance between two adjacent wiring layers.

[0206] [7.3.2 Second example of wiring layout between wiring layers] Figure 22A shows a second example of wiring layout between wiring layers. Figure (a) shows the wiring layout in a plan view of the semiconductor substrate on which the latch circuit L1 is formed. Figure (b) shows a cross-section of line BB in (a), which includes two wiring layers M2 and M3. Figure 22A shows a schematic enlarged view of the portion of the wiring formed in wiring layers M2 and M3 that relates to a redundant wiring pair. Figure 22A shows wiring 11 and wiring 12 of the redundant wiring pair.

[0207] In the plan view shown in Figure (a), wiring 12 is positioned to bypass the end of wiring 11 so that it does not overlap with wiring 11.

[0208] This arrangement makes it easy to satisfy the above relationship (i.e., a > c).

[0209] According to the layout shown in Figure 22A, the deterioration of soft error tolerance caused by short circuits in redundant wiring pairs can be reduced. This is because, even if a foreign object of roughly the same size as the interlayer distance c is introduced, a short circuit between wiring 11 and wiring 12 is less likely to occur. As a result, the occurrence of short circuits in redundant wiring pairs is suppressed.

[0210] [7.3.3 Second example of wiring layout between wiring layers] Figure 22B shows a modified example of the second wiring layout between wiring layers. This figure differs from Figure 22A in that it includes wiring 31. The differences will be explained below. Wiring 31 is located next to wiring 11 or wiring 12 and includes a via contact v1 and an extended portion e1. The via contact v1 connects the wiring 31 portion of another wiring layer M4 to the wiring 31 of wiring layer M3. The extended portion e1 extends from the via contact v1. Furthermore, the following extension rule may be established: the length e1 from via v1 to the end of the extended portion e1 is greater than the minimum wiring dimension in the semiconductor device design rules. Note that this extension rule may also be applied to extended portions in other drawings.

[0211] In Figure 22B, the extended portion e1 of wiring 31 is positioned so that it is adjacent to one of the redundant wiring pairs within the same wiring layer, and adjacent to the other wiring in a different wiring layer. Furthermore, distance a is greater than the distance between wiring 11 and wiring 31, and greater than the distance between wiring 12 and wiring 31.

[0212] Depending on the wiring design CAD software, attempting to achieve Figure 22A without wiring 31 may impose limitations, requiring the use of only minimal wiring between redundant pairs, which can make layout difficult. By appropriately placing wiring 31 next to wiring 11 or 12, the layout of redundant wiring pairs can be easily designed. As a result, a layout of redundant wiring pairs like that shown in Figure 22B can be easily achieved.

[0213] [7.4 Other Circuit Examples for Semiconductor Devices] Next, we will describe other circuit examples that have redundant wiring pairs.

[0214] Figure 23 shows another example of a circuit formed in the semiconductor device according to Embodiment 1. The semiconductor device in this figure shows an example of a BISER (Built in Soft Error Resilience) type flip-flop circuit configuration as a circuit incorporating soft error tolerance.

[0215] The flip-flop circuit in the figure comprises a delay circuit DL, an inverter IV, master latches ML0 and ML1, master C element CM, slave latches SL0 and SL1, slave C element CS, master weak hold circuit WM, and slave weak hold circuit WS, forming a redundant master-slave structure. The redundant wiring pairs in Figure 23 are the wiring connected to the output Qn of slave latch SL0 and the wiring connected to the output Qn of slave latch SL1.

[0216] The delay circuit DL delays the input data D to master latch ML0 by time τ and outputs it to master latch ML1.

[0217] Inverter IV outputs a clock signal Cn, which is the inverted version of the clock signal Cp.

[0218] The master latch ML0 latches the input data D and outputs data Qp in synchronization with the clock signals Cp and Cn. Output data Qp is non-inverted output data at the same logic level as data D.

[0219] The master latch ML1 latches the delayed input data D in synchronization with the clock signals Cp and Cn, and outputs data Qp. Output data Qp is non-inverted output data at the same logic level as data D.

[0220] The Master C element (CM) is a 2-input, 1-output inverting circuit. When the two inputs are at the same fixed logic level, it outputs the inverted level of that logic level. When the two inputs are not at the same fixed logic level, it becomes high impedance.

[0221] The master weak-hold circuit (WM) is a weak-keeper circuit that holds the logic level output by the master C element (CM). When the output of the master C element (CM) is high impedance, it outputs the logic level it was holding just before it became high impedance.

[0222] The slave latch SL0 latches the input data D in synchronization with the clock signals Cp and Cn, and outputs the data Qn. The output data Qn is the logic-level data obtained by inverting the data D.

[0223] The slave latch SL1 latches the input data D in synchronization with the clock signals Cp and Cn, and outputs the data Qn. The output data Qn is the inverted version of the data D.

[0224] The slave C element CS is a 2-input, 1-output inverting circuit. When the two inputs are at the same confirmed logic level, it outputs the inverted logic level of those inputs. When the two inputs are not at the same confirmed logic level, it becomes high impedance. An example circuit of the slave C element CS is shown in Figure 24. The slave C element CS in this figure consists of two PMOS transistors and two NMOS transistors. The two PMOS transistors and the two NMOS transistors are connected in series. The master C element CM can be the same as in Figure 24.

[0225] The slave weak-hold circuit WS is a weak-keeper circuit that holds the same logic level as the output of the slave C element CS, and outputs the logic level it was holding just before the output of the slave C element CS became high impedance.

[0226] In such a flip-flop circuit, if one of the two sets of master-slave-blatch flips due to a soft error, the output of the master C element CM or slave C element CS becomes high impedance, but the correct data can be preserved by the logic level held by the master weak-hold circuit WM or slave weak-hold circuit WS.

[0227] In the flip-flop circuit shown in Figure 23, the redundant wiring pairs consist of a wire connecting the output terminal of slave latch SL0 to one of the two input terminals of slave C element CS, and a wire connecting the output terminal of slave latch SL1 to the other of the two input terminals of slave C element CS. In other words, the output wires of slave latch SL0 and slave latch SL1 are redundant wiring pairs.

[0228] This wiring pair satisfies the arrangement layout relationship described in Figures 13 to 22B. This reduces the deterioration of soft error tolerance caused by short circuits in redundant wiring pairs within the flip-flop circuit shown in Figure 23.

[0229] Note that the output wiring of master latch ML0 and master latch ML1 in Figure 23 may be treated the same as a redundant wiring pair. In other words, the arrangement layout relationships described in Figures 13 to 22B may be satisfied.

[0230] The input data D of master latch ML1 is delayed by time τ compared to the input data D of master latch ML0. Consequently, the output data Qp of master latch ML1 is delayed by time τ compared to the output data Qp of master latch ML0. In this specification, a redundant wiring pair is defined as "an independent wiring pair that has the same signal level but is not connected to each other." The output wiring of master latch ML0 and master latch ML1 does not satisfy this definition. However, the output wiring of master latch ML0 and master latch ML1 can experience the wiring short-circuit problem shown in Figure 25, and also closely matches the definition of a redundant wiring pair except for the delay time τ. Therefore, the deterioration of soft error tolerance can be reduced by having the output wiring of master latch ML0 and master latch ML1 satisfy the arrangement layout relationship described in Figures 13 to 22B.

[0231] In this embodiment, a redundant wiring pair is shown as an example of duplication. However, any combination of two wires from a triple or more multiplexed wiring array may also be considered a wiring pair. In this case, the two wires considered as a wiring pair only need to satisfy the arrangement layout relationship described in Figures 13 to 22B.

[0232] As described above, the semiconductor device in the embodiment includes a first wiring 11, a second wiring 12 that is not connected to the first wiring 11 and is provided to transmit the same signal level as the first wiring 11, and other wirings 21 and 22 that are different from the first wiring 11 and the second wiring 12, wherein within the wiring layer, the distance a between the first wiring 11 and the second wiring 12 is greater than the distances b1 and b3 between the first wiring 11 and the other wirings 21 and 22, and greater than the distance b2 or b4 between the second wiring 12 and the other wiring 21 or 22.

[0233] This approach reduces the deterioration of soft error tolerance caused by short circuits in redundant wiring pairs. This is because, when foreign objects of roughly the same size as the distance between wirings are introduced, a short circuit is more likely to occur between the first or second wiring and other wirings than between the first and second wirings. As a result, the occurrence of undetectable short circuits is suppressed, or in other words, the occurrence of short circuits in redundant wiring pairs is suppressed.

[0234] Here, the first wiring 11 and the second wiring 12 have parallel sections arranged in parallel within the wiring layer, and other wirings 21 and 22 may be sandwiched between them in the parallel section.

[0235] Here, the other wirings 21 and 22 include an extended portion e1 that extends from the main body portion of the other wirings 21 and 22 within the wiring layer, and the extended portion e1 may be sandwiched between the first wiring 11 and the second wiring 12 within the parallel section of the wiring layer.

[0236] Here, the other wirings 21 and 22 include extensions e1 extending from vias connected to the main body portions of the other wirings 21 and 22, and the extensions e1 may be sandwiched between the first wiring 11 and the second wiring 12 within a parallel section in the wiring layer.

[0237] Here, the other wirings 21 and 22 have extended portions e1 that branch off from the main body portions of the other wirings 21 and 22 within the wiring layer, and the extended portions e1 may be sandwiched between the first wiring 11 and the second wiring 12 within the parallel section of the wiring layer.

[0238] Here, the end of the extended portion e1 may be an open end that is not connected within the wiring layer.

[0239] Here, the extended portions e1 to e3 may bypass the end of the first wiring 11 within the wiring layer and may also be arranged over a parallel section.

[0240] Here, the system includes a third wire and a fourth wire that is not connected to the first wire 11 and is provided to transmit the same signal level as the third wire, and the other wires 21 or 22 may be the third wire.

[0241] Here, portions of the first wiring 11 to the fourth wiring may be arranged in the wiring layer in the order of first wiring 11, third wiring, second wiring 12, and fourth wiring.

[0242] According to this, the wiring is arranged in the order of one wire of the first redundant pair, one wire of the second redundant pair, the other wire of the first redundant pair, and the other wire of the second redundant pair, thus preventing or reducing short circuits in the redundant pairs.

[0243] Here, the via may connect the extended portion to the main body portions of other wirings 21 and 22 in a wiring layer different from the wiring layer described above.

[0244] Here, the length of the extended portion e1 may be greater than the minimum dimension specified in the design rules for the semiconductor device.

[0245] Here, the first wiring 11 and the second wiring 12 include a section within the wiring layer that is arranged in parallel, sandwiching other wirings 21, 22 and yet another set of wirings 21, 22, and the distance d1 between the other wirings 21, 22 and yet another set of wirings 21, 22 within that section may be smaller than the distance between the first wiring 11 and the second wiring 12.

[0246] Here, the first wiring 11 and the second wiring 12 may be components of a DICE (Dual Interlocked Storage Cell) latch circuit.

[0247] Here, the first wiring 11 and the second wiring 12 may be components of a BISER (Built in Soft Error Resiliency) flip-flop circuit.

[0248] Furthermore, the semiconductor device in this embodiment includes a plurality of wiring layers, a first wiring 11, and a second wiring 12 that is not connected to the first wiring 11 and is provided to transmit the same signal level as the first wiring 11. The first wiring 11 and the second wiring 12 belong to different wiring layers, and the distance a1 between the first wiring 11 and the second wiring 12 is greater than the interlayer distance c between adjacent wiring layers.

[0249] This reduces the deterioration of soft error tolerance caused by short circuits in redundant wiring pairs. This is because, if a foreign object roughly the same size as the distance between the wires is introduced, a short circuit between the first and second wires becomes less likely. In other words, the occurrence of short circuits in redundant wiring pairs is suppressed.

[0250] Here, the semiconductor device has a portion where the first wiring 11 and the second wiring 12 overlap in a plan view, and the distance between the first wiring 11 and the second wiring 12 in the overlapping portion may be twice or more the interlayer distance c.

[0251] Here, in a plan view of the semiconductor device, the first wiring 11 and the second wiring 12 intersect at the overlapping portion, and the second wiring 12 has a first partial wiring 12b corresponding to the overlapping portion, a second partial wiring 12a connected to one end of the first partial wiring 12b, and a third partial wiring 12c connected to the other end of the first partial wiring 12b, the first partial wiring 12b belongs to the first wiring layer M1, the second partial wiring 12a and the third partial wiring 12c belong to a second wiring layer M2 different from the first wiring layer M1 and are connected to the first partial wiring 12b via via contacts v1 and v2, and the first wiring 11 may belong to a third wiring layer M3 which is further away from the first wiring layer M1 than the second wiring layer M2.

[0252] Here, the second wiring 12 may be arranged to bypass the end of the first wiring 11 so that the first wiring 11 and the second wiring 12 do not overlap in a plan view of the semiconductor integrated circuit.

[0253] Herein, the wiring further comprises a third wiring 31 that faces at least one of the first wiring 11 and the second wiring 12 between or within the wiring layers, wherein the third wiring 31 may have an extended portion e1 extending from a via.

[0254] Here, the length of the extended portion e1 may be greater than the minimum dimension specified in the design rules for the semiconductor device.

[0255] Although several embodiments have been described above, it is also possible to combine the components of these embodiments to create new embodiments. Furthermore, even if a circuit other than an inverter or a 2-input NAND gate is used, as long as it has the function of inverting the relationship between its input and output, it may be considered an inverter without limiting the specific circuit configuration.

[0256] Although semiconductors relating to one or more embodiments of this disclosure have been described above based on embodiments, this disclosure is not limited to these embodiments. Without departing from the spirit of this disclosure, various modifications that a person skilled in the art can conceive of these embodiments, or forms constructed by combining components from different embodiments, may also be included within the scope of one or more embodiments of this disclosure. [Industrial Applicability]

[0257] As described above, the semiconductor device according to the present disclosure can realize a semiconductor device with high soft error tolerance in a small area, and thus is useful as a semiconductor integrated circuit or the like mounted on an electronic device such as an in-vehicle device that requires stable operation in a small area. [Explanation of Signs]

[0258] Wn1 N-well region Wp1, Wp2 P-well regions p1, p2, p3, p4 Drain nodes p11, p21, p31, p41 Drain nodes p12, p22, p32, p42 Drain nodes pt1~pt4 PMOS transistors pt11, pt21, pt31, pt41 PMOS transistors pt12, pt22, pt32, pt42 PMOS transistors 101, 104, 111 PMOS transistors [[ID=3l]]n11, n21, n31, n41 Drain nodes n12, n22, n32, n42 Drain nodes nt1~nt4 NMOS transistors nt11, nt21, nt31, nt41 NMOS transistors nt12, nt22, nt32, nt42 NMOS transistors 102, 105, 112 NMOS transistors g1, g2, g3, g4 Gates g11, g21, g31, g41 Gates g12, g22, g32, g42 Gates gck, gr Common gates i1~i8 First to eighth inverter circuits CK Clock input signal CKI, CKIN Clock signals D Data input signal S1, S2 Switch Circuit Q Output Signal R Reset Input Signal Id Data Input Circuit Ick Clock Input Circuit O1 Output Circuit L1, L2 Latch Circuit F1 Flip-Flop Circuit

Claims

1. A first latch circuit consisting of first to fourth inverting circuits, First and second Type 1 well regions, A second type well region is provided, The first to fourth inverting circuits are, respectively, Type 1 MOS transistor and Type 2 MOS transistor and It has an output node connected to the drain of the first type MOS transistor and the drain of the second type MOS transistor, The output node of the first inverting circuit is connected to the gate of the first type MOS transistor of the second inverting circuit and the gate of the second type MOS transistor of the fourth inverting circuit. The output node of the second inverting circuit is connected to the gate of the first type MOS transistor of the third inverting circuit and the gate of the second type MOS transistor of the first inverting circuit. The output node of the third inverting circuit is connected to the gate of the first type MOS transistor of the fourth inverting circuit and the gate of the second type MOS transistor of the second inverting circuit. The output node of the fourth inverting circuit is connected to the gate of the first type MOS transistor of the first inverting circuit and the gate of the second type MOS transistor of the third inverting circuit. Each of the drains of the first type MOS transistors of the first to fourth inverting circuits is located in the second type well region. The drains of the first and second type 2 MOS transistors of the inverting circuit are each located in the first type 1 well region. The drains of the second type MOS transistors of the third and fourth inverting circuits are each located in the second first type well region. The second type well region is positioned between the first type well region and the second type well region. In a plan view, the distance between the drain of the first type MOS transistor of the first inverting circuit and the drain of the first type MOS transistor of the third inverting circuit is greater than the distance between the drain of the first type MOS transistor of the first inverting circuit and the drain of the first type MOS transistor of the fourth inverting circuit. The sources of the first type MOS transistors in the first and second inverting circuits are shared and connected to the power line. The sources of the first type MOS transistors in the third and fourth inverting circuits are shared and connected to the power line. Semiconductor equipment.

2. The first and second first-type well regions are P-type wells, The aforementioned Type 2 well region is an N-type well. The semiconductor device according to claim 1.

3. In a plan view, the distance between the drain of the first type MOS transistor in the second inverting circuit and the drain of the first type MOS transistor in the fourth inverting circuit is greater than the distance between the drain of the first type MOS transistor in the second inverting circuit and the drain of the first type MOS transistor in the third inverting circuit, and greater than the distance between the drain of the first type MOS transistor in the third inverting circuit and the drain of the first type MOS transistor in the fourth inverting circuit. The semiconductor device according to claim 1 or 2.

4. At least one of the first and second first to fourth inverting circuits is a clocked inverting circuit that takes a clock signal as input. A semiconductor device according to any one of claims 1 to 3.

5. The semiconductor device includes a second latch circuit consisting of fifth to eighth inverting circuits after the first latch circuit. The fifth to eighth inverting circuits are, respectively, Type 1 MOS transistor and Type 2 MOS transistor and It has an output node connected to the drain of the first type MOS transistor and the drain of the second type MOS transistor, The output node of the fifth inverting circuit is connected to the gate of the first type MOS transistor of the sixth inverting circuit and the gate of the second type MOS transistor of the eighth inverting circuit. The output node of the sixth inverting circuit is connected to the gate of the first type MOS transistor of the seventh inverting circuit and the gate of the second type MOS transistor of the fifth inverting circuit. The output node of the seventh inverting circuit is connected to the gate of the first type MOS transistor of the eighth inverting circuit and the gate of the second type MOS transistor of the sixth inverting circuit. The output node of the eighth inverting circuit is connected to the gate of the first type MOS transistor of the fifth inverting circuit and the gate of the second type MOS transistor of the seventh inverting circuit. Each of the drains of the first type MOS transistors in the fifth to eighth inverting circuits is located in the second type well region. The drains of the second-type MOS transistors of the fifth and sixth inverting circuits are each located in the first first-type well region. The drains of the second type MOS transistors of the seventh and eighth inverting circuits are each located in the second first type well region. In a plan view, the distance between the drain of the first type MOS transistor in the fifth inverting circuit and the drain of the first type MOS transistor in the seventh inverting circuit is greater than the distance between the drain of the first type MOS transistor in the fifth inverting circuit and the drain of the first type MOS transistor in the eighth inverting circuit. A semiconductor device according to any one of claims 1 to 4.

6. In a plan view, the drain of the first type MOS transistor of the first inverting circuit is arranged to be aligned in one direction with the drain of the first type MOS transistor of the seventh inverting circuit. In a plan view, the drain of the first type MOS transistor of the second inverting circuit is arranged to be aligned with the drain of the first type MOS transistor of the eighth inverting circuit in the same direction. The semiconductor device according to claim 5.

7. In a plan view, the drain of the first type MOS transistor of the first inverting circuit is arranged to be aligned in one direction with the drain of the first type MOS transistor of the seventh inverting circuit. In a plan view, the drain of the first type MOS transistor of the second inverting circuit is arranged to be aligned with the drain of the first type MOS transistor of the eighth inverting circuit in the same direction. In a plan view, the drain of the first type MOS transistor of the third inverting circuit is arranged to be aligned with the drain of the first type MOS transistor of the fifth inverting circuit in the same direction. In a plan view, the drain of the first type MOS transistor of the fourth inverting circuit is arranged to be aligned with the drain of the first type MOS transistor of the sixth inverting circuit in the same direction. The semiconductor device according to claim 5.

8. The semiconductor device is such that at least one of the first to eighth inverting circuits is a clocked inverting circuit that takes a clock signal as input. The semiconductor device according to claim 5.

9. The semiconductor device is a NAND type inverting circuit in which at least one of the first to eighth inverting circuits takes a reset signal or a set signal as input. The semiconductor device according to claim 5.

10. The semiconductor device comprises a data input circuit and a clock input circuit. The data input circuit is an inverter circuit including at least one first-type MOS transistor, The aforementioned clock input circuit includes a two-stage inverter circuit. The aforementioned two-stage inverter circuit includes at least one first-type MOS transistor, The drain of the first type MOS transistor in the data input circuit and the drain of the first type MOS transistor in the clock input circuit are arranged in a first direction, aligned with the drain of the first type MOS transistor in the first inverting circuit and the drain of the first type MOS transistor in the second inverting circuit. The drain of the first type MOS transistor in the data input circuit and the other drain of the first type MOS transistor in the clock input circuit are arranged in the first direction, aligned with the drain of the first type MOS transistor in the third inverting circuit and the drain of the first type MOS transistor in the fourth inverting circuit. The semiconductor device according to claim 5.

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