Multilayer wiring structure and its manufacturing method

Abstract

To provide a multilayer wiring structure capable of reducing disconnection in a bottom part or the like of a connection hole.SOLUTION: A multilayer wiring structure according to an embodiment of the present disclosure contains: a first insulation layer containing a first wiring layer 102, a first inorganic layer 104 that is provided onto the first wiring layer 102, and cover and contact a side surface of the first wiring layer 102, and at least one part of an upper surface, and a first organic resin film 106 that is provided onto the first inorganic layer 104; and a second insulation layer containing a second wiring layer 108 provided onto the first organic resin film 106, a second inorganic layer 109 that is provided onto the second wiring layer 108, and cover and contact a side surface of the second wiring layer 108 and at least one part of an upper surface, and a second organic resin film 111 that is provided onto the second inorganic layer 109.SELECTED DRAWING: Figure 1

Description

Technical Field

[0005]

[0001] The present invention relates to a multilayer wiring structure and a method for manufacturing the same. In particular, the present invention relates to a multilayer wiring structure in which Cu wirings are multilayered via an insulating layer and a method for manufacturing the same.

Background Art

[0002] A multilayer wiring structure is known in which a plurality of wirings are arranged in a plurality of layers and connection holes are provided for connecting the plurality of wirings arranged in different layers (see, for example, Patent Document 1). In such a multilayer wiring structure, an organic resin material such as polyimide is often used as an insulating material between layers. This is because the dielectric constant of the organic resin material is generally a small value, and it is difficult for a delay of a signal transmitted through the wiring to occur.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] However, the thermal expansion coefficient of the organic resin material is larger than that of copper or the like which is the material of the wiring. Therefore, when a thermal cycle test is performed on the wiring structure or it is used in a high-temperature environment, disconnection is likely to occur at the bottom of the connection hole or the like due to the difference between the thermal expansion coefficient of the resin material and the thermal expansion coefficient of the wiring.

[0005] In other words, while the thermal expansion coefficient (linear expansion coefficient) of organic resin is 50-100E-6 / K, when copper (Cu) is used as the wiring material, the thermal expansion coefficient (linear expansion coefficient) of the wiring material is 17E-6 / K. Thus, the thermal expansion coefficient of the organic resin is several times larger than that of the wiring material, and if the wiring layer is exposed to an atmosphere exceeding 200°C during the formation process, tensile stress will be generated in the copper at the connection holes. This tensile stress occurs because the thermal expansion of the organic resin acts to increase the distance between the wiring above and below the organic resin.

[0006] Therefore, in an attempt to relieve this tensile stress, the copper inside the connection hole tries to move, forming a void at the bottom of the connection hole. This void causes a poor electrical connection between the upper and lower wiring.

[0007] In addition to the occurrence of such voids, the low adhesion between the barrier conductive layer covering the bottom and sides of the connection holes and the organic resin can also lead to deformation of the barrier conductive layer and delamination from the organic resin.

[0008] Generally, multilayer wiring structures such as printed circuit boards and interposers are intended for use in environments where temperature cycles from -25°C to 125°C occur. These temperature cycles in such environments also generate strong tensile stress on the copper within the connection holes, leading to connection failures similar to those described above.

[0009] Furthermore, in recent years, as LSIs have become smaller and more integrated, there has been a growing trend towards mounting LSI chips on printed circuit boards and interposers. Consequently, the demand for higher density wiring layers in multilayer wiring structures is increasing.

[0010] To achieve such high density, the width of the wiring, the spacing between wirings, and the size of the connection holes are reduced, and a structure called stacked vias is used, in which additional connection holes are placed on top of the connecting copper. This is necessary. As a result, the tensile stress on the copper within the connection hole is further increased, leading to a higher failure rate in connections and a decrease in reliability.

[0011] Therefore, one of the objectives of the present invention is to provide a multilayer wiring structure that reduces wire breakage at the bottom of connection holes and the like.

[0012] Furthermore, reducing the height of the connection holes can slightly reduce tensile stress. However, this reduces the distance between the upper and lower wiring layers, leading to increased parasitic capacitance, crosstalk, and signal propagation delay. As a result, it becomes difficult to fully utilize the performance of LSIs mounted on printed circuit boards or interposers.

[0013] Therefore, another objective of the present invention is to provide a multilayer wiring structure that can suppress the increase in parasitic capacitance, crosstalk, and signal propagation delay more effectively than conventional multilayer wiring structures, even when the distance between the upper and lower wiring layers is reduced.

[0014] Furthermore, if the height of the connection hole decreases, the effect of the additive (leveler) in the electroplating solution becomes reduced when filling the connection hole with copper by electroplating, making it impossible to adequately fill it with copper. As a result, voids are formed within the connection hole, which, like the formation of voids at the bottom of the connection hole, reduces reliability.

[0015] Therefore, another objective of the present invention is to provide a multilayer wiring structure and the like that suppresses the generation of voids within connection holes.

[0016] Furthermore, when using an organic resin film as an insulating film between copper wirings, in conventional multilayer wiring structures, the outer circumference of the copper wiring, except for the bottom, was in direct contact with the organic resin film. As a result, copper atoms are thermally diffused into the surrounding organic resin film each time heat treatment is applied. In addition, copper atoms are ionized and diffused by the electric field generated between adjacent wirings. Due to this diffusion, when the distance between wirings becomes small, there is a problem that short circuits between wirings and dielectric breakdown of the organic resin insulating film are more likely to occur.

[0017] Furthermore, in LSI construction, the damascene method is used to form Cu wiring. In the damascene method, barrier metal is placed on the sides and bottom of the Cu wiring to suppress the diffusion of Cu atoms. However, materials containing Ti or Ta used as barrier metal have high electrical resistance. Therefore, there is a problem in that the resistance of the wiring increases as the thickness of the barrier metal increases relative to the wiring width. [Means for solving the problem]

[0018] One embodiment of the present invention provides a multilayer wiring structure comprising a substrate, a lower Cu wiring, an upper Cu wiring, and a via connection portion. The lower Cu wiring is disposed on the substrate. The upper Cu wiring is disposed on an insulating layer including an inorganic material film located on the lower Cu wiring and an organic resin material film located on the inorganic material film. The via connection portion is disposed in a via connection hole that penetrates the insulating layer vertically in the region where the lower Cu wiring and the upper Cu wiring overlap. The via connection portion also has a barrier conductive layer disposed on the lower Cu wiring exposed at the bottom of the via connection hole and on the inner wall of the via connection hole. Furthermore, the dielectric constant of the material constituting the organic resin material film is smaller than the dielectric constant of the material constituting the inorganic material film.

[0019] Furthermore, as an embodiment of the present invention, a multilayer wiring structure formed by stacking a plurality of layers is provided. The plurality of layers include adjacent first and second layers. The first layer has first Cu wiring. The second layer has second Cu wiring, an insulating film, via connections, The insulating film, comprising the above, is disposed between the second Cu wiring and the first Cu wiring. The via connection portion is disposed in a via connection hole that penetrates vertically through the insulating layer in the region where the first Cu wiring and the second Cu wiring overlap. The insulating film comprises an inorganic material film covering at least the surface of the second Cu wiring on the side of the first Cu wiring, and an organic material film covering the inorganic material film. The via connection portion has a barrier conductive layer disposed on the second Cu wiring exposed at the bottom of the via connection hole and on the inner wall of the via connection hole. Furthermore, the dielectric constant of the material constituting the organic resin material film is smaller than the dielectric constant of the material constituting the inorganic material film.

[0020] Furthermore, as an embodiment of the present invention, a method for manufacturing a multilayer wiring structure is provided, comprising forming a lower layer Cu wiring on a substrate, forming an inorganic material film on the lower layer Cu wiring, forming an organic resin material film on the inorganic material film to form an insulating layer including the inorganic material film and the organic material film, opening the insulating layer to reach the lower layer Cu wiring to form via connection holes, forming a barrier conductive layer at the bottom and inner wall of the via connection holes, filling the via connection portions with Cu to form via connection portions, and forming upper layer Cu wiring on the via connection portions, wherein the dielectric constant of the material constituting the inorganic material film is smaller than the dielectric constant of the material constituting the inorganic material film.

[0021] According to such a multilayer wiring structure and manufacturing method, the proportion of the organic resin material film in the upper substrate can be reduced. As a result, voids such as those at the bottom of via connection holes are generated due to the difference in thermal expansion coefficients between the organic resin material film and Cu, thereby reducing the occurrence of disconnections between the upper Cu wiring or the first wiring and the lower Cu wiring or the second wiring. Furthermore, an increase in wiring capacitance between Cu wirings can be suppressed.

[0022] Furthermore, in the above embodiment of the present invention, the end of the inorganic insulating film on the inner wall side of the via connection hole may be in contact with the barrier conductive layer.

[0023] With this configuration, it is possible to suppress the occurrence of voids at the bottom of via connection holes and the like.

[0024] Further, in the above-described embodiment of the present invention, the inorganic insulating film may be configured to be formed so as to cover the upper surface and the side surfaces of the lower layer Cu wiring or the second wiring. Note that the upper surface of the second wiring refers to the surface of the second wiring on the side of the first wiring.

[0025] With this configuration, it is possible to suppress the diffusion of Cu atoms and Cu ions from the lower layer Cu wiring or the second wiring. This effect becomes remarkable by using a silicon nitride film as the inorganic insulating film. This is because silicon nitride has a large effect of controlling the diffusion of Cu. In addition, since there is no need to dispose a barrier metal on the side surface of the lower layer Cu wiring or the second wiring, it is possible to reduce the increase in the resistance value that increases as the width of the lower layer Cu wiring or the second wiring becomes smaller.

[0026] Further, in the above-described embodiment of the present invention, it is preferable that the ratio of the inorganic material film to the total film thickness of the inorganic material film and the organic resin material film is 20% or more and 80% or less.

[0027] By setting the ratio of the inorganic material film in this way, it is possible to more effectively prevent disconnection between the upper layer Cu wiring or the first wiring and the lower layer Cu wiring or the second wiring. In addition, generally, the dielectric constant of the organic resin material film is lower than that of the inorganic material film, so the wiring capacitance between the upper layer Cu wiring or the first wiring and the lower layer Cu wiring or the second wiring can be reduced, and the delay of the signal transmitted by the wiring can be suppressed.

[0028] Further, in the above-described embodiment of the present invention, it is preferable that the inorganic material film contains silicon and the material of the barrier conductive layer contains a high melting point metal or its compound. Furthermore, it is preferable that the inorganic material film and the barrier metal layer are in contact with each other.

[0029] Since the silicon-containing inorganic material film and the material containing a high-melting-point metal or its compound exhibit good adhesion, it is possible to more effectively prevent disconnection between the upper Cu wiring or first wiring and the lower Cu wiring or second wiring. [Effects of the Invention]

[0030] According to one embodiment of the present invention, it is possible to provide a multilayer wiring structure that suppresses the occurrence of wire breakage at the bottom of connection holes, etc. Furthermore, according to one embodiment of the present invention, it is possible to provide a multilayer wiring structure that suppresses the increase in wiring capacitance between wires. [Brief explanation of the drawing]

[0031] [Figure 1] This is a cross-sectional view including connection holes in a wiring structure according to one embodiment of the present invention. [Figure 2A] This figure shows the manufacturing process of a wiring structure according to one embodiment of the present invention. [Figure 2B] This figure shows the manufacturing process of a wiring structure according to one embodiment of the present invention. [Figure 2C] This figure shows the manufacturing process of a wiring structure according to one embodiment of the present invention. [Figure 3] This figure shows the manufacturing process of a wiring structure according to one embodiment of the present invention. [Figure 4] This is an example diagram of a structure in which an LSI chip is arranged using a wiring structure according to one embodiment of the present invention. [Figure 5A] This figure shows the manufacturing process of a wiring structure according to one embodiment of the present invention. [Figure 5B] This figure shows the manufacturing process of a wiring structure according to one embodiment of the present invention. [Figure 5C] This figure shows the manufacturing process of a wiring structure according to one embodiment of the present invention. [Figure 5D] This figure shows the manufacturing process of a wiring structure according to one embodiment of the present invention. [Figure 5E] This figure shows the manufacturing process of a wiring structure according to one embodiment of the present invention. [Figure 5F]This figure shows the manufacturing process of a wiring structure according to one embodiment of the present invention. [Figure 6] This figure shows the manufacturing process of a wiring structure according to one embodiment of the present invention. [Figure 7] This figure shows the manufacturing process of a wiring structure according to one embodiment of the present invention. [Figure 8] This is an example diagram of a structure in which an LSI chip is arranged using a wiring structure according to one embodiment of the present invention. [Figure 9A] This figure shows the manufacturing process of a wiring structure according to one embodiment of the present invention. [Figure 9B] This figure shows the manufacturing process of a wiring structure according to one embodiment of the present invention. [Figure 9C] This figure shows the manufacturing process of a wiring structure according to one embodiment of the present invention. [Figure 9D] This figure shows the manufacturing process of a wiring structure according to one embodiment of the present invention. [Figure 9E] This figure shows the manufacturing process of a wiring structure according to one embodiment of the present invention. [Figure 10] This figure shows an example of a cross-section of a wiring structure according to one embodiment of the present invention. [Figure 11] This graph shows the defect rate in the manufacturing of a wiring structure according to one embodiment of the present invention. [Figure 12] This graph shows the defect rate in the manufacturing of a wiring structure according to one embodiment of the present invention. [Modes for carrying out the invention]

[0032] The following describes embodiments for carrying out the present invention. However, the present invention is not limited to these embodiments, and these embodiments can be modified as needed. Note that the width, length, thickness, etc., in the drawings may be exaggerated and may differ from those when the present invention is carried out. Furthermore, the film thickness, materials, conditions, etc., during film formation described below are illustrative and can be modified as needed.

[0033] (Embodiment 1) Figure 1 shows a cross-sectional view of a wiring structure according to one embodiment of the present invention. Figure 1 also includes a cross-section of a connection hole for connecting the wiring of the first layer (lower layer) and the wiring of the second layer (upper layer). The connection hole is located in the region where the wiring of the first layer and the wiring of the second layer overlap. The portion of the wiring of the second layer located in the connection hole is sometimes called a via connection.

[0034] In Figure 1, wiring material 102 is arranged on a substrate (substrate) 101. There are no particular restrictions on the material of the substrate 101, but examples include semiconductors such as silicon and glass. If the substrate 101 is a silicon substrate, it is preferable to form a silicon oxide film as an insulating film on the silicon substrate. There are no particular restrictions on the thickness of the substrate 101, but it can be set in the range of 300 μm to 1000 μm, for example. If a support substrate is used under the substrate 101 (not shown), a substrate with a thickness of 10 μm to 100 μm can also be used. Furthermore, the substrate 101 may have a layered structure and wiring may already be formed on one or more of the layers.

[0035] The wiring material 102 constitutes the wiring of the first layer. The wiring material 102 is made of conductive materials such as Au, Al, and Cu. Among these, Cu is preferred because it has high conductivity and low material cost. There are no particular restrictions on the thickness of the wiring material 102, but for example, it is about 4 μm. It is preferable to place a barrier metal 103 between the substrate 101 and the wiring material 102. This prevents the metal constituting the wiring material 102 from diffusing toward the substrate 101. The barrier metal 103 can be a high-melting-point metal or a compound thereof. The high-melting-point metal or a compound thereof is a material whose melting point is higher than the temperature at which the organic insulating material constituting the organic resin material film is heat-cured, and whose melting point is 1500°C or higher. As a high-melting-point metal or a compound thereof, for example, the barrier metal 103 can be made of materials such as Ti, TiN, or Ta, TaN.

[0036] An inorganic material film is placed on the upper surface of the substrate 101 and on the upper and side surfaces of the wiring material 102. The inorganic material film constitutes an insulating film in all areas except the connection holes between the wiring of the first layer and the wiring of the second layer. The inorganic material film is composed of one or more layers. Preferably, the inorganic material film is composed of multiple inorganic material films of different materials stacked together. In Figure 1, the inorganic material film is composed of a first inorganic material film 104 and a second inorganic material film 105 formed on the first inorganic material film 104.

[0037] The first inorganic material film 104 is, for example, a film formed of silicon nitride and is deposited by plasma CVD. The second inorganic material film 105 is, for example, a film formed of silicon oxide and is deposited by plasma CVD. By covering the top and sides of the wiring material 102 with the silicon nitride film, the diffusion of atoms, molecules, and ions of the wiring material 102 can be prevented. In addition, since a barrier metal 103 is placed on the bottom surface of the wiring material 102, the diffusion of atoms, molecules, and ions of the wiring material 102 can also be prevented by the barrier metal 103. The thicknesses of the first inorganic material film and the second inorganic material film can be appropriately selected to obtain the desired insulation. The thickness of the first inorganic material film 104 may be 0.1 μm and the thickness of the second inorganic material film 105 may be 2 μm.

[0038] An organic resin material film 106 made of an organic insulating material is placed on top of the second inorganic material film 105. The organic material film 106 constitutes an insulating film in all areas except the connection holes between the wiring of the first layer and the wiring of the second layer. For example, polyimide can be used as the material for the organic resin material film 106. Organic materials such as polyimide have a dielectric constant that is lower than that of inorganic materials such as P-SiN films and P-SiO2 films formed by plasma CVD, so multiple wiring materials arranged in multiple layers The capacitance between the wires can be reduced, and the delay of the signal transmitted through the wiring material can be reduced. The thickness of the organic resin material film 106 can be appropriately selected to obtain the desired insulation. Alternatively, by adjusting the thickness of the organic resin material film 106 on the second inorganic material film 105 positioned above the wiring material 102 so that it is between 20% and 80% of the sum of the thicknesses of the first inorganic material film 104, the second inorganic material film 105, the organic material film 106, and the organic resin material film 106, it is possible to achieve both miniaturization and buffering of surrounding thermal expansion. This is because the dielectric constant of inorganic materials is generally greater than that of organic resin materials, so if it falls below 20%, it will lead to an increase in parasitic capacitance due to miniaturization. Also, because the thermal expansion coefficient of organic materials is greater than that of wiring materials, if it exceeds 80%, the rate of void generation due to thermal expansion will increase. For example, the thermal expansion coefficient (linear expansion coefficient) of a P-SiO2 film is 0.5~2E-6 / K. It is about one-tenth to one-hundredth the size of an organic resin film.

[0039] Preferably, the dielectric constant of the material constituting the first organic material film 106 is smaller than that of the material constituting the first inorganic material film 104 and the material constituting the second inorganic material film 105. This makes it possible to suppress an increase in wiring capacitance between wiring materials. Furthermore, the relationship between the dielectric constant of the material constituting the first inorganic material film 104 and the dielectric constant of the material constituting the second inorganic material film 105 may be equal, the former may be greater than the latter, or the former may be less than the latter.

[0040] The specific dielectric constant values ​​for the materials are as follows. When polyimide is used as the material constituting the first organic material film 106, it is preferable that the dielectric constant of the polyimide be 3.5 or less. This is because the dielectric constant of P-SiN, an example of a material constituting the first inorganic material film 104, is usually 7.0, and the dielectric constant of P-SiO2, an example of a material constituting the second inorganic material film 105, is usually 4.1. When P-SiN is used as the material for the first inorganic material film 104, and P-SiO2 is used as the material constituting the second inorganic material film 105, the dielectric constant of the material constituting the first inorganic material film 104 is the second The dielectric constant of the inorganic material film 105 becomes greater than that of the material constituting the inorganic material film 104. Therefore, in this case, from the viewpoint of suppressing an increase in wiring capacitance, it is preferable that the thickness of the first inorganic material film 104 be small, for example, smaller than the thickness of the second inorganic material film 105.

[0041] When a P-SiN film is used as the first inorganic material film 104, a P-SiO2 film is used as the second inorganic material film 105, and a polyimide film is used as the organic resin material film 106, The thickness of each film can be, for example, 0.1 μm, 2.0 μm, and 8.0 μm (thickness on the wiring). Therefore, in this case, the thickness of the P-SiO2 film is equal to the thickness of the polyimide film. This will be 25% of the original thickness. Since polyimide undergoes thermal shrinkage of approximately 15% due to heat treatment for curing, when applying polyimide, this thermal shrinkage should be taken into consideration, and the thickness on the wiring should be 9.4 μm. The thickness of the wiring material 102 can be 4.0 μm, in which case the total thickness will be 13.4 μm. Since the first inorganic material film 104 and the second inorganic material film 105 have the same thickness on and off the wiring, the first inorganic material film 104 and the second inorganic material film 105 can be ignored.

[0042] To connect the wiring of the first layer and the wiring of the second layer, via connection holes are formed in the organic resin material film 106, the second inorganic material film 105, and the first inorganic material film 104, with the bottom reaching the wiring material 102. A barrier metal film 107 is formed on the bottom and sides as a barrier conductive layer, and the wiring material 108 is placed on top of the barrier metal film 107. The material of the barrier metal film 107 can be a high melting point metal or a compound thereof. For example, the barrier metal 103 can be made of materials such as Ti, TiN, or Ta, TaN. The wiring material 108 constitutes the wiring in the upper second layer. That is, the wiring material 108 constitutes wiring placed in a layer different from the layer on which the wiring material 102 is placed.

[0043] Polyimide films can be formed using methods such as spin coating or film lamination. However, there are limitations to the film thickness. For example, spin coating or film lamination... When using this method, the limit is approximately 20 μm. On the other hand, in the deposition of P-SiO2 films, the film thickness There are virtually no restrictions on this. Therefore, if the height of the connection hole is insufficient, the P-SiO2 film The height of the connection holes can be adjusted by changing the thickness. This allows for matching the wiring capacitance and impedance between the lower and upper layers of wiring.

[0044] Furthermore, when using a silicon wafer as the substrate 101, the organic resin and Cu wiring have tensile stress, which can cause the wafer to warp. This warping increases with the number of wiring layers, making it unsuitable for processing with exposure equipment or plasma CVD equipment. Also, even when the interposer is cut from the wafer and made into chips, this warping remains, which can cause defects in stacking chips or bonding to motherboards. However, this problem can be solved by giving the P-SiO2 film compressive stress, which can cause the organic resin and C This allows for balancing the tensile stress inherent in the U-shaped wiring.

[0045] As described above, the P-SiO2 film, which has a lower coefficient of thermal expansion than the organic resin film, is used as the organic resin material film 10 By placing it below 6, the tensile stress when using Cu in the connection hole can be reduced. For example, if the distance between the upper and lower wiring layers, i.e., the height of the connection hole, is 10 μm, and a P-SiO2 film with a thickness of 2 μm is formed in this 10 μm distance, the remaining approximately The 8 μm thick layer is made of organic resin material. The tensile stress in this case is 20% lower than when the entire 10 μm distance is made of organic resin material.

[0046] This value is simply calculated from the difference in thermal expansion coefficients, but the strong adhesion between the Ti and Ta-containing material of the barrier metal film 107 formed on the side of the connection hole and P-SiO2 (800N) It becomes more than / m. On the other hand, the adhesion force between the barrier metal layer 107 material and polyimide is 300 N / m or less. ) and the high elastic modulus of P-SiO2 (40 GPa or more. On the other hand, poly The elastic modulus of imide is 3-7 GPa. Applying the action of ( ) further reduces the tensile stress. For this reason, even if the polyimide in the layer where the wiring is placed tries to undergo elastic deformation due to thermal expansion by high-temperature treatment during the wiring formation process, the P-SiO2 placed above and below the polyimide Because of its high modulus of elasticity, it cannot be easily deformed. This further reduces the tensile stress within the connection hole.

[0047] The top and sides of the wiring material 108 are covered with an inorganic material film, similar to the wiring material 102. For example, a first inorganic material film 109 is placed on the top and sides of the wiring material 108, and a second inorganic material film 110 is placed on top of the first inorganic material film 109. Furthermore, an organic resin material film 111 is placed on top of the second inorganic material film 110.

[0048] By covering the parts of the wiring material 108 that are not in contact with the barrier metal, and the top and side surfaces of the wiring material 102 with a plasma nitride film (P-SiN film), it is possible to prevent atoms, molecules, and ions of the wiring materials 108 and 102 from diffusing into the organic resin material films 106 and 111 due to heat or other factors. Furthermore, the barrier metal film 107 on the bottom and side surfaces of the connection holes also prevents atoms, molecules, and ions of the wiring material 108 from diffusing into the organic resin material film 106 due to heat or other factors.

[0049] Furthermore, by using silicon oxide as the material for the second inorganic material film 105, the adhesion with the barrier metal placed on the inner surface of the connection hole is increased, and wire breakage can be suppressed. In this case, by making the second inorganic material film 105 thicker than the first inorganic material film 104, the adhesion with the barrier metal can be further improved. Also, when a P-SiN film is used as the first inorganic material film 104, the adhesion with the barrier metal can be further improved by making it about the same thickness as the first inorganic material film 104.

[0050] Furthermore, the sides of the upper and lower wiring, which are composed of wiring materials 108 and 102, are deburred. There is no need to cover with barrier metal. Barrier metal generally has a higher resistance than wiring materials such as Cu, and using a large amount of barrier metal increases the resistance of the wiring. Therefore, in this embodiment, there is no need to cover the sides of the wiring made up of wiring materials 108 and 102 with barrier metal, so the increase in the resistance of the wiring can be suppressed.

[0051] For example, if the width of the wiring is 1 μm, and a 0.1 μm barrier metal is placed on the side of the wiring, the area occupied by the barrier metal will be 20% of the wiring's cross-sectional area. Therefore, the wiring resistance will increase by 20% compared to when no barrier metal is used. This increase in wiring resistance will increase as the wiring width decreases.

[0052] It is thought that this increase in wiring resistance can be avoided by making the barrier metal thinner. However, when the barrier metal is thinned, the barrier metal oxidizes in the thickness direction due to oxygen diffusing from the insulating film surrounding the barrier metal, and the barrier performance deteriorates. On the other hand, since P-SiN is stable to oxygen, deterioration does not occur due to covering the sides of the wiring with P-SiN as in this embodiment. Therefore, according to this embodiment, the increase in wiring resistance can be suppressed, and the increase in wiring resistance can be suppressed even when the wiring is miniaturized and the wiring width is reduced.

[0053] The manufacturing process of the wiring structure according to this embodiment will be described with reference to Figures 2A, 2B, 2C, and 3.

[0054] First, as shown in Figure 2A(a), a barrier metal 103 is placed in the portion of the substrate 101 where the wiring material 102 will be placed, and the wiring material 102 is placed by electroplating to a thickness of, for example, 4 μm. Then, a first inorganic material film 104 with a thickness of 0.1 μm and a second inorganic material film 105 with a thickness of 2.0 μm are formed in sequence.

[0055] Next, as shown in Figure 2A(b), an organic resin material such as a photosensitive polyimide, which will become the organic resin material film 106, is coated onto the second inorganic material film 105 using a method such as spin coating to a thickness of, for example, 15 μm, and an opening 106a is created by lithography. The opening 106a becomes part of the via connection hole.

[0056] After creating the opening 106a, the organic resin material film 106 is heat-cured. Upon heat curing, as shown in Figure 3, the upper portion 106b of the wiring material 102 may become convex due to the presence of the wiring material 102 and the thermal shrinkage of the organic resin material. In such cases, the upper surface can be flattened using a fly cutter or the like. Alternatively, to avoid such convex shapes, an organic resin material with a low thermal shrinkage rate can be used.

[0057] Next, as shown in Figure 2A(d), the organic resin material film 106 is used as a mask to form via connection holes by etching, penetrating the second inorganic material film 105 and the first inorganic material film 104, with their bottoms reaching the wiring material 102. This ensures that the via connection holes penetrate the insulating film composed of the organic resin material film 106, the second inorganic material film 105, and the first inorganic material film 104 up to their upper limit. It is not necessary to provide openings 106a anywhere other than the location where the via connection holes are placed. Since the limit of the photosensitive resolution of polyimide is 0.5 μm, the minimum diameter of the via connection holes is considered to be 0.5 μm.

[0058] Next, as shown in Figure 2B(e), a barrier metal film 107 is placed on the upper surface of the organic resin material film 106, including the inner surface of the opening 106a, and the Cu film 108a is placed on top of it. At this time, it is preferable to bring the barrier metal film 107 and the second inorganic material film 105 into contact. This is because high adhesion between the barrier metal film 107 and the second inorganic material film 105 can suppress wire breakage.

[0059] Next, a photoresist is applied to the Cu film 108a, and by exposure and development, a wiring pattern 108b is formed as shown in Figure 2B(f).

[0060] Next, using electroplating, Cu is grown on the portion of the Cu film 108a that is not covered by the wiring pattern 108b, and as shown in Figure 2B(g), Cu is filled as wiring material 108 into the via connection holes and the wiring pattern 108b, forming via connections within the via connection holes, and then an upper layer of wiring is formed on top of the via connections.

[0061] Next, the wiring pattern 108b is removed, and the exposed Cu film 108a and the barrier metal film 107 beneath it are removed using an acidic aqueous solution or the like to obtain the configuration shown in Figure 2C(h).

[0062] Subsequently, as shown in Figure 2C(i), a first inorganic material film 109 is formed to cover the organic resin material film 106 and the wiring material 108, and then, as shown in Figure 2C(j), a second inorganic material film 110 is formed.

[0063] When further wiring is to be formed on top of the wiring formed by the wiring material 108, the wiring material 108 is considered as wiring material 102, the first inorganic material film 109 as the first inorganic material film 104, and the second inorganic material film 110 as the second inorganic material film 105, and the process from Figure 2A(a) onward is repeated again.

[0064] In this embodiment, since it is not necessary to cover the sides of the wiring material 102 with barrier metal, an increase in the resistance value of the wiring can be suppressed. Furthermore, by covering the sides of the wiring material 102 with the first inorganic material film 104, the diffusion of atoms constituting the wiring material 102 can be suppressed. In addition, if the adhesion between the barrier metal formed on the inner surface of the connection hole and the inorganic material film (e.g., P-SiO2 film) is good, the organic resin material film 106 This can suppress the occurrence of wire breakage in connection holes due to thermal expansion. Furthermore, by using a photosensitive material as the material for the organic resin material film 106, an opening 106a can be formed in the organic resin material film 106, and it can be used as a mask to form openings in the first inorganic material film 104 and the second inorganic material film 105, thereby simplifying the process.

[0065] As mentioned above, the minimum diameter of the via connection hole is considered to be 0.5 μm, and the minimum wiring width is a small value of 0.5 μm. In this embodiment, since it is not necessary to cover the sides of the wiring with barrier metal, even if the wiring width is 0.5 μm, the increase in wiring resistance can be suppressed.

[0066] (Embodiment 2) Figure 4 shows an example of LSI chip arrangement using a wiring structure according to Embodiment 2 of the present invention. This is an example of an arrangement known as 2.5-dimensional packaging.

[0067] In Figure 4, the interposer 401 is a multilayer wiring structure according to this embodiment. Logic LSIs 402, such as a CPU (Central Processing Unit) and an ASIC (Application Specific Integrated Circuit), and memory LSIs 403, 404, 405, and 406, such as a DRM and flash memory, are arranged on the interposer 401, and these are connected via wiring within the interposer 401. This configuration allows signal lines, power lines, and ground lines to be connected over short distances between the memory LSIs 403, 404, 405, and 406 and the logic LSIs 402. As a result, high-speed processing is possible overall.

[0068] The manufacturing process of the wiring structure as the interposer 401 according to this embodiment will be explained with reference to Figures 5A, 5B, 5C, and 5D.

[0069] As shown in Figure 5A(a), a 3 μm thick SiO2 film (P-SiO2 film) 502 is formed on a substrate 501 such as a silicon substrate using plasma CVD. Next, a 0.1 μm thick Ti film 503 and a 0.3 μm thick Cu film 504a are deposited by sputtering. The Ti film 503 acts as a barrier metal film to prevent Cu from diffusing into the substrate 501. The Cu film 504a acts as a seed for growing Cu by electroplating. Note that other barrier metal materials such as TiN or high-melting-point metals like Ta can also be used.

[0070] Next, as shown in Figure 5A(b), a photoresist is applied to the Cu film 504a, and then exposure and development are performed to form the wiring pattern 505. Subsequently, a Cu film 504 is grown on the Cu film 504a exposed from the wiring pattern 505 using electroplating to a thickness of 4.4 μm. In this embodiment, the Cu is used as the wiring material for the first layer, and the design dimension value for the wiring thickness is 4.0 μm.

[0071] Next, the photoresist that forms the wiring pattern 505 after growing the Cu is removed with an organic solvent to obtain the structure shown in Figure 5A(c). Alternatively, instead of using an organic solvent, ashing with oxygen plasma can be used to remove the photoresist.

[0072] Next, as shown in Figure 5A(d), the portions of the Cu film 504a and Ti film 503 that were covered by the wiring pattern 505 are removed with an acidic aqueous solution to form the Cu wiring 504b in the first layer. By removing the Cu film 504a in the portion covered by the wiring pattern 505, the thickness of the Cu film 504, which was 4.4 μm, is reduced to approximately 4.0 μm, thus achieving the design dimension. Alternatively, instead of using an acidic aqueous solution to remove the Cu film 504a and Ti film 503, ion milling can also be used.

[0073] When using an acidic aqueous solution, the undercut 601 becomes larger, as shown in Figure 6. In particular, when the width of the wiring is 5 μm or less, sufficient adhesion cannot be achieved between the Cu wiring 504b and the underlying substrate, and the Cu wiring may peel off due to its own stress. On the other hand, when using ion milling, such undercuts are less likely to occur, making it possible to form fine wiring.

[0074] Next, as shown in Figure 5A(e), a P-SiN film 506 with a thickness of 0.1 μm is deposited on the Cu wiring 504b in the first layer by plasma CVD, followed by a P-SiO2 film 507 with a thickness of 2 μm. For the deposition of the P-SiN film 506, SiH4 can be used as the Si source and NH3 as the nitrogen source. For the deposition of the P-SiO2 film 507, SiH4 can be used as the Si source and N2O as the oxygen source. Tetraethoxysilane (TEOS) can also be used as the Si source. O2 can also be used as the oxygen source. This is also possible. Furthermore, the structure shown in Figure 2A(a) can be considered to be included in the structure shown in Figure 5A(e).

[0075] P-SiO2 suppresses the warping of the wafer that forms the substrate 501, reducing film stress by -100. It is preferable to adjust the compressive stress to ~-300 MPa. In particular, it is preferable to adjust the membrane stress to -200 MPa.

[0076] Furthermore, if copper oxide is present on the surface of the Cu wiring 504b in the first layer, the adhesion between P-SiN and Cu will decrease, so it is preferable to wash the wiring 504b with dilute sulfuric acid or the like before forming the P-SiN film 506. In addition, before forming the P-SiN film 506, Cu should be treated in the same chamber. The surface of wiring 504b can also be exposed to NH3 plasma to remove copper oxide.

[0077] The P-SiN film 506 prevents the Cu atoms, Cu molecules, and Cu ions of the Cu wiring 504b from thermally diffusing from the sides and top of the Cu wiring 504b to the P-SiO2 film 507, and further It acts as a barrier insulating film that prevents diffusion caused by electric fields between adjacent wirings. Instead of using P-SiN as the barrier insulating film, SiC (which may contain several percent to 10% oxygen) can be used. SiC films can also be deposited by plasma CVD and have the effect of preventing the diffusion of Cu atoms, Cu molecules, and Cu ions in Cu wiring 504b.

[0078] Alternatively, instead of forming a P-SiO2 film 507, film formation can be performed using SiOC, SiFO, etc. This may also be done. SiOC and SiOF films can also be deposited by plasma CVD. Furthermore, SiOC and SiOF have a lower dielectric constant than P-SiO2, and the dielectric between adjacent wirings Linear capacitance can be reduced.

[0079] Next, polyimide is applied to the P-SiO2 film 507 by spin coating, with a thickness of [thickness] on the wiring. The coating should be applied to a thickness of 9.4 μm. Bisbenzocyclobutene can be applied instead of polyimide. It is also possible to use a non-photosensitive resin. However, if a non-photosensitive resin is used, it is necessary to apply a photosensitive resin and perform patterning by lithography. Therefore, using a non-photosensitive resin may increase the number of steps. The following explanation will use photosensitive polyimide.

[0080] When photosensitive polyimide 508 is applied, exposure is performed using a photomask, followed by development to form an aperture pattern 508a above the Cu wiring 504b at the required location, as shown in Figure 5B(f). However, "required location" refers to the location where the Cu wiring 504b needs to be connected to wiring formed in a higher layer. Note that the structure shown in Figure 2A(c) can be considered to be included in Figure 5B(f).

[0081] To cure the polyimide applied after the formation of the opening pattern 508a, a heat-curing treatment is performed at a temperature of 250°C for one hour under an N2 atmosphere. Note that the temperature is not limited to 250°C. It is generally preferable to set the temperature below the glass transition temperature of the polyimide. If curing is performed at a temperature above the glass transition temperature, the shape of the opening 508a will deform, causing problems such as the opening diameter becoming larger than the design dimensions. For example, if the glass transition temperature of the polyimide is 280°C, the temperature should be set to 250°C as described above. In addition to the heat curing treatment, it is preferable to perform subsequent processes so as not to exceed the glass transition temperature of the polyimide.

[0082] When polyimide is heat-cured, the unevenness caused by the Cu wiring 504b may result in steps 508a on the surface of the photosensitive polyimide 508 other than the openings 508a, as shown in Figure 7. If no treatment is applied to these steps, they will increase in size as more wiring layers are added, causing focus misalignment during pattern exposure. This makes it difficult to form wiring patterns based on the design dimensions, resulting in failure to obtain the desired contact resistance or causing short circuits due to connections between adjacent wiring. To reduce such steps, it is preferable to use polyimide with a low thermal shrinkage rate (preferably 15% or less). Furthermore, a fly cutter can be used to remove surface irregularities of the polyimide with high precision. It is also possible to remove irregularities by chemical mechanical polishing (CMP).

[0083] Next, using photosensitive polyimide 508 as a mask, the P-SiO2 film 507 located at the bottom of the opening 508a is etched by plasma etching. Therefore, a mixed gas of CF4 (flow rate 20 sccm) and H2 (flow rate 5 sccm) is used. Yes, it is possible. By changing the flow rate ratio of the mixed gas, it is possible to change the etching rate of the cured photosensitive polyimide 508 and the P-SiO2 film 507, respectively. Therefore, the etching rate for the P-SiO2 film 507 increases, and the photosensitive polyethylene It is preferable to reduce the etching rate for Mid-508. Generally, the ratio of the etching rate of P-SiO2 to the etching rate of polyimide is approximately 5. The ratio of the etching rate of P-SiO2 to the etching rate of P-SiN is approximately 8. Furthermore, the etching gas is not limited to those mentioned above; CHF3 or CH2F2 can be used instead of CF4.

[0084] After etching the P-SiO2 layer 507, the etching gas is a mixed gas of CF4 and O2. Instead, the P-SiN layer 506 is etched. At this time, for example, CF4 is etched to 20 sc. The flow rate can be set to cm, and the flow rate of O2 can be set to 2 sccm. Etching of polyimide The ratio of the etching rate of P-SiN to the etching rate can be approximately 2.

[0085] Etching of the P-SiN layer 506 creates a first connection hole that electrically connects the first layer of Cu wiring 504b to the second layer of Cu wiring formed in a subsequent process. Immediately after the formation of this first connection hole, carbon compounds containing Si and F adhere to the side walls and bottom of the first connection hole. To remove these carbon compounds, cleaning is performed with an organic solvent. In addition, the Cu surface exposed at the bottom of the first connection hole is oxidized by plasma etching. To remove the oxides caused by this oxidation, cleaning is performed with dilute sulfuric acid.

[0086] Plasma etching of the P-SiO2 layer 507 and the P-SiN layer 506 results in photosensitivity. The surface of polyimide 508 may be damaged by plasma, impairing its inherent heat resistance. In such cases, the plasma-damaged surface can be removed by heat treatment at a temperature of 250°C for 30 minutes, for example. Note that 250°C is an example of a temperature below the glass transition temperature of polyimide.

[0087] As a result of the above processing, the structure shown in Figure 5B(g) is obtained. It can be considered that the structure shown in Figure 2A(d) is included in Figure 5B(g).

[0088] Next, a Ti film with a thickness of 0.1 μm and a Cu film 509 with a thickness of 0.3 μm are deposited on the structure shown in Figure 5B(g) by sputtering. The Ti film functions as a barrier metal to prevent the diffusion of Cu atoms, Cu molecules, and Cu ions from the Cu film 509, as described above. The Cu film 509 also functions as a seed for growing Cu in subsequent electroplating.

[0089] As shown in Figure 5B(h), after applying a photoresist to the Cu film 509, exposure and development are performed to form the wiring pattern 510. After this, electroplating is used to grow a Cu film 511 on the Cu film 509 exposed from the wiring pattern 510. If the final thickness of the Cu film 511 from the top of the first connection hole (i.e., the thickness of the second layer of Cu wiring) is 4.0 μm, then it is preferable to make the Cu film 511 4.4 μm thick from the top of the first connection hole.

[0090] Next, as shown in Figure 5C(i), after growing the Cu film 511, the photoresist forming the wiring pattern 510 is removed, for example, with an organic solvent. As mentioned above, the photoresist can also be removed by ashing with oxygen plasma. Note that the structure shown in Figure 2C(h) can be considered to be included in Figure 5C(i).

[0091] Next, for example, an acidic aqueous solution is used to remove the exposed Cu film 509 and the Ti film beneath it, thereby forming the second layer of Cu wiring 511. The thickness of film 511 is reduced, allowing the design dimensions to be achieved. Furthermore, ion milling can be used instead of an acidic aqueous solution.

[0092] As described above, the first layer Cu wiring 504b and the second layer Cu wiring 511 are connected via a via connection formed in the first connection hole.

[0093] Next, we will describe the process of forming a third layer of Cu wiring and connecting it to the second layer of Cu wiring 511.

[0094] As shown in Figure 5C(j), a P-SiN film 512 with a thickness of 0.1 μm is deposited on the Cu wiring 511 by plasma CVD, and a P-SiO2 film 513 with a thickness of 2 μm is deposited. The reaction system is the same as when the P-SiN film 506 was formed. Furthermore, considering the glass transition temperature of polyimide, it is preferable to use a temperature of, for example, 250°C for film formation. If film formation is performed at a temperature exceeding the glass transition temperature of polyimide, the thermal expansion of the polyimide increases, and due to the difference in thermal expansion coefficients with P-SiN and P-SiO2, wrinkles will form in the photosensitive polyimide 508. In cases where cracks occur in the P-SiN film 512 or the P-SiO2 film 513, It is possible to consider that the structure shown in Figure 2(j) is included in Figure 5C(j).

[0095] Furthermore, in order to remove copper oxide present on the surface of the second layer Cu wiring 511, the second layer Cu wiring 511 is washed with dilute sulfuric acid before the P-SiN film 512 is deposited. Also, before the P-SiN film 512 is deposited, the surface of the Cu wiring 511 is exposed to NH3 plasma in the same chamber. Furthermore, copper oxide may be removed. Note that excessive exposure to NH3 plasma may damage the photosensitive poly Since this breaks the imide bond of Mido 508, the exposure time should preferably be 30 seconds or less, for example, 20 seconds.

[0096] The deposition of the P-SiN film 512 differs from the deposition of the P-SiN film 506 on the first layer of Cu wiring 504b because the substrate is photosensitive polyimide 508 instead of P-SiO2. This is the point. When the photosensitive polyimide 508 is exposed to an acidic aqueous solution during the removal of the Cu film 509 and the underlying Ti film, it is in a state where it contains a lot of moisture. Furthermore, even after the removal of the Cu film 509 and the underlying Ti film, the photosensitive polyimide 508 absorbs moisture from the atmosphere. In general, when a P-SiN film is deposited on a polyimide that is in a state where it contains moisture, the moisture contained in the polyimide vaporizes, pushing up the P-SiN film and causing it to peel off. To prevent this, the substrate 501 is heated in the same chamber before NH3 plasma treatment, and the photosensitive polyimide 508 is exposed to a high concentration of moisture. It is preferable to remove the moisture contained in the photopolymer polyimide 508. For example, the substrate temperature of the plasma CVD apparatus is set to 250°C, and a degassing treatment is performed for 3 minutes before the NH3 plasma is used. Perform the process.

[0097] Next, a photosensitive polyimide is coated onto the P-SiO2 film 513 by spin coating, with a film thickness of C The coating is applied to the u wiring to a thickness of 9.4 μm. As mentioned above, a photosensitive resin such as bisbenzocyclobutene can be used instead of polyimide. A non-photosensitive resin can also be used. In this case, the non-photosensitive resin is applied first, followed by the photosensitive resin, and then the pattern is created by lithography.

[0098] Next, the coated photosensitive polyimide is exposed to light using a photomask and developed to form an opening pattern 514a at the desired location on the second layer of Cu wiring 511. After this formation, the polyimide is cured at a temperature of 250°C for 1 hour in an N2 atmosphere. A heat curing treatment is performed. Then, the P-SiO2 film is formed using the aperture pattern 514a as a mask. Etching is performed on 513 and the P-SiN film 512 to obtain the structure shown in Figure 5C(k) having second connecting holes 514a, 513a, and 512a. Note that the structure shown in Figure 2A(d) is shown in Figure It can be considered that this structure is included in the structure shown in 5C(k).

[0099] Next, barrier metal is formed on the inner surfaces of the second connection holes 514a, 513a, and 512a and on the upper surface of the opening pattern 514a using the same process as described above, and then the third layer of Cu wiring is formed.

[0100] Furthermore, by repeating the same process, a wiring structure having Cu wiring in layers 1 through 5 can be obtained, for example, as shown in Figure 5D(l). It can be considered that the structure shown in Figure 2A(d) is included in the structure shown in Figure 5C(l).

[0101] In the cross-section shown in Figure 5D(l), Cu wiring that is not connected to the Cu wiring of the upper and lower layers is arranged in the even-numbered layers of the second and fourth layers. By placing layers of unconnected Cu wiring in this way, with another layer in between, the wiring capacitance between the Cu wirings can be controlled. It should be noted that the present invention is not limited to the cross-section shown in Figure 5D(l), and such Cu wiring may be arranged in any layer.

[0102] Furthermore, by lowering the thermosetting temperature of the polyimide in the upper layers, the thermal load on the lower polyimide layers is reduced, and the thermal stress on the polyimide, P-SiN film, P-SiO2 film, and Cu wiring is reduced. This reduces the likelihood of peeling or disconnection of wiring due to thermal expansion. Furthermore, when there are many layers, it is preferable to lower the thermosetting temperature as the layers progress upwards, and to lower the temperature of plasma deposition and other processes accordingly.

[0103] In Figure 5D(l), for example, the third layer is referred to as the first layer, the second layer as the second layer, and the Cu wiring of the first layer is referred to as the first Cu wiring. The Cu wiring of the second layer is referred to as the second Cu wiring. In this case, the first inorganic material film (e.g., P-SiN film) covers the surface of the second Cu wiring that is on the side of the first layer and the side surfaces.

[0104] Furthermore, in the wiring structure shown in Figure 5D(l), inorganic material films, namely P-SiN and P-SiO2 films, are arranged in each layer. However, the present invention is not limited to this embodiment. Rather, the layers where the P-SiN film and P-SiO2 film are not placed are the wiring structure. It may be included.

[0105] For example, Figure 5E(m) is the same as Figure 5C(i), and shows a state in which a structure is obtained in which the Cu wiring 504b of the first layer and the Cu wiring 511 of the second layer are connected via a via connection formed in the first connection.

[0106] Once the structure shown in Figure 5C(m) is obtained, to obtain the structure shown in Figure 5C(j), instead of forming a P-SiN film and a P-SiO2 film, a photosensitive polyimide is used, for example, with a thickness of Cu. Alternatively, the polyimide can be coated to a thickness of 9.4 μm along a line, exposed to light using a photomask, and developed to form the required opening pattern 514a on the second layer of Cu wiring 511. The polyimide can then be cured to obtain the structure shown in Figure 5E(n). Comparing Figure 5E(n) and Figure 5C(k), in Figure 5C(k), the portion of the second layer of Cu wiring 511 excluding the opening 514a is covered by the first inorganic material film 512 and the second inorganic material film 513, whereas in Figure 5E(n), the first inorganic material film 512 and the second inorganic material film 513 are absent, and the second layer of Cu wiring 511 is not covered by the first and second inorganic material films.

[0107] For the third, fourth, and fifth layer Cu wiring, the wiring structure shown in Figure 5F can be obtained by covering the portions of the organic resin material film, excluding the openings, with the first and second inorganic material films. Compare Figure 5F(p) and Figure 5D(l). In Figure 5D(l), the portion of the second layer of Cu wiring, excluding the opening, is covered by the first and second inorganic material films, whereas in Figure 5F(p), the second layer of Cu wiring is not covered by the first and second inorganic material films. Therefore, it can be said that the second layer of Cu wiring is positioned between the first layer of organic resin material film and the second layer of organic material film.

[0108] Furthermore, the via connection between the first and third layer Cu wirings is divided into an upper portion belonging to the second layer and a lower portion belonging to the first layer, by the Cu wiring in the second layer that is located between the first and third layer Cu wirings. In other words, the upper portion is located above the Cu wiring located between the first and third layer Cu wirings, and the lower portion is located below the Cu wiring located between the first and third layer Cu wirings. Additionally, a barrier conductive material is placed between the upper portion and the Cu wiring located between the first and third layer Cu wirings, in other words, at the bottom of the upper portion.

[0109] Cu wiring not covered by the first and second inorganic material films is not limited to being placed in the second layer, but can be placed in any layer. Furthermore, Cu wiring not covered by the first and second inorganic material films can also be placed in consecutive layers.

[0110] By arranging Cu wiring that is not covered by the first and second inorganic material films in this manner, the processes for the first and second inorganic material films can be omitted, thereby reducing the number of processes. Furthermore, the thickness of the organic resin material film can be controlled, which allows for control of the warping of the substrate 501 and impedance matching between wirings.

[0111] In particular, as shown in Figures 5D(l) and 5F(p), between the second and third Cu wirings from the left among the four Cu wirings shown in the second layer, and between the second and third Cu wirings from the left among the four Cu wirings shown in the fourth layer, only an insulating film exists, and no other Cu wirings are placed between them. In this way, by not placing Cu wiring between a Cu wiring placed in a certain layer and a Cu wiring placed in the layer above it, impedance matching can be performed between a Cu wiring placed in a certain layer and a Cu wiring placed in the layer above it. In particular, the number of layers between a certain layer and a layer above it may be one layer or two or more layers. Furthermore, only an organic insulating film may be placed between a Cu wiring placed in a certain layer and a Cu wiring placed in the layer above it, or any number of inorganic insulating films may be placed. By configuring it in this way, impedance matching can be performed between a Cu wiring placed in a certain layer and a Cu wiring placed in the layer above it, and the transmission characteristics can be improved.

[0112] (Embodiment 3) Figure 8(a) shows the arrangement of an LSI chip using a wiring structure according to Embodiment 3 of the present invention. This is an example of an arrangement known as three-dimensional mounting.

[0113] In Figure 8(a), the CPU 803 is located on the motherboard 801 via an interposer 802. The ASIC 805 is located on the CPU 803 via an interposer 804. A DRAM is located on the ASIC 805 via an interposer 806, another DRAM via another interposer 807, and yet another DRAM 809 via another interposer 808. The wiring structures according to this embodiment are located on both the upper and lower surfaces of the interposers 802, 804, 806, 807, and 808, and bump connections are made with each LSI.

[0114] In this 3D mounting configuration, the signal lines, power lines, and ground lines of each LSI are connected via Cu wiring in the interposer. Compared to 2.5D mounting, 3D mounting requires shorter wiring lengths, making it suitable for higher-speed information processing.

[0115] Figure 9(b) shows a cross-section of a Si interposer as an example of an interposer. The Si interposer has a structure in which Cu is embedded by electroplating in multiple vias that penetrate a Si substrate with a thickness of 300 μm. For example, the diameter of each via can be 10 μm, and the via arrangement pitch can be 40 μm. In this embodiment, it is possible to form wiring with a width of 1 μm or less and stacked vias, so wiring layers can be stacked at high density even on an interposer with such small-pitch vias.

[0116] Furthermore, in order to insulate the Cu of the Si interposer from the Si substrate, as shown in Figure 8(b), a P-SiO2 film 814 and a P-SiN film 815 are deposited in that order on the inside of the via. Cu813 is embedded inside. Furthermore, the thickness of each film is, for example, 0.5 μm for the P-SiO2 film 814 and 0.1 μm for the P-SiN film 815. Furthermore, P-SiN film 814 and P-SiO2 film 81 are also applied to the upper and lower surfaces of the Si interposer. 5 has been deposited.

[0117] As shown in Figure 9A(a), a Ti film 821 with a thickness of 0.1 μm and a Cu film 822a with a thickness of 0.3 μm are deposited on the upper and lower surfaces of the Si interposer 811 by sputtering. The Ti film 821 acts as a barrier metal to prevent Cu from diffusing into the Si substrate. The Cu film 822a also functions as a seed for growing the Cu layer by subsequent electroplating.

[0118] Next, as shown in Figure 9A(b), a photoresist is applied to the Cu film 822a, and a wiring pattern 823 is formed by photosensitization and development. After this, a Cu layer 822 with a thickness of 2.2 μm is grown on the exposed Cu film 822a by electroplating. In this case, the design dimension value for the thickness of the first layer of Cu wiring formed by the Cu layer 822 is 2.0 μm.

[0119] After growing the Cu layer 822, the photoresist forming the wiring pattern 823 is removed, for example, with an organic solvent to obtain the structure shown in Figure 9A(c). As mentioned above, ashing with oxygen plasma can be used instead of an organic solvent.

[0120] Next, as shown in Figure 9A(d), the exposed Cu film 822a and Ti film 821 portions are removed using an acidic aqueous solution, forming the first layer of Cu wiring with the Cu layer 822. By removing the exposed Cu film 822a, the thickness of the Cu layer 822 can be reduced to the design dimension of 2.0 μm. The exposed Cu film 822a and Ti film 821 portions can also be removed by ion milling.

[0121] Next, as shown in Figure 9A(e), a P-SiN film 824 with a thickness of 0.1 μm is deposited on the first layer of Cu wiring by plasma CVD, and then a P-SiO2 film 825 with a thickness of 1 μm is deposited. Formed. It can be considered that the structure shown in Figure 2A(a) is included in Figure 9A(e). A P-SiN film 824 and a P-SiO2 film are formed on the side surface of the first layer of Cu wiring. This allows for a reduction in the spacing between adjacent Cu wirings in the first layer when viewed from a plan perspective.

[0122] Furthermore, if the Cu wiring density and wiring pattern of the first layer differ on the upper and lower surfaces of the interposer 811, the residual stress on the wiring will differ on both sides, and the interposer 811 may warp to one side. In this case, the thickness of the P-SiO2 film on one side may be changed, or the film stress may be reduced. By changing this, warping can be controlled. For example, the film stress of the P-SiO2 film 825 can be adjusted to -200 MPa.

[0123] Next, copper oxide present on the surface of the first layer of Cu wiring is removed in the same manner as in Embodiment 2.

[0124] Next, on the P-SiO2 film 825 on the upper surface of the interposer 811, a spin coat is applied. A more photosensitive polyimide is applied to the Cu wiring to a thickness of 4.7 μm. Other resins besides polyimide can be used, as in Embodiment 2.

[0125] The coated polyimide is exposed to light using a photomask and then developed to form a pattern 826 on the upper surface of the interposer 811, having an opening 826a at the required position above the first layer of Cu wiring.

[0126] Similarly, a pattern 826 having an opening 826a is formed on the lower surface of the interposer 811.

[0127] Subsequently, the polyimide is cured in the same manner as in the embodiment described above to obtain the structure shown in Figure 9B(f). It can be considered that the structure shown in Figure 2A(c) is included in Figure 9B(f).

[0128] Next, the pattern 826 on the upper surface of the interposer 811 is used as a mask, and the P-SiO2 film 825 and the P-SiN film 824 are etched by plasma etching, and the first Connection holes 826a, 825a, and 824a are formed. Similarly, the first connection holes 826a, 825a, and 824a are also formed on the lower surface of the interposer 811. As a result, the structure shown in Figure 9B(g) is obtained. It can be considered that the structure shown in Figure 2A(d) is included in Figure 9B(g).

[0129] Subsequently, the process of removing carbon compounds containing Si and F adhering to the side walls and bottom of the first connection hole, removing the oxidized Cu surface, and performing heat treatment to restore the polyimide damaged by plasma etching is the same as in Embodiment 2.

[0130] Next, a Ti film with a thickness of 0.1 μm and a Cu film 827 with a thickness of 0.3 μm are deposited on the upper surface of the interposer 811 by sputtering. The same Ti film and Cu film 827 are deposited on the lower surface of the interposer 811. Then, a photoresist is applied to the Cu film 827 on the upper surface of the interposer 811, and a wiring pattern 828 is formed by exposure and development. Similarly, a wiring pattern 828 is formed on the lower surface of the interposer 811. Then, a Cu layer 829 with a thickness of 2.2 μm is grown on the exposed Cu film 827 using electroplating to obtain the structure shown in Figure 9C(h). The design dimension of the Cu wiring is, for example, 2.0 μm.

[0131] Next, using the same method as in the embodiment described above, the photoresist forming the wiring pattern 828 is removed, and the exposed Cu film 827 and Ti film are removed to obtain the structure shown in Figure 9C(i). By removing the exposed Cu film 827, the thickness of the Cu layer 829 can be set to the design dimension. As a result, as shown in Figure 9C(i), the Cu layer 829 forms a second wiring layer, which connects to the first wiring layer. It can be considered that the structure shown in Figure 2C(h) is included in Figure 9C(i).

[0132] Next, as shown in Figure 9D(j), a 0.1 μm thick P-SiN film 830 is deposited on the upper and lower surfaces of the interposer 811 by plasma CVD, and a 1 μm thick P-SiO2 film 831 is deposited on top of it. The reaction system is the same as when the P-SiN film 824 and P-SiO2 film 825 were deposited, and the deposition temperature exceeds the glass transition temperature of the polyimide. To prevent this from happening. Furthermore, it can be considered that the structure shown in Figure 2A(a) is included in Figure 9D(j).

[0133] The process of cleaning the Cu wiring to remove copper oxide from the surface of the second layer of Cu wiring before film formation, and removing moisture from the polyimide 826, is the same as in Embodiment 2.

[0134] Next, a photosensitive polyimide or the like is applied to the upper surface of the interposer 811 to a thickness of 4.7 μm, and a pattern 831 with openings 832 at the required locations of the second layer of Cu wiring is formed by exposure and development. Similarly, a pattern 831 is formed on the lower surface of the interposer 811. After that, the polyimide is cured as in Embodiment 2, and the P-SiO2 film 831 and the P-SiN film 830 are etched using the polyimide as a mask. This results in the structure shown in Figure 9D(k) having a second connection hole 832. It can be considered that the structure shown in Figure 2A(d) is included in Figure 9D(k).

[0135] After exposing the second layer of Cu wiring 829 at the bottom of the second connection hole 832, the same process is repeated to form the third layer of Cu wiring, and similarly, the fourth layer of Cu wiring and the fifth layer of Cu wiring can be formed as shown in Figure 9E(l). It can be considered that the structure shown in Figure 2A(d) is included in the fifth wiring layer in Figure 9E(l).

[0136] By lowering the thermosetting temperature of the polyimide layers towards the upper layers, the thermal load on the lower polyimide layers is reduced, thereby reducing thermal stress and thermal expansion of the polyimide, P-SiN film, P-SiO2 film, and Cu wiring. Similar to Embodiment 2, this method makes it less likely for peeling or disconnection of wiring to occur, and when there are many layers, it is preferable to lower the thermosetting temperature as the layers become higher, and to lower the temperature of plasma deposition and other processes accordingly.

[0137] Furthermore, in this embodiment, the same number of Cu wiring layers are formed on both sides of the interposer 811, but the number of layers can be different on the top and bottom surfaces of the interposer 811 if necessary.

[0138] In this embodiment, as described in Embodiment 2, there may be layers in which the Cu wiring is not covered by the first inorganic material film and the second inorganic material film. Also, instead of placing Cu wiring that is not connected to the Cu wiring in the upper and lower layers in adjacent layers, another layer may be interposed between them.

[0139] (Examples) Figure 11 is a graph showing the failure rate when a thermal cycling test was performed on a Si interposer whose wiring structure was fabricated using the process described in Example 3. In this thermal cycling test, a stacked via chain consisting of 4 layers (number of chains: 1000) connected via vias was used on both the top and bottom surfaces of the Si interposer. The temperature cycle from -25°C to 125°C was repeated 3000 times, and the wiring structure was judged to be defective when the chain resistance increased by 20% or more.

[0140] The measurement samples were prepared with two types of connection hole diameters: 0.5 μm and 20 μm. The 0.5 μm connection hole diameter represents the resolution limit during exposure and development of polyimide. The 20 μm diameter represents the maximum diameter for which miniaturization offers advantages. The ratio of P-SiO2 film thickness in the connection hole was varied. The SiO2 film thickness ratio was calculated by including the P-SiN film thickness (fixed at 0.1 μm).

[0141] Here, the P-SiO2 film thickness ratio is calculated as [P-SiO2 film thickness / (P-SiO2 film thickness + polyimide film thickness)]. That is, referring to Figure 10, the wiring of the first layer 1 Let X be the distance from the top end of 003 to the bottom end of the barrier metal under the second layer wiring 1008, i.e., the height of the connection hole, and let Y be the thickness of the P-SiO2 film between the top end of the first layer wiring 1003 and the bottom end of the barrier metal under the second layer wiring 1008. Then, Y / X is This is the calculated value. Specifically, Y / X is the ratio of P-SiO2 to the height of the connection hole (the length through which the connection hole penetrates the insulating layer).

[0142] As shown in Figure 11, the defect rate decreased as Y / X increased. When the connection hole diameter was 20 μm, the defect rate was 0% at a Y / X of 20%. When the connection hole diameter was 0.5 μm, the defect rate was 0% at a Y / X of 30%. From these results, it can be said that the P-SiO2 film thickness ratio in the connection hole is preferably 20% or more, and more preferably 30% or more. Strictly speaking, since Y / X is calculated including the film thickness of P-SiN, it can also be said that it is preferable for the film thickness of the Si-containing inorganic material film to be 20% or more. However, as the P-SiO2 film thickness ratio increases, the capacitance between the upper and lower wiring increases, and impedance matching becomes difficult, so it is preferable that the upper limit be 80% or less.

[0143] Figure 12 shows the failure rate when the above thermal cycling test was performed on a Si interposer whose wiring structure was fabricated using the process described in Example 3. The measurement samples consisted of two types of connection hole diameters, 0.5 μm and 20 μm, with the connection hole height varied within a range of approximately 5 to 20 μm. For a connection hole diameter of 0.5 μm, the P-SiO2 ratio with respect to the connection hole height was... The film thickness ratio (including the P-SiN film thickness of 0.1 μm) Y / X was set to 20% and 30%. Also, when the connection hole diameter was 20 μm, the P-SiO2 film thickness ratio (P-SiN film thickness) was set to 20% and 30%. The concentrations (including 0.1 μm) were set at 10% and 20%.

[0144] When the diameter of the connection hole was 0.5 μm and the film thickness ratio was 20%, the defect rate was approximately 18%, independent of the height of the connection hole. When the film thickness ratio was increased to 30%, the defect rate became 0% at all connection hole heights. Furthermore, when the diameter of the connection hole was 20 μm and the film thickness ratio was 10%, the defect rate was approximately 15%, independent of the height of the connection hole. When the film thickness ratio was increased to 20%, the defect rate became 0% at all connection hole heights.

[0145] From these results, it was found that in the range of connection hole diameters from 0.5 μm to 20 μm, the height of the connection hole does not affect the defect rate. Even if the height of the connection hole changes, if the P-SiO film thickness ratio remains the same, the high elastic modulus of P-SiO suppresses the thermal expansion of the polyimide. Furthermore, the strong adhesion between P-SiO and the barrier metal is thought to reduce the tensile stress on Cu within the connection hole, suppressing void formation at the bottom of the via connection hole and thus lowering the defect rate.

Claims

1. First wiring and, A first inorganic layer located on the first wiring, covering and in contact with at least a portion of the side surface and the upper surface of the first wiring, A first organic resin located at least on the first inorganic layer, The second wiring located on the first organic resin, A second inorganic layer located on the second wiring, covering and in contact with at least a portion of the side surface and the upper surface of the second wiring, A second organic resin located at least on the second inorganic layer, The third wiring located on the second organic resin, A third organic resin located on the third wiring, A wiring structure that includes this.

2. The first inorganic layer comprises a first inorganic film located on the first wiring and a second inorganic film located on the first inorganic film, The wiring structure according to claim 1, wherein the second inorganic layer includes a third inorganic film located on the second wiring and a fourth inorganic film located on the third inorganic film.

3. The wiring structure according to claim 1, further comprising a via connection portion located in a via connection hole penetrating the second organic resin in a region where the second wiring and the third wiring overlap each other.

4. A fourth wiring located below the first wiring, The wiring structure according to claim 1, further comprising a fourth organic resin located between the fourth wiring and the first wiring, covering and in contact with at least a portion of the side surface and the upper surface of the fourth wiring.

5. A fourth wiring located on the third organic resin, The wiring structure according to claim 1, further comprising a fourth organic resin located on the fourth wiring and covering and in contact with at least a portion of the side surface and the upper surface of the fourth wiring.

6. The first wiring and A first inorganic layer located on the first wiring, covering and in contact with at least a portion of the side surface and the upper surface of the first wiring, A first organic resin located at least on the first inorganic layer, The second wiring located on the first organic resin, A second organic resin located on the second wiring, The third wiring located on the second organic resin, A third inorganic layer located on the third wiring, covering and in contact with at least a portion of the side surface and the upper surface of the third wiring, A third organic resin located at least on the third inorganic layer, A wiring structure that includes this.

7. The first inorganic layer comprises a first inorganic film located on the first wiring and a second inorganic film located on the first inorganic film, The wiring structure according to claim 6, wherein the third inorganic layer includes a fifth inorganic film located on the third wiring and a sixth inorganic film located on the fifth inorganic film.

8. The wiring structure according to claim 6, further comprising a via connection portion located in a via connection hole penetrating the second organic resin in a region where the second wiring and the third wiring overlap each other.

9. A fourth wiring located below the first wiring, The wiring structure according to claim 6, further comprising a fourth organic resin located between the fourth wiring and the first wiring, covering and in contact with at least a portion of the side surface and the upper surface of the fourth wiring.

10. A fourth wiring located on the third organic resin, The wiring structure according to claim 6, further comprising a fourth organic resin located on the fourth wiring and covering and in contact with at least a portion of the side surface and the upper surface of the fourth wiring.

11. The first wiring and A first organic resin located on the first wiring, The second wiring located on the first organic resin, A second inorganic layer located on the second wiring, covering and in contact with at least a portion of the side surface and the upper surface of the second wiring, A second organic resin located at least on the second inorganic layer, The third wiring located on the second organic resin, A third inorganic layer located on the third wiring, covering and in contact with at least a portion of the side surface and the upper surface of the third wiring, A third organic resin located at least on the third inorganic layer, A wiring structure that includes this.

12. The second inorganic layer comprises a third inorganic film located on the second wiring and a fourth inorganic film located on the third inorganic film, The wiring structure according to claim 11, wherein the third inorganic layer includes a fifth inorganic film located on the third wiring and a sixth inorganic film located on the fifth inorganic film.

13. The wiring structure according to claim 11, further comprising a via connection portion located in a via connection hole penetrating the second organic resin in a region where the second wiring and the third wiring overlap each other.

14. A fourth wiring located below the first wiring, The wiring structure according to claim 11, further comprising a fourth organic resin located between the fourth wiring and the first wiring, covering and in contact with at least a portion of the side surface and the upper surface of the fourth wiring.

15. A fourth wiring located on the third organic resin, The wiring structure according to claim 11, further comprising a fourth organic resin located on the fourth wiring and covering and in contact with at least a portion of the side surface and the upper surface of the fourth wiring.

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