Doped silicon nitride for 3D NAND

Abstract

An exemplary method for forming a semiconductor structure may include forming a silicon oxide layer from a silicon-containing precursor and an oxygen-containing precursor. The method may include forming a silicon nitride layer from a silicon-containing precursor, a nitrogen-containing precursor, and an oxygen-containing precursor. The silicon nitride layer may be characterized by an oxygen concentration of about 5 atomic % or greater. The method may also include repeating the formation of a silicon oxide layer and the formation of a silicon nitride layer to produce a stack of alternating layers of silicon oxide and silicon nitride.

Description

[Technical Field]

[0001] Cross-reference of related applications

[0001] This application claims the interests and priority of U.S. Patent Application No. 17 / 142,641, “DOPED SILICON NITRIDE FOR 3D NAND,” filed on 6 January 2021, which is incorporated herein by reference in its entirety.

[0002]

[0002] This technology relates to semiconductor processing and materials. More specifically, this technology relates to forming alternating layer film stacks. [Background technology]

[0003]

[0003] Integrated circuits are made possible by a process that generates intricately patterned material layers on the substrate surface. Generating patterned material on a substrate requires a controlled method for forming and removing exposed material. Stacked memory such as vertical or 3D NAND involves the formation of a series of alternating layers of dielectric material, through which several memory holes or openings may be etched. The material properties of the material layers, as well as the process conditions and materials for etching, can affect the uniformity of the formed structure. Material defects can lead to inconsistent patterning, further affecting the uniformity of the formed structure.

[0004]

[0004] Therefore, improved systems and methods are needed that can be used to manufacture high-quality devices and structures. This technology addresses these and other needs. [Overview of the Initiative]

[0005]

[0005] An exemplary method for forming a semiconductor structure may include forming a silicon oxide layer from a silicon-containing precursor and an oxygen-containing precursor. This method may include forming a silicon nitride layer from a silicon-containing precursor, a nitrogen-containing precursor, and an oxygen-containing precursor. The silicon nitride layer may be characterized by an oxygen concentration of about 30 atomic percent or less. The silicon nitride layer has an oxygen concentration of about 3.0 g / cm³. 3 The following densities may be characterized. The method may also involve repeatedly forming silicon oxide layers and silicon nitride layers to generate a stack of alternating silicon oxide and silicon nitride layers.

[0006]

[0006] In some embodiments, the oxygen-containing precursor used to form the silicon oxide layer and the oxygen-containing precursor used to form the silicon nitride layer may be the same precursor. Forming the silicon nitride layer may involve performing plasma-enhanced deposition at a substrate temperature of about 500°C or higher. Forming the silicon nitride layer may involve performing plasma-enhanced deposition at a plasma pulse frequency of about 10 kHz or lower and a duty cycle of about 50% or lower. The oxygen concentration of the silicon nitride layer may be between about 10 atomic percent and about 30 atomic percent. The nitrogen atom percentage may be about 30 atomic percent or higher. Forming the silicon nitride layer may involve introducing the silicon-containing precursor and the nitrogen-containing precursor into the substrate processing area. The method may involve forming a certain amount of silicon nitride. The method may involve adding the oxygen-containing precursor while continuing to form the silicon nitride. The oxygen-containing precursor may be introduced at a constant flow rate. The formed silicon nitride layer may include a bilayer of substantially oxygen-free silicon nitride and silicon nitride characterized by an oxygen concentration of about 5 atomic percent or higher. The oxygen-containing precursor can be flowed at a varying flow rate. The silicon nitride layer formed may contain an oxygen concentration gradient through the silicon nitride layer. The flow rate of the oxygen-containing precursor may be increased while the oxygen-containing precursor is being added. This method may involve forming one or more features through a stack of alternating silicon oxide and silicon nitride layers. Lateral removal of the silicon nitride layer at the interface between the silicon nitride layer and the overlying silicon oxide layer may extend to a distance of approximately 50% or less of the distance corresponding to the thickness of the silicon nitride layer.

[0007]

[0007] Some embodiments of this technology may encompass methods for forming semiconductor structures. The method may include forming a silicon oxide layer from a silicon-containing precursor and an oxygen-containing precursor. The method may include forming a silicon nitride layer from a silicon-containing precursor, a nitrogen-containing precursor and a phosphorus-containing precursor. The silicon nitride layer has a phosphorus concentration of about 15 atomic% or less and about 3.0 g / cm³ 3 The following densities may be characterized. This method may involve repeatedly forming silicon oxide layers and silicon nitride layers to generate a stack of alternating silicon oxide and silicon nitride layers.

[0008]

[0008] In some embodiments, forming a silicon nitride layer may include performing plasma-enhanced deposition at a substrate temperature of about 500°C or higher. Forming a silicon nitride layer may include performing plasma-enhanced deposition at a plasma pulse frequency of about 10 kHz or lower and a duty cycle of about 50% or lower. The phosphorus concentration of the silicon nitride layer may be about 10 atomic percent or less. The nitrogen atom percentage may be about 30 atomic percent or more. Forming a silicon nitride layer may include introducing a silicon-containing precursor and a nitrogen-containing precursor into the substrate processing area. This method may include forming a certain amount of silicon nitride. This method may include adding a phosphorus-containing precursor while continuing to form silicon nitride. The phosphorus-containing precursor may be introduced at a constant flow rate. The formed silicon nitride layer may include a bilayer of substantially phosphorus-free silicon nitride and silicon nitride characterized by a phosphorus concentration of about 1 atomic percent or more. Phosphorus may be incorporated into about 30% or less of the thickness of the silicon nitride layer.

[0009]

[0009] Some embodiments of the present technology may encompass methods for forming semiconductor structures. The method may include forming a silicon oxide layer from a silicon-containing precursor and an oxygen-containing precursor. The method may include forming a silicon nitride layer from a silicon-containing precursor, a nitrogen-containing precursor, and a dopant precursor. The silicon nitride layer has a dopant concentration of about 30 atomic percent or less and about 3.0 g / cm³ 3The following densities may be characterized. The method may involve repeatedly forming silicon oxide layers and silicon nitride layers to generate a stack of alternating silicon oxide and silicon nitride layers. In some embodiments, forming the silicon nitride layer may involve performing plasma-enhanced deposition at a substrate temperature of about 500°C or higher. Forming the silicon nitride layer may involve performing plasma-enhanced deposition at a plasma pulse frequency of about 10 kHz or lower and a duty cycle of about 50% or lower.

[0010]

[0010] Such technologies can offer many advantages over conventional systems and techniques. For example, the process and structure can prevent the formation of defects during the etching process. In addition, the process of the embodiments of this technology can improve the formation of memory holes through the stack. These embodiments and other embodiments, along with many of their advantages and features, will be described in more detail in conjunction with the following description and accompanying drawings.

[0011]

[0011] The nature and advantages of the disclosed technology can be further understood by referring to the remainder of this specification and the drawings. [Brief explanation of the drawing]

[0012] [Figure 1]

[0012] A schematic cross-sectional view of an exemplary processing chamber according to several embodiments of the present technology is shown. [Figure 2]

[0013] Figures A through C show schematic cross-sectional views of substrate materials according to several embodiments of this technology. [Figure 3]

[0014] The following steps are selected in the formation method according to several embodiments of this technology. [Figure 4]

[0015] Figure 4 shows notching of the structure according to several embodiments of this technology. [Modes for carrying out the invention]

[0013]

[0016] Some drawings are included as schematic diagrams. It should be understood that drawings are for illustrative purposes only and should not be considered to scale unless explicitly stated otherwise. In addition, the diagrams are provided as schematic diagrams to aid understanding and may not include all aspects or information compared to actual depictions, and may include materials that are exaggerated for illustrative purposes.

[0014]

[0017] In the attached drawings, similar components and / or features may have the same reference numeral. Furthermore, various components of the same kind may be distinguished according to their reference numerals by letters that distinguish similar components from each other. Where only the first reference numeral is used in this specification, its description is applicable to any of the similar components having the same first reference numeral, regardless of the letters used.

[0015]

[0018] As the number of cells forming the 3D NAND structure increases, the aspect ratio of memory holes and other structures also increases (sometimes dramatically). During 3D NAND processing, a stack of placeholder layers and dielectric material may form interelectrode dielectric layers or polyinterpolydielectric ("IPD") layers. Various processes can be performed on these placeholder layers to place structures on them before the material is completely removed and replaced with metal. IPD layers are often formed to overlap conductive layers, such as polycrystalline silicon. When memory holes are formed, the openings may extend through all alternating layers of material before accessing the polycrystalline silicon or other material substrate. Subsequent processing may form stepped structures for contacts, and the placeholder material may be excavated laterally.

[0016]

[0019] Reactive ion etching ("RIE") processes can be performed to generate high aspect ratio memory holes. RIE processes often involve a combination of chemical and physical removal of alternating layers, which can form a carbon polymer layer on the sidewalls during etching, protecting the layers from further etching. As one non-limiting example, if the alternating layers may contain silicon oxide and silicon nitride, the silicon oxide may be removed more to a greater extent by physical collisions of the layers during RIE, and the silicon nitride may be removed more to a greater extent by a chemical reaction between the RIE precursor and the nitride material.

[0017]

[0020] Conventional techniques can present challenges in achieving uniformity and control during memory hole formation due to material differences between the two layer types, as well as the RIE process and materials. This technique overcomes these problems by tuning material properties before the RIE process, thereby addressing or limiting one or more of the challenges that might otherwise arise. While the remaining disclosure routinely identifies specific materials and semiconductor structures that utilize the disclosed technique, it will be readily apparent that the systems, methods, and materials are equally applicable to several other structures that may benefit from aspects of this technique. Therefore, this technique should not be considered limited to use only in 3D NAND processes or materials. Furthermore, while exemplary chambers are described to provide the basis for this technique, it should be understood that the technique is applicable to substantially any semiconductor processing chamber that can enable the described process.

[0018]

[0021] FIG. 1 shows a cross-sectional view of an exemplary processing chamber 100 according to some embodiments of the present technology. Although the chamber 100 may be utilized to form a film layer in accordance with some embodiments of the present technology, it will be understood that the method may be similarly performed in any chamber where film formation can occur. The processing chamber 100 may include a chamber body 102, a substrate support 104 disposed inside the chamber body 102, and a lid assembly 106 connected to the chamber body 102 and surrounding the substrate support 104 in a processing space 120. The substrate 103 may be provided to the processing space 120 through an opening 126, and this opening may be conventionally sealed for processing using a slit valve or a door. The substrate 103 may be placed on the surface 105 of the substrate support during processing. The substrate support 104 may be rotatable along an axis 147 where the shaft 144 of the substrate support 104 can be located, as indicated by arrow 145. Alternatively, the substrate support 104 may be lifted to rotate as needed during the deposition process.

[0019]

[0022] A plasma profile modulator 111 may be disposed within the processing chamber 100 to control the plasma distribution across a substrate 103 disposed on the substrate support 104. The plasma profile modulator 111 may include a first electrode 108 disposed adjacent to the chamber body 102 and separable from other components of the lid assembly 106. The first electrode 108 may be a part of the lid assembly 106 or a separate sidewall electrode. The first electrode 108 may be an annular or ring-shaped member and may be a ring electrode. The first electrode 108 may be a continuous loop around the outer periphery of the processing chamber 100 surrounding the processing space 120 and may be discontinuous at selected positions if desired. Also, the first electrode 108 may be a perforated electrode such as a perforated ring or a mesh electrode, or may be a flat electrode such as a secondary gas distributor, for example.

[0020]

[0023] One or more isolators 110a, 110b, which can be a dielectric material such as a ceramic or a metal oxide, such as aluminum oxide and / or aluminum nitride, can contact the first electrode 108 and electrically and thermally isolate the first electrode 108 from the gas distributor 112 and the chamber body 102. The gas distributor 112 can define apertures 118 for distributing process precursors into the processing space 120. The gas distributor 112 can be connected to a first power source 142, such as an RF generator, an RF power supply, a DC power supply, a pulsed DC power supply, a pulsed RF power supply, or any other power supply that can be connected to the processing chamber. In some embodiments, the first power source 142 can be an RF power supply.

[0021]

[0024] The gas distributor 112 can be a conductive gas distributor or a non - conductive gas distributor. Also, the gas distributor 112 can be formed from conductive and non - conductive components. For example, while the body of the gas distributor 112 is conductive, the faceplate of the gas distributor 112 can be non - conductive. The gas distributor 112 can be powered by a first power source 142 as shown in FIG. 1 or, in some embodiments, the gas distributor 112 can be connected to ground.

[0022]

[0025] The first electrode 108 may be connected to a first tuning circuit 128 that can control the grounding path of the processing chamber 100. The first tuning circuit 128 may include a first electronic sensor 130 and a first electronic controller 134. The first electronic controller 134 may be a variable capacitor or other circuit element, or may include one. The first tuning circuit 128 may be one or more inductors 132, or may include one. The first tuning circuit 128 may be any circuit that enables a variable or controllable impedance under the plasma conditions present in the processing space 120 during processing. In some embodiments as illustrated, the first tuning circuit 128 may include a first circuit leg and a second circuit leg connected in parallel between ground and the first electronic sensor 130. The first circuit leg may include a first inductor 132A. The second circuit leg may include a second inductor 132B connected in series with the first electronic controller 134. A second inductor 132B may be positioned between the first electronic controller 134 and a node that couples both the first and second circuit legs to the first electronic sensor 130. The first electronic sensor 130 is a voltage or current sensor connected to the first electronic controller 134 and may allow for some degree of closed-loop control of the plasma conditions inside the processing space 120.

[0023]

[0026] The second electrode 122 may be connected to the substrate support 104. The second electrode 122 may be embedded within the substrate support 104 or connected to the surface of the substrate support 104. The second electrode 122 may be a plate, a perforated plate, a mesh, a wire screen, or other distributed arrangement of conductive elements. The second electrode 122 may also be a tuning electrode and may be connected to a second tuning circuit 136 by a conduit 146, such as a cable with a selected resistance, such as 50 ohms, located within the shaft 144 of the substrate support 104. The second tuning circuit 136 may have a second electronic sensor 138 and a second electronic controller 140, the second electronic controller 140 may be a second variable capacitor. The second electronic sensor 138 is a voltage or current sensor and may be connected to the second electronic controller 140 to provide further control over the plasma conditions in the processing space 120.

[0024]

[0027] A third electrode 124, which may be a bias electrode and / or an electrostatic chuck electrode, may be connected to a substrate support 104. The third electrode is connected to a second power source 150 through a filter 148, which may be an impedance matching circuit. The second power source 150 may be DC power, pulsed DC power, RF bias power, pulsed RF source or bias power, or a combination of these or other power sources. In some embodiments, the second power source 150 may be RF bias power.

[0025]

[0028] The lid assembly 106 and substrate support 104 in Figure 1 can be used with any processing chamber for plasma or heat treatment. In operation, the processing chamber 100 may allow real-time control of plasma conditions within the processing space 120. The substrate 103 is placed on the substrate support 104, and process gas can be flowed through the lid assembly 106 using the inlet 114 according to any desired flow plan. The gas can exit the processing chamber 100 through the outlet 152. Power may be connected to a gas distributor 112 to establish plasma within the processing space 120. In some embodiments, the substrate may be electrically biased using a third electrode 124.

[0026]

[0029] When the plasma in the processing space 120 is excited, a potential difference can be established between the plasma and the first electrode 108. A potential difference can also be established between the plasma and the second electrode 122. Next, electronic controllers 134 and 140 can be used to adjust the flow characteristics of the ground path, represented by two tuning circuits 128 and 136. Setpoints can be provided for the first tuning circuit 128 and the second tuning circuit 136 to provide independent control of the deposition rate and the uniformity of the plasma density from the center to the edge. In embodiments where both electronic controllers are variable capacitors, electronic sensors can independently adjust the variable capacitors to maximize the deposition rate and minimize thickness non-uniformity.

[0027]

[0030] Each of the tuning circuits 128 and 136 may have a variable impedance that can be adjusted using their respective electronic controllers 134 and 140. If the electronic controllers 134 and 140 are variable capacitors, the capacitance range of each variable capacitor and the inductances of the first inductor 132A and the second inductor 132B may be selected to provide an impedance range. This range depends on the frequency and voltage characteristics of the plasma, and there may be a minimum value in the capacitance range of each variable capacitor. Therefore, when the capacitance of the first electronic controller 134 is at its minimum or maximum, the impedance of the first tuning circuit 128 becomes high, which may result in a plasma shape with minimal air or lateral coverage on the substrate support. As the capacitance of the first electronic controller 134 approaches the value that minimizes the impedance of the first tuning circuit 128, the air coverage of the plasma may grow to its maximum, effectively covering the entire working area of ​​the substrate support 104. If the capacitance of the first electronic controller 134 deviates from the minimum impedance setting, the plasma shape may contract away from the chamber wall, reducing the air coverage of the substrate support. The second electronic controller 140 has a similar effect, and since the capacitance of the second electronic controller 140 can be changed, the air coverage of the plasma on the substrate support can be increased or decreased.

[0028]

[0031] Electronic sensors 130 and 138 may be used to tune their respective circuits 128 and 136 in a closed loop. Depending on the type of sensor used, a current or voltage setpoint may be set for each sensor, and control software may be provided to the sensors to determine the adjustments to their respective electronic controllers 134 and 140, minimizing deviations from the setpoint. As a result, the plasma shape may be selected and dynamically controlled during processing. The above discussion is based on electronic controllers 134 and 140, which may be variable capacitors, but it will be understood that any electronic component with adjustable characteristics may be used to provide tuning circuits 128 and 136 with adjustable impedance.

[0029]

[0032] As mentioned above, the reactive ion etching ("RIE") process can produce several structural effects through stacks of semiconductor materials, which, if uncontrolled, can lead to the creation of defective devices. Figures 2A–2C illustrate some structural problems that can occur during the formation of memory holes. For example, Figure 2A shows an etching effect known as notching, which can create graded defects in the silicon nitride layer. The figure includes a structure 200 having a stack 205, which may include multiple parts 210 of alternating layers of material formed on a substrate 215. Although shown in three parts 210a, 210b, and 210c, it should be understood that the stack 205 may include any number of parts in embodiments encompassed by this technology. Each part 210 may represent four alternating layers of silicon oxide material 212 and silicon nitride material 214. Although four layers are illustrated, it should be understood that any number of layers may be included not only in each part but also in the entire stack. In addition, while the diagram shows silicon nitride as the bottom layer in a specific orientation, please understand that the layers may be reversed, and the process may start with the silicon oxide layer.

[0030]

[0033] As described above, etching of silicon oxide materials during the RIE process can occur in large quantities due to ion collisions, while etching of silicon nitride materials can occur in larger quantities due to chemical reactions between the RIE precursor and the nitride material. Therefore, silicon oxide etching is controlled by the control of the RIE beam, and oxides positioned laterally outward from the RIE beam (which may also include radial etching in some embodiments) may not be etched. However, nitride materials may be etched based on contact and chemical reactions between the RIE beam and the precursor or wastewater. Also, in some embodiments, silicon nitride may etch more slowly than silicon oxide. Due to hydrogen or other materials associated with silicon nitride, interaction with RIE wastewater, which may contain carbon, can generate polymer materials, which can passivate or protect the sidewalls of memory holes and limit lateral etching.

[0031]

[0034] However, polymerization can be minimized at the interface between the oxide material and the underlying silicon nitride material. In addition, the etching rate of silicon nitride may differ from that of silicon oxide, which may result in longer exposure times or wastewater retention times in the nitride layer. Before the protective polymerization material is formed, for example during the transition between the oxide layer and the nitride layer, wastewater may react with the exposed nitride, increasing lateral etching of the material. When polymer accumulation occurs, this lateral etching tapers, and a notch 220 may be formed around the leading edge in the etching direction of the silicon nitride material. This notching may hinder or affect the formation of subsequent layers or materials, and in some embodiments, may increase the diameter of the memory holes, i.e., the critical dimension.

[0032]

[0035] Eliminating notching may involve using materials that can interact better in the interface region, and in this technique, doped materials that may contain silicon oxynitride may be used, as will be further described below. However, oxidizing the silicon nitride layer is often avoided because it can create further problems. For example, Figure 2B may show an example of polygonal distortion that can occur during the formation of memory holes in both the vertical section 230 and the horizontal section 240. Polygonal distortion refers to the deformation of the memory hole into an elliptical shape rather than the rounded shape formed by the etching process. This type of distortion can occur when silicon oxynitride is used, and the higher the oxygen content, the greater the distortion that can be observed. Polygonal distortion can occur when the chemical properties of the etching change between the silicon oxide and silicon oxynitride layers. The amount of byproducts produced increases and deposits on top of the structure, which then affect the etching beam and can distort the penetrations through the structure.

[0033]

[0036] Figure 2C illustrates another problem with silicon oxynitride, where pinhole or void formation may occur within the nitride layer. For example, the figure shows a detailed view of void 250, which may be a region of reduced contrast within the nitride layer after memory hole formation. Unlike pure silicon nitride, polymerization is less likely to occur at the interface between the silicon oxide layer and the silicon oxynitride layer. The low density of the oxynitride may be due to the switching chemistry, but this can still increase stagnation at the interface and cause etching damage. Thus, several problems can occur during the RIE process and affect the memory hole structure in various ways. This technique involves one or more adjustments to the material properties of the stack layers, which may counteract or prevent one or more of the problems described.

[0034]

[0037] This technology can be used to modify the material properties of one or more layers or materials in an exemplary stack, thereby targeting one or more of the challenges described above. After a general description of how to form one or more parts of a layered semiconductor material stack, modifications that can be combined or performed in any variation or combination to improve the formation of memory holes will be described. The chamber 100 described above may be used when carrying out an exemplary method including the formation method, but according to embodiments of this technology, any number of deposition chambers may be used. Figure 3 shows exemplary steps in method 300 for forming a semiconductor structure according to embodiments of this technology. Prior to the first step of the method, the substrate may be processed in one or more ways before being placed in the processing area of ​​the chamber in which method 300 may be performed. Some or all of the steps may be performed in a chamber or system tool as described above, or in different chambers on the same system tool which may include the chamber in which the steps of method 300 may be performed.

[0035]

[0038] Method 300 may include several optional steps, as illustrated, which may or may not be particularly relevant to some embodiments of the method according to the present art. For example, many of the steps are described to provide a broader range of structure formation but are not essential to the present art, or may be performed by alternative methods, as further described below. Method 300 involves forming a stack of alternating layers of material, which in some embodiments may be used for 3D NAND memory formation. The alternating layers of material may be produced by any number of methods, including plasma chemical vapor deposition, physical vapor deposition, atomic layer deposition, thermochemical vapor deposition, or any other formation technique.

[0036]

[0039] In some embodiments, plasma vapor deposition may be carried out in a processing chamber, such as the processing chamber 100 described earlier. The remaining disclosure describes a stack of alternating layers of silicon oxide and silicon nitride, but embodiments of the art may use different combinations of materials, such as silicon oxide and silicon, silicon nitride and silicon, silicon and doped silicon, or any number of other materials. Method 300 describes the formation of silicon nitride following the formation of silicon oxide, but in embodiments similarly included in the art, the formation order may be reversed. In addition, any number of layers of material may be manufactured in a stack, or any part of any stack, and different parts of a stack may contain more, fewer, or similar numbers of layers of any other part of the stack, according to embodiments of the art.

[0037]

[0040] Method 300 may include, in step 305, forming a silicon oxide layer on a substrate. This formation may be carried out using a silicon-containing precursor and an oxygen-containing precursor. The method may also include, in step 310, forming a silicon nitride layer on top of the silicon oxide layer. This formation may be carried out using a silicon-containing precursor and a nitrogen-containing precursor. These steps may be repeated any number of times until a predetermined number of layers constituting a stack of layers is formed, which may include two or more pairs, about ten or more pairs, about fifty or more pairs, about 100 or more pairs, or more. Any particular number of pairs encompassed by any of these specified ranges should be understood as if specifically specified herein.

[0038]

[0041] In some embodiments, several parts, including all parts, may be formed between steps 305 and 310, and in some embodiments, those parts may be manufactured in several steps. For example, one or more optional steps may be performed between the formation of overlapping parts of the stack, and adjustments such as those described below may be performed between any of those parts, which may be shown as different parts. For example, high-temperature annealing may be performed before forming the second part of the stack. Optional steps may also include the formation of the first part of the memory holes and the preparation of the precursor. The second part of the stack is formed by forming at least one layer of silicon oxide material and at least one layer of silicon nitride material, and this is repeated to produce any number of pairs of layers similar to the first part described above.

[0039]

[0042] A mask material may be formed on any portion of the stack before forming memory holes or other features through the structure. Structures according to this technique may be characterized by any aspect ratio or height-to-width ratio of the structure, but in some embodiments, the material is characterized by a larger aspect ratio, which, as described above, can increase the effect on the form of the manufactured structure. For example, in some embodiments, the aspect ratio of an exemplary structure, e.g., the ratio of the opening or memory hole to the depth of the cross-sectional diameter, may be about 10:1 or greater, about 20:1 or greater, about 30:1 or greater, about 40:1 or greater, about 50:1 or greater, or greater. Such high aspect ratios may interfere with many conventional etching processes or cause or exacerbate any of the problems described above.

[0040]

[0043] Substrates on which paired materials can be formed may include materials such as crystalline silicon, silicon oxide, strained silicon, silicon germanium, doped or undoped polycrystalline silicon, doped or undoped wafers, patterned or unpatterned wafers, silicon-on-insulator, carbon-doped silicon oxide, silicon nitride, doped silicon, germanium, gallium arsenide, or sapphire. Substrates may have various dimensions, including rectangular or square panels, as well as wafers with diameters of 200 mm or 300 mm. Silicon-containing precursors that can be used during either silicon oxide formation or silicon nitride formation may include, but are not limited to, silane (SiH4), disilane (Si2H6), silicon tetrafluoride (SiF4), silicon tetrachloride (SiCl4), dichlorosilane (SiH2Cl2), tetraethyl orthosilicate (TEOS), and other silicon-containing precursors that can be used for silicon-containing film formation. Oxygen-containing precursors used in any step as described throughout this technology may include O2, N2O, NO2, O3, H2O, and any other oxygen-containing precursors that can be used in silicon oxide film formation, silicon oxynitride film formation, or other film formation. Nitrogen-containing precursors used in any step may include N2, N2O, NO2, NH3, N2H2, and any other nitrogen-containing precursors that can be used in silicon nitride film formation. Additional dopant precursors may include PH3 or any other phosphorus-containing precursors. One or more additional precursors may be included in any of the formation steps, such as inert precursors that may include Ar, He, Xe, Kr, nitrogen, hydrogen, or other precursors.

[0041]

[0044] As mentioned above, notching can occur in the silicon nitride layer during memory hole formation because reactive species diffuse laterally through the structure before sufficient polymerization is formed. However, in some embodiments, the formation of the silicon nitride layer may involve the incorporation of a certain amount of oxygen. As described above, the RIE process occurs to a greater extent from collisions with oxygen, and in some embodiments, notching can be reduced or eliminated by incorporating oxygen into the nitride layer to a controlled amount. For example, during the formation of one or more silicon nitride layers in any part of the stack, an oxygen-containing precursor may be flowed together with a nitrogen-containing precursor and / or a silicon-containing precursor to create a film that incorporates a certain amount of oxygen. The oxygen-containing precursor is any of the oxygen-containing precursors described above, and in some embodiments, it may be the same oxygen-containing precursor used to form the silicon oxide material. Using the same precursor in some embodiments may reduce the number of modifications made during stack formation and shorten waiting times.

[0042]

[0045] In some embodiments, one or more layers of silicon nitride material may contain about 5 atomic percent or more of oxygen, and may contain about 10 atomic percent or more of oxygen, about 15 atomic percent or more of oxygen, about 20 atomic percent or more of oxygen, about 25 atomic percent or more of oxygen, about 30 atomic percent or more of oxygen, or more of oxygen. Since the additional incorporation of oxygen may affect downstream processes, such as excavation of the silicon nitride layer, in some embodiments the amount of oxygen may be maintained at about 30 atomic percent or less of oxygen, about 25 atomic percent or less of oxygen, about 20 atomic percent or less of oxygen, or less of this. This may facilitate the selective removal of the nitride material during subsequent processes without damaging the silicon oxide material. Similarly, in some embodiments, one or more layers of the silicon nitride material may contain phosphorus, which may be incorporated into the film at a concentration of about 15 atomic percent or less, and may be incorporated at concentrations of about 12 atomic percent or less, about 10 atomic percent or less, about 8 atomic percent or less, about 6 atomic percent or less, about 5 atomic percent or less, about 4 atomic percent or less, about 3 atomic percent or less, about 2 atomic percent or less, about 1 atomic percent or less, or lower. In some embodiments, the layers of silicon nitride material may maintain a nitrogen content above a threshold such as about 20 atomic percent or more, and may produce silicon nitride material characterized by nitrogen content of about 25 atomic percent or more, about 30 atomic percent or more, about 35 atomic percent or more, about 40 atomic percent or more, about 45 atomic percent or more, or higher.

[0043]

[0046] As described above, notching can occur at the leading edge of the silicon nitride material in the etching direction toward the substrate. In some embodiments, the incorporation of oxygen may be adjusted to accommodate this effect. For example, in some embodiments, the formation of the silicon nitride material may involve the formation of a bilayer for each layer of silicon nitride, consisting of silicon nitride and silicon oxynitride and / or phosphorus-doped silicon nitride. For example, a silicon-containing precursor and a nitrogen-containing precursor are flowed to produce a certain amount of silicon nitride, and then an oxygen-containing precursor and / or phosphorus-containing precursor are added to the flow, which may include maintaining or adjusting the flow rate of the silicon-containing precursor and / or nitrogen-containing precursor. Each layer of the bilayer may constitute any proportion of the bilayer between about 10% and about 90% of the bilayer thickness. However, in some embodiments, in order to maintain differentiation between layers and to facilitate downstream processing that can selectively remove the silicon nitride material, the doped portion of the bilayer, such as the oxygen and / or phosphorus-containing portion, may constitute about 50% or less of the bilayer. In addition, the oxygen and / or phosphorus-containing portion may constitute approximately 45% or less of the double layer, approximately 40% or less of the double layer, approximately 35% or less of the double layer, approximately 30% or less of the double layer, approximately 25% or less of the double layer, approximately 20% or less of the double layer, approximately 15% or less of the double layer, approximately 10% or less of the double layer, or less than or equal to these amounts.

[0044]

[0047] Whether the oxygen / phosphorus-containing dopant precursor is added at the beginning of the silicon nitride material formation or at some point after the initial formation, the flow rate of the dopant precursor can be kept constant, decreased, or increased during layer formation. For example, a gradient of dopant concentration can be generated in the silicon nitride material from approximately 0 atomic percent dopant introduction to any of the introductions described above. By initiating and then adjusting the flow rate of the dopant precursor, the silicon nitride material can contain an incorporated gradient. For example, since the flow rate of the dopant precursor is increased during the formation of a layer or bilayer of the silicon nitride material, a portion of the silicon nitride material at the interface of the overlapping silicon oxide material may be characterized by a higher amount of dopant than the lower portion of the silicon nitride material. Thus, in some embodiments, a state in which more nitride is incorporated throughout the film can be maintained while reducing the notching effect where it is most likely to occur.

[0045]

[0048] The amount of dopant incorporated into one or more layers of silicon nitride material may also be adjusted in some embodiments between different parts of the stack, so that any layer in any part may be characterized by the incorporation of any amount of dopant as described above, or may remain substantially free of dopant incorporation. For example, in a second part of the stack, some grooving effects and / or profile changes may occur. These problems may be suppressed or resolved by adjusting the dopant introduction into silicon nitride in this part of the stack. For example, radical wastewater from the RIE process may laterally etch the silicon nitride, causing some warping and grooving, which may further expose silicon oxide, increasing the amount of etching on those materials and thus increasing the effect. By limiting the impact on the nitride material, the impact on the oxide material may also be suppressed, and these problems and the uniformity of memory hole formation may be improved. By increasing the dopant introduction into the nitride layer in areas where grooving and / or warping may occur, resistance to lateral etching may be improved, and the effects of these problems may be limited.

[0046]

[0049] Similarly, the alignment and distortion issues of memory holes can be improved by increasing the dopant concentration of the nitride material in the lower part of the stack. Silicon oxide can improve or better control stress effects and limit the aforementioned deformation by reducing the amount of hydrogen in the film. Therefore, in some embodiments, the first part of the stack may include an increased dopant concentration in the nitride layer to reduce stress effects due to gas release. Optional annealing may also be performed as described above, and with or without an increase in the dopant concentration in the nitride material, the temperature of the formed film may be increased to increase gas release before the formation of additional parts of the stack. The annealing may include a process of raising the temperature of the first part of the stack to about 500°C or higher, and may be raised to about 550°C or higher, about 600°C or higher, about 650°C or higher, about 700°C or higher, about 750°C or higher, about 800°C or higher, about 850°C or higher, about 900°C or higher, or higher. For example, when the temperature exceeds approximately 650°C, a certain amount of gas is released to limit structural deformation, which can improve the alignment between the memory holes.

[0047]

[0050] Similarly, the deposition process may also be carried out at higher temperatures, which can further increase the density of the doped silicon nitride film. For example, in some embodiments, silicon nitride is formed at a substrate temperature of about 400°C or higher, and may be carried out at substrate temperatures of about 450°C or higher, about 500°C or higher, about 550°C or higher, about 600°C or higher, about 650°C or higher, or higher. Combined with controlled dopant introduction and plasma modification, as described later, the density of the silicon nitride film can be adjusted over a range of densities. For example, as a bilayer or as a continuous layer, silicon nitride may have regions characterized by a density lower than that of silicon nitride, but the density can be maintained higher than that of silicon oxynitride. This ensures that pinholes and polygonal distortions are controlled or prevented in embodiments of the present technology. Thus, the density within the silicon nitride layer is about 3.0 g / cm³. 3 The above, or approximately 3.1 g / cm³ 3From the above, it may be in the range up to the density of silicon nitride, or the density may be reduced to include a density of about 3.0 g / cm 3 or less, and the density may be reduced to include a density of about 2.95 g / cm 3 or less, about 2.9 g / cm 3 or less, about 2.85 g / cm 3 or less, about 2.8 g / cm 3 or less, about 2.75 g / cm 3 or less, about 2.7 g / cm 3 or less, about 2.65 g / cm 3 or less, about 2.6 g / cm 3 or less, or may include a density below this.

[0048]

[0051] By including an amount of dopant within the nitride material, in some embodiments of the present technology, notching can be reduced or eliminated. FIG. 4 shows a close-up view of a portion where a lower layer of silicon nitride material 405 overlaps with silicon oxide material 407, where notch 410 can be formed. The notch can be characterized by the lateral intrusion distance A at the interface between the silicon nitride layer and the silicon oxide material above it. The layer of silicon nitride material can also be characterized by thickness B. In some embodiments, any particular layer of the silicon nitride material can include a notch having an intrusion distance A that is about 100% or less of the distance corresponding to thickness B. In some embodiments, distance A may be about 75% or less of distance B, distance A may be about 50% or less of distance B, distance A may be about 40% or less of distance B, distance A may be about 30% or less of distance B, distance A may be about 20% or less of distance B, distance A may be about 10% or less of distance B, distance A may be about 5% or less of distance B, distance A may be about 1% or less of distance B, or distance A may be zero, in which case no notch may be formed in the layer.

[0049]

[0052] Dopant concentrations may also be adjusted to affect the etching rate of the silicon nitride material, thereby improving etching in areas such as the first portion of the stack where tapering or narrowing may occur. These dopants may have an affinity for certain materials in the chemical properties of the RIE, which may increase etching through that portion. Therefore, incorporating these dopants may increase the etching of the material. Similarly, silicon nitride may be formed with increased carbon content, which may partially reduce etching. Many RIE etchants may contain halogenated carbons such as chlorinated hydrocarbons, carbon fluoride, or fluorocarbons, and etching may be reduced in films with higher carbon content compared to films with lower carbon content. Therefore, as one non-limiting example, one or more layers or one or more portions of a stack may contain increased carbon concentrations, such as between about 1% and about 10%, to control etching.

[0050]

[0053] The nitrogen-to-silicon ratio within the silicon nitride material layers can also be adjusted in some embodiments to affect the etching rate. For example, increasing the nitrogen-to-silicon ratio can increase the etching rate of the material, while decreasing the ratio can decrease it. Thus, in some embodiments, one or more layers of the silicon nitride material may be characterized by an increased nitrogen-to-silicon ratio relative to one or more other layers, for example, in a first portion, and / or one or more layers of the silicon nitride material may be characterized by a decreased nitrogen-to-silicon ratio relative to one or more other layers, for example, in a second portion. The increase in the nitrogen-to-silicon ratio may be about 1.3 or more, about 1.4 or more, about 1.5 or more, about 1.6 or more, or higher. The decrease in the nitrogen-to-silicon ratio may be about 1.3 or less, about 1.2 or less, about 1.1 or less, about 1.0 or less, or lower.

[0051]

[0054] Adjusting the plasma formation process can also facilitate the formation of the silicon nitride layer by influencing the removal of hydrogen from the film being produced, in some embodiments. For example, some embodiments of the art may include pulsing the plasma power during plasma generation for forming the silicon nitride layer. In some embodiments, pulsing the plasma may be applied to the formation of silicon oxide or silicon nitride, or both. The plasma may be generated at a plasma generation frequency such as 13.56 MHz in one non-limiting example. The plasma power may also be pulsed at a pulse frequency that may be about 10 kHz or less, and may be about 9 kHz or less, about 8 kHz or less, about 7 kHz or less, about 6 kHz or less, about 5 kHz or less, about 4 kHz or less, about 3 kHz or less, about 2 kHz or less, about 1 kHz or less, or lower. The duty cycle of the pulse frequency may provide some amount of "off" time for plasma generation.

[0052]

[0055] During the plasma's "off" period, deposition may not occur. While previously formed ions may quickly disappear, radical species can still come into contact with the heated substrate and transfer energy to the resulting amorphous lattice. This continues to activate and break further hydrogen bonds within the film, which can then be removed from the film. At high duty cycles, there may not be enough time to achieve this effect before deposition resumes. Therefore, in some embodiments, the duty cycle may be maintained at or below approximately 50%, approximately 45%, approximately 40%, approximately 35%, approximately 30%, approximately 25%, approximately 20%, approximately 15%, approximately 10%, approximately 5%, or lower.

[0053]

[0056] By utilizing one or more of the described processes, the formation of memory holes may be improved, which can limit effects such as notching and improve the uniformity of the profile through the memory holes. For example, in some embodiments, a layer or portion through the stack may be characterized by a variation in diameter through the memory holes of the stack of about 200% or less, and may be characterized by a variation in diameter through the memory holes of about 150% or less, about 100% or less, about 90% or less, about 80% or less, about 70% or less, about 60% or less, about 50% or less, about 40% or less, about 30% or less, about 20% or less, about 10% or less, or less. As a result, the present technology enables improved manufacturing and can produce a more uniform stack structure than conventional technologies.

[0054]

[0057] The above description has provided numerous details for illustrative purposes to facilitate understanding of various embodiments of this technology. However, it will be apparent to those skilled in the art that certain embodiments can be implemented without some of these details, or with additional details.

[0055]

[0058] While several embodiments have been disclosed, those skilled in the art will recognize that various modifications, alternative structures, and equivalents can be used without departing from the spirit of the embodiments. Furthermore, some well-known processes and elements have not been described in order to avoid unnecessarily obscuring the Art. Therefore, the above description should not be construed as limiting the scope of the Art. Moreover, while methods or processes may be described sequentially or stepwise, it should be understood that actions may occur simultaneously or in an order different from that listed.

[0056]

[0059] Where a range of values ​​is given, unless explicitly stated otherwise in the context, each intervening value between the upper and lower limits of that range is understood to be specifically disclosed down to the smallest unit of the lower limit. This includes any narrower range between any stated or unstated intervening values ​​within the stated range, and any other stated or intervening values ​​within that stated range. The upper and lower limits of such narrower ranges may be individually included in or excluded from that range. Each range in which one, neither, or both of the limit values ​​are included is also included in the Art, provided that there are limit values ​​specifically excluded within the stated range. Where a stated range includes one or both of the limit values, it also includes ranges that exclude one or both of these included limit values.

[0057]

[0060] As used herein and in the claims, the singular forms “a,” “an,” and “the” include multiple references unless the context clearly indicates otherwise. Thus, for example, “a precursor” includes multiple such precursors, and “the layer” includes one or more layers and their equivalents known to those skilled in the art, and so on.

[0058]

[0061] Furthermore, the terms “comprise(s),” “comprising,” “contain(s),” “containing,” “include(s),” and “including,” as used herein and in the claims, are intended to identify the presence of the described feature, integer, component, or action, but not to exclude the presence or addition of one or more other features, integers, components, actions, activities, or groups.

Claims

1. A method for forming a semiconductor structure, Forming a silicon oxide layer from a silicon-containing precursor and an oxygen-containing precursor, The silicon nitride layer is formed from a silicon-containing precursor, a nitrogen-containing precursor, and an oxygen-containing precursor, wherein the silicon nitride layer has an oxygen concentration of 30 atomic percent or less and 3.0 g / cm³. ３ The formation of a silicon nitride layer characterized by the following densities, In order to generate a stack of alternating silicon oxide and silicon nitride layers, the process of forming the silicon oxide layer and the silicon nitride layer is repeated. Methods that include...

2. A method for forming a semiconductor structure according to claim 1, wherein the oxygen-containing precursor used to form the silicon oxide layer and the oxygen-containing precursor used to form the silicon nitride layer are the same precursor.

3. A method for forming a semiconductor structure according to claim 1, wherein forming the silicon nitride layer includes performing plasma-enhanced deposition at a substrate temperature of 500°C or higher.

4. A method for forming a semiconductor structure according to claim 1, wherein the formation of the silicon nitride layer includes performing plasma-enhanced deposition at a plasma pulse frequency of 10 kHz or less and a duty cycle of 50% or less.

5. A method for forming a semiconductor structure according to claim 1, wherein the oxygen concentration of the silicon nitride layer is between 10 atomic percent and 30 atomic percent, and the nitrogen atom percentage is 30 atomic percent or more.

6. Forming the silicon nitride layer is The silicon-containing precursor and the nitrogen-containing precursor are introduced into the substrate processing area. Forming a certain amount of silicon nitride, The oxygen-containing precursor is added while continuing the formation of silicon nitride. A method for forming the semiconductor structure according to claim 1, including the method described in claim 1.

7. A method for forming a semiconductor structure according to claim 6, wherein the oxygen-containing precursor is flowed at a constant flow rate, and the silicon nitride layer formed comprises a bilayer of substantially oxygen-free silicon nitride and silicon nitride characterized by an oxygen concentration of 5 atomic percent or more.

8. A method for forming a semiconductor structure according to claim 6, wherein the oxygen-containing precursor is flowed at a varying flow rate, and the silicon nitride layer formed includes a gradient of oxygen concentration through the silicon nitride layer.

9. A method for forming a semiconductor structure according to claim 8, wherein the flow rate of the oxygen-containing precursor is increased while the oxygen-containing precursor is being added.

10. A method for forming a semiconductor structure according to claim 1, further comprising forming one or more features through the stack of alternating layers of silicon oxide and silicon nitride.

11. A method for forming a semiconductor structure according to claim 10, wherein the removal of the side of the silicon nitride layer at the interface between the silicon nitride layer and the silicon oxide layer superimposed thereon extends to a distance of 50% or less of the distance corresponding to the thickness of the silicon nitride layer.

12. A method for forming a semiconductor structure, Forming a silicon oxide layer from a silicon-containing precursor and an oxygen-containing precursor, The silicon nitride layer is formed from a silicon-containing precursor, a nitrogen-containing precursor, and a phosphorus-containing precursor, wherein the silicon nitride layer has a phosphorus concentration of 15 atomic% or less and 3.0 g / cm³ ３ The formation of a silicon nitride layer characterized by the following densities, In order to generate a stack of alternating silicon oxide and silicon nitride layers, the process of forming the silicon oxide layer and the silicon nitride layer is repeated. Methods that include...

13. A method for forming a semiconductor structure according to claim 12, wherein forming the silicon nitride layer includes performing plasma-enhanced deposition at a substrate temperature of 500°C or higher.

14. A method for forming a semiconductor structure according to claim 12, wherein forming the silicon nitride layer includes performing plasma-enhanced deposition at a plasma pulse frequency of 10 kHz or less and a duty cycle of 50% or less.

15. A method for forming a semiconductor structure according to claim 12, wherein the phosphorus concentration of the silicon nitride layer is 10 atomic percent or less, and the nitrogen atom percentage is 30 atomic percent or more.

16. Forming the silicon nitride layer is The silicon-containing precursor and the nitrogen-containing precursor are introduced into the substrate processing area. Forming a certain amount of silicon nitride, The phosphorus-containing precursor is added while continuing the formation of silicon nitride. A method for forming the semiconductor structure according to claim 12, including the method described in claim 12.

17. A method for forming a semiconductor structure according to claim 16, wherein the phosphorus-containing precursor is flowed at a constant flow rate, and the silicon nitride layer formed comprises a bilayer of substantially phosphorus-free silicon nitride and silicon nitride characterized by a phosphorus concentration of 1 atomic percent or more.

18. A method for forming a semiconductor structure according to claim 16, wherein phosphorus is incorporated into the silicon nitride layer in a thickness of 30% or less.

19. A method for forming a semiconductor structure, Forming a silicon oxide layer from a silicon-containing precursor and an oxygen-containing precursor, The silicon nitride layer is formed from a silicon-containing precursor, a nitrogen-containing precursor, and a dopant precursor, wherein the silicon nitride layer has a dopant concentration of 30 atomic% or less and 3.0 g / cm³. ３ The formation of a silicon nitride layer characterized by the following densities, In order to generate a stack of alternating silicon oxide and silicon nitride layers, the process of forming the silicon oxide layer and the silicon nitride layer is repeated. Methods that include...

20. A method for forming a semiconductor structure according to claim 19, wherein forming the silicon nitride layer includes performing plasma-enhanced deposition at a substrate temperature of 500°C or higher, and forming the silicon nitride layer includes performing the plasma-enhanced deposition at a plasma pulse frequency of 10 kHz or lower and a duty cycle of 50% or lower.

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