Insulating substrates and semiconductor devices

Abstract

The purpose of the present invention is to provide a technology that makes it possible, in a semiconductor device, to minimize insulating failure such as short-circuiting between circuit patterns and deterioration in appearance quality caused by a plating residue. An insulated substrate (2) comprises: a ceramic substrate (2b); and a circuit pattern (2a) which is joined to the surface of the ceramic substrate (2b) and on which a semiconductor element (3) is mounted. At the back surface side of the outer peripheral part of the circuit pattern (2a) joined to the ceramic substrate (2b), a dug part (8) which is not in contact with the surface of the ceramic substrate (2b) is formed.

Description

Technical Field

[0001] The present disclosure relates to an insulating substrate and a semiconductor device.

Background Art

[0002] For example, Patent Document 1 proposes a semiconductor device capable of improving the bonding reliability between a circuit pattern and a semiconductor element.

[0003] For an insulating substrate mounted on a semiconductor device, a plating process and a plating peeling process are performed for the purpose of soldering the circuit pattern formed on the surface of the ceramic substrate included in the insulating substrate and the semiconductor element. In the plating process, plating is applied to the entire insulating substrate. In the plating peeling process, only the portion necessary for soldering is masked with a resist material, and for the portion where plating is unnecessary, the plating is dissolved and removed with a stripping solution, and then the plating residue is removed with an air blow.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] However, when manufacturing a circuit pattern, minute sagging portions may be formed on the outer peripheral side of the bonding surface between the ceramic substrate and the circuit pattern. In the sagging portions, since the air blow hits poorly, plating residues tend to remain in the sagging portions even after the plating peeling process. When manufacturing a semiconductor device with plating residues remaining, due to the heat load during soldering and the flow of the sealing resin, the plating residues staying in the sagging portions may flow out, which may deteriorate the appearance quality of the semiconductor device. Furthermore, when the plating residues flow out so as to cross between the circuit patterns, there is also a risk of causing insulation failures such as short circuits between the circuit patterns.

[0006] In the technology described in Patent Document 1, a brazing reservoir recess is formed on the outer periphery of the circuit pattern. However, the brazing reservoir recess is limited to the function of accumulating the brazing material used for bonding the semiconductor element and the circuit pattern, and does not take into consideration problems caused by plating residue.

[0007] Therefore, the present disclosure aims to provide a technology that can suppress deterioration of appearance quality and insulation defects such as short circuits between circuit patterns caused by plating residue in semiconductor devices. [Means for solving the problem]

[0008] The insulating substrate according to this disclosure comprises a ceramic substrate and a circuit pattern bonded to the surface of the ceramic substrate on which a semiconductor element is to be mounted, wherein a recessed portion is formed on the back side of the outer periphery of the circuit pattern that is bonded to the ceramic substrate, and the recessed portion is formed around the entire circumference of the outer periphery of the circuit pattern. In the circuit pattern, a sagging area is formed on the outer periphery of the bonding surface with the ceramic substrate, and the recessed area is larger than the sagging area. . [Effects of the Invention]

[0009] According to this disclosure, in the plating removal process performed before bonding the circuit pattern to the semiconductor element, the stripping solution penetrates more easily to the back side of the outer periphery of the circuit pattern, and the airflow for removing plating residue is improved, making it possible to remove unwanted plating residue more effectively. As a result, it is possible to suppress deterioration of appearance quality and insulation defects such as short circuits between circuit patterns caused by plating residue in semiconductor devices.

[0010] The purpose, features, aspects, and benefits of this disclosure will become clearer from the following detailed description and accompanying drawings. [Brief explanation of the drawing]

[0011] [Figure 1] This is a cross-sectional view of the semiconductor device according to Embodiment 1. [Figure 2] This is a cross-sectional view of the semiconductor device according to Embodiment 2. [Figure 3] This is a cross-sectional view of the semiconductor device according to Embodiment 3. [Figure 4] This is a cross-sectional view of a semiconductor device according to a modified example 1 of Embodiment 3. [Figure 5] This is a cross-sectional view of a semiconductor device according to a modified example 2 of Embodiment 3. [Figure 6] These are a top view, a cross-sectional view along line AA, and a cross-sectional view along line BB of the semiconductor device according to Embodiment 4, viewed from above the semiconductor element. [Figure 7] This is a top view of a part of a semiconductor device according to Modification 1 of Embodiment 4, viewed from above the semiconductor element. [Figure 8] This is a top view of a part of a semiconductor device according to a modified example 2 of Embodiment 4, viewed from above the semiconductor element. [Figure 9] This is a top view of a part of a semiconductor device according to Modification 3 of Embodiment 4, viewed from above the semiconductor element. [Modes for carrying out the invention]

[0012] <Embodiment 1> Embodiment 1 will be described below with reference to the drawings. Figure 1 is a cross-sectional view of the semiconductor device 100 according to Embodiment 1.

[0013] As shown in Figure 1, the semiconductor device 100 comprises a base plate 1, an insulating substrate 2, a semiconductor element 3, a main terminal 4, a resin case 5, and a sealing resin 6.

[0014] The base plate 1 has a rectangular shape when viewed from above and is made of a material with relatively high thermal conductivity, such as copper, copper alloy, aluminum, or aluminum alloy.

[0015] The insulating substrate 2 has a surface circuit pattern 2a, a ceramic substrate 2b, and a back surface circuit pattern 2c. The ceramic substrate 2b is made of ceramics such as Al2O3, AlN, and Si3N4, for example. The surface circuit pattern 2a and the back surface circuit pattern 2c are made of a metal having, for example, Cu as a main component. The surface circuit pattern 2a and the back surface circuit pattern 2c are joined to the surface and the back surface of the ceramic substrate 2b, respectively, with a brazing material (not shown) or the like. Also, the surface circuit pattern 2a is a circuit pattern on which the semiconductor element 3 is to be mounted, and is selectively patterned. That is, a plurality of surface circuit patterns 2a are formed, and circuits necessary for the semiconductor device 100 are formed.

[0016] On the surface circuit pattern 2a, the back surface electrode (for example, collector electrode) of the semiconductor element 3 is joined via a bonding material 7 made of a lead-free solder such as Sn-Ag, etc., whereby the semiconductor element 3 is mounted. The semiconductor element 3 is a power semiconductor element made of, for example, Si, SiC, or GaN, etc. Since the power semiconductor element generates high temperature during operation, it is important to ensure high heat dissipation. Although two semiconductor elements 3 are shown in FIG. 1, the number is not limited to two and may be one or more.

[0017] To the surface electrode (for example, emitter electrode or gate electrode) of the semiconductor element 3, a main terminal 4 having Cu as a main component is joined via the bonding material 7, whereby various wirings are formed and circuits necessary for the semiconductor device 100 are formed.

[0018] The resin case 5 is formed in a rectangular frame shape in a top view by a high heat-resistant resin such as PPS, for example. The resin case 5 is fixed to the outer peripheral portion of the base plate 1 with an adhesive (not shown) or the like so as to surround the circuit including the semiconductor element 3. Inside the resin case 5, a sealing resin 6 such as an epoxy resin is filled, and the circuit including the semiconductor element 3 is protected.

[0019] Next, we will explain the problems that occur during the manufacturing of the insulating substrate 2. The manufacturing process of the insulating substrate 2 involves a plating process and a plating removal process for the purpose of soldering the surface circuit pattern 2a and the semiconductor element 3. In the plating process, the entire insulating substrate 2 is plated. In the plating removal process, only the parts necessary for soldering are masked with a resist material, and the parts where plating is not needed are removed by dissolving the plating with a stripping solution, and then the plating residue is removed by air blowing.

[0020] During the manufacturing of the surface circuit pattern 2a, minute sagging areas may form on the outer periphery of the bonding surface between the surface circuit pattern 2a and the ceramic substrate 2b. Because air blowing is ineffective in these sagging areas, plating residue tends to remain in these areas even after the plating removal process. When manufacturing the semiconductor device 100 with plating residue remaining, the thermal load during soldering and the flow of the sealing resin 6 may cause the plating residue accumulated in the sagging areas to flow out, potentially degrading the appearance quality of the semiconductor device 100. Furthermore, if the plating residue flows across the surface circuit patterns 2a, it may cause insulation failures such as short circuits between the surface circuit patterns 2a.

[0021] In contrast, in Embodiment 1, as shown in Figure 1, a recessed portion 8 is formed on the back side of the outer periphery of the surface circuit pattern 2a that is joined to the ceramic substrate 2b, and this recessed portion does not come into contact with the surface of the ceramic substrate 2b. The recessed portion 8 is formed around the entire circumference of the outer periphery of the surface circuit pattern 2a.

[0022] Since the recessed portion 8 is provided as an opening larger than the sagging portion in the area where a minute sagging portion is formed, it is possible to sufficiently penetrate the back side of the outer periphery of the surface circuit pattern 2a with the plating stripping solution and improve the airflow exposure of the air blower. This makes it possible to reduce the amount of plating residue.

[0023] As described above, the semiconductor device 100 according to Embodiment 1 comprises an insulating substrate 2, a semiconductor element 3 mounted on the surface of a surface circuit pattern 2a, and a base plate 1 bonded to the back side of a ceramic substrate 2b.

[0024] Furthermore, the insulating substrate 2 comprises a ceramic substrate 2b and a surface circuit pattern 2a bonded to the surface of the ceramic substrate 2b, on which the semiconductor element 3 is to be mounted. On the back side of the outer periphery of the surface circuit pattern 2a that is bonded to the ceramic substrate 2b, a recessed portion 8 is formed that does not come into contact with the surface of the ceramic substrate 2b.

[0025] Therefore, in the plating removal process performed before bonding the surface circuit pattern 2a to the semiconductor element 3, the stripping solution can more easily penetrate the back side of the outer periphery of the surface circuit pattern 2a, and the airflow for removing plating residue is improved, making it possible to remove unwanted plating residue more effectively. As a result, in the semiconductor device 100, it is possible to suppress deterioration of appearance quality and insulation defects such as short circuits between surface circuit patterns 2a caused by plating residue.

[0026] Based on the above, it becomes possible to improve the durability of the insulating substrate 2 and the semiconductor device 100, as well as improve the yield.

[0027] <Embodiment 2> Next, a semiconductor device 200 according to Embodiment 2 will be described. Figure 2 is a cross-sectional view of the semiconductor device 200 according to Embodiment 2. In Embodiment 2, the same reference numerals are used for components that are the same as those described in Embodiment 1, and their descriptions are omitted.

[0028] As shown in Figure 2, in Embodiment 2, the recessed portion 8 is not formed in the surface circuit pattern 2a, while the recessed portion 9 is formed in the ceramic substrate 2b.

[0029] The recessed portion 9 is formed so as to be recessed downward in the portion of the ceramic substrate 2b adjacent to the outer periphery of the surface circuit pattern 2a. Specifically, the recessed portion 9 is formed on the ceramic substrate 2b from the portion facing the entire outer periphery of the surface circuit pattern 2a toward the outer periphery. Because the recessed portion 9 is formed, the outer periphery of the surface circuit pattern 2a does not come into contact with the surface of the ceramic substrate 2b.

[0030] Since the recessed portion 9 is provided as an opening larger than the sagging portion adjacent to the portion where a minute sagging portion is formed, it is possible to sufficiently penetrate the back side of the outer periphery of the surface circuit pattern 2a with the plating stripping solution and improve the airflow exposure of the air blower. This makes it possible to reduce the amount of plating residue.

[0031] As described above, in the semiconductor device 200 according to Embodiment 2, the insulating substrate 2 comprises a ceramic substrate 2b and a surface circuit pattern 2a bonded to the surface of the ceramic substrate 2b, on which a semiconductor element 3 is to be mounted. A recessed portion 9 is formed in the portion of the ceramic substrate 2b adjacent to the outer periphery of the surface circuit pattern 2a, with the recess being lowered.

[0032] Therefore, in the plating removal process performed before bonding the surface circuit pattern 2a to the semiconductor element 3, the stripping solution can more easily penetrate the back side of the outer periphery of the surface circuit pattern 2a, and the airflow for removing plating residue is improved, making it possible to remove unwanted plating residue more effectively. As a result, in the semiconductor device 200, it is possible to suppress deterioration of appearance quality and insulation defects such as short circuits between surface circuit patterns 2a caused by plating residue.

[0033] <Embodiment 3> Next, a semiconductor device 300 according to Embodiment 3 will be described. Figure 3 is a cross-sectional view of the semiconductor device 300 according to Embodiment 3. In Embodiment 3, the same reference numerals are used for components that are the same as those described in Embodiments 1 and 2, and their descriptions are omitted.

[0034] As shown in Figure 3, in Embodiment 3, the recessed portions 8 and 9 are not formed, and the outer periphery of the surface circuit pattern 2a is formed in a tapered shape 10, where the width of the surface circuit pattern 2a narrows from the back surface, which is bonded to the ceramic substrate 2b, towards the front surface on which the semiconductor element 3 is mounted. The tapered shape 10 is formed around the entire circumference of the outer periphery of the surface circuit pattern 2a.

[0035] By forming the outer periphery of the surface circuit pattern 2a into a tapered shape 10, the outer surface of the surface circuit pattern 2a faces upward, making it easier for the stripping solution to penetrate the entire outer periphery of the surface circuit pattern 2a. Furthermore, the airflow for removing plating residue is improved, making it possible to remove unwanted plating residue more effectively.

[0036] As described above, in the semiconductor device 300 according to Embodiment 3, the insulating substrate 2 comprises a ceramic substrate 2b and a surface circuit pattern 2a bonded to the surface of the ceramic substrate 2b, on which the semiconductor element 3 is to be mounted. The outer periphery of the surface circuit pattern 2a is formed in a tapered shape 10, where the width of the surface circuit pattern 2a narrows from the back surface bonded to the ceramic substrate 2b towards the surface on which the semiconductor element 3 is to be mounted.

[0037] Therefore, in the plating stripping process performed before bonding the surface circuit pattern 2a to the semiconductor element 3, the stripping solution can more easily penetrate the entire outer periphery of the surface circuit pattern 2a, and the airflow for removing plating residue is improved, making it possible to remove unwanted plating residue more effectively. As a result, in the semiconductor device 300, it is possible to suppress deterioration of appearance quality and insulation defects such as short circuits between surface circuit patterns 2a caused by plating residue.

[0038] <Modified form of Embodiment 3> Next, modified examples 1 and 2 of Embodiment 3 will be described. Figure 4 is a cross-sectional view of the semiconductor device 400 according to Modified Example 1 of Embodiment 3. Figure 5 is a cross-sectional view of the semiconductor device 500 according to Modified Example 2 of Embodiment 3.

[0039] As shown in Figure 4, the tapered shape 11 on the outer periphery of the surface circuit pattern 2a may be formed in a curved shape. Also, as shown in Figure 5, the tapered shape 12 on the outer periphery of the surface circuit pattern 2a may be formed in a stepped shape. In these cases as well, the same effects as in Embodiment 3 can be obtained.

[0040] <Embodiment 4> Next, the semiconductor device 600 according to Embodiment 4 will be described. Figure 6(a) is a top view of the semiconductor device 600 according to Embodiment 4, viewed from above the semiconductor element 3. Figure 6(b) is a cross-sectional view along line AA of Figure 6(a), and Figure 6(c) is a cross-sectional view along line BB of Figure 6(a). In Embodiment 4, the same reference numerals are used for components that are the same as those described in Embodiments 1 to 3, and their descriptions are omitted.

[0041] As shown in Figure 6(a), in Embodiment 4, notches 13 are formed in place of the recessed portions 8, 9 and tapered shapes 10, 11, 12. Multiple notches 13 are formed continuously around the entire circumference of the outer edge of the surface circuit pattern 2a. Specifically, the notches 13 have a rectangular shape when viewed from above, and two are formed on each side of the surface circuit pattern 2a.

[0042] As shown in Figures 6(a), (b), and (c), the notches 13 are formed to have the same thickness as the thickness of each surface circuit pattern 2a. Also, as shown in Figures 6(a) and (b), the portions of each surface circuit pattern 2a without the notches 13 have the same width d2 as a conventional structure without the notches 13.

[0043] In the conventional structure without the notch portion 13, the width of one side at the outer peripheral portion of each surface circuit pattern 2a is d2. Since plating residues having a length corresponding to d2 stay, there is a possibility that the plating residues flow out so as to cross the length d1 between adjacent surface circuit patterns 2a during the manufacture of the semiconductor device, and the plating residues may cause insulation failures such as short circuits between the surface circuit patterns 2a. Here, d2≧d1.

[0044] On the other hand, in the fourth embodiment, the width d3 of one side at the outer peripheral portion of each surface circuit pattern 2a, which is the length between adjacent notch portions 13 in the outer peripheral portion of each surface circuit pattern 2a, is formed to be sufficiently shorter than the length d1 between adjacent surface circuit patterns 2a (d3<d1). Therefore, even when plating residues having a length corresponding to d3 stay and flow out so as to cross the length d1 between the surface circuit patterns 2a during the manufacture of the semiconductor device 600, it is possible to suppress the contact between the plating residues and the adjacent surface circuit patterns 2a.

[0045] As described above, in the semiconductor device 600 according to the fourth embodiment, the insulating substrate 2 includes a ceramic substrate 2b and a surface circuit pattern 2a joined to the surface of the ceramic substrate 2b on which the semiconductor element 3 is to be mounted. A plurality of continuous notch portions 13 are formed in the outer peripheral portion of the surface circuit pattern 2a. Further, each notch portion 13 is formed in a rectangular shape in a top view.

[0046] Therefore, even when plating residues flow out so as to cross between adjacent surface circuit patterns 2a during the manufacture of the semiconductor device 600, it is possible to suppress the contact between the plating residues and the adjacent surface circuit patterns 2a. As a result, in the semiconductor device 600, it is possible to suppress a decrease in appearance quality due to plating residues and insulation failures such as short circuits between the surface circuit patterns 2a.

[0047] <Modification Example of the Fourth Embodiment> Next, modifications 1 to 3 of Embodiment 4 will be described. Figure 7 is a top view of a part of the semiconductor device 700 according to modification 1 of Embodiment 4, viewed from above the semiconductor element 3. Figure 8 is a top view of a part of the semiconductor device 800 according to modification 2 of Embodiment 4, viewed from above the semiconductor element 3. Figure 9 is a top view of a part of the semiconductor device 900 according to modification 3 of Embodiment 4, viewed from above the semiconductor element 3.

[0048] As shown in Figure 7, each notch 14 may be formed in a triangular shape when viewed from above. Also, as shown in Figure 8, each notch 15 may be formed in a stepped shape when viewed from above. Also, as shown in Figure 9, each notch 16 may be formed in an arc shape when viewed from above. In these cases as well, the same effects as in Embodiment 4 can be obtained.

[0049] Although this disclosure has been described in detail, the above description is illustrative and not limiting in all respects. It is understood that countless variations not illustrated are conceivable.

[0050] Furthermore, it is possible to freely combine each embodiment, or to modify or omit each embodiment as appropriate. [Explanation of Symbols]

[0051] 1 Base plate, 2 Insulating substrate, 2a Surface circuit pattern, 2b Ceramic substrate, 3 Semiconductor element, 8,9 Recessed section, 10 Tapered shape, 11 Curved shape, 12 Stepped shape, 13,14,15,16 Notched section, 100,200,300,400,500,600,700,800,900 Semiconductor device.

Claims

1. Ceramic substrate and The ceramic substrate comprises a circuit pattern bonded to its surface on which a semiconductor element is to be mounted, On the outer periphery of the circuit pattern, on the back side that is joined to the ceramic substrate, a recessed portion is formed that does not come into contact with the surface of the ceramic substrate. The recessed portion is formed around the entire circumference of the outer edge of the circuit pattern. A sagging portion is formed on the outer periphery side of the bonding surface with the ceramic substrate in the circuit pattern. The recessed portion is larger than the sagging portion, and is an insulating substrate.

2. Ceramic substrate and The ceramic substrate comprises a circuit pattern bonded to its surface on which a semiconductor element is to be mounted, Multiple continuous notches are formed on the outer periphery of the circuit pattern. Each of the aforementioned cutouts is formed in an arc shape towards the inside of the circuit pattern when viewed from above, in an insulating substrate.

3. The circuit pattern comprises multiple such patterns, The insulating substrate according to claim 2, wherein the length between adjacent notches on the outer periphery of each circuit pattern is shorter than the length between adjacent circuit patterns.

4. An insulating substrate according to any one of claims 1 to 3, The semiconductor element mounted on the surface of the circuit pattern, A base plate bonded to the back side of the ceramic substrate, A semiconductor device equipped with the following features.

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