Plasma processing apparatus, plasma processing method, and semiconductor device manufacturing method

Abstract

To provide a plasma processing apparatus, a plasma processing method, and a method of manufacturing a semiconductor device capable of shortening a cleaning time.SOLUTION: A plasma processing apparatus comprises a chamber, a plurality of DC power supplies, and a control unit. The plurality of DC power supplies that is individually controllable is provided on an upper part and a side wall of the chamber. The control unit controls the plurality of DC power supplies so as to apply DC voltages independently of each other.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] This embodiment relates to a plasma processing apparatus, a plasma processing method, and a method of manufacturing a semiconductor device.

Background Art

[0002] Depending on the type of gas used for plasma processing or the like, a film may easily deposit in the chamber, or the deposited film may be difficult to remove. In this case, the cleaning time in the chamber becomes long.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

Means for Solving the Problems

[0005] The plasma processing apparatus according to this embodiment includes a chamber, a plurality of DC power supplies, and a control unit. The plurality of DC power supplies that can be individually controlled are provided on the upper part and side walls of the chamber. The control unit controls the plurality of DC power supplies so as to apply DC voltages independently of each other.

Brief Description of the Drawings

[0006] [Figure 1] It is a cross-sectional view showing an example of the structure of a plasma processing apparatus according to the first embodiment. [Figure 2] It is a cross-sectional view showing an example of the configuration of a DC power supply according to the first embodiment. [Figure 3]This is a plan view showing an example of the configuration of the upper DC power supply according to the first embodiment. [Figure 4] This is a timing chart showing an example of the operation of a plasma processing apparatus according to the first embodiment. [Figure 5] This is a cross-sectional view showing an example of the structure of a semiconductor device according to the second embodiment. [Figure 6A] This is a cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the second embodiment. [Figure 6B] This is a cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the second embodiment. [Figure 7A] This is a cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the second embodiment. [Figure 7B] This is a cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the second embodiment. [Figure 8A] This is a cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the second embodiment. [Figure 8B] This is a cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the second embodiment. [Figure 9A] This is a cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the second embodiment. [Figure 9B] This is a cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the second embodiment. [Figure 10A] This is a cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the second embodiment. [Figure 10B] This is a cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the second embodiment. [Modes for carrying out the invention]

[0007] Embodiments of the present invention will be described below with reference to the drawings. These embodiments are not limiting to the present invention. The drawings are schematic or conceptual, and the proportions of each part may not necessarily be the same as those of actual objects. In the specification and drawings, elements similar to those described above with respect to previously shown drawings are denoted by the same reference numerals, and detailed explanations are omitted as appropriate.

[0008] (First Embodiment) FIG. 1 is a cross-sectional view showing an example of the structure of a plasma processing apparatus 100 according to the first embodiment. The plasma processing apparatus in FIG. 1 is a processing apparatus (semiconductor manufacturing apparatus) such as a plasma etching apparatus, for example.

[0009] The plasma processing apparatus in FIG. 1 includes a processing chamber 11, a mounting table (stage) 12, an upper electrode 13, an AC power supply 14, a process gas supply unit 15, a sensor 16, a DC power supply 17, and a control unit 19. The stage 12, the upper electrode 13, and the AC power supply 14 are examples of a gas processing unit.

[0010] The processing chamber 11 houses a wafer W to be processed. FIG. 1 shows an X2 direction and a Y2 direction that are parallel to the surface S1 and the back surface of the wafer W and perpendicular to each other, and a Z2 direction that is perpendicular to the surface S1 and the back surface of the wafer W. In this specification, the +Z2 direction is treated as the upward direction, and the -Z2 direction is treated as the downward direction. The -Z2 direction of the present embodiment may coincide with the gravitational direction or may not coincide with the gravitational direction.

[0011] The wafer W in the processing chamber 11 is placed on the stage 12. The stage 12 also functions as a lower electrode for plasma processing.

[0012] The upper electrode 13 is provided above the stage 12. The upper electrode 13 is provided, for example, at an upper part of the processing chamber 11 and at a position away from the top plate 111. The plasma processing apparatus 100 generates plasma between the upper electrode 13 and the stage 12, supplies the plasma to the surface S1 side of the wafer W, and processes the wafer W with the plasma. Specifically, the surface S1 of the wafer W is etched by dry etching using plasma. In an embodiment, for example, holes are formed in a processed film formed on the surface S1 of the wafer W by dry etching.

[0013] The AC power supply 14 applies an AC voltage to the stage 12. Thereby, plasma P is generated between the upper electrode 13 and the stage 12. The AC power supply 14 includes an AC power supply 141 and an AC power supply 142. The AC power supply 141 is, for example, a high-frequency power supply having a frequency of 60 MHz. The AC power supply 142 is, for example, a high-frequency power supply having a frequency of 400 kHz.

[0014] The process gas supply unit 15 supplies a process gas for plasma generation into the processing chamber 11. The process gas, for example, passes through a plurality of through-holes provided in the upper electrode 13. The upper electrode 13 and the stage 12 generate plasma from the process gas using the AC voltage from the AC power supply 14. The process gas includes, for example, a fluorocarbon gas. The process gas includes, for example, hydrogen (H2).

[0015] The sensor 16 detects the amount of radicals used for plasma processing in the processing chamber 11, that is, in the plasma P. The sensor 16 is, for example, a device analyzed by emission spectroscopy. The sensor 16 is, for example, an OES (Optical Emission Spectrometry) device. The sensor 16 measures the emission intensity of the products (radicals) in the processing chamber 11 during plasma etching (that is, during the generation of plasma). The emission intensity is calculated, for example, from the emission wavelength of each product. For example, when a gas containing C2F4 is used as the etching gas, CF2 radicals and C2 radicals are generated in the processing chamber 11. The sensor 16 measures the generation amount of each radical by measuring the emission intensity of each from the emission wavelengths of the CF2 radicals and the C2 radicals.

[0016] Multiple DC power supplies 17 are provided and can be controlled individually. The DC power supplies 17 are provided, for example, outside the processing chamber 11. Multiple DC power supplies 17 apply a DC voltage to the top and side walls 112 of the processing chamber 11. The DC power supplies 17 that apply a DC voltage to the top of the processing chamber 11 are electrically connected, for example, to the upper electrode 13. The power applied by the DC power supplies 17 is, for example, about 200W to about 1000W. This makes it possible to etch the deposited film D deposited in the processing chamber 11 during plasma processing of the wafer W. The deposited film D is, for example, a film formed by the deposition of reaction products of plasma processing on the upper electrode 13 and side walls 112. The deposited film D is, for example, a fluorocarbon-based deposited film. In this case, the fluorocarbon-based (C) material generated by etching the deposited film D x F y Radicals can be supplied to wafer W. As a result, while partially removing the deposited film D, the radicals generated from the deposited film D can be used for plasma treatment of wafer W.

[0017] The control unit 19 controls the operation of the plasma processing apparatus 100. For example, the control unit 19 controls the operation of the processing chamber 11, the operation of the stage 12, the on / off state and current of the AC power supply 14, the on / off state and process gas supply amount of the process gas supply unit 15, and so on.

[0018] More specifically, the control unit 19 controls multiple DC power supplies 17 to apply DC voltages independently of each other. This allows for partial removal of the deposited film D in the processing chamber 11, thereby shortening the cleaning time. More specifically, the control unit 19 controls multiple DC power supplies 17 to apply DC voltages independently of each other during plasma processing (during etching of the film to be processed on the wafer W). This allows for partial removal of the deposited film D in the processing chamber 11 during plasma processing.

[0019] Furthermore, after the plasma treatment of the wafer W is completed, the processing chamber 11 may be cleaned. In the cleaning after the plasma treatment of the wafer W, for example, a cleaning gas containing oxygen (O2) is supplied into the processing chamber 11. At this time, the control unit 19 controls the multiple DC power supplies 17 to apply a DC voltage during cleaning.

[0020] Furthermore, the control unit 19 controls a plurality of DC power supplies 17 to apply DC voltages independently to each other according to the detection results of the sensor 16. More specifically, the control unit 19 calculates the spatial distribution of radicals used for plasma processing within the processing chamber 11 based on the detection results of the sensor 16, and controls the plurality of DC power supplies 17 to apply DC voltages independently to each other according to the calculated spatial distribution. The control unit 19 calculates the spatial distribution, for example, by an Abel transform.

[0021] Furthermore, the control unit 19 controls the process gas supply unit 15. More specifically, the control unit 19 controls the process gas supply unit 15 according to the timing of the application of DC voltage by the multiple DC power supplies 17.

[0022] Next, we will explain the details of the DC power supply 17.

[0023] Figure 2 is a cross-sectional view showing an example of the configuration of the DC power supply 17 according to the first embodiment.

[0024] The multiple DC power supplies 17 include one or more upper DC power supplies 171 and one or more side wall DC power supplies 172.

[0025] The upper DC power supply 171 is located on the upper electrode 13 side, i.e., on the top plate (upper part) 111 of the processing chamber 11. One or more upper DC power supplies 171 are arranged and installed at different positions on the top plate 111 of the processing chamber 11 and can be controlled individually. One or more upper DC power supplies 171 apply a DC voltage to the upper part of the processing chamber 11. In the example shown in Figure 2, the multiple upper DC power supplies 171 include three upper DC power supplies 171C, 171M, and 171E.

[0026] The sidewall DC power supplies 172 are provided on the sidewall 112 of the processing chamber 11. One or more sidewall DC power supplies 172 are provided at different locations on the sidewall 112 of the processing chamber 11 and can be controlled individually. One or more sidewall DC power supplies 172 apply a DC voltage to electrodes (not shown) provided on the sidewall 112 of the processing chamber 11. In the example shown in Figure 2, the multiple sidewall DC power supplies 172 include two sidewall DC power supplies 172U and 172L.

[0027] The sidewall DC power supply 172 is provided along the sidewall 112 of the processing chamber 11 when viewed from the Z2 direction. The sidewall DC power supply 172U is provided, for example, at the top of the sidewall 112. The sidewall DC power supply 172L is provided, for example, at the bottom of the sidewall 112.

[0028] Figure 3 is a plan view showing an example of the configuration of the upper DC power supply 171 according to the first embodiment. Figure 3 is a view of the upper DC power supply 171 shown in Figure 2 from the Z2 direction.

[0029] The upper DC power supply 171C is located in the center of the top plate 111. In the example shown in Figure 3, the shape of the upper DC power supply 171C is approximately circular.

[0030] The upper DC power supply 171E is provided at the outer edge of the top plate 111. In the example shown in Figure 3, the shape of the upper DC power supply 171E is roughly ring-shaped.

[0031] The upper DC power supply 171M is installed between the upper DC power supply 171C and the upper DC power supply 171E. In the example shown in Figure 3, the shape of the upper DC power supply 171M is roughly ring-shaped.

[0032] As shown in Figures 2 and 3, multiple upper DC power supplies 171C, 171M, 171E and multiple side wall DC power supplies 172U, 172L are provided separately. This allows a DC voltage to be applied independently to each of the positions of the multiple upper DC power supplies 171C, 171M, 171E and the multiple side wall DC power supplies 172U, 172L.

[0033] Next, a plasma treatment method using the plasma treatment apparatus 100 will be described.

[0034] Figure 4 is a timing chart showing an example of the operation of the plasma processing apparatus 100 according to the first embodiment. The timing chart on the left in Figure 4 shows an example of operation related to the center of the wafer W. The timing charts on the center and right in Figure 4 show examples of operation related to the outer edge of the wafer W.

[0035] The horizontal axis of the graph in Figure 4 represents time. The vertical axis of the graph in Figure 4 represents the amount of radicals in the processing chamber 11 (in the plasma P) during plasma processing of the wafer W, the process gas flow rate, the thickness of the deposited film D on the inner wall of the processing chamber 11, and the DC (Direct Current) controlled DC voltage. The amount of radicals in the processing chamber 11 represents the detection result of the sensor 16. Radicals are, for example, fluorocarbon or carbon-based active species. The process gas flow rate represents the flow rate of the process gas supplied by the process gas supply unit 15. The thickness of the deposited film D on the inner wall of the processing chamber 11 shows an example of the time change in the thickness of the deposited film D. The DC controlled DC voltage represents the applied voltage of the DC power supply 17.

[0036] First, let's explain the operations related to the central part of wafer W.

[0037] First, at time t11, the control unit 19 sets the flow rate of the process gas to flow rate F1. Also, the control unit 19 sets the applied voltage (DC control) of the upper DC power supply 171C to voltage V1. Voltage V1 is, for example, 0V.

[0038] During the period from time t11 to time t12, reaction products generated by the plasma treatment accumulate in the processing chamber 11, so the thickness of the deposited film D continues to increase.

[0039] Next, at time t12, the control unit 19 changes the applied voltage to the upper DC power supply 171C from voltage V1 to voltage V2. Voltage V2 is a higher voltage than voltage V1. In other words, the control unit 19 applies a voltage to the upper DC power supply 171C. Also, the control unit 19 changes the flow rate of the process gas from flow rate F1 to flow rate F2. Flow rate F2 is a lower flow rate than flow rate F1. In other words, the control unit 19 reduces the flow rate of the process gas.

[0040] During the period from time t12 to time t13, the deposited film D is etched by the application of a DC voltage, so the thickness of the deposited film D continues to decrease. The application of the DC voltage supplies radicals from the deposited film D into the chamber (into the plasma P).

[0041] Furthermore, the amount of radicals in the processing chamber 11 remains approximately constant (a predetermined value Ac) between the period from time t11 to time t12 and the period from time t12 to time t13. This is because the flow rate of the process gas is reduced in order to suppress the increase in the amount of radicals caused by the application of a DC voltage. In other words, the control unit 19 controls the process gas supply unit 15 to reduce the amount of process gas supplied while a DC voltage is applied by multiple DC power supplies 17.

[0042] Next, at time t13, the control unit 19 changes the applied voltage of the upper DC power supply 171C back from voltage V2 to voltage V1. That is, the control unit 19 stops applying voltage from the upper DC power supply 171C. The control unit 19 also changes the flow rate of the process gas back from flow rate F2 to flow rate F1.

[0043] Subsequently, the same control is repeatedly performed during the period from time t11 to time t13. That is, the control unit 19 controls the multiple DC power supplies 17 to apply a DC voltage at a predetermined cycle.

[0044] Next, we will explain the operations related to the outer periphery of the wafer W.

[0045] In the example shown in Figure 4, the voltage applied by the upper DC power supply 171E changes during the operation (between the period from time t21 to time t27 and the period from time t31 to time t37).

[0046] In the example shown in Figure 4, the DC control for the upper DC power supply 171E during the period from time t21 to time t27 is approximately the same as the DC control for the upper DC power supply 171C during the period from time t11 to time t17. However, the amount of radicals at the outer edge of the wafer W may decrease to a predetermined value A1, which is lower than the predetermined value Ac at the center of the wafer W. This is because the environment inside the processing chamber 11 is not necessarily the same between the center and the outer edge of the wafer W, such as the plasma P not being uniform. Because the amount of radicals differs between the center and the outer edge of the wafer W, etching may not be performed uniformly, potentially reducing the in-plane uniformity of the wafer W.

[0047] Therefore, the control unit 19 increases the DC voltage applied to the upper DC power supply 171E from voltage V2 to voltage V3. If the detection result of the sensor 16 is less than or equal to a predetermined value A1, the control unit 19 controls the DC power supply 17 at the corresponding position to increase the applied DC voltage. On the other hand, if the detection result of the sensor 16 is greater than or equal to a predetermined value A2, the control unit 19 controls the DC power supply 17 at the corresponding position to decrease the applied DC voltage. The predetermined value A2 is higher than the predetermined value A1.

[0048] During the period from time t31 to time t37, the amount of decrease in the deposited film D increases as the applied DC voltage increases. Since the deposited film D is etched by the application of DC voltage, the amount of radicals supplied from the deposited film D to the plasma P increases as the applied DC voltage increases. As a result, in the example shown in Figure 4, the amount of radicals during the period from time t31 to time t37 increases from a predetermined value A1 to a predetermined value Ac. That is, the amount of radicals can be made approximately the same between the center and the outer edge of the wafer W.

[0049] Furthermore, as shown in Figure 4, the process gas flow rate was not changed between the period from time t21 to time 27 and the period from time t31 to time t37. If the process gas flow rate were increased to increase the amount of radicals at the outer edge of the wafer W, the center of the wafer W would also be affected, and the amount of radicals would increase. In contrast, by changing the voltage applied to the upper DC power supply 171E, the amount of radicals at the outer edge of the wafer W can be locally increased without affecting the center of the wafer W. That is, the control unit 19 controls the process gas supply unit 15 so that the amount of process gas supplied is approximately the same as the detection result of the sensor 16.

[0050] Furthermore, regarding in-plane uniformity, for example, if an abnormality occurs in the hole shape formed by etching on the outer periphery side, the applied voltage on the outer periphery side may be changed. This can improve in-plane uniformity.

[0051] Furthermore, in the example shown in Figure 4, the DC control of the DC power supply 17 is performed so that the amount of radicals is approximately the same between the center and the outer edge of the wafer W. However, the amount of radicals does not necessarily need to be adjusted to be the same. In this case, for example, the predetermined values ​​A1 and A2 may be different between the upper DC power supply 171C and the upper DC power supply 171E.

[0052] Furthermore, the etching selectivity ratio can sometimes be changed depending on the amount of radicals supplied from the deposited film D. Adjusting the selectivity ratio can also improve in-plane uniformity.

[0053] As described above, according to the first embodiment, the control unit 19 controls a plurality of DC power supplies 17 to apply DC voltages independently of each other. By applying DC voltage, a portion of the deposited film D in the processing chamber 11 can be removed, thereby shortening the cleaning time. Furthermore, since the plurality of DC power supplies 17 can be controlled individually, the in-plane uniformity of the wafer W can be improved.

[0054] Furthermore, during plasma processing (etching the film on the wafer W), the control unit 19 applies a DC voltage to a plurality of DC power supplies 17, thereby etching the deposited film D in the processing chamber 11 and supplying radicals from the deposited film D into the processing chamber 11 so that they can be used for plasma processing (etching the film on the wafer W). This shortens the cleaning time while utilizing the etching of the deposited film D to supply radicals to the plasma P. Note that the etching of the deposited film D by applying a DC voltage may be performed by sputtering, for example.

[0055] Furthermore, as shown in Figure 4, the flow rate of the process gas can be reduced while a DC voltage is applied. This allows for a reduction in the amount of process gas used.

[0056] Furthermore, the number and arrangement of the multiple DC power supplies 17 are not limited to the examples shown in Figures 2 and 3.

[0057] Furthermore, in the example shown in Figure 4, the time for which voltages V1 and V2 are applied is approximately the same between the upper DC power supply 171C and the upper DC power supply 171E, but the magnitude of the DC voltage is changed. However, this is not limited to this, and for example, the time for which voltages V1 and V2 are applied may be changed instead of the DC voltage. The control unit 19 controls the DC power supply 17 at the corresponding position to increase the ratio of the time for which voltage V2 is applied to the time for which voltage V1 is applied when the detection result of the sensor 16 is less than or equal to a predetermined value A1. On the other hand, the control unit 19 controls the DC power supply 17 at the corresponding position to decrease the ratio of the time for which voltage V2 is applied to the time for which voltage V1 is applied when the detection result of the sensor 16 is greater than or equal to a predetermined value A2.

[0058] (Comparative example) As a comparative example, we will describe the case where the DC power supply 17 is not provided.

[0059] The plasma processing apparatus in the comparative example operates in the same manner as shown in Figure 4, from time t11 to time t12. That is, as the plasma processing continues, the deposited film D continues to accumulate in the processing chamber 11.

[0060] Here, depending on the type of gas used as the process gas, the ease with which the deposited film D is deposited in the processing chamber 11 and the quality of the deposited film D may differ. For example, low-temperature etching is performed at a low temperature, such as below 0°C. In low-temperature etching, the type of process gas is different from that used in room-temperature etching, which is performed at room temperature, such as above 0°C. The process gas used in low-temperature etching contains less oxygen (O2) and more hydrogen (H2) compared to the gas used at room temperature. Depending on the type of gas used in the process gas, the deposited film D may be more easily formed, or the deposited film D may be more difficult to clean. As a result, the cleaning time may be even longer in low-temperature etching than in room-temperature etching. In addition, it is difficult to finely suppress the spatial distribution bias of radicals within the processing chamber 11 (in the plasma P). In this case, the in-plane uniformity of the wafer W may decrease.

[0061] In contrast, in the first embodiment, the control unit 19 controls a plurality of DC power supplies 17 to apply DC power independently to each other. This partially removes the deposited film D in the processing chamber 11 during plasma processing (etching the film to be processed on the wafer W), thereby shortening the subsequent cleaning time. Furthermore, the plurality of upper DC power supplies 171C, 171M, 171E and the plurality of side wall DC power supplies 172U, 172L can be controlled individually. This allows for adjustment of the spatial distribution of radicals within the processing chamber 11 (in the plasma P), thereby improving the in-plane uniformity of the wafer W.

[0062] (Second Embodiment) Figure 5 is a cross-sectional view showing an example of the structure of a semiconductor device according to the second embodiment. The semiconductor device in Figure 5 includes a three-dimensional flash memory and is manufactured from the wafer W of the first embodiment. Figure 5 shows two memory elements ME within the flash memory.

[0063] The semiconductor device in Figure 5 comprises a semiconductor substrate 31 and an underlying film 32. The underlying film 32 may include a conductive layer or a semiconductor layer within an insulating layer such as a silicon oxide film, and these layers may have a stacked structure. Alternatively, the underlying film 32 may not be provided. The semiconductor device in Figure 5 further comprises a first memory insulating film 33, a semiconductor layer 34, a second memory insulating film 35, a charge storage layer 36, a third memory insulating film 37, a plurality of conductive layers 38, and a plurality of insulating films 39. The semiconductor device in Figure 5 further comprises an insulating film 40.

[0064] An example of the semiconductor substrate 31 is a silicon substrate. The underlayer film 32 may be formed directly on the semiconductor substrate 31, or it may be formed on the semiconductor substrate 31 via another layer.

[0065] The first memory insulating film 33 has a cylindrical shape extending in the Z direction. An example of the first memory insulating film 33 is a silicon oxide film.

[0066] The semiconductor layer 34 is in contact with the side surface of the first memory insulating film 33. Except for the portion near the lower surface of the first memory insulating film 33, the semiconductor layer 34 has a tubular shape that extends in the Z direction around the first memory insulating film 33. An example of the semiconductor layer 34 is a polysilicon layer.

[0067] The second memory insulating film 35 is in contact with the side surface of the semiconductor layer 34. The second memory insulating film 35 has a tubular shape that extends in the Z direction around the semiconductor layer 34. An example of the second memory insulating film 35 is a silicon oxide film.

[0068] The charge storage layer 36 is in contact with the side surface of the second memory insulating film 35. The charge storage layer 36 has a tubular shape that extends in the Z direction around the second memory insulating film 35. An example of the charge storage layer 36 is a silicon nitride film.

[0069] The third memory insulating film 37 is in contact with the side surface of the charge storage layer 36. The third memory insulating film 37 has a tubular shape that extends in the Z direction around the charge storage layer 36. An example of the third memory insulating film 37 is a silicon oxynitride film.

[0070] Multiple conductive layers 38 and multiple insulating films 39 are alternately stacked on the underlying film 32 and are in contact with the side surface of the third memory insulating film 37. These conductive layers 38 and insulating films 39 surround the third memory insulating film 37. Each conductive layer 38 includes a barrier metal layer 38a and a wiring material layer 38b. Examples of barrier metal layers 38a include TiN (titanium nitride) layers, TaN (tantalum nitride) layers, and WN (tungsten nitride) layers. Examples of wiring material layers 38b include Ni (nickel) layers, Co (cobalt) layers, and W (tungsten) layers. An example of each insulating film 39 is a silicon oxide film.

[0071] The insulating film 40 divides the multiple conductive layers 38 in the Y direction. An example of the insulating film 40 is a silicon oxide film.

[0072] Figures 6A to 10B are cross-sectional views showing an example of a method for manufacturing a semiconductor device according to the second embodiment.

[0073] First, a base layer 32 is formed on a semiconductor substrate 31 (not shown), and multiple sacrificial films 41 and multiple insulating films 39 are alternately formed on the base layer 32 (Figure 6A). An example of each sacrificial film 41 is a silicon nitride film. An example of each insulating film 39 is a silicon oxide film.

[0074] Next, memory holes MH are formed by lithography and plasma etching, penetrating the sacrificial film 41 and the insulating film 39 to reach the underlying film 32 (Figure 6B). The symbol S indicates the bottom surface of the memory hole MH. This plasma etching is performed in the plasma processing apparatus 100 according to the first embodiment using the plasma processing method of the first embodiment. Although multiple memory holes MH are formed in this process, Figure 6B shows one of them.

[0075] Next, a third memory insulating film 37, a charge storage layer 36, a second memory insulating film 35, and the first layer 34a of the semiconductor layer 34 are sequentially formed on the entire surface of the semiconductor substrate 31 (Figure 7A). As a result, the third memory insulating film 37, the charge storage layer 36, the second memory insulating film 35, and the first layer 34a are sequentially formed on the side and bottom surfaces S of the memory holes MH. An example of the first layer 34a is an amorphous silicon layer.

[0076] Next, the third memory insulating film 37, the charge storage layer 36, the second memory insulating film 35, and the first layer 34a are removed from the bottom surface S of the memory hole MH by lithography and etching (Figure 7B). As a result, the bottom surface S of the memory hole MH is exposed again. Furthermore, the underlying film 32 is also etched, so that the bottom surface S of the memory hole MH is lower than the uppermost surface of the underlying film 32. This etching may be performed in the plasma processing apparatus 100 according to the first embodiment.

[0077] Next, the second layer 34b of the semiconductor layer 34 and the first memory insulating film 33 are sequentially formed on the entire surface of the semiconductor substrate 31 (Figure 8A). As a result, the second layer 34b is formed on the bottom surface S of the memory hole MH, and the second layer 34b is formed on the side surface of the memory hole MH via the third memory insulating film 37, the charge storage layer 36, the second memory insulating film 35, and the first layer 34a. Furthermore, the memory hole MH is completely filled by the first memory insulating film 33. An example of the second layer 34b is an amorphous silicon layer.

[0078] Next, the surfaces of the first memory insulating film 33 and the semiconductor layer 34 are planarized by CMP (Chemical Mechanical Polishing) (Figure 8B). Subsequently, the semiconductor substrate 31 is annealed, causing the semiconductor layer 34 to crystallize and transform into a single-crystal silicon layer.

[0079] Figures 6A to 8B show cross-sections of a single memory element ME, while Figures 9A to 10B show cross-sections of two memory elements ME.

[0080] Next, lithography and plasma etching are used to form an opening H1 that penetrates the sacrificial film 41 and the insulating film 39 and reaches the underlying film 32 (Figure 9A). In this process, the underlying film 32 is also etched, so that the bottom surface of the opening H2 is lower than the top surface of the underlying film 32. This plasma etching is performed inside the plasma processing apparatus 100 according to the first embodiment. The opening H1 is formed in the area where the insulating film 40 is to be formed in Figure 5.

[0081] Next, the sacrificial film 41 is removed by selective etching while leaving the insulating film 39 intact (Figure 9B). As a result, multiple recesses H2 are formed between the insulating films 39. Recesses H2 are also formed between the bottom insulating film 39 and the lower film 32. This etching exposes the sides of the third memory insulating film 37 within these recesses H2.

[0082] Next, a barrier metal layer 38a and a wiring material layer 38b are sequentially formed on the entire surface of the semiconductor substrate 31 (Figure 10A). As a result, a barrier metal layer 38a is formed on the upper, lower, and side surfaces of each recess H2, and a wiring material layer 38b is formed within each recess H2 via the barrier metal layer 38a. This process is carried out so that the recess H2 is completely filled by the barrier metal layer 38a and the wiring material layer 38b.

[0083] Next, the barrier metal layer 38a and the wiring material layer 38b are etched by wet etching (Figure 10B). As a result, the barrier metal layer 38a and the wiring material layer 38b outside each recess H2 are removed, and a conductive layer 38 containing the barrier metal layer 38a and the wiring material layer 38b is formed inside each recess H2.

[0084] Subsequently, an insulating film 40 is formed within the opening H1. Furthermore, various interlayer insulating films, wiring layers, plug layers, etc., are formed on the semiconductor substrate 31. In this way, the semiconductor device of this embodiment is manufactured.

[0085] As described above, in this embodiment, a semiconductor device is manufactured from a wafer W by performing plasma treatment of the wafer W using the plasma processing apparatus according to the first embodiment. Therefore, according to this embodiment, it is possible to shorten the cleaning time.

[0086] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents. [Explanation of Symbols]

[0087] 100 Plasma processing apparatus, 11 Processing chamber, 111 Top plate, 112 Side wall, 12 Stage, 13 Upper electrode, 14 AC power supply, 15 Process gas supply unit, 16 Sensor, 17 DC power supply, 171 Upper DC power supply, 171C Upper DC power supply, 171M Upper DC power supply, 171E Upper DC power supply, 172 Side wall DC power supply, 172U Side wall DC power supply, 172L Side wall DC power supply, 19 Control unit, A1 Predetermined value, A2 Predetermined value, D Deposited film, F1 Flow rate, F2 Flow rate, P Plasma, V1 Voltage, V2 Voltage, W Wafer

Claims

1. Chamber and, Multiple DC power supplies, individually controllable, are provided on the upper and side walls of the chamber. A control unit that controls a plurality of DC power supplies so as to apply DC voltages to each other independently, Equipped with, Multiple DC power supplies are, Two or more upper DC power supplies are provided at different distances from the center of the upper part of the chamber, and are capable of applying a DC voltage to the upper part of the chamber. The side wall of the chamber is provided with two or more side wall DC power supplies at different positions along the side wall of the chamber, capable of applying a DC voltage to the side wall of the chamber, A plasma processing apparatus having

2. A stage for placing a substrate, The stage further comprises an upper electrode provided above the aforementioned stage, The plasma processing apparatus according to claim 1, wherein the sidewall DC power supply is located between the stage and the upper electrode in a direction along the sidewall of the chamber.

3. The plasma processing apparatus according to claim 1, wherein at least one of the upper DC power supplies has an annular shape.

4. A gas supply unit that supplies gas into the chamber, A gas processing unit including electrodes that turns the gas into plasma, Furthermore, The plasma processing apparatus according to any one of claims 1 to 3, wherein the control unit controls a plurality of DC power supplies so as to apply DC voltages independently to each other during plasma processing.

5. The chamber further includes a sensor for detecting the amount of radicals used in plasma processing, The plasma processing apparatus according to claim 4, wherein the control unit controls a plurality of DC power supplies so as to apply DC voltages independently to each other according to the detection results of the sensors.

6. The plasma processing apparatus according to claim 5, wherein the control unit calculates the spatial distribution of radicals used for plasma processing in the chamber based on the detection results of the sensor, and controls a plurality of DC power supplies to apply DC voltages independently to each other according to the calculated spatial distribution.

7. The plasma processing apparatus according to claim 6, wherein the control unit controls the DC power supply at the corresponding position to increase the applied DC voltage when the detection result of the sensor is less than or equal to a first predetermined value, and controls the DC power supply at the corresponding position to decrease the applied DC voltage when the detection result of the sensor is greater than or equal to a second predetermined value which is higher than the first predetermined value.

8. The plasma processing apparatus according to claim 5, wherein the control unit controls the gas supply unit so that the amount of gas supplied is substantially the same as the detection result of the sensor.

9. The plasma processing apparatus according to claim 4, wherein the control unit controls the gas supply unit according to the timing of the application of DC voltages from the plurality of DC power supplies.

10. The plasma processing apparatus according to claim 9, wherein the control unit controls the gas supply unit to reduce the amount of gas supplied while a DC voltage is applied by a plurality of DC power supplies.

11. The plasma processing apparatus according to claim 4, wherein the control unit controls a plurality of DC power supplies to apply DC at a predetermined period.

12. The plasma processing apparatus according to claim 4, wherein the gas includes a fluorocarbon gas.

13. A plasma processing method using a plasma processing apparatus comprising a chamber, a plurality of individually controllable DC power supplies provided on the upper and side walls of the chamber, and a control unit that controls the plurality of DC power supplies to apply DC voltages independently to each other, wherein During plasma processing, the deposited film in the chamber is etched by applying a DC voltage to multiple DC power supplies. It is equipped with the following: Multiple DC power supplies are, Two or more upper DC power supplies are provided at different distances from the center of the upper part of the chamber, and are capable of applying a DC voltage to the upper part of the chamber. The side wall of the chamber is provided with two or more side wall DC power supplies at different positions along the side wall of the chamber, capable of applying a DC voltage to the side wall of the chamber, A plasma treatment method having the following characteristics.

14. A method for manufacturing a semiconductor device, comprising a plasma processing apparatus that etches a film to be processed formed on a wafer, the apparatus comprising: a chamber for housing a wafer; a plurality of individually controllable DC power supplies provided on the upper and side walls of the chamber; and a control unit that controls the plurality of DC power supplies to apply DC voltages independently to each other, wherein the apparatus etches a film to be processed formed on a wafer, During the etching of the workpiece, a DC voltage is applied to a plurality of DC power supplies to etch the deposited film in the chamber. It is equipped with the following: Multiple DC power supplies are, Two or more upper DC power supplies are provided at different distances from the center of the upper part of the chamber, and are capable of applying a DC voltage to the upper part of the chamber. The side wall of the chamber is provided with two or more side wall DC power supplies at different positions along the side wall of the chamber, capable of applying a DC voltage to the side wall of the chamber, A method for manufacturing a semiconductor device having the following characteristics.

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