Semiconductor equipment

Abstract

To provide a semiconductor device with excellent electric characteristics, a semiconductor device capable of high voltage driving, and a semiconductor device capable of large current flow.SOLUTION: A semiconductor device includes a semiconductor layer 108, a first insulating layer 110, a second insulating layer 116, a metal oxide layer 114, a conductive layer 112, and an insulating region 115. The metal oxide layer exists between the first insulating layer and the conductive layer. The insulating region is adjacent to the metal oxide layer and exists between the first insulating layer and the conductive layer. The semiconductor layer includes a region 108C that is in contact with the first insulating layer and overlaps with the metal oxide layer and the conductive layer through the first insulating layer, a region 108L1 that is in contact with the first insulating layer and overlaps with the insulating region and the conductive layer through the first insulating layer, a region 108L2 that is in contact with the first insulating layer, and a region 108N that is in contact with the second insulating layer. The insulating region exhibits the dielectric constant different from that of the first insulating layer.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] One aspect of the present invention relates to a semiconductor device and a method of manufacturing the same. One aspect of the present invention relates to a display device.

[0002] Note that one aspect of the present invention is not limited to the above technical field. Examples of the technical field of one aspect of the present invention disclosed in this specification and the like include a semiconductor device, a display device, a light-emitting device, a power storage device, a storage device, an electronic device, a lighting device, an input device, an input / output device, a driving method thereof, or a manufacturing method thereof. The semiconductor device refers to all devices that can function by utilizing semiconductor characteristics.

Background Art

[0003] As a semiconductor material applicable to a transistor, an oxide semiconductor using a metal oxide has attracted attention. For example, in Patent Document 1, a plurality of oxide semiconductor layers are stacked, and among the plurality of oxide semiconductor layers, an oxide semiconductor layer serving as a channel contains indium and gallium, and by making the ratio of indium larger than the ratio of gallium, a semiconductor device with enhanced field-effect mobility (sometimes simply referred to as mobility or μFE) is disclosed.

[0004] Since the metal oxide that can be used for the semiconductor layer can be formed using a sputtering method or the like, it can be used for the semiconductor layer of a transistor constituting a large display device. In addition, since part of the production equipment for transistors using polycrystalline silicon or amorphous silicon can be improved and utilized, capital investment can be suppressed. Further, a transistor using a metal oxide has a higher field-effect mobility than when using amorphous silicon, so a high-performance display device provided with a driving circuit can be realized.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

[0006] One aspect of the present invention aims to provide a semiconductor device with good electrical characteristics. Another aspect of the present invention aims to provide a semiconductor device capable of high-voltage driving. Another aspect of the present invention aims to provide a semiconductor device capable of carrying a large current. Another aspect of the present invention aims to provide a highly reliable semiconductor device.

[0007] Furthermore, the description of these problems does not preclude the existence of other problems. Moreover, one aspect of the present invention does not need to solve all of these problems. Other problems can be identified from the description in the specification, drawings, claims, etc. [Means for solving the problem]

[0008] One aspect of the present invention is a semiconductor device having a semiconductor layer, a first insulating layer, a second insulating layer, a metal oxide layer, a conductive layer, and an insulating region. The metal oxide layer is located between the first insulating layer and the conductive layer. The insulating region is adjacent to the metal oxide layer and located between the first insulating layer and the conductive layer. The semiconductor layer has a first region, a second region, a third region, and a fourth region. The first region is in contact with the first insulating layer and overlaps with the metal oxide layer and the conductive layer via the first insulating layer. The second region is in contact with the first insulating layer and overlaps with the insulating region and the conductive layer via the first insulating layer. The third region is in contact with the first insulating layer. The fourth region is in contact with the second insulating layer. Furthermore, the insulating region exhibits a different dielectric constant from the first insulating layer.

[0009] Furthermore, in the above, in a plan view, it is preferable that the edge of the metal oxide layer is located inside the edge of the conductive layer. Also, in a plan view, it is preferable that the edge of the conductive layer is located inside the edge of the first insulating layer.

[0010] Furthermore, it is preferable that the first insulating layer, the metal oxide layer, and the conductive layer are processed using the same resist mask.

[0011] Furthermore, in the above, it is preferable that the insulating region includes air gaps.

[0012] Furthermore, in the above, it is preferable that the insulating region includes a part of the second insulating layer. In this case, it is more preferable that the second insulating layer includes a nitride.

[0013] Furthermore, in the above, among the first, second, third, and fourth regions, it is preferable that the first region has the lowest carrier concentration and the fourth region has the highest carrier concentration.

[0014] Furthermore, in the above, among the first, second, third, and fourth regions, it is preferable that the first region has the lowest hydrogen concentration and the fourth region has the highest hydrogen concentration.

[0015] Furthermore, it is preferable that the above also includes a third insulating layer and a fourth insulating layer. In this case, it is preferable that the third insulating layer has a region that overlaps with the first insulating layer via the semiconductor layer, and the fourth insulating layer has a region that overlaps with the semiconductor layer via the third insulating layer. It is also preferable that the third insulating layer contains an oxide, and the fourth insulating layer contains a nitride.

[0016] Furthermore, in the above, it is preferable that the fourth insulating layer has a portion that is in contact with the second insulating layer in a region that does not overlap with the semiconductor layer. [Effects of the Invention]

[0017] According to one aspect of the present invention, a semiconductor device with good electrical characteristics can be provided. Alternatively, a semiconductor device capable of high-voltage driving can be provided. Alternatively, a semiconductor device capable of carrying a large current can be provided. Alternatively, a highly reliable semiconductor device can be provided.

[0018] Furthermore, the description of these effects does not preclude the existence of other effects. Moreover, one aspect of the present invention does not necessarily have to possess all of these effects. Other effects can be extracted from the description in the specification, drawings, claims, etc. [Brief explanation of the drawing]

[0019] [Figure 1] Figures 1A to 1C show examples of semiconductor device configurations. [Figure 2] Figures 2A to 2C show examples of semiconductor device configurations. [Figure 3] Figures 3A and 3B show examples of semiconductor device configurations. [Figure 4] Figures 4A and 4B show examples of semiconductor device configurations. [Figure 5] Figures 5A and 5B show examples of semiconductor device configurations. [Figure 6] Figures 6A to 6C show examples of semiconductor device configurations. [Figure 7] Figures 7A and 7B show examples of semiconductor device configurations. [Figure 8] Figures 8A and 8B show examples of semiconductor device configurations. [Figure 9] Figures 9A to 9F illustrate examples of methods for manufacturing semiconductor devices. [Figure 10] Figures 10A to 10E illustrate examples of methods for manufacturing semiconductor devices. [Figure 11] Figures 11A to 11C are top views of the display device. [Figure 12] Figure 12 is a cross-sectional view of the display device. [Figure 13] Figure 13 is a cross-sectional view of the display device. [Figure 14] Figure 14 is a cross-sectional view of the display device. [Figure 15] Figure 15 is a cross-sectional view of the display device. [Figure 16]Figure 16A is a block diagram of the display device. Figures 16B and 16C are circuit diagrams of the display device. [Figure 17] Figures 17A, 17C, and 17D are circuit diagrams of the display device. Figure 17B is a timing chart. [Figure 18] Figures 18A and 18B show examples of the display module configuration. [Figure 19] Figures 19A and 19B show examples of electronic device configurations. [Figure 20] Figures 20A to 20E show examples of electronic device configurations. [Figure 21] Figures 21A to 21G show examples of electronic device configurations. [Figure 22] Figures 22A to 22D show examples of electronic device configurations. [Figure 23] Figures 23A and 23B show the relationship between carrier concentration and sheet resistance. [Figure 24] Figure 24 shows the relationship between carrier concentration and Fermi level. [Modes for carrying out the invention]

[0020] The embodiments will be described below with reference to the drawings. However, it will be readily apparent to those skilled in the art that the embodiments can be implemented in many different ways, and their form and details can be modified in various ways without departing from the spirit and scope thereof. Accordingly, the present invention shall not be construed as being limited to the contents of the following embodiments.

[0021] Furthermore, in the figures described herein, the size of each component, the thickness of the layers, or the area may be exaggerated for clarity.

[0022] Furthermore, the ordinal numbers "first," "second," and "third" used in this specification are added to avoid confusion of constituent elements and do not imply any numerical limitation.

[0023] Furthermore, in this specification, terms indicating placement, such as "above" and "below," are used for convenience to explain the positional relationships between components with reference to the drawings. The positional relationships between components change as appropriate depending on the direction in which each component is depicted. Therefore, the terms described in this specification are not limited to those used in this specification and can be appropriately rephrased depending on the situation.

[0024] Furthermore, in this specification, the source and drain functions of a transistor may be reversed when transistors with different polarities are used or when the direction of current changes during circuit operation. For this reason, the terms source and drain may be used interchangeably.

[0025] In this specification, the channel length direction of a transistor refers to one of the directions parallel to the straight line connecting the source region and the drain region by the shortest distance. In other words, the channel length direction corresponds to one of the directions of current flowing through the semiconductor layer when the transistor is in the ON state. The channel width direction refers to the direction perpendicular to the channel length direction. Depending on the structure and shape of the transistor, the channel length direction and channel width direction may not be uniquely determined.

[0026] Furthermore, in this specification, "electrically connected" includes cases where connections are made via "something that has some kind of electrical function." Here, "something that has some kind of electrical function" is not particularly limited as long as it enables the exchange of electrical signals between the connected objects. For example, "something that has some kind of electrical function" includes electrodes and wiring, as well as switching elements such as transistors, resistive elements, inductors, capacitors, and other elements with various functions.

[0027] Furthermore, in this specification, the terms "film" and "layer" are interchangeable. For example, the terms "conductive layer" and "insulating layer" can sometimes be replaced with the terms "conductive film" and "insulating film."

[0028] Furthermore, unless otherwise specified in this specification, off-current refers to the drain current when the transistor is in the off state (also called the non-conducting state or cutoff state). Unless otherwise specified, the off state in an n-channel transistor is defined as the voltage V between the gate and source. gs The threshold voltage V th Lower than (in p-channel transistors, V th This refers to a state that is higher than [a certain value].

[0029] In this specification, a display panel, which is one form of a display device, has the function of displaying (outputting) images or the like on its display surface. Therefore, a display panel is one form of an output device.

[0030] Furthermore, in this specification, a display panel on which a connector such as an FPC (Flexible Printed Circuit) or TCP (Tape Carrier Package) is attached, or on which an IC is mounted on the board using a COG (Chip On Glass) method, may be referred to as a display panel module, display module, or simply a display panel.

[0031] In this specification, a touch panel, which is one form of a display device, has the function of displaying images, etc., on its display surface, and the function of a touch sensor that detects when a detectable object such as a finger or stylus touches, presses, or approaches the display surface. Therefore, a touch panel is one form of an input / output device.

[0032] A touch panel can also be called, for example, a display panel (or display device) with a touch sensor, or a display panel (or display device) with touch sensor functionality. A touch panel can also have a configuration comprising a display panel and a touch sensor panel. Alternatively, the display panel may have a touch sensor function located inside or on its surface.

[0033] Furthermore, in this specification, a touch panel circuit board with connectors and ICs mounted on it may be referred to as a touch panel module, display module, or simply a touch panel.

[0034] (Embodiment 1) This embodiment describes a semiconductor device according to one aspect of the present invention. Below, as an example of a semiconductor device, an example of the configuration of a transistor and an example of its manufacturing method will be described.

[0035] One aspect of the present invention is a transistor having a semiconductor layer on which a channel is formed on a surface to be formed, a gate insulating layer (also referred to as a first insulating layer) on the semiconductor layer, and a conductive layer on the gate insulating layer that functions as a gate electrode. Preferably, the semiconductor layer is composed of a metal oxide (hereinafter also referred to as an oxide semiconductor) that exhibits semiconductor properties.

[0036] In another aspect of the present invention, a metal oxide layer is provided between the first insulating layer and the conductive layer. Preferably, the metal oxide layer is conductive, and in this case, the metal oxide layer functions as part of the gate electrode.

[0037] Furthermore, it is preferable that the first insulating layer, conductive layer, and metal oxide layer are processed such that a portion of their edges are located on the semiconductor layer. In particular, it is preferable that the first insulating layer, conductive layer, and metal oxide layer are processed using the same resist mask.

[0038] Furthermore, it is preferable that the conductive layer is processed so that its edges are located inside the edges of the first insulating layer. Similarly, it is preferable that the metal oxide layer is processed so that its edges are located inside the conductive layer. In other words, in a plan view, it is preferable that the conductive layer is located inside the edges (contours) of the first insulating layer, and that the metal oxide layer is located inside the edges (contours) of the conductive layer.

[0039] Furthermore, in one aspect of the present invention, an insulating region is adjacent to the metal oxide layer so as to surround it. This insulating region is a region sandwiched between the first insulating layer and the conductive layer, and has insulating properties.

[0040] The semiconductor layer includes a first region where a channel is formed, a pair of second regions flanking the first region, a pair of third regions flanking the first and second regions, and a pair of fourth regions flanking the first to third regions and functioning as a source region and a drain region.

[0041] Here, the first region is the region that is in contact with the first insulating layer and overlaps with the metal oxide layer and the conductive layer. The second region is the region that is in contact with the first insulating layer and overlaps with the insulating region and the conductive layer. The third region is the region that is in contact with the first insulating layer and does not overlap with the conductive layer, the metal oxide layer, or the insulating region. The fourth region is the region located outside the edge of the first insulating layer.

[0042] Furthermore, the fourth region is preferably in contact with a second insulating layer that functions as a protective layer. In this case, the second insulating layer is preferably capable of supplying carriers to the fourth region of the semiconductor layer during film formation.

[0043] Of the four regions in a semiconductor layer, the first region, which functions as a channel-forming region, has the lowest carrier concentration. The fourth region, which functions as both a source and drain region, has the highest carrier concentration. The second and third regions can function as buffer regions to prevent carrier sources contained in the fourth region from diffusing into the first region, which is the channel-forming region. By providing the second and third regions, the carrier concentration in the first region can be made extremely low. The second and third regions may also function as LDD (Lightly Doped Drain) regions.

[0044] Furthermore, the second region overlaps with the conductive layer that functions as the gate electrode, separated by an insulating region, and can therefore also be called the overlap region (Lov-LDD region). On the other hand, the third region does not overlap with the conductive layer and can therefore also be called the offset region (Loff-LDD region).

[0045] Furthermore, since the second overlapping region is superimposed on the gate electrode with an insulating region in between, the electric field applied from the gate electrode to the second region can be mitigated by the insulating region. This makes it possible to create a transistor with high reliability even when driven at high voltages.

[0046] Furthermore, it is preferable that the insulating region exhibits a different dielectric constant from that of the first insulating layer. For example, the insulating region may include air gaps (spaces), or it may be a region where a part of the second insulating layer, which functions as a protective layer, is provided. Alternatively, the insulating region may be a region where air gaps and a part of the second insulating layer are mixed. By providing such an insulating region, the electric field applied from the gate electrode to the second region of the semiconductor layer can be effectively mitigated.

[0047] Thus, in one aspect of the present invention, since overlapping regions and offset regions are provided between the channel formation region and the source and drain regions of the semiconductor layer, a high voltage can be applied to allow a large current to flow, and a highly reliable transistor can be realized.

[0048] The following sections will explain more specific examples with reference to the diagrams.

[0049] [Configuration Example 1] Figure 1A is a top view of transistor 100, Figure 1B corresponds to a cross-sectional view of the section along the dashed-dotted line A1-A2 shown in Figure 1A, and Figure 1C corresponds to a cross-sectional view of the section along the dashed-dotted line B1-B2 shown in Figure 1A. Note that in Figure 1A, some components of transistor 100 (such as the protective insulating layer) are omitted from the illustration. The direction of the dashed-dotted line A1-A2 corresponds to the channel length direction, and the direction of the dashed-dotted line B1-B2 corresponds to the channel width direction. Furthermore, in subsequent drawings, the top view of the transistor will also be shown with some components omitted, similar to Figure 1A.

[0050] The transistor 100 is provided on a substrate 102 and has an insulating layer 103, a semiconductor layer 108, an insulating layer 110, a metal oxide layer 114, a conductive layer 112, an insulating layer 116, an insulating layer 118, etc. The island-shaped semiconductor layer 108 is provided on the insulating layer 103. The insulating layer 110 is provided covering a part of the upper surface of the insulating layer 103 and a part of the upper surface of the semiconductor layer 108. The metal oxide layer 114 and the conductive layer 112 are stacked in this order on the insulating layer 110 and have a portion that overlaps with the semiconductor layer 108. The insulating layer 116 is provided covering the upper and side surfaces of the conductive layer 112, the upper and side surfaces of the insulating layer 110, the upper and side surfaces of the semiconductor layer 108, and the upper surface of the insulating layer 103. The insulating layer 118 is provided covering the insulating layer 116.

[0051] Figure 1A shows the outlines of the metal oxide layer 114 and the insulating layer 110 with dashed lines. The metal oxide layer 114 and the conductive layer 112 are positioned inward from the edge of the insulating layer 110 in a plan view. The metal oxide layer 114 is also positioned inward from the edge of the conductive layer 112 in a plan view. Here, it is preferable that the conductive layer 112, the metal oxide layer 114, and the insulating layer 110 are processed using the same resist mask.

[0052] A portion of the conductive layer 112 functions as a gate electrode. A portion of the insulating layer 110 functions as a gate insulating layer. The transistor 100 is a so-called top-gate type transistor in which the gate electrode is provided on the semiconductor layer 108.

[0053] The insulating layer 103 preferably has a laminated structure in which an insulating film 103b and an insulating film 103a are laminated from the substrate 102 side. In this case, the insulating film 103b located on the substrate 102 side preferably functions as a barrier film that prevents the diffusion of impurities contained in the substrate 102. On the other hand, the insulating film 103a in contact with the semiconductor layer 108 preferably contains an oxide.

[0054] More specifically, insulating film 103a preferably contains oxides such as silicon oxide and silicon oxide nitride. On the other hand, insulating film 103b preferably contains nitrides such as silicon nitride, silicon oxide nitride, aluminum oxide nitride, and aluminum nitride. Alternatively, insulating film 103b may contain metal oxides such as aluminum oxide, hafnium oxide, and hafnium aluminate.

[0055] Furthermore, as shown in Figures 1A and 1B, the transistor 100 may have conductive layers 120a and 120b on the insulating layer 118. Conductive layers 120a and 120b function as source electrodes or drain electrodes. Conductive layers 120a and 120b are electrically connected to a region 108N of the semiconductor layer 108 via openings 141a or 141b provided in the insulating layer 118 and insulating layer 116, respectively.

[0056] The metal oxide layer 114, located between the insulating layer 110 and the conductive layer 112, functions as a barrier film that prevents oxygen contained in the insulating layer 110 from diffusing to the conductive layer 112. Furthermore, the metal oxide layer 114 also functions as a barrier film that prevents hydrogen and water contained in the conductive layer 112 from diffusing to the insulating layer 110. It is preferable that the metal oxide layer 114 be made of a material that is less permeable to oxygen and hydrogen than, for example, the insulating layer 110.

[0057] The metal oxide layer 114 prevents oxygen from diffusing from the insulating layer 110 to the conductive layer 112, even when the conductive layer 112 uses a metal material that easily attracts oxygen, such as aluminum or copper. Furthermore, even when the conductive layer 112 contains hydrogen, it prevents hydrogen from diffusing from the conductive layer 112 to the semiconductor layer 108 via the insulating layer 110. As a result, the carrier concentration in the channel formation region of the semiconductor layer 108 can be kept extremely low.

[0058] Furthermore, the metal oxide layer 114 has the function of supplying oxygen to the insulating layer 110. In addition, if a conductive film containing an easily oxidized metal or alloy is used as the conductive layer 112, the metal oxide layer 114 can also function as a barrier layer to prevent the conductive layer 112 from being oxidized by oxygen in the insulating layer 110.

[0059] The metal oxide layer 114 can be an insulating material or a conductive material. If the metal oxide layer 114 is insulating, it functions as part of the gate insulating layer. On the other hand, if the metal oxide layer 114 is conductive, it functions as part of the gate electrode. In particular, in one embodiment of the present invention, it is preferable that the metal oxide layer 114 is conductive and functions as part of the gate electrode.

[0060] As the metal oxide layer 114, conductive oxides such as indium oxide, indium tin oxide (ITO), silicon-containing indium tin oxide (ITSO), or indium zinc oxide can also be used. Conductive oxides containing indium are particularly preferred due to their high conductivity.

[0061] Furthermore, it is preferable to use an oxide material containing one or more of the same elements as the semiconductor layer 108 as the metal oxide layer 114. In particular, it is preferable to use an oxide semiconductor material applicable to the semiconductor layer 108. In this case, it is preferable to use a metal oxide film formed using the same sputtering target as the semiconductor layer 108 as the metal oxide layer 114, as this allows for the commonality of the apparatus.

[0062] Furthermore, it is preferable to form the metal oxide layer 114 using a sputtering apparatus. For example, when forming an oxide film using a sputtering apparatus, forming it in an atmosphere containing oxygen gas allows for the appropriate addition of oxygen to the insulating layer 110 and the semiconductor layer 108.

[0063] Furthermore, when using an insulating material as the metal oxide layer 114, it is preferable to use an insulating material with a higher dielectric constant than silicon oxide. In particular, using an aluminum oxide film, a hafnium oxide film, or a hafnium aluminate film is preferable because it can reduce the driving voltage.

[0064] The semiconductor layer 108 is composed of a metal oxide exhibiting semiconductor properties (hereinafter also referred to as an oxide semiconductor). Preferably, the semiconductor layer 108 contains at least indium and oxygen. By including an indium oxide in the semiconductor layer 108, the carrier mobility can be increased, making it possible to realize a transistor that can carry a larger current than amorphous silicon, for example.

[0065] As shown in Figure 1B, the semiconductor layer 108 includes a region 108C that functions as a channel formation region, a pair of regions 108L1 that sandwich region 108C, a pair of regions 108L2 that sandwich region 108C and region L1, and a pair of regions 108N that sandwich region 108C, region 108L1 and region 108L2 and function as a source region and a drain region.

[0066] Regions 108C, 108L1, and 108L2 each have their upper surfaces in contact with the insulating layer 110. Region 108C is a region that overlaps with the insulating layer 110, the metal oxide layer 114, and the conductive layer 112. Region 108L1 is a region that overlaps with the insulating layer 110, the insulating region 115, and the conductive layer 112. Region 108L2 is a region that overlaps with the insulating layer 110 but does not overlap with the conductive layer 112.

[0067] Region 108C functions as a channel-forming region. Here, if the metal oxide layer 114 has a conductive layer, it functions as part of the gate electrode, and an electric field is applied from the gate electrode to region 108C via the insulating layer 110, which functions as a gate insulating layer, and a channel is formed.

[0068] Region 108L1 functions as a buffer region to mitigate the drain electric field. Here, since region 108L1 is superimposed on the conductive layer 112, a channel can be formed when a gate voltage is applied to the conductive layer 112. However, since region 108L1 is superimposed on the conductive layer 112 via the insulating region 115, the electric field applied to region 108L1 is weaker than the electric field applied to region 108C. As a result, region 108L1 becomes a region with higher resistance than region 108C and functions as an LDD region to mitigate the drain electric field. Furthermore, even if, for example, the carrier concentration in region 108L1 is extremely low and similar to that of region 108C, a channel can be formed by the electric field of the conductive layer 112, so region 108L1 can function as an LDD region.

[0069] Region 108L2, like region 108L1, functions as a buffer region to mitigate the drain electric field. Since region 108L2 does not overlap with the conductive layer 112 and the metal oxide layer 114, it is a region where almost no channels are formed even when a gate voltage is applied to the conductive layer 112. It is preferable that the carrier concentration in region 108L2 is higher than that of region 108C. This allows region 108L2 to function as an LDD region.

[0070] In this way, by providing regions 108L1 and 108L2, which function as LDD regions, between region 108C, which is the channel formation region, and region 108N, which is the source region or drain region, it is possible to realize a highly reliable transistor that combines high drain breakdown voltage and high on-current.

[0071] Region 108N functions as a source region or a drain region and is the region with the lowest resistance compared to other regions of the semiconductor layer 108. Alternatively, region 108N can also be said to be the region with the highest carrier concentration, the highest oxygen defect density, or the highest impurity concentration compared to other regions of the semiconductor layer 108.

[0072] The lower the electrical resistance of region 108N, the more preferable. For example, the sheet resistance of region 108N is 1 Ω / □ or more and less than 1×10 3 Ω / □, preferably 1 Ω / □ or more and 8×10 2 Ω / □ or less. Also, the higher the electrical resistance of region 108C in the state where no channel is formed, the more preferable. For example, the sheet resistance of region 108C is 1×10 9 Ω / □ or more, preferably 5×10 9 Ω / □ or more, more preferably 1×10 10 Ω / □ or more.

[0073] The sheet resistance of region 108L2 is, for example, 1×10 3 Ω / □ or more and 1×10 9 Ω / □ or less, preferably 1×10 3 Ω / □ or more and 1×10 8 Ω / □ or less, more preferably 1×10 3 Ω / □ or more and 1×10 7 Ω / □. By setting the resistance within such a range, a transistor with good electrical characteristics and high reliability can be obtained. Note that the sheet resistance can be calculated from the resistance value. By providing such a region 108L2 between region 108N and region 108C, the source-drain breakdown voltage of transistor 100 can be increased.

[0074] Also, it is preferable that the sheet resistance of region 108L1 is equivalent to that of region 108C or lower than that of region 108C and higher than that of region 108L2.

[0075] Furthermore, it is preferable that the carrier concentration in the semiconductor layer 108 has a distribution such that it is lowest in region 108C, and increases in the order of region 108L1, region 108L2, and region 108N. By providing regions 108L1 and 108L2 between region 108C and region 108N, the carrier concentration in region 108C can be kept extremely low, even if impurities such as hydrogen diffuse from region 108N during the manufacturing process.

[0076] A lower carrier concentration is preferable in region 108C, which functions as a channel-forming region, such as 1 × 10⁻⁶. 18 cm -3 The following is preferable: 1 × 10 17 cm -3 More preferably, 1 × 10 16 cm -3 It is even more preferable that the following conditions apply: 1 × 10 13 cm -3 It is even more preferable that the following conditions apply: 1 × 10 12 cm -3 The following is even more preferable. There are no particular limitations on the lower limit of the carrier concentration in region 108C, but for example, 1 × 10 -9 cm -3 It can be done this way.

[0077] On the other hand, the carrier concentration in region 10⁸N is, for example, 5 × 10⁻⁶. 18 cm -3 Preferably 1 × 10 19 cm -3 The above is more comfortable 5x10 19 cm -3 The above can be applied. There is no particular limit to the upper limit of the carrier concentration in region 10⁸N, but for example, 5 × 10⁻⁶ 21 cm -3 , or 1 × 10 22 cm -3 It can be done in this way.

[0078] The carrier concentration in region 108L2 can be a value between that of region 108C and region 108N. For example, 1 × 10⁻⁶ 14cm -3 The above 1 x 10 20 cm -3 The value should be within the range of less than [value]. Furthermore, the carrier concentration in region 108L1 can be equivalent to or greater than that in region 108C, and lower than that in region 108L2.

[0079] Furthermore, in the semiconductor layer 108, it is preferable that region 108C is the region with the lowest hydrogen concentration and region 108N is the region with the highest hydrogen concentration. It is also preferable that the hydrogen concentration in the semiconductor layer 108 has a distribution such that region 108C has the lowest concentration, followed by regions 108L1, 108L2, and 108N in increasing order.

[0080] The width of region 108L1 can be appropriately adjusted according to the channel length (width of region 108C in the channel length direction), the voltage applied between the source and drain of transistor 100, and the voltage applied to the gate electrode. As the channel length decreases, the drain breakdown voltage decreases, so it is preferable to increase the ratio of the width of region 108L1 to the channel length. For example, the width of region 108L1 can be 5 nm or more and 10 μm or less, preferably 10 nm or more and 5 μm or less, and more preferably 20 nm or more and 3 μm or less.

[0081] Similarly, the width of region 108L2 can be appropriately adjusted according to the channel length, the source-drain distance of transistor 100, and the voltage applied to the gate electrode. For example, the width of region 108L2 can be 5 nm or more and 10 μm or less, preferably 10 nm or more and 5 μm or less, and more preferably 20 nm or more and 3 μm or less.

[0082] The insulating layer 116 is provided in contact with the upper surface of region 108N. The insulating layer 116 has the function of reducing the resistance of region 108N. As such an insulating layer 116, an insulating film can be used that can supply impurities into region 108N by heating during or after the deposition of the insulating layer 116. Alternatively, an insulating film can be used that can create oxygen vacancies in region 108N by heating during or after the deposition of the insulating layer 116.

[0083] For example, an insulating film that functions as a source for supplying impurities to region 108N can be used as the insulating layer 116. In this case, it is preferable that the insulating layer 116 is a film that releases hydrogen when heated. By forming such an insulating layer 116 in contact with the semiconductor layer 108, impurities such as hydrogen can be supplied to region 108N, thereby lowering the resistance of region 108N.

[0084] The insulating layer 116 is preferably a film formed using a deposition gas containing impurity elements such as hydrogen. Furthermore, by increasing the deposition temperature of the insulating layer 116, a large amount of impurity elements can be effectively supplied to the semiconductor layer 108. The deposition temperature of the insulating layer 116 can be, for example, 200°C to 500°C, preferably 220°C to 450°C, and more preferably 250°C to 400°C.

[0085] Furthermore, by forming the insulating layer 116 under reduced pressure and heating, the desorption of oxygen in the region 108N within the semiconductor layer 108 can be promoted. By supplying impurities such as hydrogen to the semiconductor layer 108 where many oxygen vacancies have formed, the carrier concentration in region 108N increases, making it possible to more effectively reduce the resistance of region 108N.

[0086] As the insulating layer 116, insulating films containing nitrides such as silicon nitride, silicon oxide nitride, silicon oxynitride, aluminum nitride, and aluminum oxide nitride can be suitably used. In particular, silicon nitride has blocking properties for hydrogen and oxygen, so it can prevent both the diffusion of hydrogen from the outside into the semiconductor layer and the desorption of oxygen from the semiconductor layer to the outside, thereby realizing a highly reliable transistor.

[0087] Furthermore, the insulating layer 116 may be an insulating film that has the function of attracting oxygen from the semiconductor layer 108 and creating an oxygen vacancy. In particular, it is especially preferable to use a metal nitride such as aluminum nitride for the insulating layer 116.

[0088] Furthermore, when using metal nitrides, it is preferable to use nitrides of aluminum, titanium, tantalum, tungsten, chromium, or ruthenium. In particular, it is especially preferable to include aluminum or titanium. For example, an aluminum nitride film formed by a reaction sputtering method using aluminum as the sputtering target and a nitrogen-containing gas as the film-forming gas can be made into a film that combines extremely high insulating properties with extremely high blocking properties against hydrogen and oxygen by appropriately controlling the flow rate of nitrogen gas relative to the total flow rate of the film-forming gas. Therefore, by providing such an insulating film containing a metal nitride in contact with the semiconductor layer 108, it is possible not only to reduce the resistance of the semiconductor layer 108, but also to effectively prevent oxygen from detaching from the semiconductor layer 108 and hydrogen from diffusing into the semiconductor layer 108.

[0089] When aluminum nitride is used as the metal nitride, it is preferable that the thickness of the insulating layer containing the aluminum nitride be 5 nm or more. Even with such a thin film, it is possible to achieve both high blocking properties against hydrogen and oxygen and the function of reducing the resistance of the semiconductor layer. The thickness of the insulating layer can be any thickness, but considering productivity, it is preferable to set it to 500 nm or less, preferably 200 nm or less, and more preferably 50 nm or less.

[0090] When an aluminum nitride film is used for the insulating layer 116, the composition formula is AlN x It is preferable to use a film that satisfies the condition (where x is a real number greater than 0 and less than or equal to 2, preferably a real number greater than 0.5 and less than or equal to 1.5). This makes it possible to create a film with excellent insulating properties and excellent thermal conductivity, thereby improving the heat dissipation of heat generated when the transistor 100 is driven.

[0091] Alternatively, an aluminum titanium nitride film, a titanium nitride film, or the like can be used as the insulating layer 116.

[0092] By providing such an insulating layer 116 in contact with region 108N, the insulating layer 116 can draw oxygen from region 108N, thereby forming oxygen vacancies in region 108N. Furthermore, by performing a heat treatment after forming such an insulating layer 116, more oxygen vacancies can be formed in region 108N, thereby promoting lower resistance. In addition, if a film containing a metal oxide is used for the insulating layer 116, the insulating layer 116 may draw oxygen from the semiconductor layer 108, resulting in the formation of a layer containing an oxide of the metal element (e.g., aluminum) contained in the insulating layer 116 between the insulating layer 116 and region 108N.

[0093] In this case, when an indium-containing metal oxide film is used as the semiconductor layer 108, a region where indium oxide is deposited, or a region with a high indium concentration, may be formed near the interface of region 108N on the insulating layer 116 side. This makes it possible to form a region 108N with extremely low resistance. The existence of such a region can sometimes be observed by analytical methods such as X-ray photoelectron spectroscopy (XPS).

[0094] The insulating layer 118 functions as a protective layer to protect the transistor 100. As the insulating layer 110, an inorganic insulating material such as an oxide or nitride can be used. More specifically, inorganic insulating materials such as silicon oxide, silicon oxide-nitride, silicon nitride, silicon oxide nitride, aluminum oxide, aluminum oxide-nitride, aluminum nitride, hafnium oxide, and hafnium aluminate can be used.

[0095] The composition of the semiconductor layer 108 will now be described. Preferably, the semiconductor layer 108 contains at least indium and a metal oxide containing oxygen. In addition, the semiconductor layer 108 may also contain zinc. Furthermore, the semiconductor layer 108 may contain gallium.

[0096] For example, the semiconductor layer 108 preferably contains indium, M (where M is one or more selected from gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium), and zinc. In particular, it is preferable that M is one or more selected from aluminum, gallium, yttrium, or tin.

[0097] Typical semiconductor layers 108 can include indium oxide, indium zinc oxide (In-Zn oxide), and indium gallium zinc oxide (In-Ga-Zn oxide, also known as IGZO). Indium tin oxide (In-Sn oxide) or silicon-containing indium tin oxide can also be used. In particular, it is preferable to use an oxide containing indium, gallium, and zinc as the semiconductor layer 108.

[0098] The semiconductor layer 108 may be a laminated structure in which layers with different compositions, layers with different crystallinity, or layers with different impurity concentrations are stacked.

[0099] The composition and crystallinity of the semiconductor layer 108 significantly affect the electrical characteristics and reliability of the transistor 100. For example, increasing the indium content in the semiconductor layer 108 improves carrier mobility, making it possible to realize a transistor with high field-effect mobility.

[0100] It is preferable to use a crystalline metal oxide film for the semiconductor layer 108. For example, a metal oxide film having a CAAC (c-axis aligned crystal) structure, polycrystalline structure, microcrystalline structure, etc., as described later, can be used. By using a crystalline metal oxide film for the semiconductor layer 108, the defect level density in the semiconductor layer 108 can be reduced, and a highly reliable semiconductor device can be realized.

[0101] The higher the crystallinity of the semiconductor layer 108, the lower the defect level density in the film. On the other hand, by using a metal oxide film with low crystallinity, it is possible to realize a transistor that can carry a large current.

[0102] When depositing metal oxide films by sputtering, the higher the substrate temperature (stage temperature) during deposition, the more crystalline the metal oxide film can be deposited. Furthermore, the higher the ratio of oxygen gas flow rate to the total deposition gas flow rate (also called the oxygen flow rate ratio), the more crystalline the metal oxide film can be deposited.

[0103] Figure 2A shows a magnified view of region P in Figure 1B.

[0104] Figure 2A shows an example where the insulating region 115 contains voids (spaces). In this case, the insulating region 115 may be in a vacuum or reduced pressure state, or it may be filled with gas. Typical gases contained in the insulating region 115 are air, but it may also contain inert gases such as nitrogen or noble gases, or deposition gases used during the deposition of the insulating layer 116 or insulating layer 118.

[0105] The insulating region 115, which includes voids as shown in Figure 2A, can be formed by, for example, using a method with relatively low step coverage as the film formation method for the insulating layer 116. This method ensures that the film is not formed on the underside of the protruding portion of the conductive layer 112, thus forming the insulating region 115 as shown in Figure 2A.

[0106] Figure 2B shows an example in which the insulating region 115 includes a portion of the insulating layer 116 and a void. For example, by using a film deposition method with relatively high step coverage as the film deposition method for the insulating layer 116, a portion of the insulating layer 116 can be formed on the underside of the protruding portion of the conductive layer 112, thereby forming the insulating region 115 as shown in Figure 2B.

[0107] Figure 2C shows an example in which the insulating region 115 is filled with a portion of the insulating layer 116. For example, by using a film deposition method with extremely high step coverage properties as the film deposition method for the insulating layer 116, a portion of the insulating layer 116 is formed to fill the underside of the protruding portion of the conductive layer 112, thereby forming the insulating region 115 as shown in Figure 2C.

[0108] Here, the insulating region 115 functions as part of the gate insulating layer for region 108L1. In other words, transistor 100 can also be described as a transistor in which a first channel formation region (i.e., region 108C) with insulating layer 110 as the gate insulating layer and a second channel formation region (i.e., region 108L1) with a laminated structure of insulating layer 110 and insulating region 115 as the gate insulating layer are connected in series. In other words, region 108L1 can also be described as a second channel formation region with a gate insulating layer thicker than that of the first channel formation region.

[0109] For example, in the configuration shown in Figure 2A or Figure 2B, the insulating region 115 contains air gaps, so the insulating region 115 exhibits a different dielectric constant than the insulating layer 110. Also, as shown in Figure 2C, if the insulating region 115 is filled with a portion of the insulating layer 116, the dielectric constants of the insulating region 115 and the insulating layer 110 can be made different by using an insulating film made of a different material or formed under different conditions for the insulating layer 116 than for the insulating layer 110.

[0110] Thus, it is preferable that the insulating region 115 exhibits a different dielectric constant than the insulating layer 110. When the insulating region 115 exhibits a higher dielectric constant than the insulating layer 110, the electric field applied from the conductive layer 112 to region 108L1 is strengthened, making it easier to lower the resistance of region 108L1 compared to when they exhibit the same dielectric constant, and thus increasing the current that the transistor 100 can carry. On the other hand, when the insulating region 115 exhibits a lower dielectric constant than the insulating layer 110, the electric field is weakened, suppressing the reduction in resistance of region 108L1 compared to when they exhibit the same dielectric constant, and thus increasing the drain breakdown voltage of the transistor 100.

[0111] Figure 3A shows an enlarged view of region Q in Figure 1B. As shown in Figure 3A, the insulating layer 116 is provided covering the upper and side surfaces of region 108N of the semiconductor layer 108. In addition, the insulating layer 116 has a portion that is in contact with the insulating film 103a of the insulating layer 103 in the region where the semiconductor layer 108 is not provided.

[0112] Furthermore, Figure 3B shows an enlarged view of region R in Figure 1C. As shown in Figure 3B, an insulating region 115 is formed between the conductive layer 112 and the insulating layer 110 in the channel width direction of the transistor 100. In other words, the insulating region 115 can be said to be provided along the contour (side surface) of the metal oxide layer 114, surrounding the metal oxide layer 114. It can also be said that the metal oxide layer 114 is provided in the region surrounded by the insulating layer 110, the conductive layer 112, and the insulating region 115.

[0113] Furthermore, as shown in Figures 2A to 2C and Figure 3B, the insulating layer 110 may be thinner in areas that do not overlap with the conductive layer 112 compared to areas that overlap with the conductive layer 112. For example, this shape can occur when a portion of the insulating layer 110 is etched simultaneously during the etching process for forming the conductive layer 112. In addition, depending on the processing conditions of the conductive layer 112 and the metal oxide layer 114, the insulating layer 110 may not become thinner.

[0114] [Differentiation] Figures 4A and 4B show cross-sectional views of a transistor that differs in some respects from the configuration example 1 described above. Figure 1A can be used as the top view.

[0115] Figure 5A shows an enlarged view of region Q' in Figure 4A, and Figure 5B shows an enlarged view of region R' in Figure 4B.

[0116] The transistor illustrated here differs from Configuration Example 1 mainly in that the insulating film 103a of the insulating layer 103 is processed so that its upper surface shape is roughly the same as that of the semiconductor layer 108.

[0117] Furthermore, in areas where the semiconductor layer 108 is not provided, the insulating layer 116 and the insulating film 103b are provided in contact. This allows the transistor to be sealed around the periphery by the insulating layer 116 and the insulating film 103b. Therefore, a configuration can be achieved that makes it difficult for impurities such as water and hydrogen to enter from the outside, thus enabling a highly reliable transistor.

[0118] [Configuration Example 2] The following describes a transistor configuration example that differs in some aspects from the above configuration example. Note that in the following, explanations of parts that overlap with Configuration Example 1 may be omitted. Also, in the following diagrams, parts having the same function as the above configuration example may use the same hatching pattern and may not be labeled.

[0119] Figure 6A is a top view of transistor 100A, Figure 6B is a cross-sectional view of transistor 100A in the channel length direction, and Figure 6C is a cross-sectional view of transistor 100A in the channel width direction.

[0120] Transistor 100A differs from Configuration Example 1 mainly in that it has a conductive layer 106 between the substrate 102 and the insulating layer 103. The conductive layer 106 has at least a region 108C of the semiconductor layer 108 and a region that overlaps with the conductive layer 112. Here, an example is shown in which the conductive layer 106 overlaps with a portion of regions 108L1, 108L2, and 108N.

[0121] In transistor 100A, the conductive layer 106 functions as the first gate electrode (also called the bottom gate electrode), and the conductive layer 112 functions as the second gate electrode (also called the top gate electrode). In addition, a portion of the insulating layer 103 functions as the first gate insulating layer, and a portion of the insulating layer 110 functions as the second gate insulating layer.

[0122] The portion of the semiconductor layer 108 that overlaps with at least one of the conductive layer 112 and the conductive layer 106 functions as a channel-forming region. For the sake of simplicity, the portion of the semiconductor layer 108 that overlaps with the conductive layer 112 may be referred to as the channel-forming region below, but in reality, channels can also be formed in the portion that overlaps with the conductive layer 106 (including regions 108L1, 108L2, and 108N) without overlapping with the conductive layer 112.

[0123] Furthermore, as shown in Figures 6A and 6C, the conductive layer 106 may be electrically connected to the conductive layer 112 through openings 142 provided in the metal oxide layer 114, the insulating layer 110, and the insulating layer 103. This allows the conductive layer 106 and the conductive layer 112 to be given the same potential.

[0124] The conductive layer 106 can be made of the same material as conductive layer 112, conductive layer 120a, or conductive layer 120b. In particular, using a material containing copper for conductive layer 106 is preferable because it can reduce wiring resistance. Furthermore, using a material containing a high-melting-point metal such as tungsten or molybdenum for conductive layer 106 allows for processing at higher temperatures in subsequent processes.

[0125] Furthermore, as shown in Figures 6A and 6C, it is preferable that the conductive layer 112 and conductive layer 106 protrude outward from the edge of the semiconductor layer 108 in the channel width direction. In this case, as shown in Figure 6C, the entire channel width direction of the semiconductor layer 108 is covered by the conductive layer 112 and conductive layer 106 via the insulating layer 110 and insulating layer 103.

[0126] This configuration allows the semiconductor layer 108 to be electrically surrounded by the electric field generated by the pair of gate electrodes. In particular, it is preferable to apply the same potential to the conductive layer 106 and the conductive layer 112. This effectively applies an electric field to induce a channel in the semiconductor layer 108, thereby increasing the on-current of the transistor 100A. As a result, it becomes possible to miniaturize the transistor 100A.

[0127] Alternatively, the conductive layer 112 and the conductive layer 106 may be configured without connection. In this case, a constant potential may be applied to one of the pair of gate electrodes, and a signal for driving transistor 100A may be applied to the other. In this case, the threshold voltage for driving transistor 100A with the other electrode can be controlled by the potential applied to one gate electrode. Alternatively, one gate electrode may be electrically connected to the source electrode of transistor 100A.

[0128] The above is an explanation of Configuration Example 2.

[0129] [Configuration Example 3] The following describes an example of the configuration of a transistor according to one aspect of the present invention. Note that some parts that overlap with the above description may be omitted.

[0130] [Configuration Example 3-1] Figure 7A shows a schematic cross-sectional view of transistor 10 in the channel length direction.

[0131] The transistor 10 is provided on an insulating film 103a and has a semiconductor layer 108, an insulating layer 110, a metal oxide layer 114, a conductive layer 112, and an insulating region 115. An insulating layer 116 is also provided covering the transistor 10. The semiconductor layer 108 has regions 108C, 108L1, 108L2, and 108N.

[0132] The insulating film 103a is preferably formed of an insulating film containing an oxide. In particular, it is preferable to use an oxide film in the portion that is in contact with the semiconductor layer 108.

[0133] The insulating layer 110 has a laminated structure in which insulating film 110a, insulating film 110b, and insulating film 110c are stacked in this order from the insulating film 103a side. Insulating film 110a has a region in contact with the channel formation region of the semiconductor layer 108. Insulating film 110c has a region in contact with the metal oxide layer 114. Insulating film 110b is located between insulating film 110a and insulating film 110c.

[0134] It is preferable that insulating films 110a, 110b, and 110c each contain an oxide. In this case, it is preferable that insulating films 110a, 110b, and 110c are deposited continuously using the same deposition apparatus.

[0135] For example, the insulating film 110a, insulating film 110b, and insulating film 110c can be insulating layers containing one or more of the following: silicon oxide film, silicon oxide nitride film, silicon nitride film, aluminum oxide film, hafnium oxide film, yttrium oxide film, zirconium oxide film, gallium oxide film, tantalum oxide film, magnesium oxide film, lanthanum oxide film, cerium oxide film, and neodymium oxide film.

[0136] Furthermore, the insulating layer 110 in contact with the semiconductor layer 108 preferably has a laminated structure of oxide insulating films, and more preferably has a region containing oxygen in excess of the stoichiometric composition. In other words, the insulating layer 110 has an insulating film capable of releasing oxygen. For example, oxygen can be supplied into the insulating layer 110 by forming the insulating layer 110 in an oxygen atmosphere, performing heat treatment, plasma treatment, etc. on the insulating layer 110 after film formation in an oxygen atmosphere, or forming an oxide film on the insulating layer 110 in an oxygen atmosphere.

[0137] For example, insulating films 110a, 110b, and 110c can be formed using sputtering, chemical vapor deposition (CVD), vacuum deposition, pulsed laser deposition (PLD), atomic layer deposition (ALD), and other methods. CVD methods include plasma-enhanced chemical vapor deposition (PECVD) and thermal CVD.

[0138] In particular, insulating films 110a, 110b, and 110c are preferably formed by plasma CVD.

[0139] Since the insulating film 110a is deposited on the semiconductor layer 108, it is preferable that the film be deposited under conditions that minimize damage to the semiconductor layer 108. For example, it can be deposited under conditions where the deposition rate (also called the deposition rate) is sufficiently low.

[0140] For example, when forming a silicon oxidizride film as the insulating film 110a by plasma CVD, the damage to the semiconductor layer 108 can be made extremely small by forming it under low power conditions.

[0141] For forming silicon oxidnitride films, the deposition gas can include a silicon-containing deposition gas such as silane or disilane, and an oxidizing gas such as oxygen, ozone, nitrous oxide, or nitrogen dioxide. In addition to the source gas, a diluent gas such as argon, helium, or nitrogen may also be included.

[0142] For example, by reducing the ratio of the deposition gas flow rate to the total deposition gas flow rate (hereinafter also simply referred to as the flow rate ratio), the deposition rate can be lowered, and a dense film with fewer defects can be deposited.

[0143] It is preferable that the insulating film 110b is a film deposited under conditions with a higher deposition rate than that of insulating film 110a. This can improve productivity.

[0144] For example, insulating film 110b can be deposited under conditions that increase the deposition rate compared to insulating film 110a.

[0145] The insulating film 110c is preferably an extremely dense film with reduced surface defects and resistance to adsorption of impurities contained in the atmosphere, such as water. For example, it can be deposited under conditions where the deposition rate is sufficiently low, similar to insulating film 110a.

[0146] Furthermore, since the insulating film 110c is deposited on the insulating film 110b, the effect on the semiconductor layer 108 during the deposition of the insulating film 110c is smaller compared to that of the insulating film 110a. Therefore, the insulating film 110c can be deposited under higher power conditions than the insulating film 110a. By reducing the flow rate ratio of the depositing gas and depositing the film at a relatively high power, a dense film with reduced surface defects can be obtained.

[0147] In other words, a laminated film deposited under conditions such that the deposition rates are in the order of insulating film 110b, insulating film 110a, and insulating film 110c, from highest to lowest deposition rate, can be used as the insulating layer 110. Furthermore, the insulating layer 110 has higher etching rates under the same conditions for wet etching or dry etching in the order of insulating film 110b, insulating film 110a, and insulating film 110c.

[0148] Furthermore, it is preferable to form the insulating film 110b thicker than insulating films 110a and 110c. By forming the insulating film 110b, which has the fastest deposition rate, thicker, the time required for the deposition process of the insulating layer 110 can be shortened.

[0149] Here, the boundaries between insulating film 110a and insulating film 110b, and between insulating film 110b and insulating film 110c, may be unclear; therefore, in Figure 7A and other figures, these boundaries are indicated by dashed lines. Note that because insulating film 110a and insulating film 110b have different film densities, these boundaries can sometimes be observed as differences in contrast in transmission electron microscope (TEM) images of the cross-section of the insulating layer 110. Similarly, the boundary between insulating film 110b and insulating film 110c can sometimes be observed.

[0150] [Configuration Example 3-2] Figure 7B is a schematic cross-sectional view of transistor 10A. Transistor 10A differs from transistor 10 mainly in the configuration of its semiconductor layer 108.

[0151] The semiconductor layer 108 of the transistor 10A has a stacked structure in which semiconductor layer 108a and semiconductor layer 108b are stacked from the insulating film 103a side. It is preferable that metal oxide films are used for semiconductor layer 108a and semiconductor layer 108b.

[0152] For simplicity, the regions of semiconductor layer 108a and semiconductor layer 108b are collectively referred to as region 108C, region 108L1, region 108L2, and region 108N. In reality, the composition of semiconductor layer 108a and semiconductor layer 108b differs, so the electrical resistivity, carrier concentration, oxygen vacancy amount, hydrogen concentration, or impurity concentration of regions 108C, 108L1, 108L2, and 108N may differ.

[0153] The semiconductor layer 108b is in contact with the upper surface of the semiconductor layer 108a and the lower surface of the insulating film 110a, respectively.

[0154] For example, the semiconductor layer 108a can be a metal oxide film with a higher gallium atomic ratio than the semiconductor layer 108b.

[0155] Because gallium has a stronger bonding force with oxygen compared to indium, using a metal oxide film with a high gallium atomic ratio in semiconductor layer 108a makes it less likely for oxygen vacancies to form. A large number of oxygen vacancies in semiconductor layer 108a leads to a decrease in the electrical characteristics and reliability of the transistor. Therefore, by using a metal oxide film with a higher gallium atomic ratio than semiconductor layer 108b as semiconductor layer 108a, a transistor 10A with good electrical characteristics and high reliability can be realized.

[0156] More specifically, it is preferable to use a metal oxide film containing indium, gallium, and zinc as the semiconductor layer 108a, wherein the atomic ratio of gallium is higher than that of semiconductor layer 108b, and the atomic ratio of indium is lower than that of semiconductor layer 108b. In other words, it is preferable to use a metal oxide film as the semiconductor layer 108b, wherein the atomic ratio of indium is higher and the atomic ratio of gallium is lower compared to semiconductor layer 108a.

[0157] Furthermore, it is preferable to use a metal oxide film as the semiconductor layer 108a, which has a region where the atomic ratio of zinc is equal to that of the semiconductor layer 108b, or a region where the atomic ratio of zinc is lower than that of the semiconductor layer 108b.

[0158] For example, as the semiconductor layer 108a, a metal oxide film can be used in which the atomic ratio of metal elements is, for example, In:Ga:Zn=1:1:1, In:Ga:Zn=1:3:2, In:Ga:Zn=1:3:4, In:Ga:Zn=1:3:6, In:Ga:Zn=2:2:1, or close to these values.

[0159] For example, as the semiconductor layer 108b, a metal oxide film can be used in which the atomic ratio of metal elements is In:Ga:Zn=2:1:3, In:Ga:Zn=3:1:2, In:Ga:Zn=4:2:3, In:Ga:Zn=4:2:4.1, In:Ga:Zn=5:1:6, In:Ga:Zn=5:1:7, In:Ga:Zn=5:1:8, In:Ga:Zn=6:1:6, In:Ga:Zn=5:2:5, or close to these values.

[0160] Typically, it is preferable to use a metal oxide film with an atomic ratio of metal elements of In:Ga:Zn=1:1:1 or close to it for the semiconductor layer 108a, and a metal oxide film with an atomic ratio of metal elements of In:Ga:Zn=4:2:3, In:Ga:Zn=5:1:6, or close to these for the semiconductor layer 108b.

[0161] Transistor 10A reduces oxygen vacancies in semiconductor layer 108 by using a metal oxide film with a relatively high gallium content in semiconductor layer 108a located on the insulating film side 103a. Furthermore, transistor 10A reduces the interface defect density between semiconductor layer 108 and insulating layer 110 by using a metal oxide film with a low gallium content or no gallium at all in semiconductor layer 108b located on the insulating layer 110 side. Therefore, transistor 10A can be said to be a transistor that achieves both extremely high electrical characteristics and extremely high reliability.

[0162] Here, it is preferable to form the semiconductor layer 108b thinner than the semiconductor layer 108a. Even if the semiconductor layer 108b is an extremely thin film, for example, 0.5 nm to 10 nm in thickness, the interface defect density with the insulating layer 110 can be reduced. On the other hand, by making the semiconductor layer 108a, which is less prone to oxygen vacancies, relatively thicker, a more reliable transistor can be realized.

[0163] For example, the thickness of semiconductor layer 108a can be 1.5 to 20 times, preferably 2 to 15 times, and more preferably 3 to 10 times, the thickness of semiconductor layer 108b. Furthermore, the thickness of semiconductor layer 108b is preferably 0.5 nm to 30 nm, preferably 1 nm to 20 nm, and more preferably 2 nm to 10 nm.

[0164] It is preferable to use crystalline metal oxide films for semiconductor layer 108a and semiconductor layer 108b. Both semiconductor layer 108a and semiconductor layer 108b may use highly crystalline metal oxide films, or they may use less crystalline metal oxide films. Alternatively, semiconductor layer 108a and semiconductor layer 108b may have different crystallinity. For example, semiconductor layer 108a may be a film with higher crystallinity than semiconductor layer 108b, or semiconductor layer 108b may be a film with higher crystallinity than semiconductor layer 108a. The crystallinity of the metal oxide films used for semiconductor layer 108a and semiconductor layer 108b can be determined based on the required electrical characteristics and reliability of the transistor, as well as the specifications of the film deposition equipment.

[0165] Alternatively, a metal oxide film of the same composition may be used for both semiconductor layer 108a and semiconductor layer 108b. In this case, it is preferable to use a metal oxide film with higher crystallinity for semiconductor layer 108b than for semiconductor layer 108a. This reduces the impact of damage to semiconductor layer 108 during the deposition of the insulating layer 110, thereby enabling a highly reliable transistor. Furthermore, by using a metal oxide film with low crystallinity for semiconductor layer 108a, a transistor with increased field-effect mobility can be realized.

[0166] [Configuration Example 3-3] Figure 8A is a schematic cross-sectional view of transistor 10B. Transistor 10B differs from transistor 10 above mainly in that it has an insulating layer 103 with a multilayer structure. Figure 8B also shows a schematic cross-sectional view of transistor 10C, which has a conductive layer 106 in addition to the structure of transistor 10B.

[0167] Since transistors 10B and 10C are identical except for the conductive layer 106, we will explain transistor 10C here.

[0168] The conductive layer 106 has a region that overlaps with the semiconductor layer 108, insulating layer 110, metal oxide layer 114, and conductive layer 112 via the insulating layer 103. The conductive layer 106 functions as a first gate electrode (also called a back gate electrode). The insulating layer 103 functions as a first gate insulating layer. In this case, the conductive layer 112 functions as a second gate electrode, and the insulating layer 110 functions as a second gate insulating layer.

[0169] For example, transistor 10C can increase the current it can supply when it is ON by applying the same potential to conductive layer 112 and conductive layer 106. Furthermore, transistor 10C can also apply a potential to control the threshold voltage to one of the conductive layer 112 and conductive layer 106, and a potential to control the ON and OFF states of transistor 10C to the other.

[0170] The insulating layer 103 has a laminated structure in which insulating films 103a, 103b1, 103b2, and 103b3 are stacked from the semiconductor layer 108 side. Insulating film 103b3 is in contact with the conductive layer 106. Also, insulating film 103a is in contact with the semiconductor layer 108.

[0171] The insulating layer 103, which functions as the first gate insulating layer, preferably satisfies one or more of the following conditions: high breakdown voltage, low film stress, poor release of hydrogen and water, few defects in the film, and suppression of diffusion of metal elements contained in the conductive layer 106. It is most preferable that it satisfies all of these conditions.

[0172] Of the four insulating films of the insulating layer 103, it is preferable to use insulating films containing nitrogen for insulating films 103b3, 103b2, and 103b1 located on the conductive layer 106 side. On the other hand, it is preferable to use an insulating film containing oxygen for insulating film 103a, which is in contact with the semiconductor layer 108. Furthermore, it is preferable to deposit each of the four insulating films of the insulating layer 103 continuously using a plasma CVD apparatus without contact with the atmosphere.

[0173] For insulating films 103b1, 103b2, and 103b3, insulating films containing nitrogen, such as silicon nitride, silicon oxide nitride, aluminum nitride, and hafnium nitride, can be used. Furthermore, for insulating film 103a, an insulating film suitable for use in the insulating layer 110 can be used.

[0174] It is preferable that insulating films 103b1 and 103b3 are dense films that can prevent the diffusion of impurities from below. It is preferable that insulating film 103b3 is a film that can block metal elements contained in the conductive layer 106, and insulating film 103b1 is a film that can block hydrogen and water contained in insulating film 103b2. Therefore, insulating films 103b3 and 103b1 can be insulating films deposited under conditions with a lower deposition rate than insulating film 103b2.

[0175] On the other hand, it is preferable to use an insulating film 103b2 that has been deposited under conditions of low stress and high deposition rate. Furthermore, it is preferable that the insulating film 103b2 is formed to be thicker than insulating films 103b1 and 103b3.

[0176] For example, even if silicon nitride films deposited by plasma CVD are used for each of the insulating films 103b1, 103b2, and 103b3, insulating film 103b2 will have a lower film density than the other two insulating films. Therefore, this difference may be observed as a difference in contrast in transmission electron microscope images of the cross-section of the insulating layer 103. Note that the boundaries between insulating film 103b3 and insulating film 103b2, and between insulating film 103b2 and insulating film 103b1, may be unclear, so these boundaries are indicated by dashed lines in Figures 8A and 8B.

[0177] The insulating film 103a in contact with the semiconductor layer 108 is preferably a dense insulating film that does not easily adsorb impurities such as water onto its surface. Furthermore, it is preferable to use an insulating film with as few defects as possible and with reduced impurities such as water and hydrogen. For example, the insulating film 103a can be an insulating film similar to the insulating film 110c of the insulating layer 110.

[0178] Furthermore, in cases where a metal film or alloy film whose constituent elements do not easily diffuse into the insulating layer 103 is used as the conductive layer 106, the insulating film 103b3 may be omitted, and a configuration in which three insulating films, insulating film 103b2, insulating film 103b1, and insulating film 103a, are laminated may be used.

[0179] By having such a layered structure in the insulating layer 103, an extremely reliable transistor can be realized.

[0180] [Example of manufacturing method] The following describes an example of a method for manufacturing a transistor according to one aspect of the present invention. Here, we will use transistor 100A, which was illustrated in Configuration Example 2, as an example.

[0181] Thin films (insulating films, semiconductor films, conductive films, etc.) that make up semiconductor devices can be formed using methods such as sputtering, chemical vapor deposition (CVD), vacuum deposition, pulsed laser deposition (PLD), and atomic layer deposition (ALD). CVD methods include plasma-enhanced CVD (PECVD) and thermal CVD. One type of thermal CVD is metal-organic CVD (MOCVD).

[0182] Furthermore, thin films (insulating films, semiconductor films, conductive films, etc.) that constitute semiconductor devices can be formed by methods such as spin coating, dip coating, spray coating, inkjet printing, dispensing, screen printing, offset printing, doctor knife coating, slit coating, roll coating, curtain coating, and knife coating.

[0183] Furthermore, when processing the thin films that constitute semiconductor devices, photolithography or the like can be used. In addition, thin films may be processed by nanoimprint lithography, sandblasting, lift-off lithography, or the like. Alternatively, island-shaped thin films may be directly formed by a film deposition method using a shielding mask such as a metal mask.

[0184] There are two main methods of photolithography. One method involves forming a resist mask on the thin film to be processed, then processing the thin film by etching or other means, and removing the resist mask. The other method involves forming a photosensitive thin film, then exposing and developing it to process the thin film into the desired shape.

[0185] In photolithography, the light used for exposure can be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture thereof. Other options include ultraviolet light, KrF laser light, or ArF laser light. Exposure may also be performed using immersion lithography. Furthermore, extreme ultraviolet (EUV) light or X-rays may be used as the light source for exposure. An electron beam can also be used instead of light for exposure. Using extreme ultraviolet light, X-rays, or an electron beam is preferable because it allows for extremely fine processing. Note that a photomask is not required when exposure is performed by scanning a beam such as an electron beam.

[0186] For etching thin films, methods such as dry etching, wet etching, and sandblasting can be used.

[0187] Figures 9 and 10 show cross-sections of the channel length and channel width at each stage of the manufacturing process of transistor 100A.

[0188] [Formation of conductive layer 106] A conductive film is formed on the substrate 102, and this is processed by etching to form a conductive layer 106 that functions as a gate electrode (Figure 9A).

[0189] In this case, it is preferable to process the ends of the conductive layer 106 so that they are tapered, as shown in Figure 9A. This improves the stepped coverage of the insulating layer 103 that is formed next.

[0190] Furthermore, by using a conductive film containing copper as the conductive layer 106, the wiring resistance can be reduced. For example, when applying transistors to large display devices or high-resolution display devices, it is preferable to use a conductive film containing copper. Moreover, even when a conductive film containing copper is used for the conductive layer 106, the insulating layer 103 suppresses the diffusion of copper to the semiconductor layer 108, thus enabling the realization of a highly reliable transistor.

[0191] [Formation of insulating layer 103] Next, an insulating layer 103 is formed by covering the substrate 102 and the conductive layer 106 (Figure 9B). The insulating layer 103 can be formed using methods such as PECVD, ALD, or sputtering.

[0192] Here, the insulating layer 103 is formed by sequentially laminating insulating film 103b and insulating film 103a.

[0193] In particular, each insulating layer constituting the insulating layer 103 is preferably formed by the PECVD method. The method for forming the insulating layer 103 can be based on the description in Configuration Example 3 above.

[0194] After forming the insulating layer 103, a process to supply oxygen to the insulating layer 103 may be performed. For example, plasma treatment or heat treatment in an oxygen atmosphere can be performed. Alternatively, oxygen may be supplied to the insulating layer 103 by plasma ion doping or ion implantation. Alternatively, oxygen may be supplied by forming a metal oxide film on the insulating layer 103 in an oxygen-containing atmosphere. In this case, it is preferable to remove the metal oxide film.

[0195] [Formation of semiconductor layer 108] Next, a metal oxide film is formed on the insulating layer 103.

[0196] The metal oxide film is preferably formed by a sputtering method using a metal oxide target.

[0197] It is preferable that the metal oxide film be a dense film with as few defects as possible. Furthermore, it is preferable that the metal oxide film be a high-purity film with impurities such as hydrogen and water reduced as much as possible. In particular, it is preferable to use a crystalline metal oxide film as the metal oxide film.

[0198] Furthermore, when forming a metal oxide film, oxygen gas may be mixed with an inert gas (for example, helium gas, argon gas, xenon gas, etc.). The higher the proportion of oxygen gas in the total deposition gas (hereinafter also referred to as the oxygen flow rate ratio) when forming the metal oxide film, the higher the crystallinity of the metal oxide film can be, resulting in a more reliable transistor. Conversely, a lower oxygen flow rate ratio results in lower crystallinity of the metal oxide film, allowing for a transistor with a higher on-current.

[0199] When forming a metal oxide film, higher substrate temperatures result in a more crystalline and dense metal oxide film. Conversely, lower substrate temperatures result in a less crystalline and more electrically conductive metal oxide film.

[0200] For depositing the metal oxide film, the substrate temperature should be between room temperature and 250°C, preferably between room temperature and 200°C, and more preferably between room temperature and 140°C. For example, depositing the film at a temperature between room temperature and 140°C is preferable as it increases productivity. Furthermore, by depositing the metal oxide film at room temperature or without intentional heating, the crystallinity can be reduced.

[0201] Furthermore, before forming the metal oxide film, it is preferable to perform a treatment to desorb water, hydrogen, organic matter, etc. adsorbed on the surface of the insulating layer 103, or to supply oxygen into the insulating layer 103. For example, a heat treatment can be performed at a temperature of 70°C to 200°C under a reduced pressure atmosphere. Alternatively, plasma treatment may be performed in an atmosphere containing oxygen. Alternatively, oxygen may be supplied to the insulating layer 103 by plasma treatment in an atmosphere containing an oxidizing gas such as nitrous oxide (N2O). Plasma treatment containing nitrous oxide gas can suitably remove organic matter from the surface of the insulating layer 103 while supplying oxygen. After such treatment, it is preferable to continuously form the metal oxide film without exposing the surface of the insulating layer 103 to the atmosphere.

[0202] Furthermore, when the semiconductor layer 108 is a stacked structure in which multiple semiconductor layers are stacked, it is preferable to deposit the next metal oxide film continuously after depositing the first metal oxide film without exposing its surface to the atmosphere.

[0203] Next, island-shaped semiconductor layers 108 are formed by etching a portion of the metal oxide film (Figure 9C).

[0204] For processing the metal oxide film, either wet etching, dry etching, or both may be used. In this case, a portion of the insulating layer 103 that does not overlap with the semiconductor layer 108 may be etched and become thinner. For example, the insulating film 103a of the insulating layer 103 may disappear due to etching, exposing the surface of the insulating film 103b.

[0205] In this case, it is preferable to perform a heat treatment after the metal oxide film has been formed, or after the metal oxide film has been processed into a semiconductor layer 108. The heat treatment can remove hydrogen or water contained in the metal oxide film or semiconductor layer 108, or adsorbed on the surface. In addition, the heat treatment may improve the film quality of the metal oxide film or semiconductor layer 108 (for example, by reducing defects or improving crystallinity).

[0206] Furthermore, heat treatment can supply oxygen from the insulating layer 103 to the metal oxide film or the semiconductor layer 108. In this case, it is more preferable to perform the heat treatment before processing the semiconductor layer 108.

[0207] The heat treatment temperature can typically be 150°C or higher but below the strain point of the substrate, or 200°C or higher but 500°C or lower, or 250°C or higher but 450°C or lower, or 300°C or higher but 450°C or lower.

[0208] The heat treatment can be carried out in an atmosphere containing a noble gas or nitrogen. Alternatively, heating may be performed in such an atmosphere followed by heating in an oxygen-containing atmosphere. Alternatively, heating may be performed in a clean dry air (CDA) atmosphere. It is preferable that the atmosphere used for the heat treatment contains as little hydrogen, water, etc. as possible. The heat treatment can be carried out using an electric furnace, an RTA (Rapid Thermal Annealing) apparatus, etc. Using an RTA apparatus can shorten the heat treatment time.

[0209] Note that this heat treatment may be omitted if it is not necessary. Alternatively, the heat treatment may be omitted here and combined with a heat treatment performed in a later step. Furthermore, in some cases, this heat treatment can be combined with a high-temperature treatment in a later step (for example, a film deposition process).

[0210] [Formation of insulating film 110f] Next, the insulating layer 103 and the semiconductor layer 108 are covered to form an insulating film 110f (Figure 9D).

[0211] The insulating film 110f is preferably formed by the PECVD method.

[0212] Furthermore, it is preferable to perform plasma treatment on the surface of the semiconductor layer 108 before depositing the insulating film 110f. This plasma treatment can reduce impurities such as water adsorbed on the surface of the semiconductor layer 108. As a result, impurities at the interface between the semiconductor layer 108 and the insulating film 110f can be reduced, enabling the realization of a highly reliable transistor. This is particularly preferable when the surface of the semiconductor layer 108 is exposed to the atmosphere between the formation of the semiconductor layer 108 and the deposition of the insulating film 110f. The plasma treatment can be performed in an atmosphere such as oxygen, ozone, nitrogen, nitrous oxide, or argon. It is also preferable that the plasma treatment and the deposition of the insulating film 110f are performed continuously without exposure to the atmosphere.

[0213] Here, it is preferable to perform a heat treatment after forming the insulating film 110f. The heat treatment can remove hydrogen or water contained in or adsorbed on the surface of the insulating film 110f. It can also reduce defects in the insulating film 110f. The conditions for the heat treatment can be based on those described above.

[0214] Note that this heat treatment may be omitted if it is not necessary. Alternatively, the heat treatment may be omitted here and combined with a heat treatment performed in a later step. Furthermore, in some cases, this heat treatment can be combined with a high-temperature treatment in a later step (for example, a film deposition process).

[0215] [Formation of metal oxide film 114f] Next, a metal oxide film 114f is formed on the insulating film 110f (Figure 9E).

[0216] The metal oxide film 114f is preferably formed in an atmosphere containing oxygen, for example. In particular, it is preferably formed by sputtering in an atmosphere containing oxygen. This allows oxygen to be supplied to the insulating film 110f during the formation of the metal oxide film 114f.

[0217] The above description can be applied when the metal oxide film 114f is formed by a sputtering method using an oxide target containing a metal oxide, similar to the case of the semiconductor layer 108.

[0218] For example, as a deposition condition for the metal oxide film 114f, the metal oxide film may be formed by a reactive sputtering method using a metal target and oxygen as the deposition gas. If, for example, aluminum is used as the metal target, an aluminum oxide film can be deposited.

[0219] When forming the metal oxide film 114f, the higher the ratio of the oxygen flow rate to the total flow rate of the deposition gas introduced into the deposition chamber of the deposition apparatus (oxygen flow rate ratio), or the higher the oxygen partial pressure in the deposition chamber, the more oxygen can be supplied to the insulating film 110f. The oxygen flow rate ratio or oxygen partial pressure is, for example, greater than 0% and 100% or less, preferably 10% or more and 100% or less, more preferably 20% or more and 100% or less, even more preferably 30% or more and 100% or less, and even more preferably 40% or more and 100% or less. In particular, it is preferable to set the oxygen flow rate ratio to 100% and to bring the oxygen partial pressure as close to 100% as possible.

[0220] In this way, by forming the metal oxide film 114f by sputtering in an oxygen-containing atmosphere, oxygen can be supplied to the insulating film 110f during the formation of the metal oxide film 114f, while preventing oxygen from detaching from the insulating film 110f. As a result, a very large amount of oxygen can be trapped in the insulating film 110f.

[0221] It is preferable to perform a heat treatment after the metal oxide film 114f is formed. The heat treatment allows oxygen contained in the insulating film 110f to be supplied to the semiconductor layer 108. By heating with the metal oxide film 114f covering the insulating film 110f, oxygen is prevented from escaping from the insulating film 110f to the outside, and a large amount of oxygen can be supplied to the semiconductor layer 108. As a result, oxygen deficiencies in the semiconductor layer 108 can be reduced, and a highly reliable transistor can be realized.

[0222] The conditions for heat treatment can be applied as described above.

[0223] Note that this heat treatment may be omitted if it is not necessary. Alternatively, the heat treatment may be omitted here and combined with a heat treatment performed in a later step. Furthermore, in some cases, this heat treatment can be combined with a high-temperature treatment in a later step (for example, a film deposition process).

[0224] [Formation of opening 142] Next, the metal oxide film 114f, the insulating film 110f, and a portion of the insulating layer 103 are etched to form an opening 142 that reaches the conductive layer 106. This allows the conductive layer 112 and the conductive layer 106, which will be formed later, to be electrically connected through the opening 142.

[0225] [Formation of conductive film 112f] Next, a conductive film 112f, which will become the conductive layer 112, is deposited on the metal oxide film 114f (Figure 9F).

[0226] It is preferable to use a low-resistance metal or alloy material as the conductive film 112f. Furthermore, it is preferable to use a material that does not easily release hydrogen and does not easily diffuse hydrogen as the conductive film 112f. Additionally, it is preferable to use a material that is resistant to oxidation as the conductive film 112f.

[0227] For example, the conductive film 112f is preferably deposited by a sputtering method using a sputtering target containing a metal or alloy.

[0228] For example, it is preferable that the conductive film 112f be a laminated film in which a conductive film that is resistant to oxidation and hydrogen diffusion is laminated with a conductive film with low resistance.

[0229] [Formation of conductive layer 112 and metal oxide layer 114] Next, a resist mask 140 is formed on the conductive film 112f (Figure 10A).

[0230] Using the resist mask 140 as a mask, the conductive film 112f and the metal oxide film 114f are etched to form the conductive layer 112 and the metal oxide layer 114 (Figure 10B).

[0231] At this time, the conductive film 112f is etched so that the edge of the conductive layer 112 is located inside the edge of the resist mask 140. This allows the insulating film 110f to be etched using the resist mask 140 in a later step. Furthermore, the metal oxide layer 114 is processed so that the edge is located inside the edge of the conductive layer 112. This allows the region that will later become the insulating region 115 to be formed.

[0232] For example, after etching only the conductive film 112f to form the conductive layer 112, the metal oxide film 114f can be etched to form the metal oxide layer 114. In this case, by using isotropic etching methods for both the etching of the conductive film 112f and the etching of the metal oxide film 114f, it is possible to form the conductive layer 112 and the metal oxide layer 114 whose edges are located inside the edges of the resist mask 140. For example, an isotropic dry etching method may be used, but since there is a risk that a part of the resist mask 140 may be etched, it is more preferable to use a wet etching method.

[0233] Alternatively, the conductive film 112f and the metal oxide film 114f may be etched in a single etching process. In this case, it is preferable to use an isotropic etching method in which the etching rate for the metal oxide film 114f is higher than the etching rate for the conductive film 112f.

[0234] Alternatively, the conductive layer 112 and the metal oxide layer 114 can be formed by first processing both the conductive film 112f and the metal oxide film 114f in a single etching process so that their upper surface shapes are roughly identical, and then performing an etching process to recess the edges of the metal oxide film 114f.

[0235] When etching the conductive film 112f or the metal oxide film 114f, a part of the insulating film 110f may be etched and thinned. For example, the shape illustrated in FIG. 2A and the like is an example in the case where the upper part of the insulating film 110f that becomes the insulating layer 110 is etched when the conductive film 112f and the metal oxide film 114f are etched.

[0236] 〔Formation of Insulating Layer 110〕 Subsequently, by using the resist mask 140 to etch the insulating film 110f, the insulating layer 110 is formed (FIG. 10C).

[0237] The etching of the insulating film 110f is preferably performed using an anisotropic etching method. For example, an anisotropic dry etching method can be preferably used.

[0238] After etching the insulating film 110f, the resist mask 140 is removed.

[0239] In the above steps, the insulating layer 110, the conductive layer 112 whose end is located inside the end of the insulating layer 110, and the metal oxide layer 114 whose end is located inside the end of the conductive layer 112 can be processed using the same resist mask 140.

[0240] Note that different resist masks can also be used for the processing of the conductive layer 112 and the metal oxide layer 114 and the processing of the insulating layer 110.

[0241] When etching the insulating film 110f, the insulating film 103a not covered by the resist mask 140 may be etched and thinned or disappear.

[0242] 〔Formation of Insulating Layer 116〕 Subsequently, an insulating layer 116 is formed in contact with the exposed portion of the semiconductor layer 108 (FIG. 10D). By forming the insulating layer 116, the exposed portion of the semiconductor layer 108 has a lower resistance, and the region 108N is formed. At the same time as the formation of the insulating layer 116, the insulating region 115 is also formed.

[0243] As the insulating layer 116, an insulating film that releases impurity elements having the function of reducing the resistance of the semiconductor layer 108 can be used. In particular, it is preferable to use an inorganic insulating film such as a silicon nitride film, silicon oxide nitride film, or silicon oxynitride film that can release hydrogen. In this case, it is preferable to use a plasma CVD method using a hydrogen-containing film-forming gas, as this allows hydrogen to be supplied to the semiconductor layer 108 during film formation.

[0244] For example, when silicon nitride is used as the insulating layer 116, it is preferable to form it by a PECVD method using a mixed gas containing silicon, such as silane, and nitrogen, such as ammonia or nitrous oxide, as the film-forming gas. In this case, it is preferable that hydrogen is contained in the silicon nitride film being formed. This makes it easier to reduce the resistance of a portion of the semiconductor layer 108 by allowing the hydrogen in the insulating layer 116 to diffuse into the semiconductor layer 108.

[0245] Furthermore, it is preferable to heat the substrate 102 under a reduced pressure atmosphere and hold it for a certain period of time when forming the insulating layer 116. This allows oxygen to be removed from the exposed portion of the semiconductor layer 108, creating an oxygen deficiency. Then, by supplying hydrogen to this region during the formation of the insulating layer 116, the resistance of region 108N can be reduced more effectively.

[0246] Furthermore, during the deposition of the insulating layer 116, some of the components of the deposition gas for the insulating layer 116 may diffuse into a portion of the semiconductor layer 108, thereby reducing the resistance of the semiconductor layer 108. For example, the semiconductor layer 108 can also be reduced in resistance by diffusing nitrogen into a portion of the semiconductor layer 108.

[0247] The hydrogen supplied to region 108N of the semiconductor layer 108 may be diffused to regions 108L2 and 108L1 by heat generated during the deposition of the insulating layer 116 or by heat treatment after deposition. In this case, a concentration gradient may be formed in the semiconductor layer 108 such that the carrier concentration decreases from region 108N to region 108L1. For example, the carrier concentration in the semiconductor layer 108 is lowest in region 108C, and increases in the order of region 108L1, region 108L2, and region 108N.

[0248] Furthermore, an insulating film having the function of creating oxygen vacancies in the semiconductor layer 108 can also be used. In particular, it is preferable to use an insulating film containing a metal nitride. For example, it is preferable to form the film by a reactive sputtering method using a sputtering target containing a metal and a mixed gas of nitrogen gas and a diluent gas such as a rare gas as the film-forming gas. This makes it easy to control the film quality of the insulating layer 116 by controlling the flow rate ratio of the film-forming gas.

[0249] For example, when using an aluminum nitride film formed by reactive sputtering using an aluminum target as the insulating layer 116, it is preferable that the flow rate of nitrogen gas relative to the total flow rate of the film formation gas be 30% to 100%, preferably 40% to 100%, and more preferably 50% to 100%.

[0250] [Formation of insulating layer 118] After forming the insulating layer 116, the insulating layer 118 is formed.

[0251] In this case, it is preferable that the insulating layer 116 and the insulating layer 118 be formed continuously without being exposed to the atmosphere.

[0252] When forming the insulating layer 118 by plasma CVD, if the deposition temperature is too high, impurities contained in region 108N may diffuse to the peripheral area including the channel formation region of the semiconductor layer 108, or the electrical resistance of region 108N may increase. Therefore, the deposition temperature of the insulating layer 118 should be determined taking these factors into consideration.

[0253] For example, the deposition temperature for the insulating layer 118 is preferably 150°C to 400°C, more preferably 180°C to 360°C, and more preferably 200°C to 250°C. By deposition of the insulating layer 118 at a low temperature, good electrical characteristics can be imparted even to transistors with short channel lengths.

[0254] Heat treatment may be performed after the deposition of the insulating layer 116 or after the deposition of the insulating layer 118. Heat treatment can promote the reduction of resistance in region 108N.

[0255] The conditions for heat treatment can be applied as described above.

[0256] Note that this heat treatment may be omitted if it is not necessary. Alternatively, the heat treatment may be omitted here and combined with a heat treatment performed in a later step. Furthermore, in some cases, this heat treatment can be combined with a high-temperature treatment in a later step (for example, a film deposition process).

[0257] [Formation of openings 141a and 141b] Next, openings 141a and 141b reaching region 108N are formed by etching a portion of the insulating layer 118 and insulating layer 116.

[0258] [Formation of conductive layer 120a and conductive layer 120b] Next, a conductive film is formed on the insulating layer 118 so as to cover the openings 141a and 141b, and the conductive film is processed into a desired shape to form the conductive layer 120a and conductive layer 120b (Figure 10E).

[0259] By following the above steps, transistor 100A can be manufactured. For example, when applying transistor 100A to a pixel of a display device, a step of forming one or more of the following can be added: a protective insulating layer, a planarization layer, a pixel electrode, or wiring.

[0260] The above is an explanation of an example of the manufacturing method.

[0261] In the case of using the transistor 100 illustrated in Configuration Example 1, the formation process of the conductive layer 106 and the formation process of the opening 142 in the above manufacturing method example may be omitted. Further, the transistor 100 and the transistor 100A can be formed on the same substrate through the same processes.

[0262] [Components of the semiconductor device] Hereinafter, components included in the semiconductor device of the present embodiment will be described.

[0263] [Substrate] There is no major limitation on the material of the substrate 102, etc., but at least it needs to have heat resistance enough to withstand subsequent heat treatment. For example, a single crystal semiconductor substrate made of silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI substrate, a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, etc. may be used as the substrate 102. Further, a substrate on which semiconductor elements are provided may be used as the substrate 102.

[0264] Further, a flexible substrate may be used as the substrate 102, and a semiconductor device may be directly formed on the flexible substrate. Alternatively, a release layer may be provided between the substrate 102 and the semiconductor device. The release layer can be used to separate from the substrate 102 after partially or completely completing the semiconductor device thereon and transfer it to another substrate. At that time, the semiconductor device can be transferred to a substrate with inferior heat resistance or a flexible substrate.

[0265] [Conductive film] The conductive layers 112 and 106 that function as gate electrodes, and the conductive layers 120a and 120b that function as one of the source electrode or drain electrode can be formed using a metal element selected from chromium, copper, aluminum, gold, silver, zinc, molybdenum, tantalum, titanium, tungsten, manganese, nickel, iron, cobalt, or an alloy containing the above-described metal elements as a component, or an alloy combining the above-described metal elements, respectively.

[0266] Furthermore, conductive layers 112, 106, 120a, and 120b can also be coated with oxide conductors or metal oxide films such as In-Sn oxide, In-W oxide, In-W-Zn oxide, In-Ti oxide, In-Ti-Sn oxide, In-Zn oxide, In-Sn-Si oxide, and In-Ga-Zn oxide.

[0267] Here, we will explain oxide conductors (OC). For example, when an oxygen vacancy is formed in a metal oxide with semiconductor properties, and hydrogen is added to the oxygen vacancy, a donor level is formed near the conduction band. As a result, the metal oxide becomes highly conductive and turns into a conductor. A metal oxide that has become conductive can be called an oxide conductor.

[0268] Furthermore, the conductive layer 112, etc., may be a laminated structure of a conductive film containing the above-mentioned oxide conductor (metal oxide) and a conductive film containing a metal or alloy. By using a conductive film containing a metal or alloy, the wiring resistance can be reduced. In this case, it is preferable to apply a conductive film containing an oxide conductor to the side that is in contact with the insulating layer that functions as a gate insulating film.

[0269] Furthermore, the conductive layers 112, 106, 120a, and 120b preferably contain one or more of the above-mentioned metallic elements, particularly titanium, tungsten, tantalum, and molybdenum. In particular, a tantalum nitride film is preferred. This tantalum nitride film is conductive, has high barrier properties against copper, oxygen, or hydrogen, and emits little hydrogen from itself, making it suitable for use as a conductive film in contact with the semiconductor layer 108 or as a conductive film in the vicinity of the semiconductor layer 108.

[0270] [Semiconductor layer] When the semiconductor layer 108 is an In-M-Zn oxide, possible atomic ratios of metal elements in the sputtering target used to deposit the In-M-Zn oxide include In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=1:3:2, In:M:Zn=1:3:4, In:M:Zn=1:3:6, In:M:Zn=2:2:1, In:M:Zn=2:1:3, In:M:Zn=3:1:2, In:M:Zn=4:2:3, In:M:Zn=4:2:4.1, In:M:Zn=5:1:6, In:M:Zn=5:1:7, In:M:Zn=5:1:8, In:M:Zn=6:1:6, In:M:Zn=5:2:5, etc.

[0271] Furthermore, using a target containing a polycrystalline oxide as the sputtering target is preferable because it facilitates the formation of a crystalline semiconductor layer 108. The atomic ratio of the deposited semiconductor layer 108 includes a variation of plus or minus 40% of the atomic ratio of the metal elements contained in the sputtering target. For example, if the composition of the sputtering target used for the semiconductor layer 108 is In:Ga:Zn=4:2:4.1 [atomic ratio], the composition of the deposited semiconductor layer 108 may be close to In:Ga:Zn=4:2:3 [atomic ratio].

[0272] Furthermore, when the atomic ratio is stated as In:Ga:Zn=4:2:3 or nearby, it includes the case where, when In is set to 4, Ga is between 1 and 3, and Zn is between 2 and 4. Also, when the atomic ratio is stated as In:Ga:Zn=5:1:6 or nearby, it includes the case where, when In is set to 5, Ga is greater than 0.1 and 2 or less, and Zn is between 5 and 7. Also, when the atomic ratio is stated as In:Ga:Zn=1:1:1 or nearby, it includes the case where, when In is set to 1, Ga is greater than 0.1 and 2 or less, and Zn is greater than 0.1 and 2 or less.

[0273] Furthermore, the semiconductor layer 108 has an energy gap of 2 eV or more, preferably 2.5 eV or more. By using a metal oxide with a wider energy gap than silicon in this way, the off-current of the transistor can be reduced.

[0274] Furthermore, it is preferable to use a metal oxide with a low carrier concentration for the semiconductor layer 108. When the carrier concentration of the metal oxide is low, the impurity concentration in the metal oxide can be lowered to reduce the defect level density. In this specification, a low impurity concentration and a low defect level density are referred to as high-purity intrinsic or substantially high-purity intrinsic. Examples of impurities in the metal oxide include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0275] In particular, hydrogen contained in metal oxides can react with oxygen bonded to metal atoms to form water, thus creating oxygen vacancies within the metal oxide. If oxygen vacancies are present in the channel-forming region of the metal oxide, the transistor may exhibit normally-on characteristics. Furthermore, defects containing hydrogen can function as donors, generating electrons as carriers. In addition, some of the hydrogen can combine with oxygen bonded to metal atoms, generating electrons as carriers. Therefore, transistors using metal oxides with a high hydrogen content tend to exhibit normally-on characteristics.

[0276] Defects where hydrogen fills an oxygen vacancy can function as donors for metal oxides. However, quantitatively evaluating such defects is difficult. Therefore, in metal oxides, evaluation is sometimes done using carrier concentration rather than donor concentration. Accordingly, in this specification, the carrier concentration, assuming no electric field is applied, may be used as a parameter for metal oxides, rather than the donor concentration. In other words, "carrier concentration" as described in this specification may sometimes be rephrased as "donor concentration."

[0277] Therefore, it is preferable that the hydrogen content in the metal oxide be reduced as much as possible. Specifically, in the metal oxide, the hydrogen concentration obtained by secondary ion mass spectrometry (SIMS) should be 1 × 10⁻⁶. 20 atoms / cm 3 Less than 1 × 10 19 atoms / cm 3 Less than 5x10 18 atoms / cm 3 Less than 1 × 10 18 atoms / cm 3 It should be less than [amount]. By using metal oxides with sufficiently reduced impurities such as hydrogen in the channel formation region of a transistor, stable electrical characteristics can be provided.

[0278] Furthermore, the carrier concentration of the metal oxide in the channel-forming region is 1 × 10⁻⁶ 18 cm -3 The following is preferable: 1 × 10 17 cm -3 It is more preferable that it be less than 1 × 10 16 cm -3 It is even more preferable that it be less than 1 × 10 13 cm -3 It is even more preferable that it be less than 1 × 10 12 cm -3 It is even more preferable that it be less than . There are no particular limitations on the lower limit of the carrier concentration of the metal oxide in the channel-forming region, but for example, 1 × 10 -9 cm -3 It can be done this way.

[0279] Furthermore, the semiconductor layer 108 is preferably a non-single-crystal structure. Non-single-crystal structures include, for example, the CAAC structure, polycrystalline structure, microcrystalline structure, or amorphous structure described later. Among non-single-crystal structures, the amorphous structure has the highest defect level density, and the CAAC structure has the lowest defect level density.

[0280] The following section describes CAAC (c-axis aligned crystal). CAAC represents one example of a crystal structure.

[0281] CAAC structure is a type of crystalline structure found in thin films and other materials that have multiple nanocrystals (crystalline regions with a maximum diameter of less than 10 nm). In this structure, each nanocrystal has its c-axis oriented in a specific direction, while its a-axis and b-axis are not oriented, and the nanocrystals are continuously connected to each other without forming grain boundaries. In particular, thin films with a CAAC structure tend to have the c-axis of each nanocrystal oriented in the direction of the film's thickness, the direction normal to the surface it is formed on, or the direction normal to the surface of the film.

[0282] CAAC-OS (Oxide Semiconductor) is a highly crystalline oxide semiconductor. Furthermore, because clear grain boundaries cannot be observed in CAAC-OS, it is less susceptible to the reduction in electron mobility caused by grain boundaries. Also, since the crystallinity of oxide semiconductors can decrease due to impurities and defects, CAAC-OS can be considered an oxide semiconductor with fewer impurities and defects (such as oxygen vacancies). Therefore, oxide semiconductors containing CAAC-OS have stable physical properties. Consequently, oxide semiconductors containing CAAC-OS are highly heat-resistant and reliable.

[0283] In crystallography, it is common to define a unit cell with a specific axis designated as the c axis, among the three axes (crystal axes) a, b, and c that constitute the unit cell. In particular, in crystals with a layered structure, it is common to define the two axes parallel to the plane direction of the layer as the a and b axes, and the axis intersecting the layer as the c axis. A typical example of such a layered crystal is graphite, which is classified as a hexagonal crystal system, where the a and b axes of its unit cell are parallel to the cleavage planes, and the c axis is perpendicular to the cleavage planes. For example, the crystal of InGaZnO4, which has a layered YbFe2O4 type crystal structure, can be classified as a hexagonal crystal system, where the a and b axes of its unit cell are parallel to the plane direction of the layer, and the c axis is perpendicular to the layer (i.e., the a and b axes).

[0284] In oxide semiconductor films with a microcrystalline structure (microcrystalline oxide semiconductor films), the crystalline regions may not be clearly visible in TEM observation images. The crystalline regions in microcrystalline oxide semiconductor films are often between 1 nm and 100 nm in size, or between 1 nm and 10 nm. In particular, oxide semiconductor films containing nanocrystals (nc) that are microcrystals between 1 nm and 10 nm, or between 1 nm and 3 nm, are called nc-OS (nanocrystalline oxide semiconductor) films. Furthermore, in nc-OS films, the grain boundaries may not be clearly visible in TEM observation images, for example.

[0285] nc-OS films exhibit periodicity in atomic arrangement in minute regions (e.g., regions between 1 nm and 10 nm, particularly between 1 nm and 3 nm). Furthermore, nc-OS films show no regularity in crystal orientation between different crystalline regions. Therefore, no orientation is observed throughout the film. Consequently, depending on the analytical method, nc-OS films may be indistinguishable from amorphous oxide semiconductor films. For example, when structural analysis of an nc-OS film is performed using an XRD instrument with an X-ray diameter larger than that of the crystalline region, out-of-plane analysis does not detect peaks indicating crystal planes. Also, when electron diffraction (also called limited-field electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter larger than that of the crystalline region (e.g., 50 nm or more), a diffraction pattern resembling a halo pattern is observed. On the other hand, when electron diffraction (also called nanobeam electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter close to or smaller than the size of the crystal region (for example, 1 nm to 30 nm), a region of high brightness is observed in a circular (ring-shaped) pattern, and multiple spots may be observed within this ring-shaped region.

[0286] nc-OS films have a lower defect level density than amorphous oxide semiconductor films. However, nc-OS films lack regularity in crystal orientation between different crystalline regions. Therefore, nc-OS films have a higher defect level density compared to CAAC-OS films. Consequently, nc-OS films may have a higher carrier concentration and higher electron mobility compared to CAAC-OS films. Therefore, transistors using nc-OS films may exhibit high field-effect mobility.

[0287] nc-OS films can be formed by reducing the oxygen flow rate ratio during deposition compared to CAAC-OS films. Furthermore, nc-OS films can also be formed by lowering the substrate temperature during deposition compared to CAAC-OS films. For example, nc-OS films can be deposited at relatively low substrate temperatures (e.g., below 130°C) or even without heating the substrate, making them suitable for use with large glass or resin substrates and increasing productivity.

[0288] An example of a metal oxide crystal structure is described below. Metal oxides formed by sputtering using an In-Ga-Zn oxide target (In:Ga:Zn = 4:2:4.1 [atomic ratio]) at a substrate temperature between 100°C and 130°C tend to adopt either an nc (nano crystal) structure or a CAAC structure, or a mixed structure of both. On the other hand, metal oxides formed at room temperature (RT) tend to adopt an nc crystal structure. Note that room temperature (RT) here includes the temperature when the substrate is not intentionally heated.

[0289] [Composition of metal oxides] The following describes the configuration of a CAC (Cloud-Aligned Composite)-OS that can be used in a transistor disclosed in one aspect of the present invention.

[0290] Note that CAAC (c-axis aligned crystal) represents an example of a crystal structure, while CAC (Cloud-Aligned Composite) represents an example of a function or material composition.

[0291] CAC-OS or CAC-metal oxide is a material that possesses conductive properties in some parts, insulating properties in others, and semiconductor properties as a whole. When CAC-OS or CAC-metal oxide is used as the active layer of a transistor, the conductive function is the function of allowing electrons (or holes) to flow, and the insulating function is the function of preventing electrons from flowing. By making the conductive and insulating functions work complementaryly, a switching function (on / off function) can be given to CAC-OS or CAC-metal oxide. By separating each function in CAC-OS or CAC-metal oxide, both functions can be maximized.

[0292] Furthermore, CAC-OS or CAC-metal oxide has conductive regions and insulating regions. The conductive regions have the conductive function described above, and the insulating regions have the insulating function described above. In addition, the conductive regions and insulating regions may be separated at the nanoparticle level within the material. Also, the conductive regions and insulating regions may be unevenly distributed within the material. Furthermore, the conductive regions may be observed as blurred around the edges and connected in a cloud-like manner.

[0293] Furthermore, in CAC-OS or CAC-metal oxide, conductive regions and insulating regions may be dispersed in the material with a size of 0.5 nm to 10 nm, preferably 0.5 nm to 3 nm.

[0294] Furthermore, CAC-OS or CAC-metal oxide is composed of components with different band gaps. For example, CAC-OS or CAC-metal oxide is composed of a component with a wide band gap due to an insulating region and a component with a narrow band gap due to a conductive region. In this configuration, when carriers flow, the carriers mainly flow in the component with the narrow band gap. In addition, the component with the narrow band gap acts complementaryly to the component with the wide band gap, and carriers also flow in the component with the wide band gap in conjunction with the component with the narrow band gap. For this reason, when the above CAC-OS or CAC-metal oxide is used in the channel formation region of a transistor, a high current driving force, i.e., a large on-current, and a high field-effect mobility can be obtained in the on-state of the transistor.

[0295] In other words, CAC-OS or CAC-metal oxide can also be referred to as a matrix composite or a metal matrix composite.

[0296] The above is an explanation of the composition of metal oxides.

[0297] The configuration examples illustrated in this embodiment, and the corresponding drawings, etc., can be implemented by appropriately combining at least a part of them with other configuration examples or drawings, etc.

[0298] This embodiment can be implemented in appropriate combination with other embodiments described herein, at least in part.

[0299] (Embodiment 2) This embodiment describes an example of a display device having the transistors illustrated in the previous embodiment.

[0300] [Example Configuration] Figure 11A shows a top view of the display device 700. The display device 700 has a first substrate 701 and a second substrate 705 bonded together by a sealing material 712. In the region sealed by the first substrate 701, the second substrate 705, and the sealing material 712, a pixel section 702, a source driver circuit section 704, and a gate driver circuit section 706 are provided on the first substrate 701. Multiple display elements are provided on the pixel section 702.

[0301] Furthermore, an FPC terminal section 708 is provided in the portion of the first substrate 701 that does not overlap with the second substrate 705, to which an FPC 716 (FPC: Flexible printed circuit) is connected. The FPC 716 supplies various signals to the pixel section 702, the source driver circuit section 704, and the gate driver circuit section 706, respectively, via the FPC terminal section 708 and the signal line 710.

[0302] Multiple gate driver circuits 706 may be provided. Furthermore, the gate driver circuit 706 and the source driver circuit 704 may each be formed separately on a semiconductor substrate or the like and packaged as an IC chip. This IC chip can be mounted on the first substrate 701 or on the FPC 716.

[0303] A transistor according to one aspect of the present invention can be applied to the transistors in the pixel section 702, the source driver circuit section 704, and the gate driver circuit section 706.

[0304] Examples of display elements provided in the pixel section 702 include liquid crystal elements and light-emitting elements. Liquid crystal elements can include transmissive liquid crystal elements, reflective liquid crystal elements, and semi-transmissive liquid crystal elements. Light-emitting elements include self-luminous light-emitting elements such as LEDs (Light Emitting Diodes), OLEDs (Organic LEDs), QLEDs (Quantum-dot LEDs), and semiconductor lasers. Furthermore, display elements employing shutter-type or optical interference-type MEMS (Micro Electro Mechanical Systems) elements, or those employing microcapsule-type, electrophoretic-type, electrowetting-type, or electronic powder fluid (registered trademark)-type methods can also be used.

[0305] The display device 700A shown in Figure 11B is an example of a display device that can be used as a flexible display, in which a flexible resin layer 743 is applied in place of the first substrate 701.

[0306] The display device 700A has a pixel section 702 that is not rectangular in shape, but has an arc-shaped corner. Also, as shown in region P1 in Figure 11B, the pixel section 702 and a part of the resin layer 743 have notches. A pair of gate driver circuit sections 706 are provided on both sides of the pixel section 702. The gate driver circuit sections 706 are also provided along the arc-shaped contour at the corners of the pixel section 702.

[0307] The resin layer 743 has a protruding shape in which the FPC terminal portion 708 is provided. Furthermore, a portion of the resin layer 743, including the FPC terminal portion 708, can be folded back to the other side in area P2 in Figure 11B. By folding back a portion of the resin layer 743, the display device 700A can be mounted on the electronic device with the FPC 716 overlapping the back of the pixel portion 702, thereby saving space in the electronic device.

[0308] Furthermore, IC717 is mounted on FPC716, which is connected to the display device 700A. IC717 functions, for example, as a source driver circuit. In this case, the source driver circuit section 704 in the display device 700A can be configured to include at least one of the following: a protection circuit, a buffer circuit, a demultiplexer circuit, etc.

[0309] The display device 700B shown in Figure 11C is a display device that can be suitably used in electronic devices having a large screen. For example, it can be suitably used in television equipment, monitor equipment, personal computers (including notebook or desktop types), tablet terminals, digital signage, and the like.

[0310] The display device 700B has multiple source driver ICs 721 and a pair of gate driver circuit sections 722.

[0311] Multiple source driver ICs 721 are each mounted on an FPC 723. Furthermore, one terminal of each FPC 723 is connected to the first board 701, and the other terminal is connected to the printed circuit board 724. By bending the FPC 723, the printed circuit board 724 can be positioned on the back of the pixel section 702, allowing it to be mounted in an electronic device and thus saving space in the electronic device.

[0312] On the other hand, the gate driver circuit section 722 is formed on the first substrate 701. This makes it possible to realize electronic devices with a narrow bezel.

[0313] This configuration makes it possible to realize large and high-resolution display devices. For example, it is possible to create display devices with screen sizes of 30 inches or more, 40 inches or more, 50 inches or more, or 60 inches or more diagonally. Furthermore, it is possible to create display devices with extremely high resolutions such as 4K2K or 8K4K.

[0314] [Example of cross-sectional configuration] Below, configurations using liquid crystal elements and EL elements as display elements will be explained with reference to Figures 12 to 15. Figures 12 to 14 are cross-sectional views along the dashed line QR shown in Figure 11A, respectively. Figure 15 is a cross-sectional view along the dashed line ST shown in Figure 11B. Figures 12 and 13 show configurations using liquid crystal elements as display elements, and Figures 14 and 15 show configurations using EL elements.

[0315] [Explanation of common parts of display devices] The display device shown in Figures 12 to 15 includes a wiring section 711, a pixel section 702, a source driver circuit section 704, and an FPC terminal section 708. The wiring section 711 has signal lines 710. The pixel section 702 has a transistor 750 and a capacitive element 790. The source driver circuit section 704 has a transistor 752. Figure 13 shows the case where the capacitive element 790 is absent.

[0316] Transistors 750 and 752 can be the transistors exemplified in Embodiment 1.

[0317] The transistor used in this embodiment has an oxide semiconductor film that has been purified to suppress the formation of oxygen vacancies. This transistor can reduce the off-current. Therefore, the holding time of electrical signals such as image signals can be extended, and the writing interval of image signals can also be set to a longer interval. As a result, the frequency of refresh operations can be reduced, which has the effect of reducing power consumption.

[0318] Furthermore, the transistors used in this embodiment can achieve relatively high field-effect mobility, enabling high-speed driving. For example, by using such high-speed drive transistors in a display device, the switching transistors in the pixel section and the driver transistors used in the driving circuit section can be formed on the same substrate. In other words, a configuration that does not require a driving circuit formed from a silicon wafer or the like is also possible, reducing the number of components in the display device. Moreover, by using high-speed drive transistors in the pixel section, high-quality images can be provided.

[0319] The capacitive element 790 shown in Figures 12, 14, and 15 has a lower electrode formed by processing the same film as the first gate electrode of the transistor 750, and an upper electrode formed by processing the same metal oxide as the semiconductor layer. The upper electrode has low resistance, similar to the source and drain regions of the transistor 750. Furthermore, a portion of the insulating film that functions as the first gate insulating layer of the transistor 750 is provided between the lower electrode and the upper electrode. In other words, the capacitive element 790 has a laminated structure in which an insulating film that functions as a dielectric film is sandwiched between a pair of electrodes. In addition, wiring obtained by processing the same film as the source and drain electrodes of the transistor is connected to the upper electrode.

[0320] Furthermore, a planar insulating film 770 is provided on transistors 750 and 752, and on the capacitive element 790.

[0321] The transistor 750 in the pixel unit 702 and the transistor 752 in the source driver circuit unit 704 may be transistors of different structures. For example, one may be a top-gate type transistor and the other a bottom-gate type transistor. The gate driver circuit unit 706 is the same as the source driver circuit unit 704.

[0322] The signal line 710 is formed by processing the same conductive film as the source and drain electrodes of transistors 750 and 752. In this case, it is preferable to use a low-resistance material such as a material containing copper, as this reduces signal delays caused by wiring resistance and enables display on a large screen.

[0323] The FPC terminal section 708 includes wiring 760, an anisotropic conductive film 780, and the FPC 716, with a portion of which functions as a connecting electrode. The wiring 760 is electrically connected to the terminals of the FPC 716 via the anisotropic conductive film 780. Here, the wiring 760 is formed by processing the same conductive film as the source electrodes and drain electrodes of transistors 750 and 752.

[0324] For the first substrate 701 and the second substrate 705, flexible substrates such as glass substrates or plastic substrates can be used. When a flexible substrate is used for the first substrate 701, it is preferable to provide an insulating layer that has barrier properties against water and hydrogen between the first substrate 701 and the transistor 750, etc.

[0325] Furthermore, the second substrate 705 is provided with a light-shielding film 738, a colored film 736, and an insulating film 734 in contact with these.

[0326] [Example configuration of a display device using liquid crystal elements] The display device 700 shown in Figure 12 has a liquid crystal element 775. The liquid crystal element 775 has a conductive layer 772, a conductive layer 774, and a liquid crystal layer 776 between them. The conductive layer 774 is provided on the second substrate 705 side and functions as a common electrode. The conductive layer 772 is electrically connected to the source electrode or drain electrode of the transistor 750. The conductive layer 772 is formed on the planarizing insulating film 770 and functions as a pixel electrode.

[0327] The conductive layer 772 can be made of a material that is transparent to visible light or a material that is reflective to visible light. For example, an oxide material containing indium, zinc, or tin may be used as the transparent material. For example, a material containing aluminum or silver may be used as the reflective material.

[0328] If a reflective material is used for the conductive layer 772, the display device 700 becomes a reflective liquid crystal display device. On the other hand, if a translucent material is used for the conductive layer 772, it becomes a transmissive liquid crystal display device. In the case of a reflective liquid crystal display device, a polarizing plate is provided on the viewing side. On the other hand, in the case of a transmissive liquid crystal display device, a pair of polarizing plates are provided so as to sandwich the liquid crystal elements.

[0329] The display device 700 shown in Figure 13 is an example that uses a transverse electric field type (e.g., FFS mode) liquid crystal element 775. A conductive layer 774, which functions as a common electrode, is provided on the conductive layer 772 via an insulating layer 773. The orientation state of the liquid crystal layer 776 can be controlled by the electric field generated between the conductive layer 772 and the conductive layer 774.

[0330] In Figure 13, the retaining capacitance can be configured by a laminated structure of conductive layer 774, insulating layer 773, and conductive layer 772. Therefore, there is no need to provide a separate capacitive element, and the aperture ratio can be increased.

[0331] Furthermore, although not shown in Figures 12 and 13, an alignment film in contact with the liquid crystal layer 776 may be provided. In addition, optical components (optical substrates) such as polarizing members, phase difference members, and anti-reflective members, as well as light sources such as backlights and sidelights, can be provided as appropriate.

[0332] The liquid crystal layer 776 can be made of thermotropic liquid crystal, low molecular weight liquid crystal, polymer liquid crystal, polymer dispersed liquid crystal (PDLC), polymer network liquid crystal (PNLC), ferroelectric liquid crystal, antiferroelectric liquid crystal, etc. Furthermore, when employing a transverse electric field method, a liquid crystal exhibiting a blue phase without an alignment layer may be used.

[0333] Furthermore, various modes can be used for the liquid crystal elements, including TN (Twisted Nematic) mode, VA (Vertical Alignment) mode, IPS (In-Plane-Switching) mode, FFS (Fringe Field Switching) mode, ASM (Axially Symmetric aligned Micro-cell) mode, OCB (Optically Compensated Birefringence) mode, ECB (Electrically Controlled Birefringence) mode, and guest host mode.

[0334] Furthermore, a scattering-type liquid crystal, such as a polymer-dispersed liquid crystal or a polymer-network liquid crystal, can be used in the liquid crystal layer 776. In this case, the configuration may be one that displays in black and white without a colored film 736, or one that displays in color using a colored film 736.

[0335] Furthermore, a time-division display method (also called a field sequential drive method) that performs color display based on a time-additive color mixing method may be applied as a driving method for the liquid crystal elements. In that case, a configuration without a colored film 736 can be used. When using a time-division display method, there is no need to provide subpixels that exhibit each of the colors, such as R (red), G (green), and B (blue), which has advantages such as improving the aperture ratio of the pixels and increasing the resolution.

[0336] [Display devices using light-emitting elements] The display device 700 shown in Figure 14 has a light-emitting element 782. The light-emitting element 782 has a conductive layer 772, an EL layer 786, and a conductive film 788. The EL layer 786 has a light-emitting material such as an organic compound or an inorganic compound.

[0337] As luminescent materials, fluorescent materials, phosphorescent materials, thermally activated delayed fluorescence (TADF) materials, and inorganic compounds (such as quantum dot materials) can be used.

[0338] The display device 700 shown in Figure 14 is provided with an insulating film 730 covering a portion of the conductive layer 772 on a planar insulating film 770. Here, the light-emitting element 782 has a translucent conductive film 788 and is a top-emission type light-emitting element that emits light towards the conductive film 788 side. The light-emitting element 782 may also have a bottom-emission structure that emits light towards the conductive layer 772 side, or a dual-emission structure that emits light towards both the conductive layer 772 side and the conductive film 788 side.

[0339] Furthermore, the colored film 736 is provided in a position overlapping with the light-emitting element 782, and the light-shielding film 738 is provided in a position overlapping with the insulating film 730, in the routing wiring section 711, and in the source driver circuit section 704. The colored film 736 and the light-shielding film 738 are covered with the insulating film 734. The space between the light-emitting element 782 and the insulating film 734 is filled with a sealing film 732. Note that when the EL layer 786 is formed in an island-like manner for each pixel or in a striped manner for each row of pixels, i.e., formed by color separation, the colored film 736 may be omitted.

[0340] Figure 15 shows a configuration of a display device that can be suitably applied to a flexible display. Figure 15 is a cross-sectional view of the display device 700A shown in Figure 11B along the dashed line ST.

[0341] The display device 700A shown in Figure 15 has a configuration in which a support substrate 745, an adhesive layer 742, a resin layer 743, and an insulating layer 744 are laminated, replacing the first substrate 701 shown in Figure 14. Transistors 750 and capacitive elements 790, etc., are provided on the insulating layer 744 which is provided on the resin layer 743.

[0342] The support substrate 745 is a substrate containing an organic resin or glass, and is thin enough to be flexible. The resin layer 743 is a layer containing an organic resin such as polyimide or acrylic. The insulating layer 744 contains an inorganic insulating film such as silicon oxide, silicon oxynitride, or silicon nitride. The resin layer 743 and the support substrate 745 are bonded together by an adhesive layer 742. It is preferable that the resin layer 743 is thinner than the support substrate 745.

[0343] Furthermore, the display device 700A shown in Figure 15 has a protective layer 740 instead of the second substrate 705 shown in Figure 14. The protective layer 740 is bonded to the sealing film 732. As the protective layer 740, a glass substrate or a resin film can be used. Alternatively, the protective layer 740 may be an optical component such as a polarizing plate or a scattering plate, an input device such as a touch sensor panel, or a configuration in which two or more of these are laminated.

[0344] Furthermore, the EL layer 786 of the light-emitting element 782 is provided in an island-like manner on the insulating film 730 and the conductive layer 772. By making the EL layer 786 emit light in different colors for each sub-pixel, color display can be achieved without using a colored film 736. In addition, a protective layer 741 is provided covering the light-emitting element 782. The protective layer 741 has the function of preventing impurities such as water from diffusing into the light-emitting element 782. It is preferable to use an inorganic insulating film for the protective layer 741. It is even more preferable to have a laminated structure containing one or more inorganic insulating films and one or more organic insulating films.

[0345] Figure 15 also shows the bendable region P2. Region P2 includes areas where no inorganic insulating film is provided, in addition to the support substrate 745 and adhesive layer 742, such as the insulating layer 744. Furthermore, a resin layer 746 is provided in region P2, covering the wiring 760. By minimizing the amount of inorganic insulating film in the bendable region P2 and by laminating only a conductive layer containing metal or alloy and a layer containing organic material, it is possible to prevent cracks from occurring when bent. In addition, by not providing the support substrate 745 in region P2, a part of the display device 700A can be bent with an extremely small radius of curvature.

[0346] [Example of a configuration in which an input device is provided to the display device] Furthermore, an input device may be provided in the display device 700 or display device 700A shown in Figures 12 to 15. Examples of such input devices include touch sensors.

[0347] For example, various sensor types can be used, such as capacitive, resistive, surface acoustic wave, infrared, optical, and pressure-sensitive types. Alternatively, two or more of these may be used in combination.

[0348] The configuration of the touch panel may include an in-cell type touch panel in which the input device is formed between a pair of circuit boards, an on-cell type touch panel in which the input device is formed on the display device 700, or an out-cell type touch panel in which the input device is attached to the display device 700.

[0349] The configuration examples illustrated in this embodiment, and the corresponding drawings, etc., can be implemented by appropriately combining at least a part of them with other configuration examples or drawings, etc.

[0350] This embodiment can be implemented in appropriate combination with other embodiments described herein, at least in part.

[0351] (Embodiment 3) In this embodiment, a display device having a semiconductor device according to one aspect of the present invention will be described with reference to Figure 16.

[0352] The display device shown in Figure 16A includes a pixel section 502, a drive circuit section 504, a protection circuit 506, and a terminal section 507. The protection circuit 506 may be omitted.

[0353] A transistor according to one aspect of the present invention can be applied to the transistors in the pixel section 502 and the drive circuit section 504. A transistor according to one aspect of the present invention may also be applied to the protection circuit 506.

[0354] The pixel unit 502 has multiple pixel circuits 501 that drive multiple display elements arranged in X rows and Y columns (where X and Y are each independent natural numbers of 2 or more).

[0355] The drive circuit section 504 includes drive circuits such as a gate driver 504a that outputs scan signals to gate lines GL_1 to GL_X, and a source driver 504b that supplies data signals to data lines DL_1 to DL_Y. The gate driver 504a may be configured to include at least a shift register. The source driver 504b may be configured using, for example, multiple analog switches. Alternatively, the source driver 504b may be configured using a shift register or the like.

[0356] The terminal section 507 refers to the part of the device that is equipped with terminals for inputting power, control signals, and image signals from an external circuit to the display device.

[0357] The protection circuit 506 is a circuit that causes a wiring to which it is connected to to become conductive when a potential outside a certain range is applied to that wiring. The protection circuit 506 shown in Figure 16A is connected to various wirings, such as the gate line GL, which is the wiring between the gate driver 504a and the pixel circuit 501, or the data line DL, which is the wiring between the source driver 504b and the pixel circuit 501.

[0358] Furthermore, the gate driver 504a and the source driver 504b may each be provided on the same substrate as the pixel section 502, or a separate substrate (for example, a drive circuit substrate made of a single-crystal semiconductor or polycrystalline semiconductor) on which the gate driver circuit or source driver circuit is formed may be mounted on the substrate by COG or TAB (Tape Automated Bonding).

[0359] Furthermore, the multiple pixel circuits 501 shown in Figure 16A can be configured as shown in Figures 16B and 16C, for example.

[0360] The pixel circuit 501 shown in Figure 16B includes a liquid crystal element 570, a transistor 550, and a capacitive element 560. Data lines DL_n, gate lines GL_m, potential supply lines VL, etc., are also connected to the pixel circuit 501.

[0361] The potential of one of the pair of electrodes of the liquid crystal element 570 is set appropriately according to the specifications of the pixel circuit 501. The orientation state of the liquid crystal element 570 is set by the data being written. A common potential (common potential) may be applied to one of the pair of electrodes of the liquid crystal element 570 in each of the multiple pixel circuits 501. Alternatively, different potentials may be applied to one of the pair of electrodes of the liquid crystal element 570 in each row of the pixel circuit 501.

[0362] Furthermore, the pixel circuit 501 shown in Figure 16C includes transistors 552 and 554, a capacitive element 562, and a light-emitting element 572. Data lines DL_n, gate lines GL_m, potential supply lines VL_a and VL_b are also connected to the pixel circuit 501.

[0363] A high power supply potential VDD is supplied to one of the potential supply lines VL_a and VL_b, and a low power supply potential VSS is supplied to the other. The current flowing through the light-emitting element 572 is controlled according to the potential supplied to the gate of transistor 554, thereby controlling the luminescence brightness from the light-emitting element 572.

[0364] The configuration examples illustrated in this embodiment, and the corresponding drawings, etc., can be implemented by appropriately combining at least a part of them with other configuration examples or drawings, etc.

[0365] This embodiment can be implemented in appropriate combination with other embodiments described herein, at least in part.

[0366] (Embodiment 4) The following describes a pixel circuit equipped with memory for correcting the gradation displayed on a pixel, and a display device having the same. The transistor exemplified in Embodiment 1 can be applied to the transistor used in the pixel circuit exemplified below.

[0367] [Circuit Configuration] Figure 17A shows the circuit diagram of the pixel circuit 400. The pixel circuit 400 includes transistor M1, transistor M2, capacitor C1, and circuit 401. Wiring S1, S2, G1, and G2 are connected to the pixel circuit 400.

[0368] Transistor M1 has its gate connected to wiring G1, one of its source and drain connected to wiring S1, and the other connected to one electrode of capacitor C1. Transistor M2 has its gate connected to wiring G2, one of its source and drain connected to wiring S2, the other connected to the other electrode of capacitor C1, and circuit 401.

[0369] Circuit 401 is a circuit that includes at least one display element. Various elements can be used as the display element, but typically, light-emitting elements such as organic EL elements and LED elements, liquid crystal elements, or MEMS (Micro Electro Mechanical Systems) elements can be applied.

[0370] Let node N1 be the node connecting transistor M1 and capacitor C1, and node N2 be the node connecting transistor M2 and circuit 401.

[0371] The pixel circuit 400 can maintain the potential of node N1 by turning off transistor M1. Similarly, it can maintain the potential of node N2 by turning off transistor M2. Furthermore, with transistor M2 in the off state, by writing a predetermined potential to node N1 via transistor M1, the potential of node N2 can be changed in accordance with the displacement of the potential of node N1 through capacitive coupling via capacitor C1.

[0372] Here, one or both of transistors M1 and M2 can be replaced with transistors that utilize an oxide semiconductor, as exemplified in Embodiment 1. Therefore, the potentials of nodes N1 and N2 can be maintained for a long period of time with an extremely low off-current. Note that if the period for maintaining the potential of each node is short (specifically, when the frame frequency is 30 Hz or higher), transistors using semiconductors such as silicon may be used.

[0373] [Example of driving method] Next, an example of how the pixel circuit 400 operates will be explained using Figure 17B. Figure 17B is a timing chart related to the operation of the pixel circuit 400. For the sake of simplicity, the effects of various resistors such as wiring resistance, parasitic capacitance of transistors and wiring, and the threshold voltage of transistors will not be considered here.

[0374] In the operation shown in Figure 17B, one frame period is divided into period T1 and period T2. Period T1 is the period during which the potential is written to node N2, and period T2 is the period during which the potential is written to node N1.

[0375] [Period T1] During period T1, a potential is applied to both wires G1 and G2 to turn the transistor ON. Additionally, a fixed potential V is applied to wire S1. ref The first data potential V is supplied to wiring S2. w To supply.

[0376] Node N1 receives a potential V from wiring S1 via transistor M1. ref The following is given. Also, node N2 has a first data potential V from wiring S2 via transistor M2. w Therefore, the potential difference V is given to capacitor C1. w -V ref This state is maintained.

[0377] [Period T2] Next, during period T2, a potential is applied to wiring G1 to turn on transistor M1, and a potential is applied to wiring G2 to turn off transistor M2. In addition, a second data potential V is applied to wiring S1. data The following is supplied: A predetermined constant potential may be applied to the wiring S2, or it may be left in a floating state.

[0378] Node N1 receives a second data potential V from wiring S1 via transistor M1. data The following is given. At this time, due to capacitive coupling by capacitance C1, the second data potential V data Accordingly, the potential of node N2 changes by a potential dV. That is, circuit 401 has a first data potential V w The input potential will be the sum of the potential dV and the second data potential V. Note that although Figure 17B shows the potential dV as a positive value, it can also be a negative value. That is, the second data potential V data The potential is V ref It can be even lower.

[0379] Here, the potential dV is roughly determined by the capacitance value of capacitor C1 and the capacitance value of circuit 401. If the capacitance value of capacitor C1 is sufficiently larger than the capacitance value of circuit 401, the potential dV is the second data potential V data The potential will be close to that.

[0380] In this way, the pixel circuit 400 can combine two types of data signals to generate a potential that is supplied to the circuit 401, which includes a display element, making it possible to perform grayscale correction within the pixel circuit 400.

[0381] Furthermore, the pixel circuit 400 can generate a potential exceeding the maximum potential that can be supplied to wiring S1 and wiring S2. For example, when using light-emitting elements, high dynamic range (HDR) display can be performed. Also, when using liquid crystal elements, overdrive driving can be realized.

[0382] [Examples of application] [Examples using liquid crystal elements] The pixel circuit 400LC shown in Figure 17C has circuit 401LC. Circuit 401LC has a liquid crystal element LC and a capacitor C2.

[0383] In a liquid crystal element (LC), one electrode is at node N2 and capacitance C2, while the other electrode is at potential V com2 Connect to the wiring provided. Capacitor C2 is connected when the other electrode is at potential V com1 Connect to the provided wiring.

[0384] Capacity C2 functions as the retention capacity. Note that capacity C2 can be omitted if it is not needed.

[0385] The 400LC pixel circuit can supply a high voltage to the liquid crystal element LC, enabling features such as high-speed display through overdrive driving and the application of liquid crystal materials with high drive voltages. Furthermore, by supplying a correction signal to wiring S1 or S2, the gradation can be corrected according to the operating temperature, the degradation state of the liquid crystal element LC, etc.

[0386] [Examples using light-emitting elements] The pixel circuit 400EL shown in Figure 17D has circuit 401EL. Circuit 401EL has a light-emitting element EL, a transistor M3, and a capacitor C2.

[0387] Transistor M3 has its gate connected to one electrode of node N2 and capacitance C2, and one of its source and drain connected to potential V. H One end of the wiring is connected to one electrode of the light-emitting element EL. Capacitor C2 is connected to the other electrode at potential V com Connect to the wiring provided. The light-emitting element EL has the other electrode at potential V L Connect to the provided wiring.

[0388] Transistor M3 controls the current supplied to the light-emitting element EL. Capacitor C2 functions as a retaining capacitor. Capacitor C2 can be omitted if not needed.

[0389] Note that although the configuration shown here connects the anode side of the light-emitting element EL to transistor M3, transistor M3 may also be connected to the cathode side. In that case, the potential V H and potential V L The value can be changed as needed.

[0390] The 400EL pixel circuit can supply a large current to the light-emitting element EL by applying a high potential to the gate of transistor M3, thereby enabling features such as HDR display. Furthermore, by supplying a correction signal to wiring S1 or S2, variations in the electrical characteristics of transistor M3 and the light-emitting element EL can be corrected.

[0391] Note that the circuit is not limited to those exemplified in Figures 17C and 17D; configurations with additional transistors, capacitors, etc., may also be used.

[0392] This embodiment can be implemented in appropriate combination with other embodiments described herein, at least in part.

[0393] (Embodiment 5) This embodiment describes a display module that can be manufactured using one aspect of the present invention.

[0394] The display module 6000 shown in Figure 18A has a display device 6006 with an FPC 6005 connected between an upper cover 6001 and a lower cover 6002, a frame 6009, a printed circuit board 6010, and a battery 6011.

[0395] For example, a display device manufactured using one aspect of the present invention can be used as the display device 6006. The display device 6006 makes it possible to realize a display module with extremely low power consumption.

[0396] The upper cover 6001 and the lower cover 6002 can be appropriately modified in shape and dimensions to match the size of the display device 6006.

[0397] The display device 6006 may also have the functionality of a touch panel.

[0398] Frame 6009 may have functions such as protecting the display device 6006, blocking electromagnetic waves generated by the operation of the printed circuit board 6010, and acting as a heat sink.

[0399] The printed circuit board 6010 includes a power supply circuit, a signal processing circuit for outputting video signals and clock signals, a battery control circuit, and the like.

[0400] Figure 18B is a schematic cross-sectional view of a display module 6000 equipped with an optical touch sensor.

[0401] The display module 6000 has a light-emitting section 6015 and a light-receiving section 6016 provided on the printed circuit board 6010. It also has a pair of light guides (light guide section 6017a, light guide section 6017b) in the area enclosed by the upper cover 6001 and the lower cover 6002.

[0402] The display device 6006 is mounted on top of the printed circuit board 6010 and battery 6011 with a frame 6009 in between. The display device 6006 and frame 6009 are fixed to the light guide section 6017a and light guide section 6017b.

[0403] Light 6018 emitted from the light-emitting unit 6015 passes over the top of the display device 6006 via the light guide unit 6017a, and then through the light guide unit 6017b to reach the light-receiving unit 6016. For example, touch operation can be detected when the light 6018 is blocked by an object to be detected, such as a finger or stylus.

[0404] Multiple light-emitting units 6015 are provided, for example, along two adjacent sides of the display device 6006. Multiple light-receiving units 6016 are provided at positions opposite the light-emitting units 6015. This makes it possible to acquire information about the location where a touch operation was performed.

[0405] The light-emitting unit 6015 can use a light source such as an LED element, and it is particularly preferable to use a light source that emits infrared rays. The light-receiving unit 6016 can use a photoelectric element that receives the light emitted by the light-emitting unit 6015 and converts it into an electrical signal. Preferably, a photodiode capable of receiving infrared rays can be used.

[0406] The light guides 6017a and 6017b, which transmit light 6018, allow the light-emitting unit 6015 and the light-receiving unit 6016 to be positioned below the display device 6006, thereby suppressing external light from reaching the light-receiving unit 6016 and causing the touch sensor to malfunction. In particular, using a resin that absorbs visible light and transmits infrared light can more effectively suppress touch sensor malfunctions.

[0407] This embodiment can be implemented in appropriate combination with other embodiments described herein, at least in part.

[0408] (Embodiment 6) This embodiment describes an example of an electronic device to which a display device according to one aspect of the present invention can be applied.

[0409] The electronic device 6500 shown in Figure 19A is a portable information terminal that can be used as a smartphone.

[0410] The electronic device 6500 has a housing 6501 and includes a display unit 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, and a light source 6508, etc. The display unit 6502 has a touch panel function.

[0411] A display device according to one aspect of the present invention can be applied to the display unit 6502.

[0412] Figure 19B is a schematic cross-sectional view of the housing 6501, including the end on the microphone 6506 side.

[0413] A light-transmitting protective member 6510 is provided on the display side of the housing 6501, and the display panel 6511, optical member 6512, touch sensor panel 6513, printed circuit board 6517, battery 6518, etc. are arranged in the space enclosed by the housing 6501 and the protective member 6510.

[0414] The protective member 6510 is fixed to the display panel 6511, the optical member 6512, and the touch sensor panel 6513 by an adhesive layer (not shown).

[0415] Furthermore, a portion of the display panel 6511 is folded back in the area outside the display unit 6502. The FPC 6515 is connected to this folded portion. IC 6516 is mounted on the FPC 6515. The FPC 6515 is also connected to terminals provided on the printed circuit board 6517.

[0416] A flexible display panel according to one embodiment of the present invention can be applied to the display panel 6511. This makes it possible to realize an extremely lightweight electronic device. Furthermore, because the display panel 6511 is extremely thin, it is possible to incorporate a large-capacity battery 6518 while keeping the thickness of the electronic device low. In addition, by folding back a part of the display panel 6511 and placing the connection part with the FPC 6515 on the back of the pixel area, a narrow-bezel electronic device can be realized.

[0417] This embodiment can be implemented in appropriate combination with other embodiments described herein, at least in part.

[0418] (Embodiment 7) This embodiment describes an electronic device equipped with a display device manufactured using one aspect of the present invention.

[0419] The electronic device described below is equipped with a display device according to one embodiment of the present invention in its display unit. Therefore, it is an electronic device that achieves high resolution. Furthermore, it is possible to create an electronic device that achieves both high resolution and a large screen.

[0420] The display unit of an electronic device according to one aspect of the present invention can display video having a resolution of, for example, Full HD, 4K2K, 8K4K, 16K8K, or higher.

[0421] Examples of electronic devices include those with relatively large screens, such as television sets, notebook computers, monitors, digital signage, pachinko machines, and game consoles, as well as digital cameras, digital video cameras, digital photo frames, mobile phones, portable game consoles, personal digital assistants, and audio playback devices.

[0422] An electronic device to which one aspect of the present invention is applied can be incorporated along a flat or curved surface of the interior or exterior walls of a house or building, the interior or exterior of an automobile, etc.

[0423] Figure 20A shows the external appearance of the camera 8000 with the viewfinder 8100 attached.

[0424] The camera 8000 includes a housing 8001, a display unit 8002, operation buttons 8003, a shutter button 8004, etc. The camera 8000 also has a detachable lens 8006 attached.

[0425] The camera 8000 may have the lens 8006 and the housing integrated into a single unit.

[0426] Camera 8000 can take an image by pressing the shutter button 8004 or by touching the display unit 8002, which functions as a touch panel.

[0427] The housing 8001 has a mount with electrodes, and in addition to the viewfinder 8100, a strobe device and the like can be connected to it.

[0428] The viewfinder 8100 includes a housing 8101, a display unit 8102, buttons 8103, etc.

[0429] The housing 8101 is attached to the camera 8000 by a mount that engages with the camera 8000's mount. The viewfinder 8100 can display images and other data received from the camera 8000 on the display unit 8102.

[0430] Button 8103 functions as a power button, etc.

[0431] A display device according to one embodiment of the present invention can be applied to the display unit 8002 of the camera 8000 and the display unit 8102 of the viewfinder 8100. The camera 8000 may also have a built-in viewfinder.

[0432] Figure 20B shows the external appearance of the head-mounted display 8200.

[0433] The head-mounted display 8200 includes a mounting section 8201, lenses 8202, a main unit 8203, a display unit 8204, a cable 8205, etc. The mounting section 8201 also has a built-in battery 8206.

[0434] Cable 8205 supplies power from battery 8206 to main unit 8203. Main unit 8203 is equipped with a wireless receiver and can display received video information on display unit 8204. In addition, main unit 8203 is equipped with a camera and can use information about the user's eyeball and eyelid movements as an input means.

[0435] Furthermore, the attachment unit 8201 may be provided with multiple electrodes at a position that touches the user, capable of detecting the current flowing in accordance with the user's eye movements, and may have a function to recognize the user's gaze. It may also have a function to monitor the user's pulse rate based on the current flowing through the electrodes. In addition, the attachment unit 8201 may have various sensors such as a temperature sensor, a pressure sensor, and an acceleration sensor, and may have a function to display the user's biometric information on the display unit 8204, or a function to change the image displayed on the display unit 8204 in accordance with the user's head movements.

[0436] A display device according to one aspect of the present invention can be applied to the display unit 8204.

[0437] Figures 20C, 20D, and 20E show the external appearance of the head-mounted display 8300. The head-mounted display 8300 comprises a housing 8301, a display unit 8302, a band-shaped fixing device 8304, and a pair of lenses 8305.

[0438] The user can view the display on the display unit 8302 through the lens 8305. It is preferable to position the display unit 8302 in a curved shape, as this allows the user to experience a greater sense of presence. Furthermore, by viewing different images displayed in different areas of the display unit 8302 through the lens 8305, three-dimensional display using parallax can be performed. Note that the configuration is not limited to a single display unit 8302; two display units 8302 may be provided, with one display unit for each of the user's eyes.

[0439] Furthermore, a display device according to one embodiment of the present invention can be applied to the display unit 8302. Because the display device having the semiconductor device according to one embodiment of the present invention has extremely high resolution, even when magnified using the lens 8305 as shown in Figure 20E, the user cannot see the pixels, and a more realistic image can be displayed.

[0440] The electronic equipment shown in Figures 21A to 21G includes a housing 9000, a display unit 9001, a speaker 9003, operation keys 9005 (including a power switch or operation switch), connection terminals 9006, sensors 9007 (including functions for measuring force, displacement, position, velocity, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared radiation), a microphone 9008, etc.

[0441] The electronic devices shown in Figures 21A to 21G have various functions. For example, they may have functions to display various information (still images, videos, text images, etc.) on a display unit, a touch panel function, a function to display a calendar, date or time, a function to control processing by various software (programs), a wireless communication function, a function to read and process programs or data recorded on a recording medium, etc. However, the functions of electronic devices are not limited to these and can have various functions. Electronic devices may have multiple display units. Furthermore, electronic devices may be equipped with a camera, etc., and have functions to capture still images and videos and save them to a recording medium (external or built into the camera), a function to display the captured images on a display unit, etc.

[0442] Details of the electronic equipment shown in Figures 21A to 21G will be explained below.

[0443] Figure 21A is a perspective view showing the television system 9100. The television system 9100 can incorporate a large screen, for example, a display unit 9001 of 50 inches or more, or 100 inches or more.

[0444] Figure 21B is a perspective view showing a personal digital assistant (PDA) 9101. The PDA 9101 can be used, for example, as a smartphone. The PDA 9101 may also be equipped with a speaker 9003, connection terminals 9006, sensors 9007, etc. The PDA 9101 can also display text and image information on multiple surfaces. Figure 21B shows an example where three icons 9050 are displayed. Information 9051, indicated by a dashed rectangle, can also be displayed on other surfaces of the display unit 9001. Examples of information 9051 include notifications of incoming emails, SNS messages, and phone calls, the subject of emails and SNS messages, the sender's name, date and time, battery level, and antenna signal strength. Alternatively, icons 9050 or the like may be displayed in the location where the information 9051 is displayed.

[0445] Figure 21C is a perspective view showing the personal digital assistant (PDA) 9102. The PDA 9102 has the function of displaying information on three or more sides of the display unit 9001. Here, an example is shown in which information 9052, information 9053, and information 9054 are displayed on different sides. For example, a user can check information 9053, which is displayed in a position that can be observed from above the PDA 9102, while the PDA 9102 is stored in the breast pocket of their clothing. The user can check the display without taking the PDA 9102 out of their pocket and decide, for example, whether or not to answer a call.

[0446] Figure 21D is a perspective view showing a wristwatch-type personal information terminal 9200. The display unit 9001 has a curved display surface, allowing it to display information along the curved surface. The personal information terminal 9200 can also make hands-free calls by communicating with, for example, a wireless headset. Furthermore, the personal information terminal 9200 can transmit data to other information terminals and be charged via a connection terminal 9006. Charging may be performed by wireless power supply.

[0447] Figures 21E, 21F, and 21G are perspective views showing a foldable personal information terminal 9201. Figure 21E shows the personal information terminal 9201 in an unfolded state, Figure 21G shows it in a folded state, and Figure 21F shows a perspective view of the state in between Figures 21E and 21G. The personal information terminal 9201 offers excellent portability in its folded state and excellent readability of the display due to its seamless, wide display area in its unfolded state. The display unit 9001 of the personal information terminal 9201 is supported by three housings 9000 connected by a hinge 9055. For example, the display unit 9001 can be bent with a radius of curvature of 1 mm to 150 mm.

[0448] Figure 22A shows an example of a television system. The television system 7100 has a display unit 7500 incorporated into a housing 7101. Here, the housing 7101 is shown supported by a stand 7103.

[0449] The television device 7100 shown in Figure 22A can be operated using the operation switches on the housing 7101 or a separate remote control unit 7111. Alternatively, a touch panel may be applied to the display unit 7500, and the television device 7100 may be operated by touching it. The remote control unit 7111 may have a display unit in addition to operation buttons.

[0450] The television equipment 7100 may also include a television broadcast receiver and a communication device for network connectivity.

[0451] Figure 22B shows the notebook personal computer 7200. The notebook personal computer 7200 has a casing 7211, a keyboard 7212, a pointing device 7213, an external connection port 7214, etc. A display unit 7500 is incorporated into the casing 7211.

[0452] Figures 22C and 22D show examples of digital signage.

[0453] The digital signage 7300 shown in Figure 22C includes a housing 7301, a display unit 7500, and a speaker 7303, etc. Furthermore, it may include LED lamps, operation keys (including a power switch or operation switch), connection terminals, various sensors, a microphone, etc.

[0454] Figure 22D also shows a digital signage 7400 mounted on a cylindrical column 7401. The digital signage 7400 has a display unit 7500 that is provided along the curved surface of the column 7401.

[0455] The larger the display area 7500, the more information can be provided at once, and because it is more eye-catching, it can have the effect of enhancing the promotional effect of advertisements, for example.

[0456] It is preferable to apply a touch panel to the display unit 7500 so that the user can operate it. This allows it to be used not only for advertising purposes but also for providing information that the user needs, such as route information, traffic information, and information on commercial facilities.

[0457] Furthermore, as shown in Figures 22C and 22D, it is preferable that the digital signage 7300 or digital signage 7400 can be linked wirelessly with an information terminal 7311 such as a smartphone owned by the user. For example, the information of the advertisement displayed on the display unit 7500 can be displayed on the screen of the information terminal 7311, or the display on the display unit 7500 can be switched by operating the information terminal 7311.

[0458] Furthermore, the digital signage 7300 or digital signage 7400 can be used to run games using the information terminal 7311 as the control device (controller). This allows a large number of users to participate in and enjoy the game simultaneously.

[0459] A display device according to one embodiment of the present invention can be applied to the display unit 7500 in Figures 22A to 22D.

[0460] Although the electronic device in this embodiment has a display unit, one aspect of the present invention can also be applied to electronic devices that do not have a display unit.

[0461] This embodiment can be implemented in appropriate combination with other embodiments described herein, at least in part. [Examples]

[0462] In this example, the relationship between carrier concentration, sheet resistance, and Fermi level in an oxide semiconductor will be explained.

[0463] In general, the relationship between the carrier concentration and sheet resistance of a semiconductor is known to satisfy the following equation (1), where n is the carrier concentration, Rs is the sheet resistance, e is the elementary charge, μ is the mobility, and t is the film thickness.

[0464]

number

[0465] Figure 23A shows the measurement results of the carrier concentration n and sheet resistance Rs of an oxide semiconductor film, measured using the Hall effect.

[0466] The data shown in Figure 23A represent measurements taken for oxide semiconductor films deposited using a sputtering target of a metal oxide with a metal elemental composition of In:Zn:Ga = 4:2:4.1 [atomic ratio]. Figure 23A plots data for 18 different samples with varying carrier concentrations, prepared by different oxygen supply conditions to the oxide semiconductor film and the subsequent bake temperature. The thickness of the oxide semiconductor film in each sample is approximately 40 nm.

[0467] Figure 23B shows the measured values ​​for oxide semiconductor films deposited using a sputtering target of a metal oxide with a metal element composition of In:Zn:Ga=1:1:1 [atomic ratio]. Figure 23B plots data for 15 different samples with varying carrier concentrations, similar to the above. The thickness of the oxide semiconductor film in each sample is approximately 40 nm.

[0468] As shown in Figures 23A and 23B, an inverse correlation is observed between the carrier concentration n and the sheet resistance Rs, satisfying equation (1). Furthermore, it can be confirmed that these relationships show a similar trend regardless of the composition of the oxide semiconductor film.

[0469] Next, we will explain the relationship between carrier concentration and Fermi level in oxide semiconductors.

[0470] Figure 24 shows the relationship between the carrier concentration n and the Fermi level Ef in an In-Ga-Zn oxide film with a metal element composition of In:Zn:Ga = 4:2:3 [atomic ratio]. Here, the results calculated at a temperature of 300 K are shown.

[0471] As shown in Figure 24, the Fermi level Ef depends on the carrier concentration n, and the higher the carrier concentration n, the closer it is to the lower end (Ec) of the conduction band. For example, when the carrier concentration n is 1×10 12 cm -3 , the Fermi level Ef is located about 0.4 eV below the lower end (Ec) of the conduction band. Also, when the carrier concentration n is 1×10 -6 cm -3 , the Fermi level Ef approximately coincides with the intrinsic Fermi level (Ei).

[0472] In the case of an In-Ga-Zn oxide film with a metal element composition of In:Zn:Ga = 1:1:1 [atomic ratio], the carrier concentration at which the Fermi level Ef approximately coincides with the intrinsic Fermi level (Ei) is 1×10 -9 cm -3 .

[0473] In a transistor using an oxide semiconductor film, the criterion for the carrier concentration (donor concentration) in the oxide semiconductor film for obtaining normally-off electrical characteristics is generally 1×10 16 cm -3 or less. When the carrier concentration is less than that, the oxide semiconductor can be regarded as substantially i-type. According to Figure 24, it can be seen that the Fermi level Ef when the carrier concentration n is 1×10 16 cm -3 exists at a position close to the lower end (Ec) of the conduction band.

Explanation of symbols

[0474] 10, 10A, 10B, 10C: Transistors, 100, 100A: Transistors, 102: Substrate, 103: Insulating layer, 103a, 103b, 103b1, 103b2, 103b3: Insulating film, 106, 112, 120a, 120b: Conductive layer, 108, 108a, 108b: Semiconductor layer, 108C, 108L1, 108L2, 108N: Regions, 110, 116, 118: Insulating layer, 110a, 110b, 110c, 110f: Insulating film, 112f: Conductive film, 114: Metal oxide layer, 114f: Metal oxide film, 115: Insulating region, 140: Resist mask, 141a, 141b, 142: Openings

Claims

1. A semiconductor device having a transistor, The first insulating layer above the substrate, The oxide semiconductor layer above the first insulating layer, A second insulating layer having a region in contact with the upper surface of the oxide semiconductor layer and functioning as a gate insulating layer, A metal oxide layer having a region in contact with the upper surface of the second insulating layer, A first conductive layer having a region in contact with the upper surface of the metal oxide layer and a region overlapping with the oxide semiconductor layer via the metal oxide layer and the second insulating layer, A third insulating layer having a region in contact with the upper surface of the first conductive layer, The material comprises a second conductive layer provided above the third insulating layer and electrically connected to the oxide semiconductor layer through an opening provided in the third insulating layer, In a cross-sectional view of the transistor in the channel length direction, the end of the second insulating layer is located on the upper surface of the oxide semiconductor layer. In the cross-sectional view, the end of the metal oxide layer is located on the upper surface of the second insulating layer. In the cross-sectional view, the first conductive layer has a first portion that protrudes from the edge of the metal oxide layer and does not overlap with the metal oxide layer. In the cross-sectional view, the first portion is located above the second insulating layer and does not protrude from the edge of the second insulating layer. The third insulating layer has a region in contact with the upper surface of the oxide semiconductor layer, a region in contact with the side surface of the second insulating layer, a region in contact with the second portion of the second insulating layer, a region in contact with the third portion of the second insulating layer, and a region in contact with the side surface of the first conductive layer. The second portion does not overlap with the first conductive layer and has a first thickness. The third portion overlaps with the first conductive layer and has a second thickness. The first thickness is smaller than the second thickness. In a cross-sectional view, the second insulating layer has a fourth portion between the second portion and the third portion that does not overlap with the first conductive layer and has a tapered shape, wherein the semiconductor device is a semiconductor device.

2. A semiconductor device having a transistor, The first insulating layer above the substrate, The oxide semiconductor layer above the first insulating layer, A second insulating layer having a region in contact with the upper surface of the oxide semiconductor layer and functioning as a gate insulating layer, A metal oxide layer having a region in contact with the upper surface of the second insulating layer, A first conductive layer having a region in contact with the upper surface of the metal oxide layer and a region overlapping with the oxide semiconductor layer via the metal oxide layer and the second insulating layer, A third insulating layer having a region in contact with the upper surface of the first conductive layer, The material comprises a second conductive layer provided above the third insulating layer and electrically connected to the oxide semiconductor layer through an opening provided in the third insulating layer, In a cross-sectional view of the transistor in the channel length direction, the end of the second insulating layer is located on the upper surface of the oxide semiconductor layer. In the cross-sectional view, the end of the metal oxide layer is located on the upper surface of the second insulating layer. In the cross-sectional view, the first conductive layer has a first portion that protrudes from the edge of the metal oxide layer and does not overlap with the metal oxide layer. In the cross-sectional view, the first portion is located above the second insulating layer and does not protrude from the edge of the second insulating layer. The third insulating layer has a region in contact with the upper surface of the oxide semiconductor layer, a region in contact with the side surface of the second insulating layer, a region in contact with the second portion of the second insulating layer, a region in contact with the third portion of the second insulating layer, a region in contact with the side surface of the metal oxide layer, and a region in contact with the side surface of the first conductive layer. The second portion does not overlap with the first conductive layer and has a first thickness. The third portion overlaps with the first conductive layer and has a second thickness. The first thickness is smaller than the second thickness. In a cross-sectional view, the second insulating layer has a fourth portion between the second portion and the third portion that does not overlap with the first conductive layer and has a tapered shape, wherein the semiconductor device is a semiconductor device.

Images