Group III element nitride semiconductor substrate

Abstract

Provided is a group III element nitride semiconductor substrate which includes a first face and a second face and has a large diameter and with which the occurrence of chipping defects is suppressed when manufacturing a device. A group III element nitride semiconductor substrate according to an embodiment of the present invention includes a first face and a second face, and has a thickness of at least 100 μm, wherein: when, on a straight line from a centroid position on the surface of the first face to a centroid position on the surface of the second face, peak wave numbers corresponding to the E2 H phonon modes are measured at intervals of 5 μm from a spot corresponding to 5 μm inward from the surface of the first face to a spot corresponding to half of the thickness of the substrate and from a spot corresponding to 5 μm inward from the surface of the second face to a spot corresponding to half of the thickness of the substrate, and n peak wave numbers obtained through the measurement are B1-Bn (where n is the number of peak wave numbers measured and an integer obtained by rounding up digits after the decimal point of [(thickness (μm) of group III element nitride semiconductor substrate–5 (μm)) / 5 (μm)]), in order from the side of the surface of the first face, the difference (Bmax-Bmin) between the maximum peak wave number Bmax and the minimum peak wave number Bmin among the n measured values is at most 2.0 cm-1.

Description

[Technical Field]

[0001] The present invention relates to a group III element nitride semiconductor substrate. More specifically, to a group III element nitride semiconductor substrate having a front and back surface, wherein the occurrence of chipping defects during device fabrication is suppressed. [Background technology]

[0002] Group III element nitride semiconductor substrates such as gallium nitride (GaN) wafers, aluminum nitride (AlN) wafers, and indium nitride (InN) wafers are used as substrates for various semiconductor devices (for example, Patent Document 1).

[0003] A semiconductor substrate comprises a first surface and a second surface. When the first surface is considered the main surface and the second surface the back surface, the main surface is typically a Group III element polar surface, and the back surface is typically a nitrogen polar surface. Epitaxial crystals can be grown on the main surface, and various devices can be fabricated.

[0004] Group III element nitride semiconductor substrates are used as base substrates for semiconductor devices such as LEDs and LDs.

[0005] In gallium nitride substrates, defects such as cracks, chips, and chipping are prone to occur during device fabrication. It is known that such defects are more likely to occur when the difference in residual stress within the substrate is large (Patent Documents 2-4). As a method for evaluating such residual stress within the substrate, Raman analysis is generally used, and E2 H Residual stress is evaluated based on the wavenumber of the peak corresponding to the phonon mode. It is believed that a larger change in wavenumber corresponds to a larger change in residual stress.

[0006] In Patent Document 2, the area is 10 cm². 2 E2 within the region excluding the area from the periphery of the surface to 5 mm inward. H The difference between the maximum and minimum values ​​of the Raman shift corresponding to the phonon mode is 0.5 cm. -1A gallium nitride substrate as described below has been reported.

[0007] In Patent Document 3, the difference between the maximum value and the minimum value of the peak frequencies corresponding to the E2 H phonon modes at a total of five locations, namely the center and four peripheral locations on the surface, is 0.1 cm -1 or more and 1 cm -1 or less, for a gallium nitride substrate with a diameter of 150 mm or more has been reported.

[0008] In Patent Document 4, the difference between the surface centroid position and the back surface centroid position of the Raman shift amount corresponding to the E2 H phonon mode is 0.1 cm -1 or more and 0.5 cm -1 or less, and the difference between the surface centroid position and the periphery is 0.1 cm -1 or more and 0.5 cm -1 or less, for a gallium nitride substrate with an area of 18 cm 2 or more has been reported.

[0009] On the other hand, a semiconductor device fabricated on a gallium nitride substrate is then diced together with the substrate. When chipping defects occur in the gallium nitride substrate during this dicing process, there is a problem that the yield of the device decreases.

Prior Art Documents

Patent Documents

[0010]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Summary of the Invention

Problems to be Solved by the Invention

[0011] The object of the present invention is to provide a group III element nitride semiconductor substrate having a first surface and a second surface, wherein the occurrence of chipping defects during device fabrication is suppressed. [Means for solving the problem]

[0012] [1] A group III element nitride semiconductor substrate according to an embodiment of the present invention is a group III element nitride semiconductor substrate comprising a first surface and a second surface. The substrate has a thickness of 100 μm or more; and along a straight line from the centroid position of the surface of the first surface to the centroid position of the surface of the second surface, E2 is present at 5 μm intervals from a point 5 μm inward from the surface of the first surface to a point half the thickness of the substrate, and from a point 5 μm inward from the surface of the second surface to a point half the thickness of the substrate. H When measuring the peak wavenumbers corresponding to the phonon modes, the n peak wavenumbers are defined as B1 to Bn in order from the surface side of the first surface (where n is the number of peak wavenumber measurements, and is an integer obtained by rounding up the decimal part of [(thickness of the group III element nitride semiconductor substrate (μm) - 5 (μm)) / 5 (μm)]), and the maximum peak wavenumber among the n measured values ​​is B max and the minimum peak wavenumber B min The difference (B max -B min ) is 2.0cm -1 The following applies: [2] In the above [1], Difference (B max -B min ) All are 1.5 cm -1 The following applies: [3] In the above [2], Difference (B max -B min ) All are 1.0 cm -1 The following applies: [4] In any of the above [1] to [3], the n peak wavenumbers fluctuate in such a way that they define a peak-and-valley shaped fluctuation curve in the thickness direction of the substrate. [5] In any of the above [1] to [4], the Group III element nitride semiconductor substrate has a diameter of 45 mm or more. [6] In any of the above [1] to [5], the thickness is 300 μm or more. [7]According to another aspect of the present invention, a bonded substrate is provided, which is formed by bonding a support substrate to any of the Group III element nitride semiconductor substrates described in [1] to [6] above. [Effects of the Invention]

[0013] According to embodiments of the present invention, it is possible to provide a group III element nitride semiconductor substrate having a first surface and a second surface, wherein the occurrence of chipping defects during device fabrication is suppressed. [Brief explanation of the drawing]

[0014] [Figure 1] This is a typical schematic cross-sectional view of a group III element nitride semiconductor substrate according to an embodiment of the present invention. [Figure 2] This is an optical microscope image of the end face of the chip obtained in Example 3. [Figure 3] This is an optical microscope image of the end face of the chip obtained in Comparative Example 1. [Figure 4] This is a conceptual graph illustrating the fluctuation state of the peak wavenumber corresponding to the E2 H phonon mode along the thickness direction of the substrate in an embodiment of the present invention. [Figure 5] This graph shows the fluctuation state of the peak wavenumber corresponding to the E2 H phonon mode along the thickness direction of the substrate in Example 3. [Figure 6] This graph shows the fluctuation state of the peak wavenumber corresponding to the E2 H phonon mode along the thickness direction of the substrate in Comparative Example 1. [Modes for carrying out the invention]

[0015] Where the term "weight" appears in this specification, it may be interpreted as "mass," which is the commonly used SI unit for weight.

[0016] The Group III element nitride semiconductor substrate according to embodiments of the present invention is typically a self-supporting substrate made of a Group III element nitride crystal. In this specification, "self-supporting substrate" means a substrate that does not deform or break under its own weight when handled and can be handled as a solid object. Self-supporting substrates can be used as substrates for various semiconductor devices such as light-emitting elements and power control elements.

[0017] The group III element nitride semiconductor substrate according to the embodiment of the present invention is typically wafer-shaped (approximately circular). However, it may be processed into other shapes, such as rectangles, as needed.

[0018] The size (diameter) of the group III element nitride semiconductor substrate according to the embodiments of the present invention can be any appropriate size as long as it does not impair the effects of the embodiments of the present invention. Examples of such sizes include 25 mm (approximately 1 inch), 45-55 mm (approximately 2 inches), 95-105 mm (approximately 4 inches), 145-155 mm (approximately 6 inches), 195-205 mm (approximately 8 inches), and 295-305 mm (approximately 12 inches). The size (diameter) of the group III element nitride semiconductor substrate according to the embodiments of the present invention is preferably 45 mm or more, and more preferably 50 mm or more.

[0019] The group III element nitride semiconductor substrate according to the embodiment of the present invention has a thickness of 100 μm or more (or the thickness at the thickest point if the thickness is not constant), preferably 300 μm to 1000 μm.

[0020] Typical examples of Group III element nitrides include gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), or mixed crystals thereof. These may consist of one element or two or more elements.

[0021] Group III element nitrides specifically include GaN, AlN, InN, and Ga x Al 1-x N(1>x>0), Ga x In 1-x N(1>x>0), Al x In 1-x N(1>x>0), Ga x Al y In z These are N(1>x>0, 1>y>0, x+y+z=1). These may be doped with various n-type or p-type dopants.

[0022] Typical p-type dopants include zinc (Zn), manganese (Mn), iron (Fe), beryllium (Be), magnesium (Mg), strontium (Sr), and cadmium (Cd). These may be present individually or in combination of two or more elements.

[0023] Typical n-type dopants include silicon (Si), germanium (Ge), tin (Sn), and oxygen (O). These may be present individually or in combination of two or more.

[0024] The plane orientation of the group III element nitride semiconductor substrate can be the c-plane, m-plane, a-plane, or specific crystal planes tilted from the c-plane, a-plane, or m-plane, and the effects of the embodiments of the present invention are particularly evident when the plane is the c-plane. Examples of specific crystal planes tilted from the c-plane, a-plane, or m-plane include so-called semipolar planes such as the {11-22} plane and the {20-21} plane. Furthermore, the plane orientation can include not only so-called just planes perpendicular to the c-plane, a-plane, m-plane, or specific crystal planes tilted from them, but also off-angles within a range of ±5°.

[0025] The Group III element nitride semiconductor substrate according to an embodiment of the present invention is a Group III element nitride semiconductor substrate having a first surface and a second surface. When the first surface is the main surface and the second surface is the back surface, if the surface orientation of the Group III element nitride semiconductor substrate is the c-plane, the main surface is typically the Group III element polar surface, and the back surface is typically the nitrogen polar surface. However, the main surface may be the nitrogen polar surface, or the back surface may be the Group III element polar surface. Epitaxial crystals can be grown on the main surface, and various devices can be fabricated. The back surface can be held by a susceptor or the like, allowing the Group III element nitride semiconductor substrate according to the embodiment of the present invention to be transported.

[0026] In describing the Group III element nitride semiconductor substrate according to embodiments of the present invention, the first surface will be described as the main surface and the second surface as the back surface. Therefore, in this specification, "main surface" may be read as "first surface," "first surface" may be read as "main surface," "back surface" may be read as "second surface," and "second surface" may be read as "back surface."

[0027] The main surface may be mirror-finished or non-mirror-finished. Preferably, the main surface is mirror-finished.

[0028] From the viewpoint of obtaining a semiconductor device with good device characteristics and little variation in device characteristics between devices, it is preferable that the main surface has substantially removed the processed altered layer and has low surface roughness in the microscopic region, achieved by epitaxial growth of the device layer.

[0029] The reverse side may be either mirrored or non-mirror-finished.

[0030] A mirror-finished surface is a surface that has been polished to a mirror finish. After polishing, the surface roughness and waviness have been reduced to the point where light reflects off the polished surface, allowing the viewer to visually confirm the reflection of an object. In other words, the surface roughness and waviness after polishing have been reduced to a level that is negligible with respect to the wavelength of visible light. Epitaxial crystal growth is entirely possible on a mirror-finished surface.

[0031] As for the method of mirror finishing, any suitable method can be adopted as long as it does not impair the effects of the embodiments of the present invention. Examples of such methods include using one or a combination of a polishing device using tape, a lapping device using diamond abrasive grains, or a CMP (Chemical Mechanical Polish) device using a slurry such as colloidal silica and a nonwoven polishing pad to perform mirror finishing. If a processed altered layer remains on the surface after processing, the processed altered layer is removed. Examples of methods for removing the processed altered layer include using RIE (Reactive Ion Etching) or chemical solutions to remove the processed altered layer, or annealing the substrate.

[0032] A non-mirror surface is a surface that has not been polished to a mirror finish, and a typical example is a rough surface obtained through a surface roughening treatment.

[0033] As for the surface roughening treatment method, any suitable method can be adopted as long as it does not impair the effects of the embodiments of the present invention. Examples of such methods include grinding using a grinding wheel, laser texturing, etching using various chemicals or gases, physical or chemical coating, and texturing by machining.

[0034] Figure 1 is a typical schematic cross-sectional view of a group III element nitride semiconductor substrate according to an embodiment of the present invention. As shown in Figure 1, the group III element nitride semiconductor substrate 100 according to an embodiment of the present invention typically has a main surface (group III element polar surface) 10 and a back surface (nitrogen polar surface) 20. The group III element nitride semiconductor substrate 100 according to an embodiment of the present invention may also have a side surface 30.

[0035] The edges of the group III element nitride semiconductor substrate according to the embodiments of the present invention can take any suitable form, as long as it does not impair the effects of the embodiments of the present invention. Examples of the edges of the group III element nitride semiconductor substrate according to the embodiments of the present invention include a shape in which the main surface and back surface are chamfered so that they are flat surfaces, a shape in which the main surface and back surface are chamfered in an R shape, a shape in which only the main surface side of the edge is chamfered so that it is flat surface, and a shape in which only the back surface side of the edge is chamfered so that it is flat surface.

[0036] In the case where the edges of the group III element nitride semiconductor substrate according to an embodiment of the present invention are chamfered, the chamfered portion may be provided over the entire circumference of the outer periphery, or it may be provided only on a part of the outer periphery.

[0037] In the embodiment of the present invention, a group III element nitride semiconductor substrate has E2 at 5 μm intervals along a straight line from the centroid of the surface of the first surface to the centroid of the surface of the second surface, from a point 5 μm inward from the surface of the first surface to a point half the thickness of the substrate, and from a point 5 μm inward from the surface of the second surface to a point half the thickness of the substrate. H When measuring the peak wavenumbers corresponding to the phonon modes, the n peak wavenumbers are defined as B1 to Bn in order from the surface side of the first surface (where n is the number of peak wavenumber measurements, and is an integer obtained by rounding up the decimal part of [(thickness of the group III element nitride semiconductor substrate (μm) - 5 (μm)) / 5 (μm)]), and the maximum peak wavenumber among the n measured values ​​is B max and the minimum peak wavenumber B min The difference (B max -B min ) is 2.0cm -1The following, preferably 1.5 cm -1 The following, and more preferably 1.0 cm -1 The following applies: difference If all of the above conditions are within the specified range, it is possible to provide a group III element nitride semiconductor substrate in which the occurrence of chipping defects during device fabrication is suppressed.

[0038] The above value n represents the number of peak wavenumbers measured.

[0039] For example, if the thickness of the group III element nitride semiconductor substrate is 300 μm (a multiple of 5 μm), then n will be 59. Measurements are taken at points 5 μm inside the surface of the first surface (peak wavenumber B1), 10 μm inside the surface of the first surface (peak wavenumber B2), 15 μm inside the surface of the first surface (peak wavenumber B3), and then proceeding inward by 5 μm at a time until the point half the thickness of the substrate is reached (150 μm inside the surface of the first surface) (peak wavenumber B30). Next, at a point 5 μm inward from the surface of the second surface (peak wavenumber B59), at a point 10 μm inward from the surface of the second surface (peak wavenumber B58), at a point 15 μm inward from the surface of the second surface (peak wavenumber B57), and then moving inward in 5 μm increments, the point at half the thickness of the substrate (150 μm inward from the surface of the second surface) coincides with the point 150 μm inward from the surface of the first surface, and is B30.

[0040] For example, if the thickness of the group III element nitride semiconductor substrate is 302 μm (not a multiple of 5 μm), then n will be 60. Measurements are taken at points 5 μm inside the surface of the first surface (peak wavenumber B1), 10 μm inside the surface of the first surface (peak wavenumber B2), 15 μm inside the surface of the first surface (peak wavenumber B3), and then proceeding inward in 5 μm increments until the point closest to the halfway point of the substrate thickness (151 μm inside the surface of the first surface), which is 150 μm inside the surface of the first surface (peak wavenumber B30). Next, measurements are taken at a point 5 μm inside the surface of the second surface (peak wavenumber B60), a point 10 μm inside the surface of the second surface (peak wavenumber B59), a point 15 μm inside the surface of the second surface (peak wavenumber B58), and then proceeding inward in 5 μm increments until the point closest to the halfway point of the substrate thickness (151 μm inside the surface of the second surface), which is 150 μm inside the surface of the second surface (peak wavenumber B31). The distance between the point 150 μm inside the surface of the first surface (peak wavenumber B30) and the point 150 μm inside the surface of the second surface (peak wavenumber B31) is 2 μm.

[0041] The inventors diligently studied to solve the conventional problem in which the yield of semiconductor devices fabricated on a group III element nitride semiconductor substrate decreases when chipping defects occur in the gallium nitride substrate during cutting of the substrate together with the semiconductor device. As a result, in a group III element nitride semiconductor substrate having a first surface and a second surface, along a straight line from the centroid position of the surface of the first surface to the centroid position of the surface of the second surface, E2 is present at 5 μm intervals from a point 5 μm inward from the surface of the first surface to a point half the thickness of the substrate, and from a point 5 μm inward from the surface of the second surface to a point half the thickness of the substrate. H When measuring the peak wavenumbers corresponding to the phonon modes, the n peak wavenumbers are defined as B1 to Bn in order from the surface side of the first surface (where n is the number of peak wavenumber measurements, and is an integer obtained by rounding up the decimal part of [(thickness of the group III element nitride semiconductor substrate (μm) - 5 (μm)) / 5 (μm)]), and the maximum peak wavenumber among the n measured values ​​is B max and the minimum peak wavenumber B minThe difference (B max -B min ) was found to be related to the size of chipping that occurs when cutting a group III element nitride semiconductor substrate. Considering that larger chips result in chipping defects, the above difference The technical idea that a Group III element nitride semiconductor substrate can be provided with suppressed chipping defects during device fabrication by designing it using the evaluation criteria led to the completion of the present invention.

[0042] Here, E2 H A phonon mode, for example, in the case of a wurtzite-type gallium nitride (GaN) crystal, is a mode in which adjacent N atoms in the GaN crystal vibrate in the in-plane direction within the C plane. E2 H The Raman shift corresponding to the phonon mode is E2 in the Raman shift spectrum obtained by Raman analysis. H It is determined by the wavenumber at the maximum peak of the peak corresponding to the phonon mode. Here, Patent Documents 2-4 describe the E2 of a wurtzite-type GaN crystal at a temperature of 300K. H The phonon mode wavenumber is 567.6 cm². -1 And its E2 H The wavenumber at the maximum peak corresponding to the phonon mode is 567.6 cm². -1 It is described that it appears in the vicinity of [location].

[0043] The above n peak wavenumbers can typically vary in such a way that they define a peak-and-valley (concave-concave) fluctuation curve in the thickness direction of the substrate. For example, the above peak wavenumbers can vary in a fluctuation curve as shown in Figure 4 from the main surface toward the back surface. According to an embodiment of the present invention, the maximum peak wavenumber B max and the minimum peak wavenumber B min The difference (B max -B min), that is, by controlling the difference between the largest peak and the largest trough in the fluctuation curve to be below a predetermined value, the occurrence of chipping defects during device fabrication can be suppressed. One of the features of the embodiments of the present invention is that the difference between the largest peak and the largest trough is controlled rather than the average degree of fluctuation in the fluctuation curve (average deviation from the center value). In the stress in the thickness direction (peak wave number), the deviation from the center value represents the magnitude of local crystal lattice strain. When the strain is large, it is as if cracks exist at the atomic level. Chipping can be presumed to occur through a mechanism in which force concentrates on atomic-level cracks during cutting and propagates into macro-level cracks. Therefore, it can be estimated that chipping defects can be suppressed by controlling the difference between the largest peak and the largest trough, which allows evaluation of local stress fluctuations, rather than the average degree of fluctuation. However, such a mechanism is merely an estimate and does not limit the interpretation of the embodiments of the present invention, nor does it restrict the embodiments of the present invention by this mechanism.

[0044] The group III element nitride semiconductor substrate according to the embodiment of the present invention can be manufactured by any suitable method without impairing the effects of the embodiment of the present invention. A preferred method for manufacturing the group III element nitride semiconductor substrate according to the embodiment of the present invention will be described below, in terms of further enhancing the effects of the embodiment of the present invention.

[0045] In an embodiment of the present invention, a group III element nitride semiconductor substrate is typically formed by creating a seed crystal film on the main surface of a substrate and creating a group III element nitride layer on the group III element polar surface of the seed crystal film. Then, the group III element nitride layer (seed crystal film + group III element nitride layer) that will become a self-supporting substrate is separated from the substrate to obtain a self-supporting substrate having a main surface and a back surface.

[0046] As for the substrate material, any suitable material can be used as long as it does not impair the effects of the embodiments of the present invention. Examples of such materials include sapphire, crystal-oriented alumina, gallium oxide, and Al. x Ga 1-x Examples include N(0≦x≦1), GaAs, and SiC.

[0047] As for the material of the seed crystal film, any suitable material can be used as long as it does not impair the effects of the embodiments of the present invention. For example, Al x Ga 1-x N(0≦x≦1) or In x Ga 1-x Examples of N(0≦x≦1) include gallium nitride.

[0048] As a method for forming the seed crystal film, any suitable formation method can be adopted as long as it does not impair the effects of the embodiments of the present invention. Examples of such formation methods include vapor phase growth, and preferably include metal-organic chemical vapor deposition (MOCVD), hydride vapor deposition (HVPE), pulsed excitation deposition (PXD), MBE, and sublimation. Among these, metal-organic chemical vapor deposition (MOCVD) is more preferred as a method for forming the seed crystal film.

[0049] The formation of seed crystal films by the MOCVD method is preferably carried out by, for example, depositing a low-temperature growth buffer layer of 20 nm to 50 nm at 450°C to 550°C, followed by stacking films with a thickness of 2 μm to 4 μm at 1000°C to 1200°C.

[0050] As for the growth direction of the group III element nitride crystal layer, any appropriate growth direction can be adopted as long as it does not impair the effects of the embodiments of the present invention. Examples of such growth directions include the direction normal to the c-plane of the wurtzite structure, the directions normal to the a-plane and m-plane respectively, and the directions normal to the planes inclined from the c-plane, a-plane, and m-plane respectively.

[0051] As for the method of forming the group III element nitride crystal layer, any suitable formation method can be adopted as long as it has a crystal orientation that generally follows the crystal orientation of the seed crystal film, provided that it does not impair the effects of the embodiments of the present invention. Examples of such formation methods include vapor phase growth methods such as metal-organic chemical vapor deposition (MOCVD), hydride vapor deposition (HVPE), pulsed excitation deposition (PXD), MBE, and sublimation; liquid phase growth methods such as Na flux, amonothermal, hydrothermal, and sol-gel methods; powder growth methods utilizing solid phase growth of powder; and combinations thereof.

[0052] When employing the Na flux method as a method for forming a group III element nitride crystal layer, it is preferable to perform the Na flux method in accordance with the manufacturing method described in Japanese Patent Publication No. 5244628, adjusting the conditions as appropriate to better exhibit the effects of the embodiments of the present invention.

[0053] The formation of a group III element nitride crystal layer by the Na flux method is typically carried out in a nitrogen atmosphere by placing a seed crystal substrate (underlying substrate + seed crystal film) in a crucible serving as a growth container, filling the crucible with a molten composition containing group III elements, metallic Na, and, if necessary, dopants (e.g., n-type dopants such as germanium (Ge), silicon (Si), and oxygen (O); p-type dopants such as beryllium (Be), magnesium (Mg), calcium (Ca), strontium (Sr), zinc (Zn), and cadmium (Cd); etc.), covering the crucible, placing the covered crucible in an outer container, and then placing the outer container in a pressure-resistant container, followed by heating and pressurizing in a nitrogen atmosphere, and then rotating while maintaining the temperature and pressure.

[0054] The above heating is carried out preferably until the temperature reaches a range of 700°C to 1000°C, more preferably until the temperature reaches a range of 800°C to 900°C. In this specification, this reached temperature may be referred to as the final reached temperature.

[0055] The heating time is preferably 105 minutes or more, more preferably 120 to 250 minutes, even more preferably 140 to 220 minutes, and particularly preferably 160 to 200 minutes. If the heating time is too short and falls outside this range, variations may occur in the timing and growth rate of crystal growth, which can result in the formation of regions with different residual stresses. This can lead to chipping defects when cutting out semiconductor devices made on the resulting Group III element nitride semiconductor substrate together with the substrate.

[0056] The above heating process, when reaching 400°C, preferably takes 5 minutes or more, more preferably 10 to 70 minutes, even more preferably 20 to 60 minutes, and particularly preferably 30 to 50 minutes.

[0057] The above heating time, from 400°C to the final target temperature, is preferably 100 minutes or more, more preferably 110 to 210 minutes, even more preferably 120 to 200 minutes, even more preferably 130 to 190 minutes, particularly preferably 140 to 180 minutes, and most preferably 150 to 170 minutes. If the heating time from 400°C to the final target temperature falls outside the above range, variations may occur in the timing and growth rate of crystal growth, resulting in the formation of regions with different residual stresses. This may lead to chipping defects when cutting out semiconductor devices fabricated on the resulting Group III element nitride semiconductor substrate together with the substrate.

[0058] The above pressurization is preferably carried out in the range of 1 MPa to 7 MPa, and more preferably in the range of 2 MPa to 6 MPa.

[0059] Next, by separating the group III element nitride crystal layer from the underlying substrate, a self-supporting substrate containing the group III element nitride crystal layer can be obtained.

[0060] As a method for separating the group III element nitride crystal layer from the underlying substrate, any suitable method can be adopted as long as it does not impair the effects of the embodiments of the present invention. Examples of such methods include a method of spontaneously separating the group III element nitride crystal layer from the underlying substrate by using the difference in thermal shrinkage during the cooling process after growing the group III element nitride crystal layer; a method of separating the group III element nitride crystal layer from the underlying substrate by chemical etching; a method of peeling off the group III element nitride crystal layer from the underlying substrate by a laser lift-off method by irradiating the underlying substrate with laser light from the back side of the underlying substrate; and a method of peeling off the group III element nitride crystal layer from the underlying substrate by grinding. Alternatively, a self-supporting substrate containing the group III element nitride crystal layer may be obtained by slicing the group III element nitride crystal layer using a wire saw or the like.

[0061] In this manner, the group III element nitride crystal layer obtained by the Na flux method is preferably flattened by grinding with a grinding wheel or the like, and then smoothed by lapping with diamond abrasive grains or the like.

[0062] Next, the outer periphery of the self-supporting substrate is ground to create a circular shape of the desired diameter.

[0063] The size of the self-supporting substrate can be any appropriate size, as long as it does not impair the effects of the embodiments of the present invention. Examples of such sizes include 25 mm (approximately 1 inch), 45-55 mm (approximately 2 inches), 95-105 mm (approximately 4 inches), 145-155 mm (approximately 6 inches), 195-205 mm (approximately 8 inches), and 295-305 mm (approximately 12 inches).

[0064] Next, the main surface and / or back surface are removed by grinding, lapping, polishing, etc., to thin and flatten the plate to the desired thickness, thereby obtaining a self-supporting substrate.

[0065] When performing surface processing such as grinding, lapping, and polishing, a self-supporting substrate is usually attached to the processing platen using wax or similar means. In this process, the pressure applied to the self-supporting substrate when attaching it to the processing platen, specifically the pressure applied to the self-supporting substrate when attaching it to the processing platen, should be appropriately adjusted.

[0066] The thickness of the self-supporting substrate after polishing (or the thickness at the thickest point if the thickness is not uniform) is preferably 300 μm to 1000 μm.

[0067] If necessary, the outer edges of the self-supporting substrate are chamfered by grinding. If a processed altered layer remains on the main surface, the processed altered layer is substantially removed. Also, if residual stress remains on the back surface due to the processed altered layer, the residual stress is removed, and finally, a group III element nitride semiconductor substrate according to the embodiment of the present invention is obtained.

[0068] In the Group III element nitride semiconductor substrate according to the embodiment of the present invention, chamfering can be performed by any suitable chamfering method, as long as it does not impair the effects of the embodiment of the present invention. Examples of such chamfering methods include grinding using a diamond grinding wheel, polishing using tape, and CMP (Chemical Mechanical Polish) using a slurry such as colloidal silica and a nonwoven polishing pad.

[0069] The resulting group III element nitride semiconductor substrate allows for epitaxial crystal growth on its main surface (group III element polar surface), enabling the deposition of a functional layer and the creation of a functional device.

[0070] Examples of epitaxial crystals grown on the resulting Group III element nitride semiconductor substrate include gallium nitride, aluminum nitride, indium nitride, or mixed crystals thereof. Specific examples of such epitaxial crystals include GaN, AlN, InN, and Ga x Al 1-x N(1>x>0), Ga x In 1-x N(1>x>0), Alx In 1-x N(1>x>0), Ga x Al y In z One example is N(1>x>0, 1>y>0, x+y+z=1). In addition, functional layers to be provided on the resulting Group III element nitride semiconductor substrate include not only light-emitting layers, but also rectifier layers, switching elements, and power semiconductor layers. Furthermore, after providing the functional layers on the Group III element polar surface of the resulting Group III element nitride semiconductor substrate, the nitrogen polar surface can be processed, for example, by grinding or polishing, to reduce the thickness and thickness distribution of the self-supporting substrate.

[0071] The resulting group III element nitride semiconductor substrate and the support substrate can be bonded together to form a bonded substrate according to an embodiment of the present invention. That is, the bonded substrate according to an embodiment of the present invention is formed by bonding the group III element nitride semiconductor substrate according to an embodiment of the present invention to the support substrate.

[0072] The bonded substrate according to the embodiment of the present invention may further have any suitable layers, as long as they do not impair the effects of the embodiment of the present invention. The type, function, number, combination, arrangement, etc., of such layers can be appropriately determined according to the purpose.

[0073] The thickness of the support substrate can be any appropriate thickness, as long as it does not impair the effects of the embodiments of the present invention. For example, the thickness of the support substrate is 100 μm to 1000 μm.

[0074] Any suitable substrate can be used as the support substrate, as long as it does not impair the effects of the embodiments of the present invention. The support substrate may be made of a single crystal or a polycrystalline material.

[0075] In the bonded substrate according to the embodiment of the present invention, for example, the bonding surface of a group III element nitride semiconductor substrate and the bonding surface of a support substrate are directly bonded. Specifically, for example, the bonding surface of the support substrate and the bonding surface of the group III element nitride semiconductor substrate are placed facing each other, the bonding surface of the support substrate and the bonding surface of the group III element nitride semiconductor substrate are surface activated, and then bonded to obtain the bonded substrate according to the embodiment of the present invention. After this, a desired epitaxial film can be formed on the film deposition surface of the group III element nitride semiconductor substrate.

[0076] In the laminated substrate according to an embodiment of the present invention, for example, a bonding layer can be provided between a group III element nitride semiconductor substrate and a support substrate. Specifically, for example, the bonding surface of the bonding layer on the main surface of the support substrate and the bonding surface of the group III element nitride semiconductor substrate are faced, the bonding surface of the bonding layer and the bonding surface of the group III element nitride semiconductor substrate are surface activated, and then bonding is performed to obtain the laminated substrate according to an embodiment of the present invention. After this, a desired epitaxial film can be formed on the film deposition surface of the group III element nitride semiconductor substrate. Alternatively, the bonding layer may be provided on the main surface of the group III element nitride semiconductor substrate and the bonding surface of the bonding layer may be directly bonded to the bonding surface of the support substrate, or a first bonding layer may be provided on the main surface of the group III element nitride semiconductor substrate and a second bonding layer may be provided on the main surface of the support substrate and the bonding surface of the first bonding layer may be directly bonded to the bonding surface of the second bonding layer.

[0077] In an embodiment of the present invention, if the bonded substrate is provided between a group III element nitride semiconductor substrate and a support substrate, the bonding layer may be tantalum pentoxide, alumina, aluminum nitride, silicon carbide, sialon, or Si (1-x) O x It is preferable that at least one element is selected from the group consisting of (0.008 ≤ x ≤ 0.408). This further improves the bonding strength between the support substrate and the group III element nitride semiconductor substrate.

[0078] Furthermore, Sialon is a ceramic obtained by sintering a mixture of silicon nitride and alumina, and has the following composition. Si 6-z Al z O z N 8-z In other words, SiAlON has a composition in which alumina is mixed in silicon nitride, and z indicates the mixing ratio of alumina. z is more preferably 0.5 or higher. z is more preferably 4.0 or lower. [Examples]

[0079] The present invention will be specifically described below with reference to examples, but the present invention is not limited in any way to these examples. The test and evaluation methods in the examples are as follows. When "parts" is written, it means "parts by weight" unless otherwise specified, and when "%" is written, it means "percent by weight" unless otherwise specified.

[0080] <Raman analysis> (Measurement conditions) Equipment: LabRam ARAMIS micro-laser Raman spectrometer (manufactured by Horiba, Ltd.) Light source: Semiconductor-pumped solid-state laser (520nm) Spectrometer slit: 100 μm Laser spot diameter: Φ0.8μm Objective lens: 100x Detector: CCD (1024 x 256 pixels) Diffraction grating: 2400 gr / mm (Correction conditions) For wavenumber calibration, use a Ne lamp at 1708 cm². -1 The peak was used for the GaN substrate E2. H After approximating the peaks corresponding to the phonon modes with the Gauss-Lorentz function, the wavenumber at the maximum peak was calculated. (Measurement method) The Ga side of the GaN substrate at its centroid was irradiated with laser light, and the position where the intensity of the reflected light was maximum was defined as the outermost surface on the Ga side. From there, the stage was moved 5 μm upwards, and a Raman spectrum was acquired. Subsequently, Raman spectra were acquired while raising the stage in 5 μm increments. The measurement was stopped when the raised stage height reached half the thickness of the GaN substrate. The substrate was then flipped over, and the N side of the GaN substrate at its centroid was irradiated with laser light, and the position where the intensity of the reflected light was maximum was defined as the outermost surface on the N side. Similar to the measurement from the Ga side, spectra were acquired in 5 μm increments while raising the stage up to half the sample thickness. If the Ga side and / or N side of the GaN substrate are roughened, it is preferable to polish the roughened surface before measuring from that side, and it is more preferable to polish it so that the arithmetic mean roughness Ra is 1.0 nm or less. Even without polishing, it is preferable that the surface to be measured has an arithmetic surface roughness Ra of 1.0 nm or less.

[0081] <E2 H Measurement of the difference between the maximum and minimum values ​​of the Raman shift corresponding to the phonon mode. E2 obtained by Raman analysis H Phonon mode corresponding peak wavenumber E2 H Based on the peak wavenumber corresponding to the phonon mode, (1) Along the straight line from the centroid of the outermost surface on the Ga side to the centroid of the outermost surface on the N side, E2 is applied at 5 μm intervals from a point 5 μm inward from the outermost surface on the Ga side to a point half the thickness of the GaN substrate, and from a point 5 μm inward from the outermost surface on the N side to a point half the thickness of the GaN substrate. H The n peak wavenumbers corresponding to the phonon modes are measured and designated as B1 to Bn in order from the surface side of the first surface (where n is the number of measured peak wavenumbers, and is an integer obtained by rounding up the decimal part of [(thickness of the group III element nitride semiconductor substrate (μm) - 5 (μm)) / 5 (μm)]). (2) The largest peak wavenumber B among the n measurements max and the minimum peak wavenumber B min The difference (B max -Bmin ) was sought.

[0082] <Evaluation of the number of chipping defects during circuit board cutting> The obtained GaN substrate was cut into 10 mm square chips, and the edges of the chips were observed using an optical microscope. Of the chipping observed at the edges, those with an inward diameter of 100 μm or more were counted as chipping defects. The "magnitude in the internal direction" referred to here was calculated as follows: First, the entire edge of the chip was imaged using a 50x optical microscope. In each of the N images obtained, two edges where chipping did not occur were connected by lines to represent the normal edge position. For each chip, a line segment was drawn from the edge position formed by the chipping to the normal edge position to obtain the shortest distance. The length of this line segment was defined as the "magnitude in the internal direction."

[0083] [Example 1] A seed crystal substrate was prepared by forming a 2 μm thick gallium nitride film on a sapphire substrate using the MOCVD method. This seed crystal substrate was placed in an alumina crucible in a glove box under a nitrogen atmosphere. Next, metallic gallium and metallic sodium were filled into the crucible so that Ga / Ga+Na (mol%) = 15 mol%, and the crucible was covered with an alumina plate. The crucible was placed in a stainless steel inner container, which was then placed in a stainless steel outer container that could house the inner container, and the container lid was closed. This outer container was placed on a rotating platform installed in the heating section of the crystal manufacturing apparatus, and the pressure vessel was sealed with a lid. Next, the inside of the pressure vessel was evacuated to 0.1 Pa or less using a vacuum pump. Subsequently, the upper heater, middle heater, and lower heater were adjusted to heat the temperature of the heating space to 870 °C. The temperature was raised to 400 °C over 60 minutes and then to 870 °C over 120 minutes. It was held in that state for 40 hours. During heating, nitrogen gas was introduced from a nitrogen gas cylinder up to 4.0 MPa, and the outer container was rotated clockwise and counterclockwise at a constant cycle at a speed of 20 rpm around the central axis. Then, it was naturally cooled to room temperature and depressurized to atmospheric pressure, after which the lid of the pressure vessel was opened and the crucible was taken out from inside. The solidified metallic sodium in the crucible was removed, and the gallium nitride crystal grown on the seed crystal substrate was recovered. The gallium nitride crystal thus obtained was separated from the seed substrate, polished, and ground to produce a self-supporting substrate of gallium nitride crystal with a diameter of 50.8 mm and a thickness of 400 μm. Raman analysis of the produced self-supporting substrate was performed, and the difference between the maximum and minimum values of the Raman shift corresponding to the E2 H phonon mode was measured. As a result, it was 1.70 cm -1 . Nine chips were cut out from the self-supporting substrate after measurement, and the ends of each chip were observed with an optical microscope. Observation was performed at 50 times magnification, and chipping with a size of 100 μm or more in the internal direction was counted as chipping failure. No chipping failure occurred.

[0084] [Example 2] A self-supporting substrate of gallium nitride crystal was produced in the same manner as in Example 1. However, in the crystal growth process, the temperature increase to 400 °C was carried out over 40 minutes, and the temperature increase from 400 °C to 870 °C was carried out over 140 minutes. Raman analysis was performed in the same manner as in Example 1, and the difference between the maximum and minimum values of the Raman shift corresponding to the E2 H phonon mode was measured. As a result, it was 1.48 cm -1 . Nine chips were cut out from the self-supporting substrate after measurement, and the ends of each chip were observed with an optical microscope. Observation was performed at 50 times magnification, and chipping with a size of 100 μm or more in the internal direction was counted as chipping failure. No chipping failure occurred.

[0085] [Example 3] A self-supporting substrate of gallium nitride crystal was fabricated in the same manner as in Example 1. However, in the crystal growth process, the temperature increase to 400 °C was carried out over 40 minutes, and the temperature increase from 400 °C to 870 °C was carried out over 160 minutes. Raman analysis was performed in the same manner as in Example 1, and the difference between the maximum value and the minimum value of the Raman shift corresponding to the E2 H phonon mode was measured. As a result, it was 0.93 cm -1 . Furthermore, the variation state of the Raman shift from the front surface to the back surface of the substrate is shown in FIG. 5. In addition, the average variation width D ave of the Raman shift (peak frequency) was calculated from FIG. 5. D ave was 0.17. Note that D ave is the average value of the absolute values of the differences between the average value of B1 to Bn and each peak frequency. Nine chips were cut out from the self-supporting substrate after measurement, and the ends of each chip were observed with an optical microscope. Observation was carried out at 50 times magnification, and chipping with a size of 100 μm or more in the inner direction was counted as chipping failure. No chipping failure occurred. In addition, an optical micrograph of the end is shown in FIG. 2.

[0086] [Comparative Example 1] A self-supporting substrate of gallium nitride crystal was fabricated in the same manner as in Example 1. However, in the crystal growth process, the temperature increase to 400 °C was carried out over 40 minutes, and the temperature increase from 400 °C to 870 °C was carried out over 60 minutes. Raman analysis was performed in the same manner as in Example 1, and the difference between the maximum value and the minimum value of the Raman shift corresponding to the E2 H phonon mode was measured. As a result, it was 2.01 cm -1 . Furthermore, the variation state of the Raman shift from the front surface to the back surface of the substrate is shown in FIG. 6. In addition, D ave was calculated from FIG. 6. D ave was 0.14. Nine chips were cut from the self-supporting substrate after measurement, and the edges of each chip were observed using an optical microscope. Observation was performed at 50x magnification, and chipping with an internal size of 100 μm or more was counted as a chipping defect. Chipping defects occurred in 4 out of 9 chips, with a total of 10 locations where chipping defects occurred. Figure 3 shows an optical microscope image of the end where chipping defects occurred.

[0087] [evaluation] As is clear from the examples and comparative examples, E2 H It can be seen that chipping defects can be suppressed by controlling the difference between the maximum and minimum values ​​of the Raman shift (peak wavenumber) corresponding to the phonon mode to be below a predetermined value. Furthermore, as is clear from comparing Example 3 and Comparative Example 1, the average fluctuation range D of the peak wavenumber is also suppressed. ave Even if the value is small, if the difference between the maximum and minimum peak wavenumbers is large, it can be seen that the chipping suppression effect cannot be obtained. [Industrial applicability]

[0088] The group III element nitride semiconductor substrate according to the embodiment of the present invention can be used as a substrate for various semiconductor devices. [Explanation of symbols]

[0089] 100 Group III element nitride semiconductor substrates 10 Main surface 20 Back side 30 Side view

Claims

1. A semiconductor substrate made of a group III element nitride, comprising a first surface and a second surface, The thickness is 100 μm or more. Along the straight line from the centroid of the first surface to the centroid of the second surface, E is present at 5 μm intervals from a point 5 μm inward from the surface of the first surface to a point half the thickness of the substrate, and from a point 5 μm inward from the surface of the second surface to a point half the thickness of the substrate. ２ Ｈ When the n peak wavenumbers corresponding to the phonon modes are measured, and these n peak wavenumbers are denoted as B1 to Bn in order from the surface side of the first surface (where n is the number of peak wavenumbers measured, and is an integer obtained by rounding up the decimal part of [(thickness of the group III element nitride semiconductor substrate (μm) - 5 (μm)) / 5 (μm)]), The maximum peak wavenumber B among the n measurements ｍａｘ and the minimum peak wavenumber B ｍｉｎ The difference (B ｍａｘ -B ｍｉｎ ) is 2.0 cm －１ The following is: Group III element nitride semiconductor substrate.

2. The difference (B max - B min) is 1.5 cm in all cases. －１ The following is the Group III element nitride semiconductor substrate according to claim 1.

3. The difference (Bmax - Bmin) is all 1.0 cm or less. －１ The group-III nitride semiconductor substrate according to claim 2, wherein the difference (Bmax - Bmin) is all 1.0 cm or less.

4. The group III element nitride semiconductor substrate according to claim 1, wherein the n peak wavenumbers fluctuate in such a way that they define a peak-and-valley shaped fluctuation curve in the thickness direction of the substrate.

5. A group III element nitride semiconductor substrate according to claim 1, wherein the diameter is 45 mm or more.

6. The group III element nitride semiconductor substrate according to claim 1, wherein the thickness is 300 μm or more.

7. A support substrate is bonded to a group III element nitride semiconductor substrate according to any one of claims 1 to 6. Bonded circuit board.

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